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1.6 v, micropower 12-, 10-, and 8-bit adcs in 6-lead sot-23 ad7466/ad7467/ad7468 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features specified for v dd of 1.6 v to 3. 6 v low power: 0.62 mw typ at 100 ksps with 3 v s u pplies 0.48 mw typ at 50 ks ps with 3 . 6 v s u pplies 0.12 mw typ at 100 ksps with 1.6 v supplies fast throughput rate: 200 ks ps wide input bandwidth: 71 db s n r at 3 0 kh z input fr e q uency flexible power/serial clock speed managem e nt n o pipeline delays high speed s e r i al interface: spi ?- /qspi?-/m i crowire?-/dsp-compatible automatic power-down power-down mode: 8 na typ 6-lea d sot-23 package 8-lea d msop package applic ati o ns battery-powered systems medical instr u ments remote data a c quisition isolated dat a a c quisition gener a l description the ad7466 /ad7467/ad7468 1 a r e 12-, 10-, and 8-b i t, hig h sp e e d, l o w p o we r , su c c e s s i ve a p p r o x ima t ion a d c s , re sp e c t i ve ly . the p a r t s o p era t e f r o m a sin g l e 1.6 v t o 3.6 v p o w e r s u p p l y a nd f e a t ur e thr o ug h p u t ra t e s u p t o 200 ks ps wi t h lo w p o w e r dissi p a t io n. t h e p a r t s co n t a i n a lo w n o i s e, wi de b a ndwi d t h t r ack-and- h o ld a m plif ier , w h ich can han d le in p u t f r e q uen c ies in exces s o f 3 mh z. the con v ersio n p r o c es s a nd da t a acq u isi t io n a r e co n t r o l l e d usin g cs a nd t h e s e r i a l clo c k, a l lo wi n g t h e de vice s to in ter f ace w i t h m i c r opro c e ss or s or d s p s . t h e i n put s i g n a l i s s a m p l e d o n th e fallin g ed g e o f cs , a n d t h e con v ersio n is als o i n i t ia t e d a t t h i s po i n t . th e r e a r e n o p i pe lin e de la ys a s soci a t ed wi th th e pa r t . the r e fer e n c e fo r t h e p a r t is t a k e n i n t e r n al l y f r o m v dd . this al lo ws t h e wi de s t d y namic i n p u t ra n g e t o t h e a d c. th us, t h e a n alog in p u t ra n g e f o r th e p a r t is 0 v t o v dd . th e con v ersion r a te i s d e te r m i n e d b y t h e s c l k . 1 pr otected by u. s. patent no. 6,681,332. func tio n a l block di agram ad7466/ad7467/ad7468 12-/10-/8-bit successive approximation adc control logic gnd v dd v in sclk sd a t a t/h 02643-001 cs fi g u r e 1 . produc t highlight s 1. s p ecif ied f o r s u p p l y v o l t a g es o f 1.6 v t o 3.6 v . 2. 12-, 10-, an d 8 - b i t ad cs in s o t - 23 p a c k a g es. 3. h i g h th r o ug h p u t ra t e wi th lo w po w e r co n s um p t i o n . p o w e r co n s u m pt io n i n n o r m a l m o de o f o p er a t i o n a t 100 ks ps an d 3 v is 0.9 mw maxim u m. 4. flexi b le p o w e r/s e r i al c l o c k sp ee d ma na g e m e n t . the con v ersio n ra t e is det e r m ine d b y t h e s e r i al clo c k, al lo w i n g t h e con v ersio n t i m e to b e r e d u ce d t h r o ug h i n c r ease s in t h e se ri al c l oc k s p ee d . a u t o ma ti c po w e r - d o wn a f t e r co n v ersio n al lo ws t h e a v era g e p o w e r co n s um p t ion t o b e r e d u ce d w h e n i n p o w e r - do w n . c u r r en t co nsum p t ion is 0.1 a maxim u m an d 8 na typ i cal l y w h en in p o w e r - do wn. 5. refer e n c e der i ve d f r o m t h e p o w e r su p p ly . 6. n o p i p e line de l a y . t h e p a r t f e at u r e s a s t a n d a r d s u c c e s s i v e ap p r ox i m at i o n a d c w i th a c cura t e c o n t r o l o f co n v e r s i o n s vi a a cs in p u t.
ad7466/ad7467/ad7468 rev. a | page 2 of 28 table of contents ad7466 specifications ..................................................................... 3 ad7467 specifications ..................................................................... 5 ad7468 specifications ..................................................................... 7 timing specifications ....................................................................... 9 timing examples ........................................................................ 10 absolute maximum ratings .......................................................... 11 esd caution ................................................................................ 11 pin configurations and function descriptions ......................... 12 ter mi nolo g y ................................................................................ 13 typical performance characteristics ........................................... 14 dynamic performance curves ................................................. 14 dc accuracy curves ................................................................. 14 power requirements curves ..................................................... 14 circuit information ........................................................................ 17 converter operation .................................................................. 17 adc transfer function ............................................................. 17 typical connection diagram ................................................... 18 analog input ............................................................................... 18 digital inputs .............................................................................. 19 normal mode .............................................................................. 19 power consumption .................................................................. 20 serial interface ................................................................................ 22 microprocessor interfacing ....................................................... 23 application hints ........................................................................... 25 grounding and layout .............................................................. 25 evaluating the performance of the ad7466 and ad7467 .... 25 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 27 revision history 11/04rev. 0 to rev. a updated format..................................................................universal changes to general description .................................................... 1 added patent number ..................................................................... 1 updated outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 27 5/03revision 0: initial version
ad7466/ad7467/ad7468 rev. a | page 3 of 28 ad7466 specifications v dd = 1.6 v to 3.6 v, f sclk = 3.4 mhz, f sample = 100 ksps, unless otherwise noted. t a = t min to t max , unless otherwise noted. the temperature range for the b version is ?40c to +85c. table 1. parameter b version unit test conditions/comments dynamic performance f in = 30 khz sine wave signal-to-noise and distortion (sinad) 69 db min 1.8 v v dd 2 v; see the terminology section 70 db min 2.5 v v dd 3.6 v 70 db typ v dd = 1.6 v signal-to-noise ratio (snr) 70 db min 1.8 v v dd 2 v; see the terminology section 71 db typ 1.8 v v dd 2 v 71 db min 2.5 v v dd 3.6 v 70.5 db typ v dd = 1.6 v total harmonic distortion (thd) ?83 db typ see the terminology section peak harmonic or spurious noise (sfdr) ?85 db typ see the terminology section intermodulation distortion (imd) fa = 29.1 kh z, fb = 29.9 khz; see the terminology section second-order terms ?84 db typ third-order terms ?86 db typ aperture delay 10 ns typ aperture jitter 40 ps typ full-power bandwidth 3.2 mhz typ @ 3 db, 2.5 v v dd 3.6 v 1.9 mhz typ @ 3 db, 1.6 v v dd 2.2 v 750 khz typ @ 0.1 db, 2.5 v v dd 3.6 v 450 khz typ @ 0.1 db, 1.6 v v dd 2.2 v dc accuracy maximum specifications apply as typical figures when v dd = 1.6 v resolution 12 bits integral nonlinearity 1.5 lsb max see the terminology section differential nonlinearity ?0.9/+1.5 lsb max guaranteed no missed codes to 12 bits; see the terminology section offset error 1 lsb max see the terminology section gain error 1 lsb max see the terminology section total unadjusted error (tue) 2 ls b max see the terminology section analog input input voltage ranges 0 to v dd v dc leakage current 1 a max input capacitance 20 pf typ logic inputs input high voltage, v inh 0.7 v dd v min 1.6 v v dd < 2.7 v 2 v min 2.7 v v dd 3.6 v input low voltage, v inl 0.2 v dd v max 1.6 v v dd < 1.8 v 0.3 v dd v max 1.8 v v dd < 2.7 v 0.8 v max 2.7 v v dd 3.6 v input current, i in , sclk pin 1 a max typically 20 na, v in = 0 v or v dd input current, i in , cs pin 1 a typ input capacitance, c in 10 pf max sample tested at 25c to ensure compliance logic outputs output high voltage, v oh v dd ? 0.2 v min i source = 200 a; v dd = 1.6 v to 3.6 v output low voltage, v ol 0.2 v max i sink = 200 a floating-state leakage current 1 a max floating-state output capacitance 10 pf max output coding straight (natural) binary
ad7466/ad7467/ad7468 rev. a | page 4 of 28 parameter b version unit test conditions/comments conversion rate conversion time 4.70 s max 16 sclk cycles with sclk at 3.4 mhz throughput rate 200 ksps max see the serial interface section power requirements v dd 1.6/3.6 v min/max i dd digital inputs = 0 v or v dd normal mode (operational) 300 a max v dd = 3 v, f sample = 100 ksps 110 a typ v dd = 3 v, f sample = 50 ksps 20 a typ v dd = 3 v, f sample = 10 ksps 240 a max v dd = 2.5 v, f sample = 100 ksps 80 a typ v dd = 2.5 v, f sample = 50 ksps 16 a typ v dd = 2.5 v, f sample = 10 ksps 165 a max v dd = 1.8 v, f sample = 100 ksps 50 a typ v dd = 1.8 v, f sample = 50 ksps 10 a typ v dd = 1.8 v, f sample = 10 ksps power-down mode 0.1 a max sclk on or off, typically 8 na power dissipation see the power consumption section normal mode (operational) 0.9 mw max v dd = 3 v, f sample = 100 ksps 0.6 mw max v dd = 2.5 v, f sample = 100 ksps 0.3 mw max v dd = 1.8 v, f sample = 100 ksps power-down mode 0.3 w max v dd = 3 v
ad7466/ad7467/ad7468 rev. a | page 5 of 28 ad7467 specifications v dd = 1.6 v to 3.6 v, f sclk = 3.4 mhz, f sample = 100 ksps, unless otherwise noted. t a = t min to t max , unless otherwise noted. the temperature range for the b version is ?40c to +85c. table 2. parameter b version unit test conditions/comments dynamic performance maximum/minimum specifications apply as typical figures when v dd = 1.6 v, f in = 30 khz sine wave signal-to-noise and distortion (sinad) 61 db min see the terminology section total harmonic distortion (thd) ?72 db max see the terminology section peak harmonic or spurious noise (sfdr) ?74 db max see the terminology section intermodulation distortion (imd) fa = 29.1 kh z, fb = 29.9 khz; see the terminology section second-order terms ?83 db typ third-order terms ?83 db typ aperture delay 10 ns typ aperture jitter 40 ps typ full-power bandwidth 3.2 mhz typ @ 3 db, 2.5 v v dd 3.6 v 1.9 mhz typ @ 3 db, 1.6 v v dd 2.2 v 750 khz typ @ 0.1 db, 2.5 v v dd 3.6 v 450 khz typ @ 0.1 db, 1.6 v v dd 2.2 v dc accuracy maximum specifications apply as typical figures when v dd = 1.6 v resolution 10 bits integral nonlinearity 0.5 lsb max see the terminology section differential nonlinearity 0.5 lsb max guaranteed no missed codes to 10 bits; see the terminology section offset error 0.2 lsb max see the terminology section gain error 0.2 lsb max see the terminology section total unadjusted error (tue) 1 ls b max see the terminology section analog input input voltage ranges 0 to v dd v dc leakage current 1 a max input capacitance 20 pf typ logic inputs input high voltage, v inh 0.7 v dd v min 1.6 v v dd < 2.7 v 2 v min 2.7 v v dd 3.6 v input low voltage, v inl 0.2 v dd v max 1.6 v v dd < 1.8 v 0.3 v dd v max 1.8 v v dd < 2.7 v 0.8 v max 2.7 v v dd 3.6 v input current, i in , sclk pin 1 a max typically 20 na, v in = 0 v or v dd input current, i in , cs pin 1 a typ input capacitance, c in 10 pf max sample tested at 25c to ensure compliance logic outputs output high voltage, v oh v dd ? 0.2 v min i source = 200 a; v dd = 1.6 v to 3.6 v output low voltage, v ol 0.2 v max i sink = 200 a floating-state leakage current 1 a max floating-state output capacitance 10 pf max sa mple tested at 25c to ensure compliance output coding straight (natural) binary conversion rate conversion time 3.52 s max 12 sclk cycles with sclk at 3.4 mhz throughput rate 275 ksps max see the serial interface section
ad7466/ad7467/ad7468 rev. a | page 6 of 28 parameter b version unit test conditions/comments power requirements v dd 1.6/3.6 v min/max i dd digital inputs = 0 v or v dd normal mode (operational) 210 a max v dd = 3 v, f sample = 100 ksps 170 a max v dd = 2.5 v, f sample = 100 ksps 140 a max v dd = 1.8 v, f sample = 100 ksps power-down mode 0.1 a max sclk on or off, typically 8 na power dissipation see the power consumption section normal mode (operational) 0.63 mw max v dd = 3 v, f sample = 100 ksps 0.42 mw max v dd = 2.5 v, f sample = 100 ksps 0.25 mw max v dd = 1.8 v, f sample = 100 ksps power-down mode 0.3 w max v dd = 3 v
ad7466/ad7467/ad7468 rev. a | page 7 of 28 ad7468 specifications v dd = 1.6 v to 3.6 v, f sclk = 3.4 mhz, f sample = 100 ksps, unless otherwise noted. t a = t min to t max , unless otherwise noted. the temperature range for the b version is ?40c to +85c. table 3. parameter b version unit test conditions/comments dynamic performance maximum/minimum spec ifications apply as typical figures when v dd = 1.6 v, f in = 30 khz sine wave signal-to-noise and distortion (sinad) 49 db min see the terminology section total harmonic distortion (thd) ?66 db max see the terminology section peak harmonic or spurious noise (sfdr) ?66 db max see the terminology section intermodulation distortion (imd) fa = 29.1 khz, fb = 29.9 khz; see the terminology section second-order terms ?77 db typ third-order terms ?77 db typ aperture delay 10 ns typ aperture jitter 40 ps typ full-power bandwidth 3.2 mhz typ @ 3 db, 2.5 v v dd 3.6 v 1.9 mhz typ @ 3 db, 1.6 v v dd 2.2 v 750 khz typ @ 0.1 db, 2.5 v v dd 3.6 v 450 khz typ @ 0.1 db, 1.6 v v dd 2.2 v dc accuracy maximum specifications apply as typical figures when v dd = 1.6 v resolution 8 bits integral nonlinearity 0.2 lsb max see the terminology section differential nonlinearity 0.2 lsb max guaranteed no missed codes to 8 bits; see the terminology section offset error 0.1 lsb max see the terminology section gain error 0.1 lsb max see the terminology section total unadjusted error (tue) 0.3 lsb max see the terminology section analog input input voltage ranges 0 to v dd v dc leakage current 1 a max input capacitance 20 pf typ logic inputs input high voltage, v inh 0.7 v dd v min 1.6 v v dd < 2.7 v 2 v min 2.7 v v dd 3.6 v input low voltage, v inl 0.2 v dd v max 1.6 v v dd < 1.8 v 0.3 v dd v max 1.8 v v dd < 2.7 v 0.8 v max 2.7 v v dd 3.6 v input current, i in , sclk pin 1 a max typically 20 na, v in = 0 v or v dd input current, i in , cs pin 1 a typ input capacitance, c in 10 pf max sample tested at 25c to ensure compliance logic outputs output high voltage, v oh v dd ? 0.2 v min i source = 200 a; v dd = 1.6 v to 3.6 v output low voltage, v ol 0.2 v max i sink = 200 a floating-state leakage current 1 a max floating-state output capacitance 10 pf max sample tested at 25c to ensure compliance output coding straight (natural) binary conversion rate conversion time 2.94 s max 10 sclk cycles with sclk at 3.4 mhz throughput rate 320 ksps max see the serial interface section
ad7466/ad7467/ad7468 rev. a | page 8 of 28 parameter b version unit test conditions/comments power requirements v dd 1.6/3.6 v min/max i dd digital inputs = 0 v or v dd normal mode (operational) 190 a max v dd = 3 v, f sample = 100 ksps 155 a max v dd = 2.5 v, f sample = 100 ksps 120 a max v dd = 1.8 v, f sample = 100 ksps power-down mode 0.1 a max sclk on or off, typically 8 na power dissipation see the power consumption section normal mode (operational) 0.57 mw max v dd = 3 v, f sample = 100 ksps 0.4 mw max v dd = 2.5 v, f sample = 100 ksps 0.2 mw max v dd = 1.8 v, f sample = 100 ksps power-down mode 0.3 w max v dd = 3 v
ad7466/ad7467/ad 7468 r e v. a | pa ge 9 o f 2 8 timing specifica t ions fo r a l l d e v i c e s , v dd = 1.6 v t o 3.6 v ; t a = t min to t max , unles s oth e r w is e n o t e d . sa m p le t e s t e d a t 25c t o en s u r e co m p lia n ce . al l in p u t sig n als a r e s p ecif ied wi t h tr = tf = 5 n s (10% t o 9 0 % o f v dd ) a nd t i m e d f r o m a vo l t a g e l e vel o f 1.4 v . table 4. parameter limit at t min , t ma x u n i t d e s c r i p t i o n f sclk 3.4 mhz max mark/space rati o for the sclk input is 40/60 to 60/40. 10 khz min 1.6 v v dd 3 v; minimum f sclk at which sp ecifi c ations ar e guaranteed. 2 0 k h z m i n v dd = 3.3 v; minimum f sclk at whi c h specifi c ation s are guarantee d . 1 5 0 k h z m i n v dd = 3.6 v; minimum f sclk at whi c h specifi c ation s are guarantee d . t con v ert 16 t sclk a d 7 4 6 6 12 t sclk a d 7 4 6 7 10 t sclk a d 7 4 6 8 acquisition tim e acquisition time /power-up time from power-do w n. see the t e rminol ogy section. the ac quisition time is the time required for the part to acquire a full- scale step input value within 1 lsb or a 30 khz ac input value w i thin 0.5 lsb. 7 8 0 n s m a x v dd = 1.6 v. 640 ns max 1.8 v v dd 3.6 v. t qu iet 1 0 n s m i n minimum quiet time required between bus relinq uish and the start of the nex t conver sion. t 1 1 0 n s m i n minimum cs pulse wid t h. t 2 5 5 n s m i n cs to sclk setup ti me. if v dd = 1.6 v and f sclk = 3.4 mhz, t 2 has to be 192 ns minimum in order to meet the maximu m figure for the acquisi t ion time. t 3 5 5 n s m a x delay from cs until sdata is three - state disabled. measured with t h e load circuit in figure 2 and defined a s the time req u ired for the outpu t to cross the v ih or v il voltage. t 4 1 4 0 n s m a x data access time after sclk falling ed ge. measured with the load circuit in figure 2 and def i ned as the time re q u ired for the output to cross the v ih or v il voltage. t 5 0.4 t sclk ns min sclk low pul s e wid t h. t 6 0.4 t sclk ns min sclk high pulse width. t 7 1 0 n s m i n sclk to data valid hold time. me asured with the load circuit in figure 2 and defined as the ti me required for the output to cr oss the v ih or v il voltage. t 8 6 0 n s m a x sclk falling edge to sdata three-state. t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit in figure 2. the m e asured numbe r is then extrapo l ated back to re move the effects of charging or discharging the 5 0 pf capacitor. t h is means that the time, t 8 , quoted in the ti ming characteri stics is th e true bus relinq uish time of the part and is independ ent of the bus lo ading. 7 ns min sclk falling edge to sdata three-state. 200 ai ol 200 ai oh 1.4v to output pin c l 50pf 02643-002 f i gure 2 . l o a d cir c ui t fo r di g i ta l o u tput t i m i ng sp eci f ic ati o ns
ad7466/ad7467/ad 7468 rev. a | page 10 of 28 timing ex amples f i g u re 3 a n d fi g u re 4 show s o me of t h e t i m i n g p a r a me te r s f r om t h e t i m i n g s p e c if ica t ion s s e c t i o n (t a b le 4). timing example 1 a s sho w n in f i g u r e 4, ha vin g f scl k = 3.4 mh z and a t h r o ug h p ut o f 100 ks ps g i ves a c y c l e tim e of t co n v e r t + t 8 + t qu ie t = 10 s. as s u m i n g v dd = 1.8 v , t co n v e r t = t 2 + 15(1/f sc l k ) = 55 n s + 4.41 s = 4.46 s, a nd t 8 = 60 n s max, then t qu iet = 5.48 s, w h ich s a t i sf ies t h e r e q u ir e m en t o f 10 n s fo r t qu ie t . th e p a r t is f u l l y p o w e r e d u p a nd t h e sig n a l is f u l l y acq u ir e d a t p o in t a. this m e a n s t h a t t h e acq u isi t io n/ p o w e r - u p t i m e i s t 2 + 2(1/f sc l k ) = 55 n s + 588 n s = 643 n s , s a tis f yin g t h e max i m u m r e q u ir emen t o f 640 n s f o r th e p o w e r - u p time . timing example 2 the ad7466 can als o o p era t e wi th s l o w er c l o c k f r eq uen c ies. a s sho w n in f i g u r e 4, as s u min g v dd = 1.8 v , f sc l k = 2 mh z, a nd a t h r o ug h p u t o f 50 ks ps g i ves a c y cle t i m e o f t co n v e r t + t 8 + t qu iet = 20 s. w i t h t co n v e r t = t 2 + 15(1/f sc l k ) = 55 n s + 7.5 s = 7.55 s, a nd t 8 = 60 n s max, this lea v es t qu iet t o b e 12.39 s, w h ich s a t i sf ies t h e r e q u ir e m en t o f 10 n s fo r t qu ie t . th e p a r t is f u l l y p o w e r e d u p a nd t h e sig n a l is f u l l y acq u ir e d a t p o in t a, w h ich m e a n s t h e acq u isi t io n/ p o w e r - u p t i me is t 2 + 2(1/f sc l k ) = 55 n s + 1 s = 1.05 s, s a tisf yin g th e maxim u m req u ir em en t o f 640 n s f o r th e p o w e r - u p time . i n this exam p l e and wi t h o t h e r s l o w er clo c k v a l u es, t h e p a r t is f u l l y p o w e r e d u p a nd t h e sig n al a l r e ad y acq u ir e d b e fo r e t h e t h ird scl k fa l l i n g e d ge; h o we ver , th e tra c k - a n d - h o ld d o e s n o t g o i n t o h o ld m o d e un til tha t po i n t . i n th is e x a m p l e , th e pa r t ca n be po w e r e d u p a n d th e si gn al ca n b e f u l l y acq u ir e d a t a p p r o x im a t e l y p o in t b in f i gur e 4. sclk t 2 t 3 t 4 t 7 t 5 t 8 t convert t quiet db11 db10 db2 db1 db0 a 4 leading zeros 13 14 15 16 t 1 three-state three- state sdat a cs 5 4 3 2 1 02643-003 t 6 0 0 0 0 f i g u re 3. a d 74 66 s e ri al int e r f ace ti mi ng d i ag r a m e x a m ple sclk t 2 t convert b a t 8 t quiet 1/throughput automatic power-down track-and-hold in hold track-and-hold in track acquisition time point a: the part if fully powered up with v in fully acquired. 1 2 3 cs 4 5 13 14 15 16 02643-004 f i g u re 4. a d 74 66 s e ri al int e r f ace ti mi ng d i ag r a m e x a m ple
ad7466/ad7467/ad 7468 rev. a | page 11 of 28 absolute maximum ra tings t a = 25c, unles s o t h e r w is e n o ted . t r a n s i en t c u r r en ts o f u p t o 100 ma do n o t ca us e scr l a t c h-u p . table 5. p a r a m e t e r s r a t i n g v dd to gnd ? 0.3 v to +7 v analog input voltage to gnd ? 0.3 v to v dd + 0.3 v digital input voltage to gnd ? 0.3 v to +7 v digital output v o ltage to gnd ? 0.3 v to v dd + 0.3 v input current to any pin ex cept supplies 10 ma operating tem p erature range commercia l (b version) ? 40c to +85c storage temperature range ? 65c to +150c junction tempe r ature 150c sot-23 package ja thermal impedance 229.6c/w jc thermal impedance 91.99c/w msop package ja thermal impedance 205.9c/w jc thermal impedance 43.74c/w lead temperature, soldering vapor phase (60 sec) 215c infared (15 sec) 220c e s d 3 . 5 k v s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7466/ad7467/ad 7468 rev. a | page 12 of 28 pin conf igura t ions and f u ncti on descriptions 6 5 4 1 2 3 v dd gnd v in sdata sclk top view (not to scale) ad7466/ ad7467/ ad7468 02643-005 cs 8 7 6 5 1 2 3 4 nc = no connect s dat a gnd v in nc nc sclk v dd top view (not to scale) a d 74 66 / a d 74 67 / ad7468 02643-006 cs f i gure 5. so t - 23 p i n c o nf igur ation f i gure 6. mso p pin c o nfigur ation ta ble 6. pi n f u nct i on d e s c ri pt i o ns m n e m o n i c f u n c t i o n cs chip select. acti ve low logic input. this in put pr ovides the dual functi on of initiating conversio n s on the device s, and frames the serial data transfer. v dd power supply input. the v dd range for the devices is from 1.6 v to 3.6 v. gnd analog ground. ground reference point for al l c i rcuitry on the d evices. al l ana l o g input signals s h ould be referre d to this gnd voltage. v in analog input. single-ended anal og inp ut channel. the input range is 0 v to v dd . sdata data out. logic output. the conversion re sult from the ad7466/ad7467/ad7468 is provid ed on this output as a serial data stream. the bits are clocked out on the falling ed ge of the sc lk i n put. the data s t ream fr om the ad7466 consist s of four leading zeros followed by the 12 bits of conversion data, prov id ed msb first. th e data stream from the ad7467 consi s ts of four leading zeros followed by the 10 bits of conversion data, provided msb first. the data strea m from the ad7 468 consists of four leading zeros followed by the 8 bits of conversio n data, provided msb first. sclk serial clock. log i c input. sclk provides th e serial clock for accessing data from the pa rts. this cloc k input is also used as t he clock source for the conversi on proces s of the p a rts. n c n o c o n n e c t .
ad7466/ad7467/ad 7468 rev. a | page 13 of 28 terminology i n t e g r a l n o nlin ea ri ty (inl) the maxi m u m de v i a t io n f r o m a st ra ig h t l i n e p a ssin g t h r o ug h th e end p o i n t s of th e ad c tra n s f er f u n c tio n . f o r th e ad7466/ ad7467/ad74 68, th e end p o i n t s o f th e tran sf er f u n c tio n a r e z e r o scale , a po in t 1 l s b b e lo w th e f i r s t code tra n si ti o n , a n d fu ll s c ale , a p o i n t 1 ls b a b o v e t h e l a s t co de t r a n si t i o n . d i f f erenti a l n o n l i n e a r i ty ( d n l ) the dif f er en ce b e tw e e n t h e m e as ur e d an d t h e i d e a l 1 ls b ch ange b e t w e e n an y t w o a d j a c e n t c o d e s i n t h e a d c . off s et err o r the devia t ion o f th e f i rs t co de t r a n si tio n (00 . . . 000) t o (00 . . . 001) f r o m t h e ideal (tha t is, a g nd + 1 ls b). ga in e r r o r the devia t ion o f th e las t c o de tr a n si tion (111 . . . 110) t o (111 . . . 111) f r o m t h e ideal (tha t is, vref ? 1 ls b) a f t e r the o f fse t e r r o r h a s been a d j u s t ed o u t . t r a c k-a nd-h o l d a c q u i s iti o n t i m e the t i m e r e q u ire d fo r t h e p a r t to acq u ir e a f u l l - s cale s t ep in p u t va l u e w i t h in 1 lsb , o r a 30 khz ac i n p u t va l u e w i t h i n 0.5 ls b . th e ad7466/ad74 67/ad7468 en ter trac k mo de on th e cs fa l l ing e d ge, a nd r e t u r n to h o ld m o de o n t h e t h ir d s c lk fall i n g e d g e . t h e pa r t s r e m a i n in h o ld m o d e un til th e f o ll o w i n g cs fal l in g e d g e . s e e f i gur e 4 an d t h e s e r i al i n t e r f ace s e c t ion fo r more d e t a i l s . s i g n a l -t o-n o is e r a ti o (s nr) the m e as ur e d ra t i o o f sig n al t o n o is e a t t h e o u t p u t o f t h e ad c. the sig n al is t h e r m s val u e o f t h e si ne w a v e i n p u t. n o is e is t h e r m s q u an t i za t i o n er r o r wi t h i n t h e n y q u ist b a nd w i d t h (f s /2). the r m s va l u e of th e sine wa v e is half o f i t s p e ak-t o -p e a k val u e divide d b y 2, a nd t h e r m s v a l u e fo r t h e q u a n t i za t i on n o is e is q/12. th e ra tio dep e n d en ts on t h e n u m b er o f q u a n t i za tion lev e l s in t h e d i g i tiz a ti o n p r oce ss; th e m o r e lev e l s, th e sm alle r th e q u an t i za t i on n o is e. f o r a n ide a l n- b i t con v er t e r , t h e s n r is def i n e d as snr = 6.02 n + 1.76 d b th us, f o r a 12-b i t con v er t e r , this is 74 db; f o r a 10-b i t con v er t e r , i t is 62 db; and f o r a n 8-b i t con v er t e r , i t is 50 db . p r ac t i cal l y , t h o u g h , va r i o u s er r o r s o ur ces in t h e ad cs c a us e t h e m e as ur ed s n r t o be l e s s th a n t h e t h eo r e t i cal val u e . th ese e r r o r s o c c u r d u e t o i n teg r al a nd dif f er en t i al n o nl i n e a r i t i es, i n t e r n al ac n o i s e so u r c e s , a n d so o n . si g n a l - t o - n o i s e a n d d i s t or t i on r a t i o ( s i n a d ) t h e me a s u r e d r a t i o of s i g n a l - t o - noi s e a n d d i s t or t i on a t t h e o u t p ut o f t h e a d c. th e sig n al is t h e r m s val u e o f t h e si n e w a v e , a nd n o is e is t h e r m s sum o f a l l n o nf u ndam e n t a l sig n a l s u p to ha lf t h e s a m p l i ng f r e q uen c y (f s /2), in cl u d i n g har m o n ics, b u t excl udin g dc. to t a l u n a d j u s t e d e r r o r ( t u e ) a co m p r e h e n s iv e sp e c if i c a t ion t h a t i n cl udes gain er r o r , li n e a r i t y er r o r , a n d o f fs et er r o r . t o t a l ha r m on i c d i s t or t i on ( t h d ) t h e r a t i o of t h e r m s su m of h a r m on i c s to t h e f u n d a me n t a l . f o r th e ad7466 /ad7467/ad7468, i t is def i n e d as () 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 db + + + + = w h er e v 1 is t h e r m s a m pli t ude o f t h e f u ndam e n t al, and v 2 , v 3 , v 4 , v 5 , and v 6 ar e t h e r m s am pl i t u d es o f t h e s e c o n d t h r o u g h six t h ha r m o n ics . p e a k h a rmo n i c o r s p uri o us n o is e (s fd r) the ra t i o o f t h e r m s val u e o f t h e n e xt la rg es t co m p on e n t i n t h e a d c o u t p u t s p ectr um (u p t o f s /2 a nd excl ud ing dc) to t h e r m s val u e o f t h e f u ndam e n t a l . t y p i c a l l y , t h e val u e o f t h is s p e c if i- ca t i on is de t e r m in e d b y t h e l a rg es t ha r m onic i n t h e s p e c t r um, b u t fo r ad cs w h er e t h e ha r m onics a r e b u r i e d i n t h e n o is e f l o o r , i t is a n o is e p e a k . intermodulati o n distortion (imd) w i t h i n put s c o n s i s t i ng of s i ne w a ve s a t t w o f r e q u e nc i e s , f a a nd fb , an y ac t i ve de vic e wi t h no n l i n e a r i t i es cr e a tes di sto r t i o n p r o d uc ts a t s u m a nd dif f er en ce f r e q uen c ies o f mfa nf b , w h ere m, n = 0, 1, 2, 3, a nd s o o n . i n te r m o d u l a t io n disto r t i o n ter m s a r e th ose f o r whic h n e i t h e r m n o r n a r e eq ual to zer o . f o r exa m ple , t h e s e co nd-o r d er t e r m s i n cl ude (fa + fb) a n d (f a ? fb), w h i l e t h e t h ird- o r d er t e r m s i n clude (2fa + fb), ( 2 fa C fb), (fa + 2fb), a nd ( f a ? 2fb). the ad7466 /ad7467/ad7468 a r e t e s t e d usin g th e ccif s t anda r d w h er e tw o i n p u t f r e q u e n c ies a r e us e d . i n t h i s cas e , th e seco n d - o r d er t e rm s a r e us uall y d i s t a n ced i n f r eq ue n c y f r o m t h e o r ig inal si ne wa v e s, w h i l e t h e t h ir d-o r d er t e r m s a r e us ual l y a t a f r eq uen c y c l ose t o th e in p u t f r eq ue n c i e s . a s a r e s u l t , t h e s e co nd- and t h i r d-o r d er ter m s a r e sp e c if ie d s e p a r a tely . t h e ca lc u l a t io n o f t h e in t e r m o d u l a t io n di st o r t i o n is as p e r t h e thd s p e c if i c a t i o n, w h er e i t is t h e ra t i o o f t h e r m s s u m o f t h e indivi d u al di s t or t i o n p r o d uc ts to t h e r m s am pli t ude o f t h e s u m o f t h e f u ndam e n t als, exp r es s e d in dbs.
ad7466/ad7467/ad 7468 rev. a | page 14 of 28 typical perf orm ance cha r acte ristics d y namic performance curves fi g u r e 7 , fi g u r e 8 , a n d fi g u r e 9 s h ow t y pi c a l f f t p l o t s f o r t h e ad7466, ad74 67, a nd ad746 8, r e s p ec ti ve l y , a t a 100 ks ps s a m p le ra te an d a 30 k h z i n p u t to n e . f i gur e 10 sh o w s t h e s i g n a l - t o - no is e a nd disto r t i o n r a t i o p e r f o r - ma n c e vs. i n p u t f r e q uen c y fo r v a r i o u s s u p p ly v o l t a g es w h i l e s a m p ling a t 100 ks ps wi t h a s c lk f r eq uen c y o f 3.4 mh z f o r the ad7466. f i gur e 11 sh o w s th e sign al-t o-n o ise ra tio (s nr) per f o r m a n c e vs. in p u t f r e q uen c y fo r va r i o u s s u p p ly v o l t a g es w h i l e s a m p li n g a t 100 ks p s wi t h a scl k f r eq uen c y o f 3.4 mh z f o r th e ad746 6. f i g u r e 12 s h o w s th e t o tal h a r m o n i c d i s t o r ti o n vs . a n alog i n p u t sig n al f r e q uen c y fo r va r i o u s s u p p l y v o l t a g es w h ile s a m p l i n g a t 100 ks ps wi t h a sclk f r eq uen c y o f 3.4 mh z f o r th e ad7466. f i g u r e 13 s h o w s th e t o tal h a r m o n i c d i s t o r ti o n vs . a n alog i n p u t f r e q uen c y fo r dif f er en t s o ur ce i m p e dan c es w i t h a s u p p ly v o l t ag e o f 2.7 v , a scl k f r eq uen c y o f 3.4 mh z, and s a m p ling a t a ra te o f 100 ks ps f o r th e ad7466 (s e e the analog i n p u t s e c t ion). dc a c cur a c y curves f i gur e 14 an d f i gur e 15 sh o w typ i cal inl an d d n l p e r f o r - ma n c e f o r th e ad7466. po wer requirement s curves f i gur e 16 sh o w s t h e s u p p ly c u r r en t vs. s u p p ly v o l t a g e fo r t h e ad7466 a t ?40 c, +25c, an d + 85c, wi t h scl k f r eq uen c y o f 3.4 mh z and a s a m p ling ra t e o f 100 ks ps. f i gur e 17 sh o w s t h e maxi m u m c u r r en t vs. s u p p ly v o l t a g e fo r t h e ad7466 wi t h dif f er en t sclk f r eq uen c ies. f i gur e 18 sh o w s t h e s h ut do w n c u r r en t vs. s u p p ly v o l t a g e . fi g u r e 1 9 s h ow s t h e p o w e r c o n s u m pt i o n v s . t h r o u g hput r a t e f o r th e ad7466 wi t h a scl k o f 3.4 mh z and dif f er en t s u p p l y vol t a g es. s e e t h e p o w e r c o nsu m p t ion s e c t ion fo r m o r e det a i l s . 02643-007 25 5 snr ( d b) ?15 ?35 ?55 ?75 ?95 ?115 0 5 10 15 20 25 30 35 40 45 50 frequency (khz) 8192 point fft v dd = 1.8v f sample = 100ksps f in = 30khz sinad = 70.82db thd = ? 84.18db sfdr = ? 85.48db f i g u re 7. a d 74 66 d y nam i c p e r f or ma n c e at 1 00 k s ps 15 ?5 s nr (db) ?2 5 ?4 5 ?6 5 ?8 5 ?105 0 5 10 15 20 25 30 35 40 45 50 frequency (khz) 8192 point fft v dd = 1.8v f sample = 100ksps f in = 30khz sinad = 61.51db thd = ? 80.61db sfdr = ? 82.10db 02643-008 f i g u re 8. a d 74 67 d y nam i c p e r f or ma n c e at 1 00 k s ps
ad7466/ad7467/ad 7468 rev. a | page 15 of 28 5 ?5 snr ( d b) ?4 5 ?3 5 ?2 5 ?1 5 ?5 5 ?6 5 ?7 5 ?8 5 ?9 5 0 5 10 15 20 25 30 35 40 45 50 frequency (khz) 8192 point fft v dd = 1.8v f sample = 100ksps f in = 30khz sinad = 49.83db thd = ? 79.37db sfdr = ? 70.46db 02643-009 f i g u re 9. a d 74 68 d y nam i c p e r f or ma n c e at 1 00 k s ps ?65 sinad ( d b) ?72 ?71 ?70 ?69 ?68 ?67 ?66 ?73 10 100 input frequency (khz) v dd = 3.6v v dd = 3v v dd = 2.7v temp = 25 c v dd = 1.8v v dd = 1.6v v dd = 2.2v 02643-010 f i g u re 10. a d 7 4 6 6 sina d v s . a n al og i n put f r equenc y at 10 0 k s ps f o r v a ri ous su p p ly v o lt ag es ?68.0 s nr (db) ?72.5 ?72.0 ?71.5 ?71.0 ?70.5 ?70.0 ?69.0 ?68.5 ?69.5 ?73.0 10 100 input frequency (khz) v dd = 3.6v v dd = 3v v dd = 2.7v temp = 25 c v dd = 1.8v v dd = 1.6v v dd = 2.2v 02643-011 f i gur e 1 1 . ad74 66 snr vs . a n a l o g inp u t f r equ e nc y a t 100 ksps fo r v a ri ous su p p ly v o lt ag es ?65 thd (db) ?83 ?81 ?79 ?77 ?75 ?73 ?69 ?67 ?71 ?85 10 100 input frequency (khz) v dd = 3.6v v dd = 3v v dd = 2.7v temp = 25 c v dd = 1.8v v dd = 1.6v v dd = 2.2v 02643-012 f i gur e 1 2 . ad74 66 th d vs . a n al o g input f r e q ue nc y a t 100 ksps fo r v a ri ous su p p ly v o lt ag es ?76 thd (db) ?83 ?82 ?81 ?80 ?79 ?78 ?77 ?84 10 100 input frequency (khz) r in = 510 ? r in = 10 ? temp = 25 c v dd = 2.7v r in = 100 ? r in = 0 ? r in = 1k ? 02643-013 f i gur e 1 3 . ad74 66 th d vs . a n al o g input f r e q ue nc y for v a ri ous s o u r ce i m pedances 1.0 inl erro r ( l sb) ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 ? 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 code v dd = 1.8v temp = 25 c f in = 50hz f sample = 100ksps 02643-014 f i gur e 1 4 . ad74 66 inl p e r f o r m a nc e
ad7466/ad7467/ad 7468 rev. a | page 16 of 28 1.0 dnl e rror (ls b ) ? 0.6 ? 0.4 ? 0.2 0 0.4 0.2 0.6 0.8 ? 0.8 0 512 1024 1536 2048 2560 3072 3584 4096 code v dd = 1.8v temp = 25 c f in = 50hz f sample = 100ksps 02643-015 f i gur e 1 5 . ad74 66 dnl p e r f o r ma nc e 290 s u p p l y curre nt ( a) 90 115 140 165 190 215 240 265 65 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 supply voltage (v) f sample = 100ksps temp = +85 c temp = ? 40 c temp = +25 c 02643-016 f i g u re 16. sup p l y current v s . sup p ly v o lt ag e , sclk 3. 4 m h z 560 max i mum curre nt ( a) 140 200 260 320 380 440 500 80 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 supply voltage (v) temp = 25 c f sclk = 3.4mhz, f sample = 200ksps f sclk = 1.2mhz, f sample = 50ksps f sclk = 2.4mhz, f sample = 140ksps 02643-017 f i gure 17. maxi mu m cu rrent v s . sup p l y v o ltag e fo r d i ffer e nt sclk f r equ e nci e s 2.5 shut do wn current ( n a) 0.5 1.0 1.5 2.0 0 1.5 2.0 2.5 3.0 3.5 4.0 supply voltage (v) temp = +25 c temp = +85 c temp = ? 40 c 02643-018 f i gure 18. sh u t do w n c u r r ent vs. sup p l y v o ltag e 1.4 power ( m w) 0.2 0.4 0.6 1.0 1.2 0.8 0 0 5 0 100 150 200 250 throughput (ksps) temp = 25 c v dd = 3.0v v dd = 2.7v v dd = 2.2v v dd = 1.8v 02643-019 f i gure 19. p o wer consumpt ion vs. throu g hput rate , scl k 3.4 mhz
ad7466/ad7467/ad 7468 rev. a | page 17 of 28 circuit i n forma t ion the ad7466 /ad7467/ad7468 a r e fas t , micr o p o w er , 12-b i t, 10-b i t, and 8-b i t ad cs, r e s p e c t i v e ly . the p a r t s ca n b e o p era t e d f rom a 1 . 6 v to 3 . 6 v supply . whe n op e r ate d f rom an y s u pply v o l t a g e wi thin t h is ra n g e , t h e ad7466/ad7467/ad7468 a r e c a p a bl e of t h rou g h put r a te s of 2 0 0 k s p s w h e n pro v i d e d w i t h a 3.4 mh z c l o c k. the ad7466 /ad7467/ad7468 p r o v ide t h e us er wi t h an o n - chi p t r ack - an d - h o ld , an ad c, and a s e r i a l in ter f ace h o us e d in a tin y 6-l e ad s o t - 23 o r a n 8-lead mso p p a c k a g e, which o f f e r th e us er co n s idera b le s p ace-s a vin g ad van t a g es o v er al t e r n a t i v e s o l u t i o n s. the s e r i al clo c k i n p u t acces s es da t a f r o m t h e p a r t b u t als o p r o v ides t h e clo c k s o ur ce fo r t h e s u cce s s i v e a p p r o x ima t ion ad c. the a n al og in p u t ra n g e is 0 v t o v dd . an ext e r n al r e fer e n c e is n o t r e q u ir e d fo r t h e ad c, and t h er e is n o o n -chi p r e f e r e n c e . th e ref e r e n c e f o r th e ad7466/ad74 67/ad7468 is der i ve d f r o m t h e p o w e r sup p ly , t h us g i v i n g t h e wi dest p o ssi b l e dy n a m i c i n put r a nge. the ad7466 /ad7467/ad7468 als o f e a t ur e a n a u t o ma tic p o w e r - do wn mo de to a l lo w p o w e r s a v i n g s b e t w e e n con v er - s i o n s . th e p o w e r - d o w n f e a t ur e is i m p l em en t e d a c r o s s th e st anda r d s e r i a l i n ter f ac e, as des c r i b e d i n t h e n o r m a l m o de secti o n . c o nverter oper a t ion the ad7466 /ad7467/ad7468 a r e s u cces s i v e a p p r o x ima t ion a n a l o g -to - d i g i t a l co n v er ters b a s e d a r o u nd a ch arge r e dist r i b u - tio n d a c. f i gu r e 20 a n d f i gure 21 sh o w sim p l i f i ed s c h e ma tics o f t h e a d c. f i g u r e 20 s h o w s t h e ad cs d u r i n g t h e acq u isi t io n p h as e . sw 2 is c l os ed an d s w 1 is in p o si tio n a, th e co m p a r a t o r i s h e l d i n a b a l a nc e d c o nd i t i o n , an d t h e s a m p l i ng c a p a c i tor acq u ir es t h e sig n al o n v in . sw2 sampling capacitor acquisition phase comparator charge redistribution dac control logic sw1 a b agnd v in v dd /2 02643-020 f i g u re 20. a d c ac quis it i o n p h as e w h en t h e ad c s t a r ts a con v ersio n , as sh o w n i n f i gur e 21, sw2 o p e n s an d sw1 m o v e s t o p o si t i o n b , ca usin g t h e com- p a ra t o r t o becom e u n balanced . the co n t r o l log i c a nd t h e cha r ge r e dist r i b u t i o n d a c a r e us e d to ad d an d sub t r a c t f i xe d amou n t s of ch ar ge f rom t h e s a m p l i ng c a p a c i tor t o br i n g t h e co m p a r a t o r back in t o a ba lan c e d co ndi t io n. w h en t h e com- p a ra t o r is r e b a lan c e d , t h e con v e r sio n is co m p lete . th e con t r o l log i c g e n e ra t e s t h e ad c o u t p ut co de . f i gur e 22 s h o w s t h e ad c tra n s f e r fun c ti o n . sampling capacitor comparator v in sw2 conversion phase sw1 a b agnd v dd /2 charge redistribution dac control logic 02643-021 f i g u re 21. a d c co nvers i on p h as e adc tr ans f er func tion the o u t p u t co din g o f th e ad74 66/ad7467 /ad7468 is s t ra ig h t b i na r y . th e desig n e d co de t r a n si t i o n s o c c u r a t succes s i v e in teg er ls b va l u es, t h a t is, 1 ls b , 2 ls b , and s o o n . th e ls b size fo r t h e de v i ces is as fol l o w s: v dd /4096 f o r the ad7466 v dd /1024 f o r the ad7467 v dd /256 f o r th e ad7468 the ide a l t r a n sfer cha r ac t e r i s t ic s fo r t h e de vi ces a r e s h o w n i n f i gur e 22. 111...111 111...110 111...000 011...111 +v dd ? 1lsb 0v 1lsb analog input adc co de 1lsb = v dd /4096 (ad7466) 1lsb = v dd /1024 (ad7467) 1lsb = v dd /256 (ad7468) 000...010 000...001 000...000 02643-022 f i gur e 2 2 . ad74 66 /ad7 46 7/ ad746 8 t r a n sfe r cha r a c te ri sti c s
ad7466/ad7467/ad 7468 rev. a | page 18 of 28 t y p i c a l c o nnec t i o n di a g r a m f i gur e 23 sh o w s a typ i cal co nn e c ti o n dia g ra m fo r th e de vi ces. v ref is t a k e n i n ter na l l y f r o m v dd a nd t h er efo r e v dd sh o u ld be w e l l de co u p le d . this p r o v ides an a n alog i n p u t r a n g e o f 0 v to v dd . ad7466 sclk sdata v in gnd 0v t o v dd i n pu t v dd 0.1 f 10 f c/ p 0.1 f 1 f tant ref192 240 a 680nf 2.5v 5v supply ser i a l i n t e r f ace cs 02643-023 f i g u re 23. r e f19 2 as p o wer sup p l y t o a d 74 66 the con v ersio n r e s u l t co n s is ts of fo ur le adin g ze r o s f o l l o w e d b y th e m s b o f the 12-b i t, 10-b i t, or 8-b i t r e s u l t f r o m t h e ad7466, ad7467, o r ad7468, r e s p ec ti vel y . s e e t h e s e r i al i n t e r f ace s e c t io n. alt e r n a t i v e l y , b e ca us e t h e su p p ly c u r r en t r e q u ir e d b y th e ad7466 /ad7467/ad7468 is s o lo w , a p r ecisio n r e f e r e n c e ca n be us e d as t h e su p p l y s o ur ce t o the devices. the ref19x s e r i es de vice s a r e pr e c isio n micr o p o w er , lo w dr o p - o u t v o l t a g e r e f e r e n c es. f o r t h e ad7466/ad7467/ad7468 v o l t a g e ra n g e op era t ion, t h e ref193, ref192, a nd ref191 can b e us e d t o s u p p ly t h e r e q u ir e d vol t a g e t o t h e a d c, de li v e r i n g 3 v , 2.5 v , and 2 . 048 v , r e s p ec tiv e l y (s ee f i gur e 23). this co nf ig - ura t io n is esp e c i a l ly us ef u l if t h e p o w e r sup p ly is q u i te n o isy o r if t h e sys t e m s u p p ly v o l t a g es a r e a t a val u e ot he r t h a n 3 v o r 2.5 v (f o r exa m p l e , 5 v). th e ref19x o u t p u t s a s t ead y v o l t a g e t o th e ad7466 /ad7467/ad74 68. i f the lo w dr o p o u t ref192 is us ed w h en t h e ad7466 is con v er tin g a t a ra t e o f 100 ks ps, t h e ref192 n eeds to s u p p l y a maxim u m o f 240 a t o th e ad7466. the lo ad r e gu l a tio n o f t h e ref 192 is typ i cal l y 10 p p m /ma (ref192, v s = 5 v ) , w h i c h re su lt s i n a n e r ror of 2 . 4 ppm ( 6 v ) f o r th e 240 a dra w n f r o m i t . this co r r es p o nds t o a 0.0098 l s b er r o r f o r th e ad7466 wi t h v dd = 2.5 v f r o m the ref192. f o r a p plic a t io n s w h er e p o w e r co n s um p t ion is i m p o r t a n t, t h e a u to m a t i c p o w e r - do wn mo de of t h e ad c and t h e sle e p m o d e of t h e r e f 1 9 x re f e re nc e s h ou l d b e u s e d to i m pro v e p o we r p e r f o r ma n c e . s e e t h e n o r m al m o de s e c t io n. t a b l e 7 p r o v ide s s o me typ i cal p e r f o r ma n c e da t a w i t h va r i o u s re f e re nc e s u s e d a s a v dd so u r c e u n de r th e sa m e se t u p co ndi tion s. th e ad r318, f o r in s t an ce , is a 1.8 v ban d ga p vo lt age re f e re nc e. i t s t i n y f o otpr i n t , l o w p o we r c o nsu m pt i o n , a nd i t s addi t i o n al s h u t do wn c a p a b i li ty make t h e ad r318 ide a l f o r ba t t e r y- po w e r e d a p p l ica t i o n s . table 7. ad 74 66 perfor manc e for voltage r e fere nce ic reference tie d to v dd ad7466 s n r p e rformance (db) adr318 @ 1.8 v 70.73 adr370 @ 2.048 v 70.72 adr421 @ 2.5 v 71.13 adr423 @ 3 v 71.44 anal og input an eq uivalen t c i r c ui t o f t h e ad7466/ad7467 /ad7468 a n alog in p u t s t r u c t ur e is s h o w n i n f i g u r e 24. the t w o dio d es , d1 an d d 2 , p r o v id e es d p r o t ecti o n f o r th e a n alog i n p u t s . ca r e m u s t be t a k e n t o en s u r e t h a t t h e analog i n p u t sig n al n e ver exce e d s t h e s u p p l y ra ils b y m o r e than 300 mv . this c a us es th es e dio d es t o b e com e fo r w a r d b i as e d and to st a r t co nd uc t i ng c u r r en t i n to t h e s u bs t r a t e . c a p a ci t o r c1 i n f i gu r e 24 is typ i cal l y a b o u t 4 pf , an d ca n p r ima r i l y b e a t t r ib u t e d t o pin c a p a ci t a n c e . resist o r r1 is a l u m p e d co m p o n en t made u p o f th e o n r e sis t ance o f a swi t ch. this r e sis t o r is t y p i cal l y a b o u t 2 00 ?. c a p a ci t o r c2 is t h e ad c sa m p l i n g c a pa ci t o r w i th a t y p i cal c a pa ci ta n c e o f 2 0 p f . c1 4pf v in v dd d2 conversion phase?switch open track phase?switch closed d1 r1 c2 20pf 02643-024 f i g u re 24. equiv a le nt a n al og input c i rcuit f o r a c a p pl i c a t i o ns , re mov i ng h i g h f r e q u e nc y c o m p o n e n t s f r o m t h e a n alog in p u t sig n al b y usin g a b a n d -p as s f i l t er o n t h e r e le van t a n a l og in p u t p i n is r e c o mm e nde d. i n a p plic a t io n s w h er e ha r m oni c dis t o r t i o n and sig n al-t o- n o is e ra t i o a r e cr i t ic al, t h e analog in p u t sh o u ld b e dr i v en f r o m a lo w i m p e dan c e s o ur ce . l a rge s o ur ce im p e dan c e s sig n if ican t l y a f fe c t t h e ac p e r f o r ma n c e o f t h e ad c. this mig h t n e ces s i t a te t h e us e o f a n in p u t b u f f er a m plif ier . the ch o i ce o f t h e o p am p is a f u n c t i o n of t h e p a r t ic u l a r a p plica t io n. t a b l e 8 p r o v ide s typ i c a l p e r f o r ma n c e da t a fo r va r i o u s o p a m ps us e d as t h e i n p u t b u f f er un der c o n s t a n t s e t u p c o n d i t io ns. table 8. ad74 66 perfor manc e for i nput buffers op a m p in the input buffer ad7466 s n r p e rformance (db) 30 kh z input, v dd = 1.8 v a d 8 5 1 0 7 0 . 7 5 a d 8 6 1 0 7 1 . 4 5 a d 7 9 7 7 1 . 4 2
ad7466/ad7467/ad 7468 rev. a | page 19 of 28 w h en n o am pli f ier is us e d t o dr i v e t h e a n alog i n p u t , t h e s o ur ce im p e dan c e sh ou ld b e l i mi t e d to lo w val u es. the maxi m u m s o ur ce i m p e dance dep e n d s o n t h e am o u n t o f tot a l ha r m onic d i s t o r ti o n (t hd ) th a t ca n be t o le ra t e d . t h e th d in cr ea se s a s t h e s o ur ce i m p e dan c e i n cr e a s e s a nd p e r f o r ma n c e deg r ades . f i g u re 1 3 s h o w s a g r a p h of t h e t o t a l h a r m o n i c d i stor t i on v s . a n alog in p u t sig n al f r e q uen c y f o r dif f er en t s o u r ce im p e dan c es when usin g a s u p p l y v o l t a g e o f 2.7 v a nd s a m p l i n g a t a ra t e o f 100 ks ps. digit a l in p u t s the dig i t a l in p u ts a p p l ie d t o t h e ad7466/ad74 67/ad7468 a r e n o t l i mi t e d b y t h e max i m u m ra t i n g s t h a t li mi t t h e a n alog in p u ts. i n ste a d , t h e dig i t a l in p u t s a p plie d can go to 7 v a nd a r e n o t r e s t ri c t ed b y th e v dd + 0.3 v limi t as o n t h e a n alog in pu t. f o r exa m p l e , if th e ad7466 /ad7467/ad7468 a r e o p era t e d wi th a v dd o f 3 v , 5 v log i c lev e ls cou l d be us e d o n t h e dig i tal in p u ts . h o w e v e r , t h e da ta o u t p u t on s d a t a s t il l has 3 v log i c lev e ls wh e n v dd = 3 v . a n ot he r a d v a n t age of s c l k a n d cs not be in g r e s t ri ct e d b y t h e v dd + 0.3 v limi t is tha t p o w e r s u p p l y s e q u e n ci n g is s u es a r e a v o i de d . i f cs o r sclk is a p p l ied bef o r e v dd , t h er e is n o r i s k o f la t c h-u p as t h er e w o u l d b e on t h e a n alo g in p u ts if a s i g n a l g r e a t e r t h a n 0. 3 v is a p plie d pr io r t o v dd . normal m o de the ad7466 /ad7467/ad7468 a u t o ma tic a l l y en t e r p o w e r - d o w n a t t h e e n d of e a ch c o n v e r s i on . t h i s mo d e of op e r a t i o n i s desig n e d to p r o v id e f l ex i b le p o w e r ma na ge m e n t o p t i on s an d to o p timize t h e p o w e r d i s s i p a t io n/th r o u gh p u t ra t e ra tio f o r lo w po w e r a p p l ica t io n r e q u i r em en ts . f i g u r e 25 s h o w s th e g e n e ral o p era t ion o f the ad7466/ad74 67/ad7468. on th e cs fal l in g e d ge, t h e p a r t b e g i n s to p o w e r u p a nd t h e t r ack-and- h o ld , w h ich was in h o ld w h i l e t h e p a r t was i n p o w e r - do wn, go es in t o t r ack m o de. the co n v ersion is a l s o ini t i a t e d a t t h is p o i n t. o n th e th i r d sc lk falli n g e d g e a f t e r th e cs fal l in g e d g e , t h e t r ac k- a nd h o l d r e t u r n s to h o ld m o de. f o r th e ad7466 , 16 s e r i al c l o c k c y c l es a r e r e q u ir ed t o co m p let e t h e co n v ersion a nd acces s t h e c o m p let e con v ersio n r e s u l t . the ad7466 a u t o ma tic a l l y en t e rs p o w e r - do wn m o de o n t h e 16 th s c l k f a lli n g edg e . f o r th e ad7467 , 14 s e r i al c l o c k c y c l es a r e r e q u ir ed t o co m p let e t h e co n v ersion a nd acces s t h e c o m p let e con v ersio n r e s u l t . the ad7467 a u t o ma tic a l l y en t e rs p o w e r - do wn m o de o n t h e 14 th s c l k f a lli n g edg e . f o r th e ad7468 , 12 s e r i al c l o c k c y c l es a r e r e q u ir ed t o co m p let e t h e co n v ersion a nd acces s t h e c o m p let e con v ersio n r e s u l t . the ad7468 a u t o ma tic a l l y en t e rs p o w e r - do wn m o de o n t h e 12 th s c l k f a lli n g edg e . the ad7466 als o en t e rs p o wer - do wn m o de if cs i s brou g h t hig h an y t i m e b e fo r e t h e 16t h s c lk fal l i n g e d ge . th e con v er - sio n t h a t was ini t ia t e d b y t h e cs fa l l in g e d ge ter m i n a t es and s d a t a g o es b a ck i n t o t h r e e- s t a t e . this als o a pplies fo r t h e ad7467 an d ad7468; if cs i s brou g h t h i g h b e f ore t h e c o n v e r - sio n is co m p lete (th e 14t h scl k fal l in g e d g e f o r th e ad7467, a nd t h e 12t h sclk fal l in g e d g e f o r th e ad7468 ), th e p a r t en t e rs p o w e r - do wn, t h e co n v ersion t e r m ina t es, an d sd a t a g o es b a ck i n to t h re e - st a t e. al t h o u g h cs ca n idle hig h o r lo w betw een co n v ersio n s, t o s a v e po w e r , b r in gi n g cs hig h on ce t h e co n v ersio n is com p let e is r e co mm e nde d . w h en s u p p lies a r e f i rs t a p plie d t o t h e de vi ces, a d u mm y con v er - s i on s h ou l d b e p e r f or me d to e n su re t h at t h e p a r t s are i n p o w e r - do wn m o de, t h e t r ack-and- h o l d is i n h o l d m o de, an d s d a t a is i n th r ee- s t a t e . o n ce a d a ta tra n s f e r i s co m p le t e (s d a t a h a s r e t u r n ed t o th r ee- s t a te), an o t h e r c o n v ersio n ca n b e ini t i a t e d a f t e r t h e q u ie t t i m e , t qu iet , h a s e l a p se d , b y b r i n gi n g cs l o w ag ai n . the part begins to power up ad7468 enters power-down ad7467 enters power-down ad7466 enters power-down valid data sclk s dat a 12 3 1 2 1 4 1 6 the part is powered up and v in fully acquired cs 02643-025 f i g u re 25. no r m a l m o de o p er at io n
ad7466/ad7467/ad 7468 rev. a | page 20 of 28 power c o n s umpti o n the ad7466 /ad7467/ad7468 a u t o ma tic a l l y en t e r p o w e r - do wn m o de a t t h e e nd o f e a ch c o n v ersio n o r if cs i s brou g h t h i g h b e f ore t h e c o n v e r s i on i s f i n i s h e d . w h en t h e ad7 466/ad7467 /ad7468 a r e in p o w e r - do wn m o de , al l t h e a n alog ci r c ui t r y is p o w e r e d do w n an d t h e c u r r en t co n- su m p t i on is t y p i c a l l y 8 na. t o achie v e t h e l o w e s t p o w e r dissi p a t i o n , t h er e ar e s o m e co n s idera t io n s t h e us er sh o u l d k e ep in mi nd . the con v ersio n t i m e is de t e r m i n e d b y t h e s e r i a l clo c k f r eq ue n c y ; th e fa s t e r t h e sc lk f r eq ue n c y , th e s h o r t e r th e co n v ersio n t i m e . this i m plies t h a t as t h e f r e q ue n c y in cr e a s e s, t h e p a r t di s s i p a tes p o w e r fo r a s h o r t e r p e r i o d o f t i me w h e n t h e co n v er sio n is ta kin g p l ace , and i t r e ma in s in p o w e r - do wn m o de fo r a lo n g er p e r c en t a g e o f t h e c y cle t i m e o r t h ro ug h p u t r a t e . f i gur e 27 sh o w s tw o ad7466s r u nnin g wi t h two dif f er en t sclk f r e q ue n c ies, sclk a a n d sclk b , wi t h s c lk a ha vin g th e h i g h e r sc lk f r eq ue n c y . f o r th e sa m e th r o ugh p u t ra t e , t h e ad7466 usin g s c lk a has a sho r t e r co n v ersio n tim e tha n t h e ad7466 usin g s c lk b , and i t r e ma in s in p o w e r - do wn m o de lo n g er . the c u r r en t co ns um p t ion i n p o w e r - do w n m o de is ver y lo w ; t h us, t h e a v era g e p o wer co n s um p t io n is g r e a t l y r e d u ce d . this can be s een in f i gur e 26, which sh o w s t h e s u p p l y c u r r en t v s . s c l k f r e q u e nc y f o r v a r i ou s supply vo lt age s a t a t h rou g h put ra t e o f 100 ks ps . f o r a f i xed thr o u g h p u t r a t e , t h e s u p p l y c u r r en t (a v e ra g e c u r r en t) dr o p s as t h e s c lk f r e q uen c y in cr e a s e s beca u s e th e pa r t i s i n po w e r - d o wn m o d e m o s t o f th e tim e . i t ca n als o b e s e en t h a t , fo r a lo w e r s u p p ly v o l t a g e, t h e s u p p ly c u r r e n t d rop s a c c ord i n g l y . 390 s u p p l y curre nt ( a) 360 330 300 270 240 210 180 150 120 90 60 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 sclk frequency (mhz) f sample = 100ksps temp = 25 c v dd = 3.6v v dd = 3.0v v dd = 2.2v v dd = 2.7v v dd = 1.8v v dd = 1.6v 02643-026 f i gure 26. sup p l y current v s . sclk f r e q uenc y for a f i x e d throughput rate and d i f f e r e nt sup p l y v o lt ag es sclk b sclk a 11 6 11 6 conversion time a conversion time b 1/throughput cs 02643-027 f i g u re 27. co nvers i on ti me co mpa r is on f o r d i f f e r e nt sc lk f r equ e nc ies and a f i x e d t h roug hp u t rate power down time b 1/throughput b 1/throughput a power down time a conversion time a conversion time b cs a s cl k cs b 11 6 02643-028 f i g u r e 28. co nve r s i on t i me v s . p o we r- d o w n ti me f o r a f i x e d sclk f r eq uenc y and d i fferent th rou g hput rates
ad7466/ad7467/ad 7468 rev. a | page 21 of 28 f i gur e 19 sh o w s po w e r co n s um p t io n vs. t h r o u g h p u t ra t e f o r a 3.4 mh z s c lk f r eq uen c y . i n t h is cas e , t h e co n v er sio n tim e is t h e s a m e fo r al l cas e s b e c a us e t h e sclk f r e q ue nc y is a f i xe d p a r a me te r . l o w t h rou g h put r a te s l e ad to l o we r c u r r e n t c o n- s u m p t i o n s , w i th a h i g h e r pe r c en ta g e o f t h e t i m e i n p o w e r - do wn m o de . f i gur e 28 s h o w s tw o ad7466s r u nnin g wi t h t h e s a m e scl k f r e q uen c y , b u t a t dif f er en t t h r o u g h p u t r a t e s. the a t h r o u g h pu t ra t e is hig h er t h a n t h e b t h r o u g h p u t r a t e . the s l o w er t h e t h r o u g h p u t r a t e , t h e lo n g er t h e p e r i o d o f t i m e t h e p a r t is i n p o w e r - do w n m o de , a nd t h e a v er ag e p o w e r co n s um p t io n dro p s acco r d in g l y . f i gur e 29 sh o w s t h e p o w e r vs. t h r o u g h p u t r a t e fo r dif f er en t s u p p l y v o l t a g e s a n d sc lk f r eq ue n c i e s. f o r th i s p l o t , all t h e el e m e n t s re g a rd i n g p o we r c o ns u m pt i o n t h at w e re e x pl ai ne d p r ev i o us l y (t h e i n f l ue n c e o f th e sc l k f r eq uen c y , th e i n f l uen c e o f t h e t h r o u g h pu t ra t e , and t h e inf l uen c e o f t h e s u p p ly v o l t a g e) a r e t a k e n in t o co n s idera t ion. 1.4 p o we r (mw) 0.2 0.4 0.6 0.8 1.0 1.2 0 0 5 0 100 150 200 250 throughput (ksps) temp = 25 c v dd = 3.0v, sclk = 2.4mhz v dd = 3.0v, sclk = 3.4mhz v dd = 1.8v, sclk = 2.4mhz v dd = 1.8v, sclk = 3.4mhz 02643-029 f i gure 29. p o wer v s . thro ughput r a te f o r d i ffer e nt sclk and sup p ly v o ltag es the fol l o w in g e x a m ples sh o w c a lc u l a t io n s fo r t h e info r m a t io n in t h is s e c t ion. power consumption example 1 this exa m ple sho w s t h a t fo r a f i xe d t h r o u g h p u t ra t e , as t h e sclk f r e q ue n c y in cr e a s e s, t h e a v era g e p o w e r c o n s um pt io n dr o p s. f r o m f i g u r e 27, ha vin g s c lk a = 3.4 m h z, s c lk b = 1.2 mh z, and a thr o u g h p u t ra t e o f 50 ks ps, whic h g i v e s a c y c l e tim e o f 20 s , t h e f o llo w i n g val u e s ca n be ob ta in ed : co n v er s i o n t i m e a = 16 (1/ sc l k a ) = 4.7 s (23.5% o f the c y c l e tim e ) po w e r- d o w n t i m e a = (1/ th r o u g h p u t ) ? co n v ers i o n t i m e a = 20 s ? 4.7 s = 15.3 s (76.5% o f the c y c l e tim e ) co n v er s i o n t i m e b = 16 (1/ sc l k b ) = 13 s (65% o f t h e c y cle t i m e ) po w e r- d o w n t i m e b = (1/ th r o u g h p u t ) ? co n v ers i o n t i m e b = 20 s ? 13 s = 7 s (35% o f th e c y c l e tim e ) the a v er a g e p o w e r co n s um p t ion i n cl ude s t h e p o w e r dis s i p a t e d w h en t h e p a r t is co n v er t i n g and t h e p o w e r di s s i p a t e d w h en t h e p a r t is in p o w e r - do w n m o de. th e a v era g e p o wer dis s i p a t e d d u r i n g con v ersi o n is calc u l a t e d as t h e p e r c en t a ge o f t h e c y cle tim e s p e n t w h en co n v e r ti n g , m u l t i p li ed b y t h e m a xi m u m c u r r en t d u r i n g co n v ersio n . th e a v era g e p o w e r dis s i p a t e d in po w e r - d o w n m o d e i s cal c ul a t ed a s th e pe r c en ta g e o f c y c l e ti m e s p en t i n p o wer - do wn m o de , m u l t i p lie d b y t h e c u r r en t f i gur e fo r p o w e r - do wn mo de . i n o r d er t o ob t a i n t h e val u e fo r t h e a v er a g e p o w e r , t h es e t e r m s m u s t b e m u lt i p lie d b y t h e v o l t a g e . c o n s ider in g t h e maxim u m c u r r en t fo r e a ch sc lk f r e q uen c y fo r v dd = 1.8 v : po w e r c o n s u m p t i o n a = ((4.7/2 0) 186 a + (15.3/20) 100 na) 1.8 v = (43.71 + 0.07 6) a 1.8 v = 78.8 w = 0.07 mw po w e r c o n s u m p t i o n b = ((13/20 ) 108 a + (7/20) 100 na) 1.8 v = (70.2 + 0.035 ) a 1.8 v = 126.42 w = 0.126 mw i t ca n b e con c l u de d t h a t fo r a f i xe d t h r o u g h p u t r a te, t h e a v er a g e p o w e r co n s u m pt io n dr o p s as t h e sclk f r e q ue nc y in cr e a s e s. power consumption example 2 this exa m ple sho w s t h a t fo r a f i xe d sclk f r e q u e n c y , as t h e t h r o u g h p u t ra t e de cr e a s e s, t h e a v era g e p o wer co n s um p t io n d rop s . f rom f i g u re 2 8 , f o r s c lk = 3 . 4 m h z , t h rou g h put a = 100 ks ps (which g i v e s a c y c l e tim e o f 10 s), and thr o u g h p u t b = 50 ks ps (whic h g i v e s a c y c l e tim e o f 20 s), t h e f o l l o w in g v a l u e s ca n be ob ta in e d : co n v er s i o n t i m e a = 16 (1/ sc l k ) = 4.7 s (47% o f th e c y c l e tim e f o r a thr o ug h p u t o f 100 ks ps) po w e r- d o w n t i m e a (1/ th r o u g h p u t a ) ? co n v ers i o n ti m e a = 10 s ? 4.7 s = 5.3 s (53% o f th e c y c l e tim e ) co n v er s i o n t i m e b = 16 (1/ sc l k ) = 4.7 s (23.5% o f the c y c l e tim e f o r a thr o u g h p u t o f 50 ks ps) po w e r- d o w n t i m e b = (1/ th r o u g h p u t b ) ? co n v ers i o n ti m e b = 20 s ? 4.7 s = 15.3 s (76.5% o f the c y c l e tim e ) the a v er a g e p o w e r co n s um p t ion is calc u l a t e d as expla i n e d in p o w e r c o n s u m p t io n e x a m ple 1, co n s ider ing t h e maxim u m c u r r en t f o r a 3.4 mh z sclk f r eq uen c y f o r v dd = 1.8 v . po w e r c o n s u m p t i o n a = ((4.7/1 0) 186 a + (5.3/10) 100 na) 1.8 v= (87.42 + 0.05 3) a 1.8 v = 157.4 w = 0.157 mw po w e r c o n s u m p t i o n b = ((4.7/2 0) 186 a + (15.3/20) 100 na) 1.8 v = (43.7 + 0.076 ) a 1.8 v = 78.79 w = 0.078 mw i t ca n b e con c l u de d t h a t fo r a f i xe d sclk f r e q u e n c y , t h e a v er a g e p o we r c o nsu m pt i o n d rop s a s t h e t h rou g h put r a te d e c r e a s e s .
ad7466/ad7467/ad 7468 rev. a | page 22 of 28 serial interf ace f i gur e 30, f i gure 31, a nd f i gur e 32 s h o w t h e t i min g dia g ra ms f o r s e r i al in t e r f acin g t o t h e ad7 466/ad7467 /ad7468. th e s e r i a l cl o c k prov i d e s t h e c o n v e r s i on cl o c k a n d c o n t ro l s t h e t r a n sfer o f info rma t io n f r o m t h e ad c d u r i n g a co n v ersio n . the p a r t beg i n s t o p o w e r u p o n th e cs fal l in g e d ge . th e f a l l in g ed g e o f cs p u ts t h e t r ack-and- h o l d i n to t r ack m o de an d t a k e s t h e b u s o u t o f t h r e e-s t a t e . th e co n v ersio n is als o ini t i a t e d a t t h is p o in t. on t h e t h ir d scl k fal l i n g e d g e a f t e r t h e cs fal l in g e d g e , t h e p a r t s h ou l d b e p o we re d - up f u l l y a t p o i n t b , a s sh ow n i n f i gur e 30, an d t h e t r ack-and- h o ld r e t u r n s to h o l d . f o r th e ad7466 , th e s d a t a line g o es bac k in t o thr e e-s t a t e a nd t h e p a r t en t e rs p o w e r - do wn on t h e 16 t h sc lk fal l in g e d g e . i f th e ri s i n g ed g e o f cs o c c u r s b e f ore 1 6 s c l k s el a p s e , t h e co n v ersio n t e r m ina t es, t h e sd a t a l i n e g o es b a ck i n t o t h r e e - s t a t e , an d t h e p a r t en t e rs p o w e r - do wn; o t h e r w is e s d a t a r e t u rn s t o th r ee- s t a t e o n t h e 16t h sc lk fallin g ed g e , a s s h o w n in f i gur e 30. s i x t een s e r i a l c l o c k c y c l es a r e r e q u ir ed t o p e r f o r m th e co n v ersion p r o c es s a nd t o acces s da t a f r o m th e ad7466. f o r th e ad7467 , th e 14 th sclk fal l in g e d g e c a us es t h e s d a t a line t o g o b a ck i n t o t h r e e- s t a t e , a nd t h e p a r t en ters p o w e r - do wn. i f t h e r i sin g edg e o f cs o c c u r s b e f ore 1 4 s c l k s e l a p s e , t h e co n v ersion ter mina t e s, t h e sd a t a l i n e g o es b a ck i n t o t h r e e - s t a t e , an d the ad7467 en t e rs p o w e r - do wn; o t her w is e s d a t a r e t u rn s t o th r ee- s t a t e o n t h e 14t h sc lk fallin g ed g e , a s s h o w n in f i gur e 31. f o ur t e en s e r i al c l o c k c y c l es a r e r e q u ir ed t o p e r f or m t h e c o n v e r s i on pro c e s s an d to a c c e ss d a t a f rom t h e ad7467. f o r th e ad7468 , th e 12 th sclk fal l in g e d g e c a us es t h e s d a t a line t o g o b a ck i n t o t h r e e- s t a t e , a nd t h e p a r t en ters p o w e r - do wn. i f t h e r i sin g edg e o f cs o c c u r s b e f ore 1 2 s c l k s e l a p s e , t h e co n v ersion ter mina t e s, t h e sd a t a l i n e g o es b a ck i n t o t h r e e - s t a t e , an d the ad7468 en t e rs p o w e r do wn; ot her w is e s d a t a r e t u rn s t o th r ee- s t a t e o n t h e 12t h sc lk fallin g ed g e , a s s h o w n in f i gur e 32. t w e l v e s e r i al c l o c k c y c l es a r e r e q u ir ed t o p e r f o r m th e co n v ersion p r o c es s a nd t o acces s da t a f r o m th e ad7468. cs g o in g lo w p r o v i d es t h e f i rs t le adin g zer o t o b e r e ad i n b y t h e m i cr oco n tr o l le r o r d s p . th e r e m a i n in g d a ta i s th en c l oc k e d o u t b y subs e q ue n t s c lk fa l l in g e d ges, b e g i nn in g w i t h t h e s e cond le adin g zer o ; t h us t h e f i rs t c l o c k fal l in g e d g e on t h e s e r i al c l o c k has t h e f i rs t le adin g zer o p r o v i d e d and als o clo c ks o u t t h e s e co nd leadin g zer o . f o r the ad7466, t h e f i nal b i t in t h e da t a tra n s f e r i s v a li d o n t h e 16t h scl k fallin g e d g e , h a vi n g been clo c k e d o u t on t h e p r e v io us (15t h) sclk f a l l ing e d g e . i n a p plic a t io n s wi t h a slo w scl k , i t is p o ssib le t o r e ad i n da t a o n e a c h s c lk r i sin g e d g e . i n s u c h a cas e , t h e f i rs t fal l in g e d ge of s c l k af te r t h e cs f a ll i n g ed g e c l oc k s o u t th e se c o n d l e a d i n g zer o a nd can be r e ad in t h e f o l l o w in g r i sin g e d g e . i f t h e f i r s t sclk e d g e a f t e r th e cs fal l in g e d g e is a fal l in g e d g e , t h e f i rs t le adi n g zer o t h a t was clo c k e d ou t w h e n cs w e n t l o w is miss ed unles s i t is n o t r e ad o n t h e f i rs t sclk fal l i n g e d g e . th e 15t h fal l in g e d g e o f s c lk c l o c ks o u t th e last b i t, and i t can be r e ad in th e f o llo w i n g ris i n g sc lk ed g e . i f t h e f i rs t scl k e d g e a f ter cs fal l in g e d g e is a r i sin g e d ge , cs cl o c k s out t h e f i r s t l e a d i n g z e ro , an d it c a n b e re a d on t h e s c l k r i s i ng e d ge. t h e ne x t s c l k f a l l i ng e d ge cl o c k s out t h e s e c o n d le adin g zer o , and i t ca n b e r e ad o n t h e fol l o w ing r i sin g e d g e . sclk t 2 t 3 t 4 t 7 t 5 t 8 t convert t quiet db11 db10 db2 db1 db0 b 4 leading zeros 13 14 15 16 t 1 three-state three- state sdat a cs 5 4 3 2 1 02643-030 t 6 12 bits of data 0 0 0 0 f i gur e 3 0 . ad74 66 se ri al int e r f a c e ti mi ng dia g r a m t quiet t 1 sclk s dat a 4 leading zeros three-state three-state 10 bits of data b 12 3 4 5 1 3 1 4 db9 db8 db0 t 2 t 3 t 4 t 7 t 5 t 8 t 6 t convert 02643-031 cs 0 0 0 0 f i gur e 3 1 . ad74 67 se ri al int e r f a c e ti mi ng dia g r a m
ad7466/ad7467/ad 7468 rev. a | page 23 of 28 t 1 sclk s dat a b 1 2 3 4 11 12 t 2 t 6 t convert t quiet 4 leading zeros three-state three-state 8 bits of data db7 db0 t 3 t 4 t 7 t 5 t 8 cs 02643-032 0 0 0 0 f i gur e 3 2 . ad74 68 se ri al int e r f a c e ti mi ng dia g r a m micr oprocessor interf a c ing the s e r i al in ter face o n t h e ad7 466/ad7467 /ad7468 al lo ws t h e p a r t s to b e c o nn e c te d dir e c t ly to ma n y dif f er en t micr o - p r o c es s o rs. this s e c t io n exp l a i ns h o w t o in t e r f ace t h e ad7466/ ad7467/ad74 68 wi th s o me o f th e m o r e co mm o n micr o- c o n t ro l l e r and d s p s e r i a l i n te r f a c e proto c o l s . ad7466/ad7467/ad7468 t o tms320c541 interface the s e r i al in ter face o n t h e t m s 320c541 us es a co n t in uo us s e r i al c l o c k and f r a m e sy n c hr o n iza t io n sig n als to syn c hr o n ize t h e da t a t r a n sfer o p era t io n s wi t h p e r i ph eral de vices li k e t h e ad7466/ad74 67/ad7468. the cs in pu t a l lo ws e a sy in t e r - facin g betw een th e t m s320c5 41 a nd t h e ad7 4 xx devices, w i t h out re qu i r i n g an y g l u e l o g i c . t h e s e r i a l p o r t of t h e t m s-320c541 is s et u p t o o p era t e in b u rs t m o de (fs m = 1 in t h e s e r i al p o r t co n t r o l r e g i s t e r , s p c) w i t h in ter nal clkx (mcm = 1 in t h e s p c r e g i s t er) a nd i n t e r n al f r a m e sig n al (t xm = 1 i n t h e s p c r e g i s t er), s o b o t h p i ns a r e co nf igur e d as o u t p u t s. f o r th e ad7466, t h e wo r d len g th s h o u ld b e s et t o 1 6 bit s ( f o = 0 i n t h e sp c re g i s t e r ) . t h e st a n d a rd s y nc h ronou s s e r i a l p o r t i n te r f a c e i n t h i s d s p a l l o w s on ly f r ame s w i t h a word len g th o f 16 b i ts o r 8 b i t s. th er ef o r e , f o r th e ad7467 a nd ad7468 w h er e 14 a nd 12 b i ts ar e r e q u ir ed , t h e fo b i t als o w o u l d b e s e t u p t o 16 b i t s. i n t h es e cas e s , t h e us er s h o u l d k e ep in min d t h a t the las t 2 b i ts an d 4 b i t s f o r the ad7467 a nd ad7468, r e s p ec ti v e l y , a r e in valid da t a as t h e s d a t a l i n e g o es ba c k in t o th r ee-s t a t e o n t h e 14t h a n d 12t h sc lk fallin g ed g e . t o s u mma r i ze , t h e v a l u es i n t h e s p c r e g i s t er a r e fo = 0, fs m = 1, m c m = 1, a n d t x m = 1. f i g u r e 33 s h o w s th e co nn ecti o n di a g ra m . f o r s i gn al p r oce s s i n g a p plic a t io n s , i t i s im p e ra t i ve t h a t t h e f r a m e sy n c hr o n iza t io n sig n al f r o m the t m s320c541 p r o v ide eq uidis t an t s a m p ling. ad7466/ ad7467/ ad7468* sclk *additional pins omitted for clarity sdata tms320c541* clkx clkr dr fsx fsr 02643-033 cs f i gure 3 3 . int e r f acing t o th e tms 3 20 c 5 41 ad7466/ad7467/ad7468 t o adsp-218x interface the ad s p -218 x fa mi ly o f ds p s is in ter face d dir e c t ly t o t h e ad7466/ad74 67/ad7468 wi t h o u t an y g l u e log i c. th e s p o r t co n t r o l r e g i s t er m u s t b e s et u p as des c r i b e d i n t a b l e 9. table 9. s e t t i n g d e s c r i p t i o n tfsw = rfsw = 1 alternate framing invrfs = i nvtf s = 1 active low frame signal dt ype = 00 right-justify d a ta isclk = 1 internal seri al cl ock tfsr = rfsr= 1 frame every wo rd irfs = 0 sets up rfs as an input itfs = 1 sets up tfs as an output slen = 1111 16 bits for the ad7466 slen = 1101 14 bits for the ad7467 slen = 1011 12 bits for the ad7468 t h e co nn ecti o n d i a g ra m i n f i gur e 34 s h o w s h o w t h e ad s p - 218x has th e tf s a nd rfs o f the s p o r t t i ed t o g e th er , wi th tf s s et as an o u t p u t a nd rfs s e t as an i n p u t. th e d s p o p era t es in al t e r n a t e f r a m ing m o de , and t h e s p o r t con t r o l r e g i s t er is s et u p as des c r i b e d . the f r a m e sy n c hr o n iza t io n sig n a l gen e r a te d o n th e t f s i s ti e d t o cs , a n d a s wi th all si gn al p r o c es si n g a p p l i - ca tio n s, eq uidista n t s a m p lin g is n e ces s a r y . h o wev e r , in this exa m ple , t h e t i m e r i n t e r r u p t is us e d t o co n t r o l t h e s a m p l i n g ra te o f t h e a d c and, under cer t a i n co ndi t i on s, e q ui dist an t s a m p ling mig h t n o t b e achie v e d .
ad7466/ad7467/ad 7468 rev. a | page 24 of 28 the t i m e r r e g i sters, fo r exa m ple , a r e lo ade d wi t h a v a l u e t h a t p r o v ide s a n in te r r u p t a t t h e r e quir e d s a m p le i n ter val. w h e n a n in t e r r u p t is r e ce i v e d , a va l u e is t r a n smi t t e d w i t h tfs/dt (ad c c o n t ro l word ) . t h e t f s i s u s e d to c o n t ro l t h e r f s an d t h e r e f ore t h e r e adin g o f da t a . th e f r e q ue n c y o f t h e s e r i a l clo c k is s et in t h e s c lkd i v r e g i s t er . w h en t h e in s t r u c t io n to t r a n smi t wi t h tfs is g i v e n (t ha t is, a x 0 = t x 0), t h e st a t e o f t h e sc lk is ch e c k e d . the d s p wa i t s un t i l t h e sc lk g o es hig h , lo w , and hi g h ag ai n b e fore t r ans m i s s i on s t ar t s . i f t h e t i me r a n d s c l k v a lu e s a r e c h os en s u c h tha t t h e in str u c t io n t o tra n smi t o c c u r s o n o r n e a r th e ri s i n g ed g e o f s c l k , th e d a ta c a n be t r a n s m i t t e d o r i t ca n w a i t un til t h e n e xt c l ock edg e . f o r exa m p l e , the ads p -2181 has a mas ter c l o c k f r eq uen c y o f 16 mh z. i f t h e sclkd i v r e g i st er is lo ade d wi t h t h e va l u e 3, an sclk o f 2 mh z is ob ta in e d , and 8 mas t er c l o c k p e r i o d s e l a p s e fo r e v er y sclk p e r i o d . i f t h e t i m e r r e g i s ters a r e lo ade d wi t h th e val u e 803, 1 00.5 sclks o c c u r betw een in t e r r u p ts a n d subs e q uen t ly b e tw e e n t r a n smi t in st r u c t io n s . th is si t u a t ion r e su l t s in n o n e quidist a n t s a m p li n g as t h e t r a n s m i t in st r u c t io n i s occurri n g o n a sc lk ed g e . i f th e n u m b e r o f sc l k s bet w een in t e r r u p ts is a w h ole i n t e g e r f i g u r e o f n, e q ui di s t a n t s a m p l i n g i s i m p l em en t e d b y th e d s p . ad7466/ad7467/ad7468 t o dsp563xx interface the co nn ec tion dia g ram in f i g u r e 35 s h o w s h o w t h e ad7466/ ad7467/ad74 68 ca n be co nn e c t e d t o t h e s y nchr o n o u s s e r i al i n te r f a c e ( s si ) of t h e d s p 5 6 3 x x f a m i ly of d s p s f rom m o toro l a . the ss i is o p er a t e d i n sy n c hr ono u s m o d e an d no r m a l m o de (s yn = 1 an d m o d = 0 in c o n t r o l reg i st er b , crb) wi t h a n in ter n a l ly gen e r a te d w o r d f r a m e sy n c fo r b o t h tx a nd rx (b i t s fs l1 = 0 a nd fs l0 = 0 in t h e c r b r e g i s ter). s et t h e word l e ng t h i n c o n t ro l r e g i ste r a ( c r a ) to 1 6 b y s e tt i n g bit s wl2 = 0, wl1 = 1, a n d wl0 = 0 f o r th e ad74 66. the w o r d len g th f o r th e ad7468 ca n be s et t o 12 b i ts (wl2 = 0, wl1 = 0, a nd wl0 = 1). this ds p do es n o t o f f e r th e o p tio n f o r a 14-b i t w o r d len g th, s o th e ad7467 w o r d len g th is s et u p t o 16 b i t s l i ke th e ad7466s. i n this cas e , t h e us er s h o u l d k eep in min d tha t t h e las t tw o b i ts a r e in vali d da t a b e c a us e t h e sd a t a g o es b a ck in to t h r e e-s t a te o n t h e 14t h scl k f a l l in g e d g e . the f r a m e sy n c p o la r i ty b i t (fs p ) in t h e c r b reg i s t er can b e s e t t o 1, w h ich m e an s t h e f r a m e g o es lo w an d a con v ersio n s t a r ts. l i k e wis e , b y m e a n s o f b i ts scd2, sckd , and s h fd in t h e crb r e g i s t er , i t is es t a b l ish e d tha t p i n s sc2 (t h e f r a m e sy n c sig n al) a nd sck in t h e s e r i a l p o r t a r e co nf igur e d as o u t p u t s a nd t h e m o st sig n if ican t b i t (ms b ) is shi f t e d f i rst. t o su mma r i ze: mod = 0 sy n = 1 wl2, wl1, wl 0 dep e nd o n t h e w o r d len g th fs l1 = 0, fs l0 = 0 f s p = 1 , ne g a t i v e f r ame s y nc scd2 = 1 sckd = 1 sh f d = 0 f o r sig n a l p r o c essin g a p plic a t ion s , i t is im p e ra t i v e t h a t t h e f r ame s y nch ron i z at i o n s i g n a l f rom t h e d s p 5 6 3 x x pro v i d e s eq ui d i s t a n t sa m p li n g . ad7466/ ad7467/ ad7468* sclk *additional pins omitted for clarity sdata adsp-218x* sclk dr rfs tfs 02643-034 cs ad7466/ ad7467/ ad7468* *additional pins omitted for clarity dsp563xx* sdata srd sclk sck sc2 02643-035 cs f i gure 3 4 . int e r f acing t o th e ads p - 2 18 x f i gure 3 5 . int e r f acing t o th e ds p5 63 x x
ad7466/ad7467/ad7468 rev. a | page 25 of 28 application hints grounding and layout the printed circuit board that houses the ad7466/ad7467/ ad7468 should be designed such that the analog and digital sections are separated and confined to certain areas. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes because it gives the best shielding. digital and analog ground planes should be joined at only one place. if the devices are in a system where multiple devices require an agnd to dgnd connection, the connection should still be made at one point only, a star ground point, that should be established as close as possible to the ad7466/ad7467/ad7468. avoid running digital lines under the device because these couple noise onto the die. the analog ground plane should be allowed to run under the ad7466/ad7467/ad7468 to avoid noise coupling. the power supply lines to the devices should use as large a trace as possible to provide low impedance paths and to reduce the effects of glitches on the power-supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough on the board. a microstrip technique is by far the best choice, but is not always possible with a double-sided board. with this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also very important. all analog supplies should be decoupled with 10 f tantalum in parallel with 0.1 f capacitors to agnd. all digital supplies should have a 0.1 f ceramic disc capacitor to dgnd. to achieve the best perform- ance from these decoupling components, the user should keep the distance between the decoupling capacitor and the v dd and gnd pins to a minimum, with short track lengths connecting the respective pins. evaluating the performance of the ad7466 and ad7467 the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via an evaluation board controller. to evaluate the ac and dc performance of the ad7466 and ad7467, the evaluation board controller can be used in conjunction with the ad7466/ad7467cb evaluation board and other analog devices evaluation boards ending in the cb designator. the software allows the user to perform ac tests (fast fourier transform) and dc tests (histogram of codes) on the ad7466 and ad7467. see the technical note in the evaluation board package for more information.
ad7466/ad7467/ad 7468 rev. a | page 26 of 28 outline dimensions 1 3 4 5 2 6 2. 90 bs c 1. 60 bs c 2. 80 b s c 1. 90 bs c 0. 95 b s c 0. 22 0. 08 10 4 0 0. 50 0. 30 0 . 1 5 ma x 1. 30 1. 15 0. 90 sea t i n g p l ane 1. 4 5 m a x 0. 60 0. 45 0. 30 pin 1 indicator compliant to jedec standards mo-178ab f i g u re 36. 6-l e ad s m a l l o u t l i n e t r ans i s t or p a ck ag e [so t - 23] (r t - 6) di me nsio ns sho w n i n mi ll im e t e r s 0.80 0.60 0.40 8 0 4 85 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa f i g u re 37. 8-l e ad m i ni s m al l o u t l ine p a ck ag e [m sop ] (rm-8) di me nsio ns sho w n i n mi ll im e t e r s
ad7466/ad7467/ad7468 rev. a | page 27 of 28 ordering guide model temperature range linearity error (lsb) 1 package option 2 branding ad7466brt-reel ?40c to +85c 1.5 max rt-6 clb ad7466brt-reel7 ?40c to +85c 1.5 max rt-6 clb ad7466brt-r2 ?40c to +85c 1.5 max rt-6 clb ad7466brm ?40c to +85c 1.5 max rm-8 clb AD7466BRM-REEL ?40c to +85c 1.5 max rm-8 clb AD7466BRM-REEL7 ?40c to +85c 1.5 max rm-8 clb ad7466brmz 3 ?40c to +85c 1.5 max rm-8 c2t ad7466brmz-reel 3 ?40c to +85c 1.5 max rm-8 c2t ad7466brmz-reel7 3 ?40c to +85c 1.5 max rm-8 c2t ad7467brt-reel ?40c to +85c 0.5 max rt-6 cmb ad7467brt-reel7 ?40c to +85c 0.5 max rt-6 cmb ad7467brt-r2 ?40c to +85c 0.5 max rt-6 cmb ad7467brtz-reel 3 ?40c to +85c 0.5 max rt-6 cmu ad7467brtz-reel7 3 ?40c to +85c 0.5 max rt-6 cmu ad7467brm ?40c to +85c 0.5 max rm-8 cmb ad7467brm-reel ?40c to +85c 0.5 max rm-8 cmb ad7467brm-reel7 ?40c to +85c 0.5 max rm-8 cmb ad7468brt-reel ?40c to +85c 0.2 max rt-6 cnb ad7468brt-reel7 ?40c to +85c 0.2 max rt-6 cnb ad7468brt-r2 ?40c to +85c 0.2 max rt-6 cnb ad7468brm ?40c to +85c 0.2 max rm-8 cnb ad7468brm-reel ?40c to +85c 0.2 max rm-8 cnb ad7468brm-reel7 ?40c to +85c 0.2 max rm-8 cnb eval-ad7466cb 4 evaluation board eval-ad7467cb 4 evaluation board eval-control brd2 5 1 linearity error here refers to integral nonlinearity. 2 rt = sot-23, rm = msop. 3 z = pb-free part. 4 this can be used as a standalone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstration pu rposes. 5 this board is a complete unit that allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designator. to order a complete evaluation kit, you ne ed to order a particular adc ev aluation board (e.g., eval-ad7466cb ), the eval-control brd2, and a 12 v ac transformer. see relevant evaluation board technical notes for more information.
ad7466/ad7467/ad 7468 rev. a | page 28 of 28 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c02643C0 C 11/04(a)

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