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w27e257 32k 8 electrically erasable eprom publication release date: january 1997 - 1 - revision a3 general description the w27e257 is a high-speed, low-power electrically erasable and programmable read only memory organized as 32768 8 bits that operates on a single 5 volt power supply. the w27e257 provides an electrical chip erase function. this part was the same eprom writer's utilities as the w27e256. features high speed access time: 100/120/150 ns (max.) read operating current: 15 ma (typ.) erase/programming operating current 1 ma (typ.) standby current: 5 m a (typ.) single 5v power supply +14v erase/+12v programming voltage full y static operation all inputs and outputs directly ttl/cmos compatible three-state outputs available packages: 28-pin 600 mil dip and 32-pin plcc pin configurations a6 a5 a4 a3 a2 a1 a0 nc q0 5 6 7 8 9 10 11 12 13 1 4 4 3 2 1 3 2 3 1 3 0 29 28 27 26 25 24 23 22 21 32-pin plcc q 1 q 2 n c q 3 q 4 q 5 g n d 26 27 28 1 2 3 4 5 6 7 8 21 22 23 24 25 16 17 18 19 20 9 10 11 12 13 14 15 q3 ce q7 q6 q5 q4 a9 a11 oe a10 a14 a13 a8 1 5 1 6 1 7 1 8 1 9 2 0 gnd q2 q1 a0 a1 a2 a3 a4 a5 a6 a7 a12 v q0 pp v cc a 7 n c a 1 2 v p p a 1 4 a 1 3 v c c a8 a9 a11 nc oe a10 q7 ce q6 28-pin dip block diagram ce oe control output buffer decoder core array q0 q7 . . a0 . . a14 v gnd cc v pp pin description symbol description a0 - a14 address inputs q0 - q7 data inputs/outputs ce chip enable oe output enable v pp program/erase supply voltage v cc power supply gnd ground nc no connection
w27e257 - 2 - functional description read mode like conventional uveproms, the w27e257 has two control functions, both of which produce data at the outputs. ce is for power control and chip select. oe controls the output buffer to gate data to the output pins. when addresses are stable, the address access time (t acc ) is equal to the delay from ce to output (t ce ), and data are available at the outputs t oe after the falling edge of oe , if t acc and t ce timings are met. erase mode the erase operation is the only way to change data from "0" to "1." unlike conventional uveproms, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the w27e257 uses electrical erasure. generally, the chip can be erased within 100 ms by using an eprom writer with a special erase algorithm. erase mode is entered when v pp is raised to v pe (14v), v cc = v ce (5v), oe = v ih (2v or above but lower than v cc ), a9 = v hh (14v), a0 = v il (0.8v or below but higher than gnd), and all other address pins equal v il and data input pins equal v ih . pulsing ce low starts the erase operation. erase verify mode after an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. the erase verify mode automatically ensures a substantial erase margin. this mode will be entered after the erase operation if v pp = v pe (14v), ce = v ih , and oe = v il . program mode programming is performed exactly as it is in conventional uveproms, and programming is the only way to change cell data from "1" to "0." the program mode is entered when v pp is raised to v pp (12v), v cc = v cp (5v), oe = v ih , the address pins equal the desired address, and the input pins equal the desired inputs. pulsing ce low starts the programming operation. program verify mode all of the bytes in the chip must be verified to check whether or not they have been successfully programmed with the desired data. hence, after each byte is programmed, a program verify operation should be performed. the program verify mode automatically ensures a substantial program margin. this mode will be entered after the program operation if v pp = v pp (12v), ce = v ih , and oe = v il . erase/program inhibit erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. when ce = v ih , erasing or programming of non-target chips is inhibited, so that except for the ce and oe pins, the w27e257 may have common inputs.
w27e257 publication release date: january 1997 - 3 - revision a3 standby mode the standby mode significantly reduces v cc current. this mode is entered when ce = v ih . in standby mode, all outputs are in a high impedance state, independent of oe . two-line output control since eproms are often used in large memory arrays, the w27e257 provides two control inputs for multiple memory connections. two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. system considerations eprom power switching characteristics require careful device decoupling. system designers are interested in three supply current issues: standby current levels (i sb ), active current levels (i cc ), and transient current peaks produced by the falling and rising edges of ce . transient current magnitudes depend on the device output's capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 m f ceramic capacitor connected between its v cc and gnd. this high frequency, low inherent- inductance capacitor should be placed as close as possible to the device. additionally, for every eight devices, a 4.7 m f electrolytic capacitor should be placed at the array's power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductances. table of operating modes (v pp = 12v, v pe = 14v, v hh = 12v, v cp = 5v, x = v ih or v il ) mode pins ce oe a0 a9 v cc v pp outputs read v il v il x x v cc v cc d out output disable v il v ih x x v cc v cc high z standby (ttl) v ih x x x v cc v cc high z standby (cmos) v cc 0.3v x x x v cc v cc high z program v il v ih x x v cp v pp d in program verify v ih v il x x v cp v pp d out program inhibit v ih v ih x x v cp v pp high z erase v il v ih v il v pe v cc v pe d ih erase verify v ih v il x x v cc v pe d out erase inhibit v ih v ih x x v cp v pp high z product identifier-manufacturer v il v il v il v hh v cc v cc da (hex) product identifier-device v il v il v ih v hh v cc v cc 02 (hex)
w27e257 - 4 - dc characteristics absolute maximum ratings parameter rating unit ambient temperature with power applied -55 to +125 c storage temperature -65 to +125 c voltage on all pins with respect to ground except v pp, a9 and v cc pins -0.5 to v cc +0.5 v voltage on v pp pin with respect to ground -0.5 to +14.5 v voltage on a9 pin with respect to ground -0.5 to +14.5 v voltage on v cc pin with respect to ground -0.5 to +7 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc erase characteristics (t a = 25 c 5 c, v cc = 5.0v 10%) parameter sym. conditions limits unit min. typ. max. input load current i li v in = v il or v ih -10 - 10 m a v cc erase current i cp ce = v il - - 30 ma v pp erase current i pp ce = v il - - 30 ma input low voltage v il - -0.3 - 0.8 v input high voltage v ih - 2.4 - 5.5 v output low voltage (verify) v ol i ol = 2.1 ma - - 0.45 v output high voltage (verify) v oh i oh = -0.4 ma 2.4 - - - a9 erase voltage v id - 13.75 14 14.25 v v pp erase voltage v pe - 13.75 14 14.25 v v cc supply voltage (erase) v ce - 4.5 5.0 5.5 v note: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . capacitance (v cc = 5v, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit input capacitance c in v in = 0v 6 pf output capacitance c out v out = 0v 12 pf
w27e257 publication release date: january 1997 - 5 - revision a3 ac characteristics ac test conditions parameter conditions input pulse levels 0.45v to 2.4v input rise and fall times 10 ns input and output timing reference level 0.8v/2.0v output load c l = 100 pf, i oh /i ol = -0.4 ma/2.1 ma ac test load and waveform +1.3v 3.3k ohm 100 pf (including jig and scope) d (in914) out input 2.4v 0.45v 2.0v 0.8v 2.0v 0.8v test points test points output
w27e257 - 6 - read operation dc characteristics (v cc = 5.0v 10%, t a = 0 to 70 c) (w27e257-10, s-10, k-10, p-10: v cc , min. = 3.0v and max. = 5.5v) parameter sym. conditions limits unit min. typ. max. input load current i li v in = 0v to v cc -5 - 5 m a output leakage current i lo v out = 0v to v cc -10 - 10 m a v cc standby current i sb ce = v ih - - 1.0 ma i sb1 ce = v cc 0.2v - 5 100 m a v cc operating current i cc ce = v il i out = 0 ma f = 5 mhz - - 30 ma v pp operating current i pp v pp = v cc - - 100 m a input low voltage v il - -0.3 - 0.8 v input high voltage v ih - 2.0 - v cc +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = -0.4 ma 2.4 - - v v pp operating voltage v pp - v cc -0.7 - v cc v read operation ac characteristics (v cc = 5.0v 10%, t a = 0 to 70 c) parameter sym. w27e257-10 w27e257-12 w27e257-15 unit min. max. min. max. min. max. read cycle time t rc 100 - 120 - 150 - ns chip enable access time t ce - 100 - 120 - 150 ns address access time t acc - 100 - 120 - 150 ns output enable access time t oe - 50 - 60 - 70 ns oe high to high-z output t df - 30 - 30 - 50 ns output hold from address change t oh 0 - 0 - 0 - ns note: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp .
w27e257 publication release date: january 1997 - 7 - revision a3 dc programming characteristics (v cc = 5.0v 10%, t a = 25 c 5 c) parameter sym. conditions limits unit min. typ. max. input load current i li v in = v il or v ih -10 - 10 m a v cc program current i cp ce = v il - - 30 ma v pp program current i pp ce = v il - - 30 ma input low voltage v il - -0.3 - 0.8 v input high voltage v ih - 2.4 - 5.5 v output low voltage (verify) v ol i ol = 2.1 ma - - 0.45 v output high voltage (verify) v oh i oh = -0.4 ma 2.4 - - v a9 silicon i.d. voltage v id - 11.5 12.0 12.5 v v pp program voltage v pp - 11.75 12.0 12.25 v v cc supply voltage (program) v cp - 4.5 5.0 5.5 v ac programming/erase characteristics (v cc = 5.0v 10%, t a = 25 c 5 c) parameter sym. limits unit min. typ. max. v pp setup time t vps 2.0 - - m s address setup time t as 2.0 - - m s data setup time t ds 2.0 - - m s ce program pulse width t pwp 95 100 105 m s ce erase pulse width t pwe 95 100 105 ms data hold time t dh 2.0 - - m s oe setup time t oes 2.0 - - m s data valid from oe t oev - - 150 ns oe high to output high z t dfp 0 - 130 ns address hold time t ah 0 - - m s address hold time after ce high (erase) t ahc 2.0 - - m s note: v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp .
w27e257 - 8 - timing waveforms ac read waveform ce outputs t high z high z valid output ce t oe t acc t oh t df address address valid v il v ih v ih v il v ih v il oe erase waveform address read sid device read sid a9 = 12.0v others = v il a0 = v il data chip erase a9 = 14.0v erase verify address stable t acc da 02 data all one 14.0v 5.0v a0= v ih 5v read verify blank check manufacturer address stable address stable others = v il others = v il t acc t as t arc t ds t ahc t vps t dfp d out d out d out t ah t acc v ih v il v pp ce oe t ce t oe t oe t oes t oev t oe v ih v il v ih v il t pwe
w27e257 publication release date: january 1997 - 9 - revision a3 timing waveforms, continued programming waveform address data 12.0v 5.0v ce address stable program read verify address stable address valid verify data in stable 5v program d out t ah d out d out t dh t ds t vps t acc t dfp t as v ih v il v ih v il v pp oe t oes t oev t oe v ih v il t pwp
w27e257 - 10 - smart programming algorithm start address = first location vcc = 5v vpp = 12v x = 0 increment x x = 25? verify one byte last address? vcc = 5v vpp = 5v compare all bytes to original data pass device increment address no fail yes pass fail fail fail device verify one byte program one 100 s pulse m no pass yes pass
w27e257 publication release date: january 1997 - 11 - revision a3 smart erase algorithm start vcc = 5v vpp = 14v increment x last address? vcc = 5v vpp = 5v compare all bytes to ffs (hex) pass device increment address no fail fail fail device x = 0 a9 = 14v; a0 = v chip erase 100 ms pulse address = first location erase verify x = 20? no yes pass pass yes il
w27e257 - 12 - ordering information part no. access time ( n s) power supply current max. ( m a) standby v cc current max. ( m a) package w27e257-10 100 30 100 600 mil dip w27e257-12 120 30 100 600 mil dip w27e257-15 150 30 100 600 mil dip W27E257P-10 100 30 100 32-pin plcc w27e257p-12 120 30 100 32-pin plcc w27e257p-15 150 30 100 32-pin plcc notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
w27e257 publication release date: january 1997 - 13 - revision a3 package dimensions 28-pin p-dip 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. 1.63 1.47 0.064 0.058 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.550 0.545 13.72 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.460 1.470 37.08 37.34 0 15 0.090 2.29 0.650 0.630 16.00 16.51 4. dimension b1 does not include dambar protrusion/intrusion. 5. controlling dimension: inches. 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 28 1 15 14 32-pin plcc l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 notes: 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: inches. 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.9 5 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.49 0 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.51 0 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 q q
w27e257 - 14 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792647 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.

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