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1/25 april 2005 m69aw024be 16 mbit (1m x16) 3v asynchronous psram features summary supply voltage: 2.7 to 3.3v access time: 60ns low standby current: 70a deep power down current: 10a compatible with standard lpsram tfbga48 package rohs compliant (directive 2002/95/ec of the european parliament) figure 1. package bga tfbga48 (zb) 6x8 mm
m69aw024be 2/25 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 address inputs (a0-a19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data inputs/outputs (dq8-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chip enable (e1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 chip enable (e2 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 upper byte enable (ub ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 lower byte enable (lb ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 vss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 deep power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. read and standby modes ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. address access after g controlled read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. ub /lb controlled read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/25 m69aw024be table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10.write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11.w controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12.write enable and ub /lb controlled, byte write ac waveforms 1 . . . . . . . . . . . . . . . . . 18 figure 13.write enable and ub /lb controlled, byte write ac waveforms 2 . . . . . . . . . . . . . . . . . 18 figure 14.write enable and ub /lb controlled, byte write ac waveforms 3 . . . . . . . . . . . . . . . . . 19 figure 15.write enable and ub /lb controlled, byte write ac waveforms 4 . . . . . . . . . . . . . . . . . 19 table 9. standby, power-down and power-up ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16.power-up mode ac waveforms - 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17.power-up mode ac waveforms - 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 18.power-down entry ad exit ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 19.standby mode entry ac waveforms, after read or write . . . . . . . . . . . . . . . . . . . . . . . 21 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 20.tfbga48 6x8mm - 6x8 ball array, 0.75 mm pitch, package outline, bottom view . . . . 22 table 10. tfbga48 6x8mm - 6x8 ball array, 0.75 mm pitch, package mechanical data. . . . . . . . 22 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
m69aw024be 4/25 summary description the m69aw024be is a 16 mbit (16,777,216 bit) cmos memory, organized as 1,024,576 words by 16 bits, and is supplied by a single 2.7v to 3.3v supply voltage range. m69aw024be is a member of stmicroelectronics psram memory family, based on the one-transis- tor per-cell architecture. these devices are manu- factured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area. however, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard asynchronous sram interface. the internal control logic of the m69aw024be handles the periodic refresh cycle, automatically, and without user involvement. write cycles can be performed on a single byte by using upper byte enable (ub ) and lower byte en- able (lb ). the device can be put into standby mode using chip enable (e1 ) or in deep power down mode by using chip enable (e2). power-down mode achieves a very low current consumption by halting all the internal activities. since the refresh circuitry is halted, the duration of the power-down should be less than the maximum period for refresh, if the user has not finished with the data contents of the memory. figure 2. logic diagram table 1. signal names ai07406b 20 a0-a19 w dq0-dq15 v cc m69aw024be g 16 e1 ub lb v ss e2 a0-a19 address input dq0-dq15 data input/output e1 , e2 chip enable, power down g output enable w write enable ub upper byte enable lb lower byte enable v cc supply voltage v ss ground nc not connected (no internal connection)
5/25 m69aw024be figure 3. tfbga connections (top view through package) ai07409 a 6 5 4 3 2 1 e b f a1 a0 g lb a17 dq7 w a12 nc a11 a8 a18 dq0 a3 a6 a5 a4 e1 a10 a9 a13 a7 a2 e2 c dq4 d dq5 a14 a15 g h dq11 a19 ub dq10 dq12 dq13 v ss dq15 dq8 dq9 dq14 dq3 dq2 dq1 v cc v cc nc v ss dq6 a16
m69aw024be 6/25 signal descriptions see figure 2., logic diagram , and table 1., signal names , for a brief overview of the sig- nals connected to this device. address inputs (a0-a19). the address inputs select the cells in the memory array to access dur- ing read and write operations. data inputs/outputs (dq8-dq15). the upper byte data inputs/outputs carry the data to or from the upper part of the selected address during a write or read operation, when upper byte enable (ub ) is driven low. data inputs/outputs (dq0-dq7). the lower byte data inputs/outputs carry the data to or from the lower part of the selected address during a write or read operation, when lower byte enable (lb ) is driven low. chip enable (e1 ). when asserted (low), the chip enable, e1 , activates the memory state ma- chine, address buffers and decoders, allowing read and write operations to be performed. when de-asserted (high), all other pins are ignored, and the device is put, automatically, in low-power standby mode. chip enable (e2). the chip enable, e2, puts the device in deep power-down mode when it is driven low. this is the lowest power mode. output enable (g ). the output enable, g , pro- vides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. write enable (w ). the write enable, w , controls the bus write operation of the memory?s com- mand interface. upper byte enable (ub ). the upper byte en- able, ub , gates the data on the upper byte data inputs/outputs (dq8-dq15) to or from the upper part of the selected address during a write or read operation. lower byte enable (lb ). the lower byte en- able, lb , gates the data on the lower byte data inputs/outputs (dq0-dq7) to or from the lower part of the selected address during a write or read operation. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read or write) and for driving the refresh logic, even when the device is not being accessed. v ss ground. the v ss ground is the reference for all voltage measurements.
7/25 m69aw024be figure 4. block diagram ai07410 dynamic memory array row decoder column decoder control logic e1 refresh controller arbitration logic internal clock generator input/output buffer address ub e2 g w lb power controller v cc v ss address v cc dq0-dq7 dq8-dq15
m69aw024be 8/25 operation operational modes are determined by device con- trol inputs w , e1 , e2, lb and ub as summarized in the operating modes table (see table 2. ). power on sequence because the internal control logic of the m69aw024be needs to be initialized, the follow- ing power-on procedure must be followed before the memory is used: ? apply power and wait for v cc to stabilize ?wait t chel while driving both chip enable signals (e1 and e2) high ? activate the memory by driving chip enable (e1 ) low. read mode the device is in read mode when: ? write enable (w ) is high and ? output enable (g ) low and ? the two chip enable signals are asserted (e1 is low, and e2 is high). the time taken to enter read mode (t elqv , t glqv or t blqv ) depends on which of the above signals was the last to reach the appropriate level. data out (dq15-dq0) may be indeterminate during t elqx , t glqx and t blqx , but data will always be valid during t avqv . write mode the device is in write mode when ? write enable (w ) is low and ? chip enable (e1 ) is low and ? the two chip enable signals are asserted (e1 is low, and e2 is high) ? one of upper byte enable (ub ) or lower byte enable (lb ) is low, while the other is high. the write cycle begins just after the event (the fall- ing edge) that causes the last of these conditions to become true (t avwl , t avel or t avbl ). the write cycle is terminated by the earlier of a ris- ing edge on write enable (w ) or chip enable (e1 ). if the device is in write mode (chip enable (e1 ) is low, output enable (g ) is low, upper byte en- able (ub ) or lower byte enable (lb ) is low), then write enable (w ) will return the outputs to high im- pedance within t whdz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the rising edge of write enable (w ), or for t dveh before the rising edge of chip enable (e1 ), whichever occurs first, and remain valid for t bhdz, t whdz , t ehdz . standby mode the device is in standby mode when: ? chip enable (e1 )ishigh and ? chip enable (e2) is high. the input/output buffers and the decoding/control logic are switched off, but the dynamic array con- tinues to be refreshed. in this mode, the memory current consumption, i sb , is reduced, and the data remains valid. deep power-down mode the device is in deep power-down mode when: ? chip enable (e2 is low).
9/25 m69aw024be table 2. operating modes note: 1. x = v ih or v il . 2. output disable mode should not be kept longer than 1s. 3. power-down mode can be entered from stand-by state, and all dq pins are in hi-z state. 4. can be either vil or vih but must be valid before read or write. operation e2 e1 w g lb ub a0-a19 dq0-dq7 dq8- dq15 i cc data retention standby (deselect) v ih v ih x (1) x (1) x (1) x (1) x (1) hi-z hi-z i sb yes output disabled (2) v ih v il v ih v ih x (1) x (1) note (4) hi-z hi-z i cc yes output disabled (no read) v ih v il v ih v il v ih v ih valid hi-z hi-z i cc yes upper byte read v ih v il v ih v il v ih v il valid hi-z output valid i cc yes lower byte read v ih v il v ih v il v il v ih valid output valid hi-z i cc yes word read v ih v il v ih v il v il v il valid output valid i cc yes upper byte write v ih v il v il v ih v ih v il valid invalid input valid i cc yes lower byte write v ih v il v il v ih v il v ih valid input valid invalid i cc yes word write v ih v il v il v ih v il v il valid input valid input valid i cc yes power-down (3) v il x (1) x (1) x (1) x (1) x (1) x (1) hi-z hi-z i pd no
m69aw024be 10/25 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. table 3. absolute maximum ratings note: 1. compliant with the jedec std j-std-020b (for small body, sn-pb or pb assembly), and the european directive on restrictio ns on hazardous substances (rohs) 2002/95/eu. symbol parameter min max unit i o output current ?50 50 ma t a ambient operating temperature ?30 85 c t lead lead temperature during soldering (1) c t stg storage temperature ?55 125 c v cc core supply voltage ?0.5 3.6 v v io input or output voltage ?0.5 3.6 v
11/25 m69aw024be dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 4., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 4. operating and ac measurement conditions note: 1. all voltages are referenced to v ss . 2. the input transition time used in ac measurements is 5ns. for other input transition times, see table 9 . figure 5. ac measurement load circuit figure 6. ac measurement i/o waveform note: 1. this waveform is given for hi-z and data transition ac pa- rameters only (see note 8. below table 7., read and standby modes ac characteristics ). parameter m69aw024be unit ?60 min max v cc supply voltage 1 2.7 3.3 v ambient operating temperature ?30 85 c load capacitance (c l ) 50 pf output circuit protection resistance (r 1 ) 50 ? input rise and fall times 4 ns input pulse voltages 0 to v cc v input and output timing ref. voltages v cc /2 v output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc v input transition time (t ) between v il and v ih (2) 5ns ai07222c v cc /2 out c l includes jig capacitance device under test c l r 1 ai07753c v cc i/o timing reference voltage 0v v cc /2 v cc output transition timing reference voltage (1) 0v 0.7v cc 0.3v cc
m69aw024be 12/25 table 5. capacitance note: 1. outputs deselected. table 6. dc characteristics note: 1. average ac current, outputs open, cycling at t avax (min). 2. maximum dc voltage on inputs and i/o pins is v cc +0.2v. during voltage transitions, data inputs may overshoot to v cc + 1.0v for a period of up to 5ns. 3. minimum dc voltage on input or i/o pins is ?0.3v. during voltage transitions, data inputs may overshoot to v ss + 1.0v for a period of up to 5ns. symbol parameter test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 5pf c out (1) output capacitance v out = 0v 8pf symbol parameter test condition min max unit i cc1 (1) operating supply current v cc = 3.3v, v in = v ih or v il , e1 = v il , e2 = v ih , i out = 0ma t rc /t wc = min 20 ma t rc /t wc = 1s 3.0 ma i li input leakage current 0v v in v cc ?1 1 a i lo output leakage current 0v v out v cc ?1 1 a i pd deep power down current v cc = 3.3v, v in = v ih or v il , e2 0.2v 10 a i sb standby supply current cmos 3.1v v cc 3.3v, v in 0.2v or v cc ?0.2v, e1 v cc ?0.2v and e2 v cc ?0.2v), i out = 0ma 100 a 2.7v v cc 3.1v, v in 0.2v or v cc ?0.2v, e1 v cc ?0.2v and e2 v cc ?0.2v), i out = 0ma 70 a v ih (2) input high voltage 2.7v v cc 3.3v 0.8v cc v cc + 0.2 v v il (3) input low voltage 2.7v v cc 3.3v ?0.3 0.2v cc v v oh output high voltage 3.1v v cc 3.3v, i oh = ?0.5ma 2.5 v 2.7v v cc 3.1v, i oh = ?0.5ma 2.2 v v ol output low voltage i ol = 1ma 0.4 v
13/25 m69aw024be table 7. read and standby modes ac characteristics note: 1. the maximum value of this timing is applicable if e1 is kept low with addresses uncha nged.if needed by the system operation, please contact your local st representative for relaxation of the 1000ns limitation. 2. addresses should not be changed during t avax (min). 3. these parameters are measured according to the conditions on input and output timing reference voltage shown on figure 6., ac measurement i/o waveform . 4. the output load capacitance is 5pf without any other load. 5. these timings are given for e1 low. 6. t avax (min) must be satisfied. 7. if the current value of t whgl is lower than the minimum value given in the above table, t avqv during the following read operation may increase by t whgl (current) ? t whgl (min). 8. all timings are measured according to the conditions for output transition timing reference voltage shown on figure 6., ac mea- surement i/o waveform . symbol alt. parameter m69aw024be unit ?60 min max t avax, t eleh (1,2) t rc read cycle time 70 1000 ns t elqv (3) t ce chip enable access time 60 ns t glqv (3) t oe output enable access time 40 ns t avqv (3,5) t aa address access time 60 ns t blqv (3) t ba lb , ub low to output valid 30 ns t axqx, t ghqx, t bhqx , t ehqx (8) t oh output hold time after chip enable low 5 ns t elqx (4,8) t clz chip enable low to output low-z 5 ns t glqx (4,8) t olz output enable low to output low-z 0 ns t blqx (4,8) t blz lb , ub low to output low-z 0 ns t ehqz (8) t chz chip enable high to output hi-z 20 ns t ghqz (8) t ohz output enable high to output hi-z 20 ns t bhqz (8) t bhz lb , ub high to output hi-z 20 ns t avel t asc address set-up time to chip enable low ?5 ns t avgl t aso address valid to output enable low 10 ns t axav (5) t ax address invalid time 10 ns t ehax (6) t chah chip enable high to address hold time ?5 ns t ghax t ohah output enable high to address hold time ?5 ns t whgl (7) t whol write enable high to output enable low (read operations) 10 1000 ns t ehel t cp chip enable high pulse width 10 ns
m69aw024be 14/25 figure 7. read mode ac waveforms note: e2 = high and w = high. figure 8. address access after g controlled read ac waveforms note: 1. e2 = high and w = high. 2. during the two consecutive read operations, the output enable signal, g , can either remain low, or be toggled. a0-a19 e1 g lb, ub valid data output dq0-dq15 tavel telqv address valid valid tehax tavel tehel tehqz tghqz tbhqz tehqx tglqv tblqv tblqx tglqx telqx ai09936 teleh address valid address valid a0-a19 e1 g ub, lb data out data out dq0-dq15 tavax tavax taxav taxav tavqv tavqv tglqv tglqx taxqx tghqz tghqx ai09937 tavgl
15/25 m69aw024be figure 9. ub /lb controlled read ac waveforms note: e2 = high and w = high. a0-a19 address valid e1 lb ub dq0-dq7 dq8-dq15 valid data output valid data out valid data out tavax taxav taxav tavqv tblqv tblqx tbhqx tbhqz tblqx tblqv tblqv tblqx tbhqx tbhqz tbhqx tbhqz ai09938b low g low
m69aw024be 16/25 table 8. write mode ac characteristics note: 1. the maximum value of this timing is applicable if e1 is kept low without any address change. if needed by system operation, please contact your local st representative for relaxation of the 1000ns limitation. 2. minimum value must be equal to or greater than the sum of the write pulse ( t eleh, t wlbh or t blbh and the write recovery time t whav . 3. write pulse is defined from the falling edge of e1 , w , or lb /ub , whichever occurs last. 4. applicable to byte masking only. byte masking set-up time is defined from the falling edge of e1 or w whichever occurs last. 5. applicable to byte masking only. byte masking hold time is defined from the rising edge of e1 or w whichever occurs first. 6. write recovery is defined from the rising edge of e1 , w , or lb /ub , whichever occurs first. 7. if g is low after t ghel (min), the read cycle is initiated. in other words, g must be brought high within t ghel (min) after e1 is brought low. once the read cycle is initiated, new write pulse should be input after t avax or t eleh minimum value. 8. if g is low after new address input, the read cycle is initiated. in other words, g must be brought high at the same time or before new address valid. once the read cycle is initiated, new write pulse should be input after t avax or t eleh minimum value. symbol alt. parameter m69aw024be unit ?60 min max t avax, t elax (1,2) t wc chip enable write cycle time 70 1000 ns t avel , t avbl , t avwl (2) t as address set-up time to chip enable low 0 ns t eleh (3) t cw chip enable write pulse width 45 ns t wlbh , t wlwh (3) t wp write enable write pulse width 45 ns t blwh , t blbh (3) t bw lb , ub pulse (write operation) 45 ns t bhwl (4) t bs lb , ub byte masking set-up time ?5 ns t whbl (5) t bh lb , ub hold time ?5 ns t whax, t ehax , t bhax (6) t wr write recovery time 0 ns t ehel t cp chip enable high pulse 10 ns t whwl t whp write enable high pulse 10 1000 ns t bhbl t bhp lb , ub high pulse 10 1000 ns t dveh , t dvwh , t dvbh t ds data set-up time 15 ns t ehdz , t whdz , t bhdz , t ghdz t dh data hold time 0 ns t ghel (7) t ohcl output enable high to chip enable low set-up time ?5 ns t ghav (8) t oes output enable set-up time 0 ns t blbh2 t bwo lb , ub low to lb , ub high for page access 30 ns
17/25 m69aw024be figure 10. write ac waveforms note: 1. e2 must be high during the write cycle. figure 11. w controlled, write ac waveforms note: 1. e2 must be high during the write cycle. address valid a0-a19 e1 w lb, ub g dq0-dq15 telax teleh twlwh tavel tavel tehax,twhax, tbhax tavwl tavwl tbhax tblwh tavbl tavbl tghel valid data input tdveh tdvwh tdvbh tehdz twhdz tbhdz ai09939 address valid tehel twhwl tbhbl a0-a19 address valid address valid low tavax tavax tavwl twlwh tavwl twlwh tghav tghdz dq0-dq15 twhdz tdvwh twhdz tdvwh ai09940 e1 w lb, ub g valid data input valid data input twhax twhax taxav tghax twhwl
m69aw024be 18/25 figure 12. write enable and ub /lb controlled, byte write ac waveforms 1 note: 1. e2 and g must be high during the write cycle. figure 13. write enable and ub /lb controlled, byte write ac waveforms 2 note: 1. e2 and g must be high during the write cycle. a0-a19 address valid address valid low taxav tavax tavax tavwl twlbh tbhax tavwl tbhax e1 w valid data input valid data input twlbh dq0-dq7 dq8-dq15 lb ub tdvbh tbhdz tdvbh tbhdz ai09941 twhwl tbhwl twhbl tbhwl twhbl a0-a19 address valid address valid low tavax tavax tavbl tblwh twhax tavbl twhax e1 w valid data input valid data input dq0-dq7 dq8-dq15 lb ub tdvwh twhdz tdvwh twhdz ai09942 twhwl tbhwl twhbl tbhwl twhbl tblwh
19/25 m69aw024be figure 14. write enable and ub /lb controlled, byte write ac waveforms 3 note: 1. e2 and g must be high during the write cycle. figure 15. write enable and ub /lb controlled, byte write ac waveforms 4 note: 1. e2 and g must be high during the write cycle. a0-a19 low tavax tavax tavbl tblbh tbhax tavbl tbhax e1 w valid data input valid data input tblbh dq0-dq7 dq8-dq15 lb ub tdvbh tbhdz tbvwh tbhdz ai09943 address valid address valid taxav twhwl tbhwl twhbl tbhwl twhbl a0-a19 low tavax tavax tavbl tblbh e1 w valid data input valid data input dq0-dq7 dq8-dq15 lb tdvbh tbhdz ai09944 tbhax tdvbh tbhdz valid data input ub valid data input tavbl tblbh tbhax tdvbh tbhdz tblbh2 tblbh tblbh2 tblbh tdvbh tbhdz tavbl tbhax tavbl tbhax address valid address valid tbhbl tbhbl
m69aw024be 20/25 table 9. standby, power-down and power-up ac parameters note: 1. applicable both to power-down and power-up. 2. some data might be written into any address location if t ehwl (min) is not satisfied. 3. the input transition time used in ac measurements is 5ns. 4. tbd = to be defined. figure 16. power-up mode ac waveforms - 1 note: t ehch2 is defined from v cc reaching v cc (min). figure 17. power-up mode ac waveforms - 2 note: t chel is defined from v cc reaching v cc (min) and applicable both for e1 and e2 signals. symbol alt. parameter m69aw024be unit ?60 min max t clel t csp e2 low setup time for power down entry 10 ns t elch t c2lp e2 low hold time after power down entry 80 ns t chel (1) t chh e1 high hold time following e2 high after power-down exit e1 high hold time following e2 high after power-up 300 s t ehch t chs e1 high setup time following e2 high after power-down exit 0 ns t ehgh t chox e1 high to g invalid time for standby entry 10 ns t ehwh (2) t chwx e1 high to w invalid time for standby entry 10 ns t (3) t input transition time 1 25 ns t ehch2 t c2lh power-up time 50 s ai07740b v cc v cc min e2 e1 tchel tehch2 tehch 0v ai09945 vdd tehel vddmin e1 e2
21/25 m69aw024be figure 18. power-down entry ad exit ac waveforms note: the power-down mode timing can also be used as a reset timing if the power-up mode timing cannot be satisfied. figure 19. standby mode entry ac waveforms, after read or write note: both t ehgh and t ehwh define the earliest entry timing for standby mode. if one of these timings is not satisfied, it takes a t avax (min) delay to enter standby mode from e1 rising edge. e2 e1 ai09946 power-down entry power-down mode dq0-d15 tehch tclel telch tchel power-down exit hi-z ai07741b e1 g w tehgh tehwh active (write) standby active (read) standby e1 g w high high
m69aw024be 22/25 package mechanical figure 20. tfbga48 6x8mm - 6x8 ball array, 0.75 mm pitch, package outline, bottom view note: drawing is not to scale. table 10. tfbga48 6x8mm - 6x8 ball array, 0.75 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.260 0.0102 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 3.750 ? ? 0.1476 ? ? ddd 0.100 0.0039 e 8.000 7.900 8.100 0.3150 0.3110 0.3189 e1 5.250 ? ? 0.2067 ? ? e 0.750 ? ? 0.0295 ? ? fd 1.125 ? ? 0.0443 ? ? fe 1.375 ? ? 0.0541 ? ? sd 0.375 ? ? 0.0148 ? ? se 0.375 ? ? 0.0148 ? ? e1 e d1 d e b a2 a1 a bga-z26 ddd fd fe sd se e ball "a1"
23/25 m69aw024be part numbering table 11. ordering information scheme the notation used for the device number is as shown in table 11. . for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest stmi- croelectronics sales office. example: m69aw024be 60 zb 8 f device type m69 = 1t/1c memory cell architecture mode a = asynchronous operating voltage w = 2.7 to 3.3v array organization 024 = 16 mbit (1m x16) option 1 b = 2 chip enable option 2 e = e die speed class 60 = 60ns package zb = tfbga48 6x8mm - 6x8 ball array, 0.75 mm pitch temperature range 8 = ?30 to 85 c packing option f = rohs compliant package, tape & reel packing
m69aw024be 24/25 revision history table 12. document revision history date rev. revision details 28-jun-2004 0.1 first issue 29-jun-2004 0.2 table 11., ordering information scheme updated. 22-mar-2005 1.0 t ehqx added in table 7., read and standby modes ac characteristics . t ghdz and t bhdz added in table 8., write mode ac characteristics . figure 19., standby mode entry ac waveforms, after read or write updated. rohs packing option added in features summary and table 11., ordering information scheme . t lead parameter added in table 3., absolute maximum ratings 05-apr-2005 2.0 figure title modified and note 2 added below figure 8.
25/25 m69aw024be information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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