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samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 1 chapter 1 introduction to KS9245 atapi automated cd-rom controller 1.0 introduction the KS9245 is a high performance single-chip cd-rom decoder with an atapi interface. the KS9245 integrates a buffer manager which supports a high performance 16-bit dram interface, cd-rom decoder, ecc engine, microcontroller interface, and atapi host interface logic. the chip decodes cd- rom media according to the sony-philips a cd-rom, cd-da ? , cd-rom/xa, cd-i and cd enhanced formats, and is designed for operation in a cost effective cd-rom drive system with industry standard drams, dsps, and microcontrollers. the KS9245 has sufficient data rates to support up to 50x speed cd-rom drives which can be daisy-chained to a hard drive through the ide/ata interface. thus, the KS9245 will continue to promote the cd-rom drive as a new standard device in multimedia pcs. the host interface logic supports atapi protocols and handles atapi packet commands all from hardware to maximize system performance and reduce firmware overhead. the atapi command and control block registers are included in the KS9245 ? s register set, allowing both the host and local microcontroller access. the KS9245 supports pio modes 3 and 4, dma modes 1 and 2, and ultradma modes 1 and 2, allowing for super fast host transfers. in addition, the KS9245 also supports command overlapping to prevent the slower cd-rom drive from becoming a bottleneck at the system level when daisy-chained to a faster eide/ata device. the buffer manager controls data flow between the host and a cd dsp. the buffer manager supports fast page mode and edo drams for high performance application. the buffer manager is programmable and provides all the necessary address and control signals for up to 512k bytes of dram. additionally, the buffer manager provides up to 42 mb/sec memory bandwidth with fast page dram and up to 80 mb/sec with edo dram for host transfers such as pio mode-3/4 and high speed cd-rom data access. the KS9245 uniquely integrates and automates the atapi sequences, cd cache manager, drq packet handler and scatter/gather features. this allows multiple block transfers of up to 1024k bytes in single burst and auto data transfers up to 128m bytes. the entire data transfer for atapi read, and read cd commands are completely processed by the KS9245 without firmware intervention. as a result, low cpu utilization is achieved in high speed cd-rom applications. the cd-da copy and audio data buffering is supported for audio application. the raw p-w subcode buffering and q- subcode de- intervealing with crc check are automated in the KS9245. the audio playback in cav mode is fully supported by KS9245. with superior cd-da concatenated techniques and audio hardware buffer manager, the KS9245 guarantees that the audio data can be played without losing audio frames during cav playback. the microcontroller interface supports high speed, low cost intel a and motorola a microcontrollers, such as the 8051 or 68hc11. it supports multiplexed address and data buses. thus, external glue logic previously required may be removed and system cost minimized. for further flexibility, four general purpose i/o pins are provided by the KS9245, which may be used for various control purposes, such as tray and volume control, etc.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 2 1.0.1 features summary general - fully compatible with atapi specification sff-8020i. - atapi command and control registers contained in the KS9245 register set. - automatic power-down on interfaces when idle. - supports up to 50x cd-rom drive. - 0.5 micron, low-power cmos technology. - 100-pin pqfp package. - low power consumption 0.6w typical. - system clock running at 33.868 / 50.8 mhz. buffer manager - advanced cd cache manger for low cpu utilization rate and auto data transfer. - advanced priority arbitration scheme to maximize buffer bandwidth for all requests. - multiple block transfer up to 1m bytes. - auto data transfer for read, read cd command up to 128m bytes. - external 16-bit wide dram supports up to 512k-bytes with edo option. - supports both physical or block addressing modes for microcontroller dram access. - scatter/gather host transfer for read cd command. - up to 42 mb/sec buffer bandwidth with fast page dram. - up to 80 mb/sec buffer bandwidth with edo dram. - up to 64 k bytes direct host transfer for toc data. atapi host interface - support industry standard ultradma mode 0, 1 and mode 2. - true real-time hardware/firmware atapi compatibility. - hardware implementation of atapi packet command receiving. - automated ata shadow command process. - automated atapi signature response. - automated protocol control on block transfers for atapi read commands. - automated command completion control for all atapi commands. - automated drq packet handler to obtain the best cpu utilization. - hardware service/release process for overlap command. - supports pio modes 3 and 4 bus transfer rate. - supports dma modes 0, 1 and 2 transfer rate. - provision for daisy-chaining two ata/ide or atapi-embedded drives. - supports automatic dasp handshake based on master or slave mode. cd-rom dsp interface - supports sony-philips a cd-rom, cd-da ? , cd-i and cd enhanced formats. - supports various compact dsp controllers such as philips, toshiba, sanyo, matsushita. - supports erasure correction up to 2 errors per codeword. - supports p,q correction up to 1 error per codeword. - repeated error correction support. - on-the- fly tm edc correction up to 50x data rate. - c2po error flags, raw subcode, and cd-da buffering support. - supports automatic sync pattern search and protection for dram data. - sector header validity check done by hardware during data transfer. - supports real-time de-interleaved q- subcode buffering and crc error checking.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 3 - supports serial dsp programming interface. - cd-to-dsp data transfer rates up to 50x drive speed. - audio playback in cav mode support. microcontroller interface - supports high speed intel a and motorola a microcontrollers, such as 8051 & 68hc11. - supports multiplexed address and data buses. - supports separate host/buffer and disk interrupt signals. - four general purpose i/o pins are provided. - interrupt or polled- microcontroller interface. - automatic power-down when idle; automatic power-up when command is received. - direct register access to facilitate low cpu utilization. 1.0.2 description of block diagram there are six key functional blocks integrated in the KS9245: 1) cd-rom dsp interface 2) buffer manager 3) host interface 4) microcontroller interface 5) ecc data corrector 6) edc-crc checker. the cd-rom dsp interface logic performs sync-mark detection and insertion for cd-rom sector synchronization. after descrambling and assembling data from the cd-dsp, the KS9245 sends the data through the on-the-fly-edc tm edc data checker before storing the data into buffer dram. the on-the-fly-edc tm logic then verifies the cd-dsp incoming data stream. if an error is encountered, the on-the-fly-edc tm logic invokes the ecc logic to correct the error. if no error is encountered, the ecc logic remains idle. the ecc correction code circuit performs circ error correction on each data block. the edc-crc checker then performs a cyclic redundancy check on the corrected data. all ecc correction, including erasure pointer correction, are done in real-time without microcontroller. this reduces firmware overhead and complexity, and minimizes microcontroller performance requirements.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 4 1.0.3 KS9245 functional block diagram ide bus gadd[19:0] gdin[7:0] mp bus dram interface subcode interface crc logic q de-interleave logic central dram control logic resource arbitration buffer manager cd cache manager packet fifo ide interface ata task file register atapi sequencer micro controller interface register decoding top block diagram transfer auto sequencer power manager data block sync detector subcode sync. detector cd dsp serial interface descrambler on the fly edc logic header and subheader logic form detector ecc logic address gen edc logic subcode data dsp data gdout[7:0] the buffer manager controls the data flow between the ide and dsp interfaces. these interfaces store and retrieve data to / from the external dram buffer memory using interleaved access cycles. the host interface supports atapi protocol, and provides the control for the corrected data to be transferred from the dram to the host cpu. diagnostic data can be transferred from the host cpu to the dram to allow testing of the ecc, edc, and host interface logic. the microcontroller interface logic allows the KS9245 to be controlled by the microcontroller through an 8-bit bus. the chip also provides registers and control functions for transferring data between the microcontroller and dram through microcontroller interface.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 5 1.1. functional and features description 1.1.1 microprocessor interface functional descriptions intel and motorola microprocessor interface support the KS9245 supports both intel and motorola type microprocessor interfaces with multiplexed addressing mode. in this mode, the microprocessor address and data lines are shared in ad0-7 pins. addresses are latched on the trailing edge of the ale signal. the rdb/wrb pins are used as read and write strobes respectively. supporting both intel and motorola type microprocessors directly enhances the flexibility of the KS9245. combined host/buffer and disk interrupt circuit the KS9245 supports host/buffer interrupts via the hintb pin and decoder/disk interrupts via the dintb pin. using separate interrupt signals, the interrupt priorities are easily realized. this increases the real- time firmware processing capabilities for high speed cd-rom applications. also, all interrupts can be combined onto the hintb pin by clearing the intmode bit in the interface configuration control register (0bh, bit 7). when power-on or reset occurs, the combined interrupt on the hintb pin is the default configuration. the host/buffer interrupt includes host command received, reset, or data transfer completed interrupts. the decoder interrupt includes cd decoder or subcode interrupts. the interrupt status is reported in the host interrupt status register (10h) and the decoder interrupt status register (11h). both hintb and dintb are active low, level triggered signals. with the organized interrupt control in the host interrupt clear/mask register (10h) and disk interrupt clear/mask register (11h), the firmware is ensured of obtaining interrupts without accidentally clearing or disabling of the interrupts. as a result, reliability of real-time process is achieved. polling mode for interrupt processing is also supported in the KS9245 by clearing the mask bits in host interrupt mask register (10h) and disk interrupt mask register (11h). direct register access from microprocessor the KS9245 supports direct register accesses. normally, no external glue logic is required to use this feature. using direct register access, firmware overhead is minimized and system performance enhanced. general purpose io pins support four general purpose i/o pins are supported in the KS9245. they are the gpio0-3 pins. also, these pins are shared with audio output pins awck/abck/adat. when the apce bit in the global configuration register (2f, bit 3) is set, these pins are configured as general purpose input or output functions. these pins can be configured as input or output by programming the port control register (44h, bit 7, bit 6, bit 5, bit4). these pins may be used for eject, cd tray, and volume, etc. controls without external glue logic. power management/auto wake-up support the sleep mode power management is supported by KS9245. in this mode, the decoder, buffer manager, and host interface circuits are in power savings mode. during sleep mode, the buffer dram contents are sustained by the KS9245 ? s internal refresh logic and the ata task file registers are available to the host. the sleep mode is enabled by setting ssleep bit in global control register (2fh,
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 6 bit7). sleep mode will automatically wake up and switch into the normal operation mode if the host has written a command to the atapi command register (07h) or ata reset occurs. the auto wake up is performed transparently and automatically. the sleep mode can only be applied when there is no host transfers and the decoder is in stop mode. thus, the KS9245 ? s power management features provides good solutions for power restricted environments. 1.1.2 atapi host interface functional descriptions the atapi interface logic is completely automated. the KS9245 can receive the atapi packet command and store the 12-byte command packet in a packet fifo. during data transfer stage, the atapi transfer protocols are processed by KS9245 without firmware intervention. when the total number of host requested blocks are transferred, the atapi command completion is posted if automatic command completion is enabled. automated dasp handle to increase master/slave compatibility the KS9245 will assert the daspb pin of the ata interface signals in the slave mode when power-on reset, hardware reset, or ata srst command is received. by asserting the daspb pin, it allows the master drive to identify the existence of the KS9245 as a slave drive. in some cases, the daspb signal is sampled by master drive as soon as the above event occurs. if the daspb signal does not assert fast enough, some master drives cannot recognize the existence of the slave drive. this feature is provided to insure the most compatibility in the master/slave handshaking sequence. the master or slave drive is configured by the mstb pin. the KS9245 will sample this pin when the above events occur. if the KS9245 is configured as a master drive, the pdiagb and daspb signals will be negated and left the slave drive to control these signals. additionally, the pdiagb and daspb pins can be asserted or negated by setting setdaspb, setpdiagb, clrdaspb, clrpdiagb bits in host interface control register (0ah, bit 6,5,2,1). the microprocessor can read daspb and pdiagb bits in the host interface signal value register (0ah, bit 2, 1) to get the values of the daspb and pdaigb signals of the ata interface. automated atapi signature process the atapi signature is the required information for host to identify an atapi device. the atapi signature is reported in the atapi byte count registers (04h, 05h) as 14h/ebh. the KS9245 will initialize the ata task file registers and setup the atapi signature automatically. moreover, the KS9245 supports the atapi signature for ata read and ata identify commands. the atapi signature is reported and command abort sequence will be posted by the KS9245 if the shadow feature is enabled. automated packet command receiving the KS9245 will process the atapi packet command (a0h) and receive 12-byte command packet after host has written the command packet into the atapi data register. the 12-byte command packet is stored in a packet fifo. the firmware is able to retrieve 12-byte command packet by consecutively reading the packet fifo register (00h). the 12-byte packet fifo is protected from over-run if more than twelve bytes have written. also, the data pointer of the packet fifo is reset whenever a new atapi command is received. the packet command interrupt mode assertion of the intrq line with the assertion of command packet drq is supported. this is enabled by setting the pcmdint bit in the interface configuration control register (0bh, bit 1). automated drq packet handle the KS9245 is able to calculate the transfer byte count and load it into the atapi byte count registers (04h, 05h) when host transfer occurs. moreover, the KS9245 will break the block-oriented transfers in the buffer manager into byte-oriented transfers in the atapi interface without firmware intervention. before a drq packet transfer starts, the atapi byte count registers are calculated and the atapi data transfer protocol are processed by the KS9245.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 7 automated bsy bit handle the bsy bit of atapi task file register is controlled by KS9245. it ensures that the protocol is in compliance with the ata specification. using this feature, the firmware is assured to be compatible with the win 95/os2/win nt operating systems. also, the bsy bit can be set or cleared by firmware as manual mode by setting setbsy or clrbsy bits in host interface control register (0ah, bit 7, 3), respectively . automated drq bit handle the drq bit in atapi status register is automated by the KS9245. the drq bit in the atapi status register is set automatically where appropriate. automated dsc bit handle the dsc bit in the atapi status register is fully automated. this is used to post overlap seek command completion. this sequence starts by setting the sdsc bit in the host sequence command register (0eh, bit 0). automated command completion handle the command with either successful or error completion sequence is supported by the KS9245. the sequence starts by setting the s cpl or scplchk bits in the host sequence command register (0eh, bit 2, 1) for atapi error or successful conditions, respectively. also, the automated command completion is extended into data transfers. with the completion of an entire host transfer, the atapi completion status is posted to the host if the acple bit in the transfer sequence command register is set (0fh, bit 6). atapi overlap command - service/release support overlap command operations are supported by the KS9245. the atapi release and service protocols are implemented by the KS9245. the release sequence starts by setting the srelease bit in the host sequence command register (0eh, bit 4). the service sequence starts by setting the sservice bit in the host sequence command register (0eh, bit 5). both interrupts on release or service can be disabled by setting the disserint or disrelint bits in the host interface diagnostic control 2 register (51h, bit 7, 6). automated ata shadow command support the shadow command is used when the drive is in the master mode and there is no slave drive connected. the KS9245 will abort the command without firmware intervention when the host has issued the command to a non-existent slave drive. the sequence is enabled by clearing the disshar bit in the interface configuration control register (0bh, bit 2) when the cdrv bit is cleared (0bh, bit 4) and the sshadow (0bh, bit 3) bit is set in the interface configuration control register. 1.1.3 buffer interface/manager functional descriptions the cd cache manager is supported by hardware in the KS9245. with the automated and integrated architecture, the data transfers for entire read and read cd command are achieved. the buffer manager state machine will monitor the buffer block count. the maximum number of blocks that can be automatically transferred is 64k blocks, or about 128m bytes. with the powerful drq packet handling of the KS9245, the host transfers are realized with very high performance. as a result, low cpu utilization for high speed cd-rom is achieved and code size minimized. the KS9245 supports up to 512k bytes of 16-bit fast page mode and edo (extended data output) drams. the cd data block are organized in either 2.5k bytes or 3k bytes per block. the cd data and subcode can be chosen to be buffered in both configurations. in the latter case, the buffering for c2po error flags and block error flags are included.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 8 all data blocks are linearly arranged without separating as auxiliary or data block. with the straight addressing mechanism, firmware overhead and programming mistakes are minimized. multiple block transfer support multiple block transfer is supported by the KS9245. the transfer block is specified in the current host transfer block length registers (18h, 19h). for multiple block transfers, up to 256 blocks, or 512k bytes, can be burst to the host without firmware intervention. in the atapi specification, the maximum host transfer in a single drq packet is 64k bytes. the KS9245 will send the maximum number of bytes in a drq packet transfer. automated transfer for entire read command the KS9245, with its advanced hardware cd cache manager, supports host transfers for entire read or read cd commands of up to 64k blocks , or 128m bytes, without firmware intervention. when the acache bit in the transfer sequence command register (0fh, bit 7) is set , the cd cache manger is enabled. at the completion of the total transfers specified in the total host transfer block length registers (16h, 17h), the atapi completion status will be posted to the host if the acple bit in the transfer sequence command register (0fh, bit 6) is set. also, the txfrdone bit in the host interrupt status register (10h, bit 7) will be set and a microprocessor interrupt will be generated if the txfrdonee bit in the host interrupt mask register (12h, bit 7) is set. scatter/gather support the KS9245 provides two sets of segment registers which specify the start offset address and the transfer byte lengths within a data block. when the transfer is completed in the first segment, the hardware will automatically chain the second segment and continue the host transfers. the advantage to using scatter/gather feature is to avoid breaking transfer into two or more sub-transfers if data is scattered within a block. two segment registers are specified in the transfer offset length low/high 1/2 (1eh, 1fh, 22h, 23h) and host block offset address low/high 1/2 registers (1ch, 1dh, 20h, 21h) . in a read cd command, the host requested data may not be in a contiguous location. for example, the 2048-byte data block and 294-byte c2po error flags are requested in the same transfer. the firmware can utilize this scatter/gather feature to chain these transfers together. cd cache manager a hardware cd cache manager is supported in KS9245. when the acache bit in the transfer sequence command register (0fh, bit 7) is set, the cd cache manager initiates the host transfer as soon as data is available in the cache. that is, the valid cache block count registers (14h, 15h) are not equal to zero, until the total host transfer block length registers (16h, 17h) is decreased to zero . the host transfer process is continuously monitored by hardware until all data are transferred. block address support all data blocks can be addressed by a sequential block number which starts from zero at the top of the buffer dram and ends at the last or bottom of the block address specified in the buffer bottom block address register (2ch). before starting host transfers, the host transfer block address low/high registers (1ah, 1bh) must be loaded with the starting block address. before starting the decoder transfers, the disk transfer block address register (38h) must be loaded with the starting block address. both host and disk address pointers are automatically increased by one when a block of data is transferred to host or from the disk. when these registers reach the values of buffer bottom block address register plus one, they are wrapped around to the top of the buffer dram. microprocessor physical and block access dram support both the physical and block addressing modes for accessing dram by the microprocessor are supported. the pamb bit in the buffer access control register (29h, bit 2) is used to specify the addressing mode. using physical address mode (pam), the dram physical address must be loaded into
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 9 the mp access physical address lsb/mid/msb registers (24h, 25h, 26h) . this mode is used for accessing the firmware variables such as toc data in the system area. using block address mode (bam), the block and offset addresses must be loaded into the mp block address register (26h) and mp block offset low/high address registers (24h, 25h) . this mode is used to access data within the cd by the KS9245. this allows the firmware to easily check the contents of the data block, such as sync pattern, without converting the block address into a dram physical address. the dram read or write operation will be initiated when the sdramrd and sdramwrt bits are set in the buffer access control register (29h, bit 0, 1), respectively. the data for read operations will be available in the mp access data port register (28h) after the drambsy bit of the buffer access control register is cleared (29h, bit 7). the data for write operation must be loaded into the mp access data port register (28h). the write operation will be completed when the drambsy bit of the buffer access control register is cleared (29h, bit 7). segmented buffer support the buffer dram is partitioned into two segments: the data and system areas. the data area, is used for storing the cd data block as cache area while the system area is for storing cd system information such as toc data , identify device information, inquiry data, and firmware variables. the system area starts below the last byte of the bottom of the block address which is specified in the buffer bottom block address registers (2ch, 2dh). therefore, the size of the system area can be adjustable by setting the buffer bottom block address registers (2ch, 2dh). up to 64k bytes direct transfer from dram host transfers from the system area is not limited to block boundaries. up to 64k bytes can be directly transferred from the buffer dram to the host. this allows the toc (table of contents) data to be transferred without the limitation of the 2.5k-byte or 3k-byte block boundary. this avoids having to break a transfer into multiple sub-transfers. as a result, the firmware can support the toc efficiently and code size is reduced. by setting the transfer offset length low/high 1/2 registers (1eh, 1fh, 22h, 23h) with the desired transfer length, the transfer will not complete until the total number of bytes specified in these registers are transferred. 1.1.4 cd decoder interface/manager functional descriptions the KS9245 supports various dsp devices such as toshiba, sony, sanyo, and matsushita by setting the dsp device type selection register (3eh). also, various subcode interface such as philips v4, eiaji and eiaj2 can be programmed by setting subcode device type selection register (42h). the main dsp data, c2po error flags, and subcode buffering are supported by setting the dsp channel sel bit in the buffer configuration control 1 register (2ah, bit 6, 4, 5). moreover, the KS9245 uses the c2po error flags to perform the erasure correction up to 2-byte error per codeword by setting the eracorr bit in the ecc control 1 register (3bh, bit 0). the q- subcode with de-interleaving and crc check are done by hardware. sync pattern protection logic is implemented in the KS9245 to prevent lost sync in the dsp incoming streams. the sync patterns in buffer dram are further protected to facilitate the read raw operations. this assures that the application is able to retrieve the correct sync pattern when sync insertion occurs. the decoder logic operates in various modes according to the setting of the decoder control register (3ah). the monitor mode is used to search the target block and synchronize the sync mark in the main data channel before data buffering operation occurs. in this mode, no buffering or ecc operation is active. the decoder interrupt occurs at the relative location of header or subheader of the incoming dsp data streams.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 10 the audio buffering mode is used for cd-da copy operations. in this mode, the descrambler, ecc, and edc logic are not active and a decoder interrupt is generated to the microprocessor for every 2352-byte. the buffering operation for data stream is active. the cd-da data can be accurately synchronized with the subcode data stream if the asynwrt bit in the ecc control 2 register (3ch, bit 3) is set. in the ecc mode, the descrambler, edc, and ecc are all active with various correction configurations. this mode is normally used for buffering cd data such as yellow book, cd-rom xa, or cd-i data. the correction modes are configured by setting the ecc control 1 register (3bh). the decoder interrupts occur at either the completion of on-the-fly-edc tm check when there is no edc error, or at the end of ecc operations in this mode. the decoder header min/sec/frame/mode registers (30h, 31h, 32h, 33h), decoder subheader 0-3 registers (34h, 35h, 36h, 37h), and the ecc status register (3dh) contains the information for the block just processed. the buffering only mode is used for processing yellow book mode 0 and 2 data. in this mode, only the descrambler is active. neither ecc nor edc logic will be applied in this mode. the settings of the ecc control 1 register (3bh) is ignored by hardware. the decoder interrupt occurs at the end of buffering a block to the buffer dram. if no correction is applied, there is a full sector time for firmware to process the decoder interrupt in most cases. for the KS9245, the maximum time allowed for firmware to process the interrupt is a half sector time. in the firmware sector process time of the hardware application note section, detailed information is provided for various disk speeds. on-the-fly-edc tm correction the KS9245 supports on-the-fly-edc tm correction. both yellow book mode 1 and xa mode 2, form 1 of incoming dsp data streams are automatically checked by the edc circuit. if there is no edc error, the decoder interrupt is immediately generated without further delay and no redundant ecc is applied. as a result, the buffer manager can transfer the data to host without ecc latency and lower cpu utilization is achieved. if there is an edc error, the consecutive ecc correction will be applied. on-the- fly-edc tm check can also resolve the buffer dram requirements. therefore, the KS9245 can support the high speed cd application up to 50x with standard drams. advanced erasure correction up to 2-byte error per codeword the KS9245 supports high performance erasure correction up to 2-byte error per codeword. the erasure correction is enabled by setting the eracorr bit in the ecc control 1 register (3bh, bit 0). the erasure correction logic uses the c2po error flags as correction indication. therefore, c2po error flags must be provided in this mode. the standard p and q parity correction are supported for 1-byte error per codeword. the p and q parity are enabled by setting the eccpen or eccqen bits in the ecc control 1 register (3bh, bit 2, 1). cd-da copy support the KS9245 also supports cd-da buffering operations. by setting the audiwrt bit in the decoder control register (3bh, bit 4), the decoder is placed into audio buffering mode. the decoder circuit starts to synchronize with the first left channel. if the asynwrt bit in the ecc control 2 register (3ch, bit 3) is set, the cd-da data stream will be synchronized with the subcode sync mark. as a result, the data of cd-da operations are smoothly connected for different accesses. in audio buffering mode, the internal counter is active and an interrupt is generated to the host for every 2352-bytes. audio playback in cav mode support in cav (constant angular velocity) applications, the KS9245 allows audio data to be buffered and played at regular cav speeds without changing the speed to clv (constant linear velocity) or single speed modes. along with the cd-da subcode synchronization techniques in KS9245, audio frame data
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 11 is guaranteed to be smoothly concatenated without losing audio frames during cav playback. in the KS9245, up to 50x cav operation in outer tracks is supported. the buffered audio data is output to the external audio dac at 44.1khz (word clock) in either eiaj or i2s audio formats regardless of the disk speed. also, the audio data underrun condition is masked by muting both output channels to guard against undesired audio noise. as results, in cav applications, the audio playback can be achieved by cd-rom controller in a low cost design. in order to simplify firmware efforts and efficiently control the audio playback sequences, the audio hardware buffer manager implemented will automatically keep track of the available audio block(s) in buffer dram. when this buffer is full, firmware is able to stop the dsp buffering operation. if the buffer is empty or underrun, the audio mute operation is automatically performed by hardware to avoid any noise from being outputted. the audio output pins can be selected and configured via the awck, abck, adat and ebuo pins. the clock source is derived directly from the system clock thus eliminating the need for another crystal for the audio clock. repeated correction support repeated correction is supported by the KS9245 for intensively non real-time correction environments. by setting the appropriate disk transfer block address registers (38h, 39h) and writing a one in the repcorr bit in the ecc control 2 register (3ch, bit 2), the correction is started. an interrupt will be generated with the decint bit set in the decoder interrupt status register (11h, bit 0) if the decinte bit in decoder interrupt mask register (13h, bit 0) is set. sync mark insertion support the sync mark insertion is supported by the KS9245. when the decoder is in the ecc, buffering only mode, or monitor mode, the sync insertion logic is active. this allows the dsp interface logic to recover from lost synchronization errors. if the decoder is in the monitor mode, the sync insertion logic will always re-synchronize with the most recent sync mark to insure that synchronization is never lost. q- subcode deinterleave with crc check support the 12-byte de-interleaved q subcode is supported by the KS9245. the de-interleaved q subcode data with four zeros data are written into buffer dram without firmware intervention. also, the crc check for q subcode is done by hardware and this crc result is reported in the subcode status register (41h, bit 7, 6) when a subcode interrupt occurs. real-time ecc and sector synchronized method support ecc operation starts as soon as the previous block has finished buffering operation with edc error. the ecc operation is synchronized with the sector sync pattern. as a result, the data block address for ecc operation is always one block behind the dsp buffering operation. because of the sector synchronized architecture of ecc corrections, blocks are processed in real-time. in other ? buffered data correction ? or ? delayed pipeline ecc correction ? methods, the buffer dram will quickly fill when some erroneous blocks occur. as a result, a consequent seek may be required. therefore, the real-time ecc correction of the KS9245 offers a superior correction scheme to other methods.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 12 1.2 KS9245 qfp pin diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 KS9245 100qfp bdat11 bdat4 bdat12 bdat3 bdat13 bdat2 bdat14 bdat1 bdat15 bdat0 awck/gp0 abck/gp1 adat/gp2 sub sfsy sbsy rck sbclk sdata lrclk c2poi xout hrstb dd7 dd8 dd6 dd9 dd5 dd4 dd11 dd3 dd12 dd2 dd13 dd1 dd0 dd15 diowb diorb iordy dmackb intrq iocs16b da1 badd4 badd3 badd5 badd2 badd1 badd7/ isel badd0 badd8 / msel rasb casb web bdat8 bdat7 bdat9 bdat6 bdat10 pdiagb daspb hintb wrb ale/rsb ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 dsp maindata interface ata host interface buffer dram interface dsp subcode interface dd10 xin /sysclk csb mstb dd14 dmarq microcontroller interface dauo/gp3 vss vss da0 da2 dintb vss vss badd6 / xsel vss vcc vss rstb vss arstb bdat5 vss cav audio interface note: badd0 (pin 89) should be pulled high by a 22k ohm resistor for ks9246 compatibility.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 13 1.3 pin assignment the pin assignments are listed in sequential order of pin number with short description in the following table. symbol and convention d open-drain pin used as an open-drain signal o output pin used as an output signal i input pin used as an input signal t tristate pin used as a tristate signal t to pin is an output signal to outside component f from pin is an input signal from outside component x don ? t care pin may either be used or not used mp microprocessor or microcontroller dsp cd dsp main data channel interface dspsub cd dsp subcode interface dram dynamic random access memory host ide host master ide master drive, drive 0 slave ide slave drive, drive 1 dac external audio dac physical pin assignment signal pin i/o description source/ destination bdat5 1 i/o dram data bus 5 t, f, dram bdat11 2 i/o dram data bus 11 t, f, dram bdat4 3 i/o dram data bus 4 t, f, dram bdat12 4 i/o dram data bus 12 t, f, dram bdat3 5 i/o dram data bus 3 t, f, dram bdat13 6 i/o dram data bus 13 t, f, dram bdat2 7 i/o dram data bus 2 t, f, dram bdat14 8 i/o dram data bus 14 t, f, dram bdat1 9 i/o dram data bus 1 t, f, dram
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 14 physical pin assignment signal pin i/o description source/ destination vss 10 i ground - bdat15 11 i/o dram data bus 15 t, f, dram bdat0 12 i/o dram data bus 0 t, f, dram awck/gp0 13 i/o audio word clock output or general purpose i/o line 0 t,dac abck/gp1 14 i/o audio bit clock output or general purpose i/o line 1 t,dac adck/gp2 15 i/o audio data output or general purpose i/o line 2 t,dac dauo/gp3 16 i/o digital audio output or general purpose i/o line 3 t,dac rstb 17 i chip power on reset - sub 18 i subcode serial data in f, dspsub sfsy 19 i subcode frame sync f, dspsub sbsy/cflg 20 i eiaj subcode block sync / cflag f, dspsub rck 21 i/o subcode bit clock t, dspsub sbclk 22 i dsp bit clock f, dsp sdata 23 i dsp channel data f, dsp lrclk 24 i dsp left channel clock f, dsp c2poi 25 i c2po error flags f, dsp vss 26 i ground - xout 27 o oscillator output t,oscillator xin/sysclk 28 i oscillator input/system clock input normally, 33.868 mhz / 50.8mhz f,oscillator arstb 29 o atapi 08 cmd reset t, mp csb 30 i chip select f, mp ad0 31 i/o microprocessor data/address bus 0 t, f, mp ad1 32 i/o microprocessor data/address bus 1 t, f, mp ad2 33 i/o microprocessor data/address bus 2 t, f, mp ad3 34 i/o microprocessor data/address bus 3 t, f, mp vss 35 i ground - ad4 36 i/o microprocessor data/address bus 4 t, f, mp ad5 37 i/o microprocessor data/address bus 5 t, f, mp ad6 38 i/o microprocessor data/address bus 6 t, f, mp ad7 39 i/o microprocessor data/address bus 7 t, f, mp vcc 40 i power -
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 15 physical pin assignment signal pin i/o description source/ destination ale rsb 41 i microprocessor address latch enable address register select in indirect access mode. f, mp rdb dsb 42 i microprocessor read strobe (intel) data strobe signal (motorola) f, mp wrb r/wb 43 i microprocessor write strobe (intel) read/write strobe (motorola) f, mp hintb 44 od microprocessor host interrupt t, mp dintb 45 od microprocessor disk interrupt t, mp vss 46 i ground - mstb 47 i master/slave configuration drive sel daspb 48 i/o ide drive active-slave present mast/slave cs3fxb 49 i ide host chip select 1 f, host cs1fxb 50 i ide host chip select 0 f, host da2 51 i ide host address 2 f, host da0 52 i ide host address 0 f, host pdiagb 53 i/o ide passed diagnostics mast/slave da1 54 i ide host address 1 f, host iocs16b 55 od ide 16-bit data transfer t, host intrq 56 ot ide host interrupt request t, host dmackb 57 i ide host dam acknowledge f, host iordy 58 ot ide i/o channel ready t, host diorb 59 i ide i/o read strobe f, host diowb 60 i ide i/o write strobe f, host dmarq 61 ot ide drive dma request t, host vss 62 i ground - dd15 63 i/o ide host data bus 15 t, f, host dd0 64 i/o ide host data bus 0 t, f, host dd14 65 i/o ide host data bus 14 t, f, host dd1 66 i/o ide host data bus 1 t, f, host dd13 67 i/o ide host data bus 13 t, f, host dd2 68 i/o ide host data bus 2 t, f, host dd12 69 i/o ide host data bus 12 t, f, host dd3 70 i/o ide host data bus 3 t, f, host
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 16 physical pin assignment signal pin i/o description source/ destination vss 71 i ground - dd11 72 i/o ide host data bus 11 t, f, host dd4 73 i/o ide host data bus 4 t, f, host dd10 73 i/o ide host data bus 10 t, f, host dd5 75 i/o ide host data bus 5 t, f, host dd9 76 i/o ide host data bus 9 t, f, host dd6 77 i/o ide host data bus 6 t, f, host dd8 78 i/o ide host data bus 8 t, f, host dd7 79 i/o ide host data bus 7 t, f, host hrstb 80 i ata host reset - badd4 81 o dram address line 4 t, dram badd3 82 o dram address line 3 t, dram badd5 83 i/o dram address line 5 must also be pulled up by 22k ohm resistor t, dram badd2 84 o dram address line 2 f, dram vss 85 i ground - badd6/xsel 86 i/o dram address line 6 22k pull-up for 50.8mhz sysclk 10k pull-down for 33.86mhz sysclk t, dram badd1 87 o dram address line 1 t, dram badd7/isel 88 i/o dram address line 7 pull-up for mp register indirect select pull-down for mp register direct select t, dram badd0 89 o dram address line 0 should be pulled up by 22k resistor t, dram vcc 90 i power - badd8/mse l 91 i/o dram address line 8 pull-up for motorola mp select pull-down for intel mp select t, dram rasb 92 o dram rasb line t, dram casb 93 o dram, casb line t, dram web 94 o dram write enable t, dram bdat8 95 i/o dram data bus 8 t, f, dram vss 96 i ground - bdat7 97 i/o dram data bus 7 t, f, dram bdat9 98 i/o dram data bus 9 t, f, dram bdat6 99 i/o dram data bus 6 t, f, dram bdat10 100 i/o dram data bus 10 t, f, dram
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 17 1.4 pin description 1.4.1 pin description in ata host interface cs1fxb (drive chip select 0) pin 50 this is the chip select signal decoded from the host address bus used to select the command block registers. cs3fxb (drive chip select 1) pin 49 this is the chip select signal decoded from the host address bus used to select the control block registers. da0,1,2 (drive address bus) pin 52,54,51 this is the chip select signal decoded from the host address bus used to select the control block registers. daspb (drive active slave present) pin 48 this is a time-multiplexed signal which indicates that a drive is active or drive 1 is present. this signal is an open collector output with a 10k ohm pull-up resistor. dd0-dd15 (drive data bus) pin 64,66,,68,70,73,75,77,79, 78,76,74,72,69,67,65,63 these signals are used for 16-bit bidirection data bus between the host and the KS9245. the dd0-7 are used for accessing 8-bit ata task file registers. in atapi data transfer mode, it is always 16-bit wide. diorb (drive i/o read) pin 59 this is the read strobe signal. the rising edge of diorb enables data from a register or the data port of the KS9245 onto the host data bus, dd0-dd7 or dd0-dd15. the rising edge of diorb latches data at the host. in ultra dma mode, this signal is used by the host as the dmardyb signal during host reads, and as the data strobe signal during host writes. diowb (drive i/o write) pin 60 this is the write strobe signal. the rising edge of diowb clocks data from the host data bus, dd0- dd7 or dd0-dd15, into the data port of the KS9245. in ultra dma mode, this signal is used by the host as the stop signal. dmackb (dma acknowledge) pin 57 this signal is used by the host in response to dmarq to either acknowledge that data has been accepted, or that data is available. dmarq (dma request) pin 61 this signal is used for dma data transfer between host and KS9245. it is asserted by the KS9245 when it is ready to transfer data to or from the host. the direction of transfer is controlled by diorb and diowb. this signal is used in a handshake manner with dmackb signal. when a dma operation is enabled, iocs16b, cs1fxb and cs3fxb are not asserted and data transfer are 16-bits wide. iordy (host io ready) pin 58
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 18 this signal is deasserted in order to extend the host access when KS9245 is not ready to response to the request. in ultra dma mode, this signal is used by the KS9245 as the drive ? s dmardyb signal during host writes, and as the drive ? s data strobe signal during host reads. intrq (drive interrupt) pin 56 this signal is used to interrupt the host. intrq pin is asserted only when the KS9245 has a pending interrupt while the drive is selected, and the host has cleared nien in the ata device control register. if nien=1 or the drive is not selected, this output is in a high impedance state, regardless of the presence or absence of a pending interrupt. iocs16b (device 16-bit i/o) pin 55 except for dma transfers, ioc16b indicates to the host that the 16-bit data port has been addressed. this is an open collector output. in atapi pio data transfer mode, the iocs16b shall always be asserted. pdiagb (drive passed diagnostics) pin 53 this signal is asserted by drive 1 (slave drive) to indicate to drive 0 (master drive) that it has completed diagnostics. a 10k ohm pull-up resistor is used on this signal by each drive on the same cable. hrstb (ata host reset) pin 80 this signal from the host system is asserted for at least 25 usec after voltage levels during power-on and negated thereafter unless some event requires that the drive be reset following power on. when this input signal is asserted, the ata task file registers will be initialized and the bsy bit in ata status register will be set. the hrst bit in host interrupt status register will be set (10h, bit 3) , if hrste bit in host interrupt mask register (12h, bit 3) is set. 1.4.2 pin description in buffer dram interface bdat 0-15 (buffer dram data bus) pin 12,9,7,5,3,1,99,97,95,98,100,2,4,6, 8,11 these signals are used for buffer dram data bus with 16-bit parallel data path to/from the buffer memory. badd 0-8 (buffer dram address bus) pin 89,87,84,82,81,83,86,88,91 these signals are used for buffer dram address bus. up to 512k bytes dram are supported by KS9245. important: badd5 pin 83 must also be pulled high by a 22k ohm resistor. casb (column address strobe) pin 93 this signal is used as column address strobe for buffer dram. rasb (row address strobe) pin 92 this signal is used as row address strobe for buffer dram. web (dram write enable) pin 94 this signal is used as the memory write enable for buffer dram.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 19 1.4.3 pin description in microprocessor interface ad0-7 (microprocessor address and data bus) pin 31,32,33,34,36,37,38,39 these signals are bi-directional multiplexed microprocessor address and data lines. ale (address latch enable) pin 41 rsb (register select) the falling edge of this signal is used as address latch for register access in intel mode. this signal is used as address register select in indirect register access mode. in this mode, rsb pin is asserted as logic low state for address register and rsb pin is negated as logic high state for data register. rdb (microprocessor read strobe) pin 42 dsb (data strobe) this signal is used as the read strobe signal in intel multiplexed register addressing mode. when the motorola microprocessor is selected, this signal is acted as data strobe signal. wrb (microprocessor write strobe) pin 43 r/wb (r/w strobe) this signal is used as the write strobe signal in intel multiplexed register addressing mode. when the motorola microprocessor is selected, this signal is acted as read/write strobe signal. hintb (microprocessor host/buffer interrupt) pin 44 this signal is asserted as logic low state when interrupt status is available to microprocessor. this interrupt indicates there is at least one host or buffer event which needs to be serviced by microprocessor. dintb (microprocessor disk interrupt) pin 45 this signal is asserted as logic low state when interrupt status is available to microprocessor. this interrupt indicates there is at least one decoder or disk event which needs to be serviced by microprocessor. the disk interrupt can be combined with host interrupt in hintb signal by clearing intmode bit in interface configuration control register (0bh, bit 7). the combined mode is the default mode at power-on. csb (chip select) pin 30 this signal must be asserted as logic low state for accessing registers of KS9245. msel (microprocessor select) pin 91 this pin is used to select the motorola microprocessor when it connects with pull-up resistor 22k. otherwise, with pull-down resistor 10k, the intel microprocessor is selected. this pin is sampled only when isel pin is negated at the power on stage. isel (microprocessor indirect register access select) pin 88 this pin is used to select the indirect register access mode when it connects with pull-up resistor 22k. otherwise, with pull-down resistor 10k, the direct register access mode is selected. this pin is sampled only at the power on stage. in the indirect register access mode, the ale/rsb pin is used to select register input. when rsb is asserted, the address register is selected. when rsb is negated, the internal register addressed by address register is accessed by microprocessor. 1.4.4 pin description in dsp interface
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 20 sub ( subcode serial data in) pin 18 this pin is used to input the subcode channel data. sfsy ( subcode frame sync) pin 19 this pin is used to indicate the subcode frame sync mark. the subcode data is available at the falling edge of this signal. in philips v4 subcode mode, this pin should be grounded. sbsy/ cflg ( subcode block sync/clag) pin 20 this pin is used to indicate the subcode block sync mark. in philips v4 subcode mode, this pin should connect to cflag. rck ( subcode clock) pin 21 this pin is used to input, output and clock the subcode data from dsp. in philips v4 subcode mode, this pin should not be connected. lrclk (dsp left channel clock) pin 24 this pin is used to indicate the left/right channel data. sdata (dsp main channel data) pin 23 this pin is used to input the dsp main channel data. sbclk (dsp bit clock) pin 22 this pin is used to input the data clock of dsp main channel. c2poi (c2 pointer input) pin 25 this pin is used to indicate the error flags of dsp main channel data. 1.4.5 pin description in power/ground/rest pins vss (ground) pin 10,26,35, 46,62,71,85,96 vdd (power supply with 5 volt source) pin 40,90 1.4.6 pin description in system configuration mstb (master/slave configuration) pin 47 this signal is used to inform the KS9245 that the drive is configured as master or slave. when this signal is asserted as logic low state, it indicates the drive is configured as master. when this signal is negated as logic high state, it indicates the drive is configured as slave. the daspb signal will be asserted when the mstb pin is negated (slave mode) during power- on/hardware reset/ata srst. the pdiagb signal will be negated when the mstb pin is asserted (master mode) during power- on/hardware reset/ata srst and ata diagnostic command.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 21 rstb (chip reset) pin 17 a logic low input will reset the KS9245. all host interface outputs are set to the high-impedance state. the registers of KS9245 will be initialized as their default values. arstb (atapi 08 cmd reset) pin 29 a logic low pulse with 40 usec will be asserted when host issues the atapi reset command (08h) to the KS9245. this signal could use as the pulse to reset the micro-controller. the output of 60 usec clock pulse is assumed that the system clock of 33.8688 mhz is used. xin/sysclk (crystal or system clock input) pin 28 this signal is the crystal or cmos-level clock input as system clock. the KS9245 contains an internal resister between xin/xout. there is no external resister required to connect these pins. the standard crystal or cmos-level clock is either 33.8688 mhz or 50.8mhz. xout (oscillator output) pin 27 this signals is the oscillator output. xsel (system clock select) pin 86 the KS9245 supports two frequencies. this pin can use an external jumper select to configure for either 33.86mhz or 50.8mhz. this pin should be pulled-up by a 22k ohm resistor for 50.8 mhz operation, and strapped-down by a 10k ohm resistor for 33.86mhz operation. gpi 0-3 (general purpose input/output lines) pin 13,14, 15, 16 these signals are used as general purpose input pins. the input or output can be configured by setting or clearing the gpc3, gpc2, gpc1, gpc0 bits in port control register (44h, bit 7,6,5, 4) and apce bit in global control register (2fh, bit3) is cleared. 1.4.7 pin description in audio dac interface dauo ( digital audio output) pin 16 this pin is used to output the digital audio as iec-958 format. this bit is enabled when apce bit in global control register (2fh, bit 3) is set. adat (audio data output) pin 15 this pin is used to as a audio data output pin when the audio playback in cav mode is selected to be used. this bit is enabled when apce bit in global control register (2fh, bit 3) is set. abck (audio bit clock output) pin 14 this pin is used to as a audio bit clock output pin. this bit is enabled when apce bit in global control register (2fh, bit 3) is set. awck (audio word clock output) pin 13 this pin is used to as a audio word clock output pin. this bit is enabled when apce bit in global control register (2fh, bit 3) is set.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 22 1.4.8 register map for KS9245 page # addres s name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 host interface registers (chapter 2) 00h r pfifo packet fifo register 01h r afeat reserved overlap dma 01h w aerr sense key mcr abrt eom ili 02h r asecc ata sector count register 02h w aintr reserved releas e io cod 03h r/w asam atapi sam tag register/ ata sector number 04h r/w abcl atapi byte count low register/ ata cylinder low register 05h r/w abch atapi byte count high register/ ata cylinder high register 06h r/w adsel rsvd lba rsvd drv reserved 07h r acmd atapi command register/ ata command register 08h r adcv reserved rsvd srst nien rsvd 09h r aistat bsy drdy rsvd dsc drq corr rsvd check 09h w hsc rsvd drdy rsvd dsc drq corr rsvd check 0ah r hisv reserved mstb daspb pdiagb 0 0ah w hic setbsy setdas pb setpdia gb sethin t clrbs y clrdasp b clrpdiag b clrhint 0bh r/w icc intmod e ata transfer mode cdrv sshado w disshad r pcmdint disiordy 0ch reserved 0dh reserved hardware sequence command registers (chapter 3) 0eh w hsc rsvd saabort sservic e srelea se stfini t scpl scplchk sdsc 0fh w tsc acache e acple rsvd ssxfr sabor t spaus e wrdir sdxfr 0fh r tss acache e acple reserved spaus e wrdir hxfrbsy microprocessor interrupt registers (chapter 4) 10h r/w hisr/hi cr txfrdon e rsvd asrst srst hrst scmdrc v acmdrc v pcmdrcv 11h r/w disr/di cr reserved dacint subint decint 12h r/w him txfrdon ee cxfrdone e asrste srste hrste scmdrc ve acmdrc ve pcmdrcv e 13h r/w dim reserved dacinte subinte decinte buffer/cd cache manger registers (chapter 5) 14h r/w vcbcl valid cache block count register b7:b0 15h reserved 16h ttbll total host transfer block length register b7:b0
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 23 r/w 17h reserved 18h r/w chtbl current host transfer block length register b7:b0 19h reserved 1ah r/w htbla host transfer block address low register b7:b0 1bh r/w reserved
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 24 page addres s name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1ch r/w hboal1 host block offset address low 1 register b7:b0 1dh r/w hboah1 reserved b11 b10 b9 b8 1eh r/w toll1 transfer offset length low 1 register b7:b0 1fh r/w tolh1 reserved b11 b10 b9 b8 20h r/w hboal2 host block offset address low 2 register b7:b0 21h r/w hboah2 reserved b11 b10 b9 b8 22h r/w toll2 transfer offset length low 2 register b7:b0 23h r/w tolh2 reserved b11 b10 b9 b8 24h r/w mpalsb mboal mp access physical address lsb b7:b0 mp block offset address low register b7:b0 25h r/w mpamid mboah mp access physical address mid b15:b8 mp block offset address high register b11:b8 26h r/w mpams b mba mp access physical address msb b18:b16 mp block address register b7:b0 27h reserved 28h r/w mpdp mp access data port register b7:b0 29h r bac drambs y reserved pamb rsvd rsvd 29h w bac incaudc nt incblkcnt reserved pamb sdramwr t sdramrd 2ah r/w bcc1 c2error dsec ssel csel blkcon f dramsz 2bh r/w reserved 2ch r/w bbba buffer bottom block address register b7:b0 2dh r/w reserved 2eh r/w drcr dram resfresh control register 2fh r/w gcr ssleep sfreset burstnu m dspbur st apce cspeed[2:0] cd block decoder registers (chapter 6) 30h r dhmin decoder header min register 31h r dhsec decoder header sec register 32h r dhfram e decoder header frame register 33h r dhmode decoder header mode register 34h r dsubh0 decoder subheader 0 register 35h r dsubh1 decoder subheader 1 register 36h r dsubh2 decoder subheader 2 register 37h r dsubh3 decoder subheader 3 register 38h r/w dtba disk transfer block address register
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 25 39h reserved 3ah r/w dcr reserved audmo n audiwrt eccrq decwrt decen descen 3bh r/w ecc1 xamode reserved edcen eccpen eccqen eracorr 3ch r/w ecc2 reserved packetw r asynwrt repcor r rsvd rsvd
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 1- 26 page addres s name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3dh r/w desr invalid overr eccfat eccerr cblk nosync illsync rsvd 3eh r/w ddts rsvd bckd1 fps bcklength lsbf lch bckf 3fh r dher esh0 esh1 esh2 esh3 emin esec eframe emode 40h r/w reserved 41h r ssr scrcerr suberr reserved 42h r/w sdts sub format selection reserved 43h r vcr version number 44h r/w pcr gpc3 gpc2 gpc1 gpc0 gp3 gp2 gp1 gp0 45h r/ w reserved 46h r/ w reserved 47h reserved 48h r/ w vabc valid audio block count register b7:b0 49h reserved 4ah r/ w daba dac block address register b7:b0 4bh reserved 4ch r/w dofs adat18 abckd1 afps abckl alsbf alch abckf 4dh r/w dacr reserved acc spa 4eh r/w accr rsvd abps daue dovs dscd xina div 4fh r/w avcr lcm rcm reserved vol diagnostic miscellaneous registers (chapter 7) not used for normal operations 50h reserved 51h reserved 52h reserved 53h reserved 54h reserved 55h reserved 56h reserved 57h reserved 57h reserved 58h reserved enhancement control registers (chapter 8) 60h r/w udtr uderr reserved udmacyc[2:0]
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 2- 1 chapter 2 ata/atapi host interface registers 2.1 ata task file registers the ata task file registers can be addressed by cs1fx/cs3fx/da2/da1/da0 pins of ata interface signal. the ata task file registers are specified as follows: cs1fxb cs3fxb da2 da1 da0 da2-0 host read host write a n 0 0 0 00h ata data register atapi data register ata data register atapi data register a n 0 0 1 01h ata error register atapi error register ata features register atapi features register a n 0 1 0 02h ata sec count register atapi interrupt reason register ata sec count register atapi reserved a n 0 1 1 03h ata sec number register atapi sam tag register ata sec number register atapi sam tag register a n 1 0 0 04h ata cyl. low register atapi byte count low register ata cyl. low register atapi byte count low register a n 1 0 1 05h ata cyl. high register atapi byte count high register ata cyl. high register atapi byte count high register a n 1 1 0 06h ata drive sel register atapi drive sel register ata drive sel register atapi drive sel register a n 1 1 1 07h ata status register atapi status register ata command register atapi command register n a 1 1 0 06h ata alternate status register atapi alternate status register ata device control register atapi device control register note: ? a ? represents signal asserted. ? n ? represents signal negated. when the bsy or drq bits are set in the status register, the task file registers are owned by the KS9245. when this occurs, the host cannot write to the task file registers. also, when the bsy bit is set, all task file registers will contain the same values as the ata status register. 2.2 host interface registers register 00h : packet fifo register (read) acronym: pfifo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 atapi packet fifo register the packet fifo register contains 12 bytes for receiving the packet command. after the host writes the packet command (a0h) into the atapi command register , the KS9245 will automatically be set to receive 12-bytes of command packet from the host to store into the packet fifo register . the firmware should then perform consecutive read operations from this register to obtain the 12-byte packet command. register 01h : atapi features register (read)
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 2- 2 ata features r egister (read) acronym: afeat bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsvd reserved (tag type) reserved overlap dma the atapi features register contains the specific features (such as dma/pio mode or overlap operation) which the host requests the drive to perform. bit 7-2: reserved these bits are reserved for future enhancements. bit 1: overlap when this bit is set during the issuance of an atapi packet command, the KS9245 may release the ata bus prior to the completion of that packet command. in this case, the KS9245 will use the release bit in it ? s atapi interrupt reason register (reg02h, bit2) to inform the host that it has released the ata bus before completing the command in progress. bit 0: dma when dma bit is set, data transfers for the command will use the dma channel. when the dma bit is cleared, data transfers for the command will be pio mode. firmware uses this bit to configure pio or dma mode for host data transfers. the ata transfer mode bits in the interface configuration control register (reg0bh, bits6,5) are used to select various transfer modes. register 01h : atapi error register (write) ata error register (write) acronym: aerr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sense key mcr abrt eom ili the atapi error register contains the errors at the command process or completion stage. the firmware must set the appropriate error bits and sense key code when an error occurs in the command processing stage. bit 7-4: sense key these bits contain the sense key information. bit 3: mcr (media change requested) when this bit is set, it indicates that a media change has occurred. bit 2: abrt (abort) when this bit is set, it indicates that the command has been aborted. bit 1: eom (end of media) when this bit is set, it indicates that the end of media has been reached.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 2- 3 bit 0: ili (illegal length indication) when this bit is set, it indicates that an illegal length has occurred in the command processing stage. register 02: ata sector count register (read) acronym: ase cc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ata sector count register the ata sector count register contains the number of sectors to be transferred for the ata operation. this register is reserved in atapi mode. register 02: atapi interrupt rea son register (write) acronym: aintr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved release io cod the atapi interrupt reason register contains the causes of interrupt when the KS9245 asserts the intrq signal to the host. the atapi interrupt reason register and the atapi status register are interpreted together to indicate the correct atapi command phase as follows: io drq cod command phase 0 1 1 command from host - command receiving phase 1 1 0 data to host - data sending phase 0 1 0 data from host - data receiving phase 1 0 1 completion status - command completion status bit 7-3: reserved these bits are reserved for future enhancements bit 2: release when this bit is set, it indicates to host that the device has released ata bus prior to completing the current overlapped command. bit 1: io (in/out) this bit indicates the direction for the information transfer. when this bit is set, the transfer direction is from the KS9245 to the host. when this bit is reset, the transfer direction is from the host to the KS9245. bit 0: cod (command/data) this bit distinguishes between command or data information. when this bit is set, the information being transferred is user data. when this bit is reset, the information transferred is command data.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 2- 4 register 03: atapi sam tag register (read/write) ata sector number (read/write) acronym: asam bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 atapi sam tag value (reserved) the atapi sam tag register contains the sam tag number for atapi/ata operations. this register is reserved in atapi mode. register 04: atapi byte count low register (read/write) ata cylinder low register (read/write) acronym: abcl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 atapi byte count low register the atapi byte count low/high registers contain the maximum byte count for each host drq packet transfers. register 05: atapi byte count high register (read/write) ata cylinder high register (read/write) acronym: abch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 atapi byte count high register see the atapi byte count low register description. register 06: atapi drive select register (read/write) ata drive select register (read/write) acronym: adsel bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsvd lba rsvd drv reserved for sam lun bit 7: rsvd (reserved) this bit is reserved for future enhancements. bit 6: lba (logic block adddress) this bit is reserved in atapi mode. bit 5: rsvd (reserved) this bit is reserved for future enhancements. bit 4: drv (drive select) when this bit is set, it indicates that drive 1 (slave drive) is selected. when this bit is reset, it indicates that drive 0 (master drive) is selected.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 2- 5 bit 3-0: reserved for sam lun these bits are reserved for future enhancements. register 07: atapi command register (read) ata command register (read) acronym: acmd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 atapi command register the atapi command register contains the command operation code. register 08h: atapi device c ontrol register (read) ata device control register (read) acronym: adcv bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved srst nien rsvd the atapi device control register contains the information for ata soft reset and host interrupt control. bit 7-3: reserved these bits are reserved for future enhancements. bit 2: srst (ata soft reset) when the host writes a one to srst bit of the ata device control register , an ata soft reset is performed. bit 1: nien (host interrupt enable) when the host writes a ? 0 ? to the nien bit and the KS9245 selected, the intrq signal is enabled. when the host writes a ? 1 ? to this bit or the KS9245 is not selected, the intrq signal is tri-stated. bit 0: reserved this bit is reserved for future enhancements. register 09h: atapi image status register (read) ata image status register (read) acronym: aistat bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bsy drdy rsvd dsc / service drq corr rsvd check this register contains an image of the atapi status register . by reading this register, the firmware can obtain the real-time value of the atapi status register in the ata task file. bit 7: bsy (busy) when this bit is set, the KS9245 is busy or in the state of accessing ata task file registers.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 2- 6 bit 6: drdy (drive ready) when this bit is set, the drive is capable of responding to a command. bit 5: rsvd (reserved) this bit is reserved for future enhancements. bit 4: dsc/service (disk seek complete/service request) this bit is set when a seek operation completes. bit 3: drq (data request) this bit is set when the KS9245 is ready to transfer data to or receive data from the host. bit 2: corr (correction occurred) this bit is set to indicate that a correctable error occurred during the processing of a command. bit 1: rsvd (reserved) this bit is reserved for future enhancements. bit 0: check (check condition) this bit is set to indicate that an error occurred during execution of the command. register 09h: host status control register (write) acronym: hsc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsvd drdy rsvd dsc / service drq corr rsvd check the host status control register controls the atapi status register of the ata task file. bit 7: rsvd (reserved) this bit is reserved for future enhancements. bit 6: drdy (drive ready) when this bit is set, the drive is ready. bit 5: rsvd (reserved) this bit is reserved for future enhancement. bit 4: dsc/service (disk seek complete/service request) this bit is set when the seek operation completes. bit 3: drq (data request) this bit is set when the KS9245 is ready to transfer data to or receive data from the host. bit 2: corr (correction occurred) this bit is set when a correctable error occurs during the processing of the command. bit 1: rsvd (reserved) this bit is reserved for future enhancements. bit 0: check (check condition)
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 2- 7 this bit is set when an error occurs during execution of the command. register 0ah: host interface signal value register (read) acronym: hisv bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved mstb daspb pdiagb 0 the host interface signal value register monitors the ata interface signals. the microprocessor can read this register to check the state of the mstb/daspb/pdiagb signals. for example, the pdiagb and daspb signals are required by firmware to process master/slave handshaking. bit 7-4: reserved these bits are reserved for future enhancements. bit 3: mstb (mstb master/slave pin signal) this bit reflects the state of the mstb pin. this bit is ? 1 ? when the mstb pin is high. this bit is ? 0 ? when the mstb pin is low. bit 2: daspb (daspb signal of ata interface) this bit reflects the physical state of the daspb pin. when this bit is ? 1 ? , the daspb pin is high (not asserted). when this bit is ? 0 ? , the daspb pin is low (asserted). bit 1: pdiagb (pdiagb signal of ata interface) this bit reflects the physical state of the pdiagb pin. when this bit is ? 1 ? , the pdiagb pin is high (not asserted). when this bit is ? 0 ? , the pdiagb pin is low (asserted). bit 0: reserved this bit is reserved for future enhancements. register 0ah: host interface control register (write) acronym: hic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 setbsy setdaspb setpdiagb sethint clrbsy clrdaspb clrpdiagb clrhint the host interface control register controls the bsy status of the ata status register and the pdiagb , daspb and intrq pins of ata interface signals. bit 7: setbsy (set bsy status of ata task file registers) when this bit is set, the KS9245 sets the bsy bit of ata status register . bit 6: setdaspb (set daspb signal of ata interface) when this bit is set, the KS9245 asserts its daspb pin low. bit 5: setpdiagb (set pdiagb signal of ata interface) when this bit is set, the KS9245 asserts its pdiagb pin low.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 2- 8 bit 4: sethint (set intrq signal of ata interface) when this bit is set, the KS9245 asserts its intrq pin high. bit 3: clrbsy (clear bsy status of ata task file registers) when this bit is set, the KS9245 clears the bsy bit of ata status register . bit 2: clrdaspb (clear daspb signal of ata interface) when this bit is set, the KS9245 drives the daspb pin high and then releases it. bit 1: clrpdiagb (clear pdiagb signal of ata interface) when this bit is set, the KS9245 drives the pdiagb pin high and then releases it. bit 0: clrhint (clear intrq signal of ata interface) when this bit is set, the KS9245 negates its intrq pin low. register 0bh: interface configuration control register (read) interface configuration control register (write) acronym: icc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intmode ata transfer mode cdrv sshadow disshadr pcmdint disiordy the interface configuration control register is used by firmware to inform the KS9245 with specific drive configuration such as master/slave drive and pio/dma etc.. bit 7: intmode (interrupt signal mode control) when this bit is cleared, all interrupt events (including disk, host, and buffer) are reported via asserting the hintb pin. when this bit is set, interrupt events from disk/decoder are reported via asserting dintb pin while host/buffer interrupt events are reported via asserting the hintb pin. bit 6-5: ata transfer mode these two bits specify the various ata transfer modes. ata pio/dma mode selection table bit 6 bit 5 ata data transfer mode 0 0 pio transfer mode (default) 0 1 single word dma transfer mode 1 1 multiword dma transfer mode 1 0 ultra dma transfer mode bit 4: cdrv (controller drive configuration) when this bit is set, the KS9245 is configured as drive 1 (slave drive). when this bit is cleared, the KS9245 is configured as drive 0 (master drive). bit 3: sshadow (slave shadow feature enabled) this bit is used together with the cdrv bit. the following table summarizes the function of this bit.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 2- 9 summary for drive configuration cdrv- bit 4 sshadow- bit 3 drive operation mode 0 0 master only mode with shadow feature disabled 0 1 master only mode with shadow feature enabled 1 x slave drive mode bit 2: disshadr (disable shadow auto response) when the disshadr bit is cleared, the sshadow bit is set, the cdrv bit is cleared, and the host issues a command to the non-existent slave drive, the KS9245 responds to the shadow command sequence automatically. when both disshadr and sshadow bits are set, the auto shadow response sequence is disabled bit 1: pcmdint (atapi packet command host interrupt enable mode) when this bit is set and the drive is selected, a hintrq is generated when the KS9245 is ready to receive the 12-byte command packet. bit 0: disiordy (disable io ready signal) when this bit is set, the iordy pin is disabled. register 0ch: reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved. register 0dh: reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 3- 1 chapter 3 hardware sequence command registers register 0eh : host sequence command register (write) acronym: hsc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsvd saabort sservice srelease stfinit scpl scplchk sdsc the host sequence command register is used to start the hardware atapi interface sequence. by using the features in this register, firmware overhead can be minimized and command operations accelerated. each of these operations are performed immediately after a ? 1 ? is written to the corresponding bit. therefore, polling is not required to check completion. writing a ? 0 ? to these bits will not cause any operation. bit 7: reserved this bit is reserved for the future enhancements. bit 6: saabort (start ata abort operation) when this bit is set, the KS9245 automatically aborting ata illegal commands. bit 5: sservice (start atapi service operation) when this bit is set, the KS9245 automatically performs the atapi service sequence in overlapped command operation. bit 4: srelease (start atapi release operation) when this bit is set, the KS9245 automatically performs the atapi release sequence in overlapped command operation. bit 3: stfinit (task file registers initialized) when this bit is set, the KS9245 initializes the ata task file registers . bit 2: scpl (start command completion with no error setting) when this bit is set, the KS9245 performs the atapi command completion without check condition sequence. bit 1: scplchk (start command completion with error setting) when this bit is set, the KS9245 performs the atapi command completion with check condition sequence. bit 0: sdsc (set dsc bit for seek completion operation) when this bit is set, the KS9245 performs the atapi seek command completion sequence .
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 3- 2 register 0fh : transfer sequence command register (write) acronym: tsc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acachee acple rsvd ssxfr sabort spause wrdir sdxfr the transfer sequence command register is used to start or control the atapi host transfer operations. bit 7: acachee (automated cache control) when the acachee bit is ? 1 ? , the auto cache mode is enabled and host transfers are completely automated . when the acachee bit is ? 0 ? , the auto cache feature is disabled . bit 6: acple (automated command completion enabled) when this bit is set, the atapi command completion sequence will automatically start when any of the following events occur: the total host transfer length register is decreased to zero when the host transfer is in the data area and initialized by setting the sdxfr bit in the transfer sequence command register (0fh, bit 0). the host transfer is in the system area and initialized by setting the ssxfr bit in transfer sequence command register (0fh, bit 4). bit 5: reserved this bit is reserved for future enhancements. bit 4: ssxfr (start host transfer operation in system area) when this bit is ? 1 ? , the KS9245 starts host transfer operations to / from the system area. bit 3: sabort (start transfer abort operation) this function is used to abort the host transfer in an emergent occasion such as an abort command or eject disc occurrence. when this bit is set, the KS9245 aborts the current host transfer operation immediately. bit 2: spause (start host transfer pause operation) when this bit is set, the KS9245 pauses the host transfer operation when the transfer in the current host transfer length register (18h) are complete. bit 1: wrdir (write/read direction control) when this bit is set, the host is transferring data to KS9245. when this bit is reset, the host is reading data from the KS9245 . bit 0: sdxfr (start host transfer operation in data area) when this bit is set, the KS9245 starts host block transfer operations.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 3- 3 register 0fh : transfer sequence status register (read) acronym: tss bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acachee acple reserved spause wrdir hxfrbsy the transfer sequence status register indicates the status of the transfer command register . bit 7: acachee (automated cache control) when this bit is set, auto cache is enabled. when this bit is reset, auto cache is disabled. bit 6: acple (automated command completion enabled) when this bit is set, the automated atapi command completion sequence is enabled . when this bit is reset, the automated atapi command completion sequence is disabled. bit 5-3: reserved these bits are reserved for future enhancements. bit 2: spause (start host transfer pause operation) when this bit is set, the transfer pause operation is in process. when this bit is reset, no pause operation is performed. bit 1: wrdir (write/read direction control) when this bit is set, the transfer operation is a write from the host to the KS9245. when this bit is reset, the transfer operation is a read from the KS9245 to the host. bit 0: hxfrbsy (host transfer operation busy) when this bit set, the host transfer operation is in progress. when this bit is cleared, the host transfer has completed.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 4- 1 chapter 4 microprocessor interface registers register 10h: host interrupt status register (read) host interrupt clear register (write) acronym: hisr/hicr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 txfrdone reserved asrst srst hrst scmdrcv acmdrcv pcmdrcv this register informs firmware of various interrupts which are reported by the KS9245. writing a ? 1 ? to any bit clears that respective interrupt. writing a ? 0 ? to any bit causes no change for that respective interrupt. bit 7: txfrdone (total host request transfer done) this bit is set when one of the following events occur: data area transfer completed. system area transfer completed. bit 6: reserved this bit is reserved for future enhancements. bit 5: asrst (atapi soft reset command (08h) received) this bit is set when the host writes the atapi soft reset command (08h) into atapi command register (07h) while the drive is selected. bit 4: srst (ata srst reset) this bit is set when the srst bit in the device control register (08h, bit 2) is set by the host. bit 3: hrst (host reset) this bit is set when the hrstb pin is asserted. bit 2: scmdrcv (shadow command received) this bit is set when the host writes a command byte into the atapi command register (07h) of the non-existent slave drive. bit 1: acmdrcv (ata command received) this bit is set when the host writes a command in the atapi command register (07h) while the drive selected. bit 0: pcmdrcv (atapi packet command received) this bit is set when the host writes the packet command (a0h) into the atapi command register (07h) while the drive selected.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 4- 2 register 11h: decoder interrupt status register (read) decoder interrupt clear register (write) acronym: disr/dicr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dacint subint decint this register informs the firmware of various cd decoder interrupts reported by the KS9245. writing a ? 1 ? to any bit clears that respective interrupt. writing a ? 0 ? to any bit causes no change for that respective interrupt. bit 7-3: reserved these bits are reserved for future enhancements. bit 2: dacint (audio dac output interrupt) this bit is set when one block of audio data (2352 byte) is output to the external audio dac via the awck/abck/adat pins. bit 1: subint (cd subcode interrupt) this bit is set when the cd subcode interrupt occurs. bit 0: decint (cd decoder interrupt) this bit is set when a cd decoder interrupt occurs. register 12h: host interrupt mask register (read) host interrupt mask register (write) acronym: him bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 txfrdonee cxfrdone e asrste srste hrste scmdrcve acmdrcve pcmdrcve this register controls the masking for each interrupt source. writing a ? 1 ? to each bit enables the interrupt for that corresponding function. writing a ? 0 ? to each bit, disables the interrupt for that corresponding function. bit 7: txfrdonee (total host request transfer done enable) when this bit is set, the txfrdone interrupt (10h, bit 7) is enabled. when this bit is reset, the txfrdone interrupt is disabled. bit 6: cxfrdonee (host block transfer done interrupt enable) when this bit is set, the cxfrdone interrupt (10h, bit 6) is enabled. when this bit is reset, the cxfrdone interrupt is disabled. bit 5: asrste (atapi soft reset command interrupt enabled) when this bit is set, the asrst interrupt (10h, bit 5) is enabled. when this bit is reset, the asrst interrupt is disabled. bit 4: srste(ata srst reset interrupt enabled) when this bit is set, the srst interrupt (10h, bit 4) is enabled. when this bit is reset, the srst interrupt is disabled.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 4- 3 bit 3: hrste(ata host rest interrupt enabled) when this bit is set, the hrst interrupt (10h, bit 3) is enabled. when this bit is reset, the hrst interrupt is disabled. bit 2: scmdrcve (shadow command interrupt enabled) when this bit is set, the scmdrcv interrupt (10h, bit 2) is enabled. when this bit is reset, the scmdrcv interrupt is disabled. bit 1: acmdrcve (ata command interrupt enabled) when this bit is set, the acmdrcv (10h, bit 1) interrupt is enabled. when this bit is reset, the acmdrcv interrupt is disabled. bit 0: pcmdrcve (atapi packet command interrupt enabled) when this bit is set, the pcmdrcv interrupt (10h, bit 0) is enabled. when this bit is reset, the pcmdrcv interrupt is disabled. register 13h: decoder interrupt mask register (read) decoder interrupt mask register (write) acronym: dim bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dacinte subinte decinte this register controls the masking for each interrupt source. writing a ? 1 ? to each bit enables the interrupt for that corresponding function. writing a ? 0 ? to each bit, disables the interrupt for that corresponding function. bit 7-3: reserved these bits are reserved for future enhancements. bit 2: dacinte (audio dac output interrupt enable) when this bit is set, the dacint interrupt (11h, bit 2) is enabled. when this bit is reset, the dacint interrupt is disabled. bit 1: subinte (cd subcode interrupt enabled) when this bit is set, the subint interrupt (11h, bit 1) is enabled. when this bit is reset, the subinte interrupt is disabled. bit 0: decint (cd decoder interrupt) when this bit is set, the decint interrupt (11h, bit 0) is enabled. when this bit is reset, the decint interrupt is disabled.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 5- 1 chapter 5 buffer/cd cache manager registers register 14h : valid cache block count register (read) valid cache block count register (write) acronym: vcbc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 valid cache block count register b7:b0 the valid cache block count register indicate the number of valid blocks in the buffer dram. these blocks have passed either ecc correction or edc check and are ready to be transferred to the host. register 15h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved for future enhancements. register 16h : total host transfer block length register (read) total host transfer block length register (write) acronym: ttbl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 total host transfer block length register b7:b0 the total host transfer length register indicate the remaining block length to be transferred between the host and the drive before finishing an atapi read (12h) or read cd ( beh) command. register 17h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved for future enhancements.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 5- 2 register 18h : current host transfer block length register (read) current host tr ansfer block length register (write) acronym: chtb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 current host transfer block length register b7:b0 the current host transfer block length register specify the current number of blocks to be transferred between the host and the drive for the current host transfer. register 19h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved for future enhancements. register 1ah : host transfer block address low register (read) host transfer block address low register (write) acronym: htbal bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 host transfer block address low register b7:b0 see host transfer block address high register . register 1bh : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved. register 1ch : host block offset address low 1 register (read) host block offset address low 1 register (write) acronym: hboal1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 host block offset address low 1 register b7:b0 see host block offset address high 1 register .
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 5- 3 register 1dh : host block offset address high 1 register (read) host block offset address high 1 register(write) acronym: hboah1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b11 b10 b9 b8 the host block offset address low/high registers specify the starting offset address of the first segment within a block in the buffer dram. register 1eh : transfer offset length low 1 register (read) transfer offset length low 1 register (write) acronym: toll1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transfer offset length low 1 register b7:b0 see the transfer offset length high 1 register . register 1fh : transfer offset length high 1 register (read) transfer offset length high 1 register (write) acronym: tolh1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b11 b10 b9 b8 the transfer offset length low/high 1 registers (1eh, 1fh) specify the number of continuous bytes to be transferred to the first segment. register 20h : host block offset address low 2 register (read) host block offset address low 2 register (write) acronym: hboal2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 host block offset address low 2 register b7:b0 see host block offset address high 2 register
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 5- 4 register 21h : host block offset address high 2 register (read) host block offset address high 2 register(write) acronym: hboah2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b11 b10 b9 b8 the host block offset address low/high 2 registers specify the starting transfer offset address after finishing the transfer for the first segment. register 22h : transfer offset length low 2 register (read) transfer offset length low 2 register (write) acronym: toll2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 transfer offset length low 2 register b7:b0 see transfer offset length high 2 register register 23h : transfer offset length high 2 register (read) transfer offset length high 2 register (write) acronym: tolh2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved b11 b10 b9 b8 the transfer offset length low/high 2 registers specify the continuous number of bytes to be transferred, after finishing the first segment . register 24h : mp access physical address lsb register(read) mp access physical address lsb register(write) or mp block offset address low register (read) mp block offset address low register (write) acronym: mpalsb mboal bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mp access physical address lsb b7:b0 mp block offset address low register b7:b0 these registers specify the dram physical address or block address when the microprocessor wants to access the dram.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 5- 5 register 25h : mp access physical address mid (read) mp access physical address mid (write) or mp block offset address high register (read) mp block offset address high register (write) acronym: mpamid mboah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mp access physical address mid b15:b8 reserved mp block offset address high register b11:b8 see mp access physical lsb register (24h). register 26h : mp access physical address msb (read) mp access physical address msb (write) or mp block address register (read) mp block ad dress register (write) acronym: mpamsb mba bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dram access physical address msb b18:b16 mp block address register b7:b0 in block addressing mode, the mp block address register specify the block address in buffer dram. also, refer to the mp access physical lsb register (24h) description. register 27h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved for future enhancements.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 5- 6 register 28h : mp acce ss data port register (read) mp access data port register (write) acronym: mpdp bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mp access data port b7:b0 the mp access data port register is used to access the content of the dram for both read and write operations. register 29h : buffer access control register (read) acronym: bac bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 drambsy reserved pamb rsvd rsvd bit 7: drambsy (dram busy status) this bit set when the dram is busy. bit 6-3: reserved these bits are reserved for future enhancements. bit 2: pamb (physical addressing mode disabled) when this bit is reset, physical addressing mode (pam) is used for dram accesses by the microprocessor. when this bit is set, block addressing mode (bam) is used for dram accesses by the microprocessor. also, refer to the mp access physical address lsb register (24h) description. bit 1-0: reserved these bits are reserved for future enhancements. register 29h : buffer access control register (write) acronym: bac bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 incaudcnt incblkcn t reserved pamb sdramwrt sdramrd bit 7: incaudcnt writing a ? 1 ? to this bit increments the valid audio block count register (48h) by one. writing a ? 0 ? to this bit causes no operation. bit 6: incblkcnt writing a ? 1 ? to this bit increments the valid cache block count register (14h) by one . bit 5-3: reserved these bits are reserved for future enhancements.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 5- 7 bit 2: pamb (physical addressing mode disabled) writing a ? 0 ? to this bit places the KS9245 into physical addressing mode (pam) for dram accesses. writing a ? 1 ? to this bit places the KS9245 into block addressing mode (bam) for dram accesses . bit 1: sdramwrt (start dram write) writing a ? 1 ? to this bit causes the KS9245 to start the dram write operation. bit 0: sdramrd (start dram read) writing a ? 1 ? to this bit causes the hardware to start the dram read operation. register 2ah : buffer configuration control 1 register (read) buffer configuration control 1 register (w rite) acronym: bcc1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c2error dsel ssel csel blkconf dramsz c2error dsp channel sel blkconf dramsz the buffer configuration control 1 register specifies the dram size and configuration. bit 7: c2error(c2 error block or format) when this bit is set, the first byte of c2 block error is the result of logically oring all of the c2 error flag bytes. when this bit is cleared, the first byte of the c2 block error is the longitudinal parity (xor) of all the c2 error flag bytes. bit 6-4 : dsp channel sel (dsp channel select for buffering) the dsp channel sel bits select various dsp data channels to be buffered when the decoder is in buffer only / ecc / audio buffering / test modes. bit 6: dsel (data channel select dsp for buffering) writing a ? 1 ? to this bit selects the dsp main data channel for buffering. writing a ? 0 ? to this bit disables the dsp main data channel and prevents it from being buffered. bit 5: ssel ( subcode channel select dsp for buffering) writing a ? 1 ? to this bit selects the dsp subcode channel for buffering. writing a zero to this bit disables the dsp subcode channel and prevents it from being buffered. bit 4: csel (c2p0 channel select dsp for buffering) writing a ? 1 ? to this bit, selects the dsp c2po error flags for buffering. writing a ? 0 ? to this bit prevents the dsp c2po error flags from being buffered. bit 3: blkconf (dram block configuration) this bit configures the cd block size in dram. when this bit is set, each cd block size is partitioned as 2.5k (2560 bytes). when this bit is cleared, each cd block size is partitioned as 3k (3072 bytes). bit 2-0: dramsz (dram size selection) these bits specify the dram size.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 5- 8 register 2bh : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 drcd1 the register is reserved. register 2ch : buffer bottom block address register(read) buffer bottom block address register(write) acronym: bbba bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 buffer bottom block address register the buffer bottom block address register configures the end or the last cd block address in dram. register 2dh : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved for future enhancements. register 2eh : dram refresh c ontrol register (read) dram refresh control register (write) acronym: drcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dram refresh control register the dram refresh control register is used to program the dram refresh period. register 2fh : g lobal control register (write) global control register (read) acronym: gcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ssleep sfreset burstnum dspburst apce cspeed[2:0] the global control register controls power management, dram arbitration mode, and soft reset operation. bit 7: ssleep (start sleep mode) when this bit is set to ? 1 ? , the KS9245 enters sleep mode immediately. writing a ? 0 ? to this bit causes the KS9245 to wake to normal operation.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 5- 9 bit 6: sfreset (start firmware reset) writing a ? 1 ? to this bit causes a firmware reset for the KS9245. bit 5: burstnum - host dram page access burst (byte) size refer to KS9245 performance table below. bit 4: dspburst - cd buffer to dram burst size refer to KS9245 performance table below. bit 3: apce (audio port configuration enable) when this bit is set, the gp0, gp1, gp2, and gp3 pins are configured as the awck, abck, adat, and dauo pins for the audio word clock, bit clock, data, and digital audio output to an external dac, respectively. bit 2-0: cspeed[2:0] - adjust arbiter ? s priority scheme refer to KS9245 performance table below. KS9245 performance table system clock dram type max disk speed burstnum,dspburst cspeed[2:0] programming value sustain mode max host mode 33.8 mhz 60ns fast page 34 x [0, 0, 0, 0, 0] pio4 / dma2 ultra dma2 33.8 mhz 45ns fast page 50ns edo 37 x [0, 0, 0, 0, 0] pio4 / dma2 ultra dma2 50.8 mhz 40ns edo 50 x [0, 0, 0, 0, 0] ultra dma1 ultra dma2 50.8 mhz 45ns fast page 50ns edo 45 x [0, 0, 0, 0, 0] ultra dma1 ultra dma2 50.8 mhz 40ns edo 35 x [0, 1, 1, 0, 0] ultra dma2 ultra dma2 50.8 mhz 45ns fast page 50ns edo 32 x [0, 1, 1, 0, 0] ultra dma2 ultra dma2
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 1 chapter 6 cd block decoder registers register 30h : decoder header min register (read) acronym: dhmin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 decoder header min register the decoder header min register contains the minute byte of the cd header information. this register is valid only after a cd decoder interrupt occurs. register 31h : decoder header sec register (read) acronym: dhsec bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 decoder header second register the decoder header sec register contains the second byte of the cd header information. register 32h : decoder header frame register (read) acronym: dhframe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 decoder header frame register the decoder header frame register contains the frame byte of the cd header information. register 33h : decoder header mode register (read) acronym: dhmode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 decoder header mode register the decoder header mode register contains the mode byte of the cd header information.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 2 register 34h : de coder subheader 0 register (read) acronym: dsubh0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 decoder subheader 0 register the decoder subheader 0 register contains the first byte of the subheader, which is the file number byte. this register is valid only after a cd decoder interrupt occurs. register 35h : decoder subheader 1 register (read) acronym: dsubh1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 decoder subheader 1 register the decoder subheader 1 register contains the second byte of the subheader, which is the channel number byte. register 36h : decoder subheader 2 register (read) acronym: dsubh2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 decoder subheader 2 register the decoder subheader 2 register contains the third byte of the subheader, which is the submode byte. register 37h : decoder subheader 3 register (read) acronym: dsubh3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 decoder subheader 3 register the decoder subheader 3 register contains the fourth byte of the subheader, which is coding information byte. register 38h : disk transfer block address register (read) disk transfer block address register (write) acronym: dtba bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 disk transfer block address register the disk transfer block address register indicate the block address of the incoming dsp data currently being buffered. register 39h : reserved
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved for future enhancements. register 3ah : decoder control register (read) decoder control register (write) acronym: dcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved submon audwrt eccrq decwrt decen decsen this register is used to control the cd decoder operation. the cd decoder stays in one of the following modes: stop mode : in stop mode, the decoder completely stopped. refer to decoder operation state table below. data monitor mode: in monitor mode, the decoder and descrambler operations are active. refer to decoder operation state table below. buffering only mode: in buffering only mode, the decoder and descrambler operations are active. refer to decoder operation state table below. audio buffering mode: in audio buffering mode, the dsel bit in the buffer configuration control 1 register (2ah, bit 6) must be set. refer to decoder operation state table below. subcode monitor mode: if the submon bit is set and the audwrt bit is cleared, the decoder is in the subcode monitor mode. refer to decoder operation state table below. ecc mode: in ecc mode, the decoder and descrambler operations are active. refer to decoder operation state table below. test mode: in test mode, the decoder operation is active while the descrambler logic is disabled. refer to decoder operation state table below.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 4 decoder operation state submon audwrt eccrq decwrt decen decscen operation status 0 0 0 0 0 0 decoder stop mode 0 0 0 0 1 1 monitor mode 0 0 0 1 1 1 buffering only mode 0 1 x x x x audio buffering mode 1 0 x x x x subcode monitor mode 0 0 1 1 1 1 ecc mode 0 0 0 1 1 0 test mode other values invalid mode bit 7-6: reserved these bits are reserved for future enhancement. bit 5: submon ( subcode monitor mode enable) when this bit is set and the audwrt bit is cleared, the decoder is placed into the subcode monitor mode. bit 4: audiwrt (audio buffer mode enable) when this bit is set, the KS9245 will buffer the cd-da data. bit 3: eccrq (error correction request) writing a ? 1 ? to this bit when both the decen and decwrt bits are set causes the decoder logic to switch into ecc mode. bit 2: decwrt (decoder writing/buffering enable) writing a ? 1 ? to this bit when the decen bit is set causes the buffering for the main data streams, dsp subcode, c2po error flags to become active . bit 1: decen (decoder operation enable) when this bit set, the cd decoder operation is active for processing the incoming dsp data. bit 0: descen ( descrambler enabled) when this bit set, the descrambler logic is active. register 3bh : ecc con trol 1 register (read) ecc control 1 register (write) acronym: ecc1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xamode reserved edcen eccpen eccqen eracorr the ecc control 1 register controls the ecc, edc, and decoder operations. bit 7: xamode (cd xa data mode enable) when this bit cleared, the ecc/edc logic assumes the data block is yellow book mode 0,1,2. when this bit is set, the ecc/edc logic assumes the data block is either xa mode 2 form 1 or mode 2 form 2. bit 6-4: reserved
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 5 these bits are reserved for future enhancements. bit 3: edcen (edc check enable) when this bit is set, the edc checker is enabled and the KS9245 performs an edc check after the ecc operation completes. bit 2: eccpen (ecc p parity check) when this bit set, the ecc p parity checker is enabled and the ecc logic will correct the data using the p codewords. bit 1: eccqen (ecc q parity check) when this bit set, the ecc q parity checker is enabled and the ecc logic will correct the data using the q codewords. bit 0: eracorr (c2po erasure correction enable) when this bit is cleared, the c2po error flags are not used for correction reference. register 3ch : ecc control 2 register (read) ecc control 2 register (write) acronym: ecc2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved packetwr asynwrt repcorr rsvd discowr the ecc control 2 register controls special decoder operations. bit 7-5: reserved these bits are reserved for future enhancements. bit 4: packetwr (packet writing blocks start/stop) when this bit is set, KS9245 will start reading cd-wo disc with packet writing. bit 3: asynwrt (audio synchronized buffering) when this bit is set, the writing or buffering of cd-da data is delayed until the first subcode in the incoming dsp subcode stream is detected. bit 2: repcorr (repeat correction start) the repcorr bit triggers the repeat correction feature. bit 1: reserved this bit is reserved for future enhancements. bit 0: reserved this bit is reserved for future enhancements.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 6 register 3dh : ecc status register (read) acronym: eccs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 invalid overr eccfat eccerr cblk nosync illsync rsvd the ecc status register is used to provide the results of ecc and edc operations. bit 7: invalid (ecc status information invalid) this bit is set when the succeeding ecc or dsp status has overwritten the ecc status register before firmware has read the status. bit 6: overr (dsp fifo overflow error) this bit is set when a fifo overflow error occurs in the dsp interface. bit 5: eccfat (fatal error in ecc logic) this bit is set when the ecc logic detected a fatal error. bit 4: eccerr (uncorrectable error block) when this bit is set, there is an uncorrectable error in the data block. bit 3: cblk (corrected block) this bit is set when one or more error bytes have been corrected by the last ecc operation. bit 2: nosync (no sync error) this bit is set when the sync pattern was not detected in its expected location. bit 1: illsync (illegal sync error) this bit is set when the sync pattern is not detected as expected.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 7 bit 0: reserved this bit is reserved for future enhancements. register 3eh : dsp device type selection register (read) dsp device type selection register (write) acronym: ddts bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsvd bckd1 fps bcklength lsbf lch bckf the dsp device type selection register selects various cd dsp and subcode interface formats. bit 7: reserved this bit is reserved for future enhancements. bit 6: bckd1 (bck data sampling delay one clock) when this bit is set, the data is delayed by one bck clock in sampling. bit 5: fps (forward packet stream) when this bit is set, the main data stream is a forward packet stream. bit 4-3: bcklength (clock length) these bits specify the dsp main channel clock length. bit 2: lsbf (main channel data lsb byte comes first) when this bit is set, the KS9245 takes the first byte of the dsp channel data as the lsb and the second byte as the msb on the sdata pin. when this bit is cleared, the KS9245 takes the first byte of the dsp channel data as the msb and the second byte as the lsb on the sdata pin. bit 1: lch (left channel high) when this bit is set, a high level on the lrck pin indicates the left channel. when this bit is cleared, a high level on the lrck pin indicates the right channel. bit 0: bckf (data latched on falling edge) when this bit is set, the data is valid on the falling edge of the bck signal. when this bit is cleared, the data is valid on the rising edge of the bck signal. register 3fh : decoder header erasure register (read) acronym: dher bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 esh0 esh1 esh2 esh3 emin esec eframe emode the decoder header erasure register contains the error flags for the header or subheader of the data block. bit 7: esh0 (error flag for subheader 0 - file number) when this bit is set, the error flag of the file number byte in both subheaders is set. when this bit is cleared, the error flag of the file number byte in either of the subheaders is cleared
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 8 bit 6: esh1 (error flag for subheader 1 - channel number) when this bit is set, the error flag of the channel number byte in both subheaders is set. when this bit is cleared, the error flag of the channel byte in either of the subheaders is cleared. bit 5: esh2 (error flag for subheader 2 - submode) when this bit is set, the error flag of the submode byte in both subheaders is set. when this bit is cleared, the error flag of the submode byte in either of the subheaders is cleared. bit 4: esh3 (error flag for subheader 3 - coding information) when this bit is set, the error flag of the coding information byte in both subheaders is set. when this bit is cleared, the error flag of the coding information byte in either of the subheaders is cleared. bit 3: emin (error flag for header min byte) when this bit is set, the error flag of the header min byte is set. when this bit is cleared, the error flag of the header min byte is cleared. bit 2: esec (error flag for header sec byte) when this bit is set, the error flag of the header sec byte is set. when this bit is cleared, the error flag of the header sec byte is cleared. bit 1: eframe (error flag for header frame byte) when this bit is set, the error flag of the header frame byte is set. when this bit is cleared, the error flag of the header frame byte cleared. bit 0: emode (error flag for header mode byte) when this bit is set, the error flag of the header mode byte is set. when this bit is cleared, the error flag of the header mode byte is cleared. register 40h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved. register 41h : subcode status register (read) acronym: ssr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scrcerr suberr reserved the subcode status register provides the results of subcode operations. bit 7: scrcerr ( subcode crc error) when this bit is set, a crc error in exists in the q channel subcode. when this bit is cleared, no crc error exists in the q channel subcode. bit 6: suberr ( subcode buffer error) when this bit is set, one of the following errors occurred: a subcode sync word is not found.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 9 a subcode sync indication comes either earlier or later than the 96 byte subcode data. bit 5-0: reserved these bits are reserved for future enhancements. register 42h : subcode device type selection register (read) subcode device type selection register (write) acronym: sdts bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sub format selection reserved these bits specify the subcode interface format and subcode interface pin connection. the philips ? v4-subcode interface, eija-1 (4-wired) and eiaj-2 (3-wired) are supported as follows: subcode format selection bits value description pin connection clock source 00 v4-subcode for philips dsp sub: connected to v4 as input sfsy: ground sbsy: ground rck: not connected internal clock for 1x-50x 01 eiaj-1 (4-wired) dsp sub: input, as channel data sfsy: input, as byte clock sbsy: input, as sync clock rck: output as bit clock rck output as bit clock 10 eiaj-2 (3-wired) dsp sub: input, as channel data sfsy: input, as byte/sync clock sbsy: ground rck: output as bit clock rck output as bit clock 11 invalid bit 7-6: sub format selection these bits specify the subcode interface format and subcode interface pin connection. the philips ? v4-subcode interface, eija-1 (4-wired) and eiaj-2 (3-wired) are supported. bit 5-0: reserved these bits are reserved for future enhancements. register 43h : version control register (rea d) acronym: vcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 version control number the version control register indicates the version number of the KS9245. the version number for the KS9245 is 20h. this register is hard-wired and read-only.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 10 register 44h : port control register (write) port control register (read) acronym: pcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpc3 gpc2 gpc1 gpc0 gp3 gp2 gp1 gp0 the port control register controls the gp0, gp1, gp2 and gp3 pins as either input/output ports. bit 7 gpc3 (general port configuration for gp3) when this bit is set, the gp3 pin is configured as an output pin. when this bit is cleared, the gp3 pin is configured as an input pin. bit 6 gpc2 (general port configuration for gp2) when this bit is set, the gp2 pin is configured as an output pin. when this bit is cleared, the gp2 pin is configured as an input pin. bit 5 gpc1 (general port configuration for gp1) when this bit is set, the gp1 pin is configured as an output pin. when this bit is cleared, the gp1 pin is configured as an input pin . bit 4 gpc0 (general port configuration for gp0) when this bit is set, the gp0 pin is configured as an output pin. when this bit is cleared, the gp0 pin is configured as an input pin. bit 3: gp3 (general port value for gp3 ) when the gp3 pin is configured as an output pin, writing a ? 1 ? to this bit sets the gp3 pin high. writing a ? 0 ? resets the gp3 pin low. when the gp3 pin is configured as an input pin, reading this bit obtains the state of the gp3 pin. bit 2: gp2 (general port value for gp2 ) when the gp2 pin is configured as an output pin, writing a ? 1 ? to this bit sets the gp2 pin high. writing a ? 0 ? resets the gp2 pin low. when the gp2 pin is configured as an input pin, reading this bit obtains the state of the gp2 pin. bit 1: gp1 (general port value for gp1 ) when the gp1 pin is configured as an output pin, writing a ? 1 ? to this bit sets the gp1 pin high. writing a ? 0 ? resets the gp1 pin low. when the gp1 pin is configured as an input pin, reading this bit obtains the state of the gp1 pin. bit 0: gp0 (general port value for gp0 ) when the gp0 pin is configured as an output pin, writing a ? 1 ? to this bit sets the gp0 pin high. writing a ? 0 ? resets the gp0 pin low. when the gp0 pin is configured as an input pin, reading this bit obtains the state of the gp0 pin. register 45h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved. register 46h : reserved
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 11 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved. register 47h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved for future enhancements. bit 7-0: reserved these bits are reserved for future enhancements. register 48h : valid audio block count register (read) valid audio block count register (write) acronym: vabc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 valid audio block count register b7:b0 the valid audio block count register indicate the number of valid audio blocks in the buffer dram which are available for audio playback in cav mode. register 49h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved for future enhancements. register 4ah : dac block address register (read) dac block address register (write) acronym: daba bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac block address register the dac block address register point to the address of the data block currently being output to the external dac during audio playback.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 12 register 4bh : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved this register is reserved for future enhancements. register 4ch : dac output format selection register (read) dac outpu t format selection register (write) acronym: dofs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adat18 abckd1 afps abckl alsbf alch abckf the dac output format selection register selects various audio output interface formats in cav playback mode only. bit 7: adat18 (audio data output as 18 bit format) when this bit is set, the audio data format is 18-bits. when this bit is cleared, audio data format is 16-bits. bit 6: abckd1 (abck data sampling delay one clock) when this bit is set, the data is delayed by one abck clock in sampling. bit 5: afps (audio forward packet stream) when this bit is set, the main data stream is a forward packet stream. bit 4-3: abckl (audio bit clock length) these two bits specify the audio data bit clock length. bit 2: alsbf (audio channel data lsb byte comes first) when this bit is set, the KS9245 takes the first byte of audio data as the lsb and the second byte as the msb in the adat pin. when this is cleared, the KS9245 takes the first byte of audio data as the msb and the second byte as the lsb in the adat pin. bit 1: alch (audio left channel high) when this bit is set, a high level on awck pin indicates the left channel. when this is cleared, a high level on the awck indicates the right channel. bit 0: abckf (audio data latched on falling edge) when this bit is set, the data is valid on the falling edge of the abck signal. when this bit is cleared, the data is valid on rising edge of the abck signal.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 13 register 4dh : dac control register (read) dac control register(write) acronym: dacr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved acc spa the dac control register controls various dac output operations such as mono, stereo, and swap left / right channel modes. bit 7-3: reserved these bits are reserved for future enhancements. bit 2-1: acc (audio channel control) these bits control various audio channel outputs. bit 0: spa (start play audio) when this bit is set and the abps bit is 0, the KS9245 starts outputting the audio data pointed to by the dac block address register (4ah). register 4eh : audio clock control register (read) audio clock control register(write) acronym: accr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsvd abps daue dovs dscd xina div the audio clock control register selects the audio clock source and various audio enables for bypass mode and digital audio as well as the dsp input oversampling rate. bit 7 reserved this bit is reserved for future enhancements. bit 6: abps (audio bypass mode start) when this bit is set regardless of what mode the cd decoder is in, the audio data is directly selected from the dsp input and then output to awck / abck / adat / dauo pins. when this bit is cleared, the audio bypass mode is disabled. bit 5: daue (digital audio output enable) writing an ? 1 ? to this bit enables the digital audio output, iec 958, on pin 4. bit 4-3: dovs (dsp input over sampling rate) these bits select the over-sampling rate for the dsp input . bit 2: dscd (disable subcode clock detect) when this bit is set, the subcode clock auto-detection is disabled and the subcode clock control and adjustments registers (40h, 45h, and 46h) are valid. when this bit is cleared, the subcode clock auto-detection is enabled and the subcode clock control register is invalid.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 6- 14 bit 1-0: xina select (audio clock select) these bits select the audio clock word length for cav mode only. register 4fh : audio volume control register (read) audio volume control register (write) acronym: avcr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcm rcm reserved vol bit 7: lcm (left audio channel mute) when this bit is set, the KS9245 mutes the left audio channel. when this bit is cleared, the KS9245 enables the left audio channel. bit 6: rcm (right audio channel mute) when this bit is set, the KS9245 mutes the right audio channel. when this bit is cleared, the KS9245 enables the right audio channel. bit 5-4: reserved these bits are reserved for future enhancements. bit 3-0: vol (volume control) the bits control the volume level.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 7- 1 chapter 7 diagnostic and miscellaneous registers the following registers are reserved for diagnostic purposes only. in normal operation, these registers need not be programmed. register 50h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bit 7-0: reserved these bits are reserved for internal diagnostic purposes. register 51h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bit 7-0: reserved these bits are reserved for internal diagnostic purposes. register 52h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bit 7-0: reserved these bits are reserved for internal diagnostic purposes. register 53h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bit 7-0: reserved these bits are reserved for internal diagnostic purposes. register 54h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bit 7-0: reserved these bits are reserved for internal diagnostic purposes.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 7- 2 register 55h : r eserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bit 7-0: reserved these bits are reserved for internal diagnostic purposes. register 56h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bit 7-0: reserved these bits are reserved for internal diagnostic purposes. register 57h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bit 7-0: reserved these bits are reserved for internal diagnostic purposes. register 58h : reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bit 7-0: reserved these bits are reserved for internal diagnostic purposes.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 8- 1 chapter 8 enhancement control registers register 60h : ultra dma timing register (read) ultra dma timing register (write) acronym: udtr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uderr reserved udmacyc bit 7 : uderr ( ultra dma error ) this status bit will be set when the crc logic of the ultra dma engine detects an error while transferring data. bit 6-3 : reserved these bits are reserved for the future enhancements. bit 2-0 : udmacyc ( ultra dma programming cycle time ) these bits defined the cycle timing for the ultra dma engine.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 9- 1 chapter 9 electrical specifications 9.1 absolute maximum ratings item symbol rating unit dc supply voltage vcc -0.3 to 7 v storage temperature tstg -40 to 125 c power dissipation pd 0.5 w dc input voltage vin -0.3 to vcc+0.3 v dc input current iin -10 to 10 ma 9.2 recommended operating conditions item symbol rating unit dc supply voltage vcc 4.5 to 5.5 v commercial temperature ta 0 to 70 c 9.3 dc characteristic (vcc=5v-5% to 5v+5%, ta=0 to 70 c, vss=0) item symbol min. type. max. unit input high voltage vih 2.0 - - v input low voltage vil - - 0.8 v output high voltage voh 2.4 - - v output low voltage vol - - 0.4 v input high current vin=vcc iih -10 - 10 ua input low current vin=vss input with pull-up iil -10 -200 - 10 -10 ua output leakage current ioz -10 - 10 ua
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 9- 2 9.4 input/output dc characteristic dc characteristics of pins signal pin i/o input level output current remark bdat5 1 i/o ttl 4 ma internal pull up resistor bdat11 2 i/o ttl 4 ma internal pull up resistor bdat4 3 i/o ttl 4 ma internal pull up resistor bdat12 4 i/o ttl 4 ma internal pull up resistor bdat3 5 i/o ttl 4 ma internal pull up resistor bdat13 6 i/o ttl 4 ma internal pull up resistor bdat2 7 i/o ttl 4 ma internal pull up resistor bdat14 8 i/o ttl 4 ma internal pull up resistor bdat1 9 i/o ttl 4 ma internal pull up resistor vss 10 i bdat15 11 i/o ttl 4 ma internal pull up resistor bdat0 12 i/o ttl 4 ma internal pull up resistor awck/gp0 13 i/o ttl 4 ma o: audio word clock abck/gp1 14 i/o ttl 4 ma o: audio bit clock adat/gp2 15 i/o ttl 4 ma o: audio data dauo/gp3 16 i/o ttl 4 ma o: digital audio rstb 17 i schmitt trigger sub 18 i ttl sfsy 19 i ttl sbsy 20 i ttl rck 21 i/o 4 ma sbclk 22 i ttl sdata 23 i ttl lrclk 24 i ttl c2poi 25 i ttl
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 9- 3 vss 26 i xout 27 o xin/sysclk 28 i 33.8688 mhz arstb 29 o 4 ma csb 30 i ttl ad0 31 i/o ttl 4 ma ad1 32 i/o ttl 4 ma ad2 33 i/o ttl 4 ma
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 9- 4 signal pin i/o input level output current remark ad3 34 i/o ttl 4 ma vss 35 i ad4 36 i/o ttl 4 ma ad5 37 i/o ttl 4 ma ad6 38 i/o ttl 4 ma ad7 39 i/o ttl 4 ma vcc 40 i ale/rsb 41 i ttl rdb/dsb 42 i ttl wrb r/wb 43 i ttl hintb 44 od 4 ma dintb 45 od 4 ma vss 46 i mstb 47 i ttl daspb 48 i/o ttl 12 ma internal pull up resistor cs3fxb 49 i ttl cs1fxb 50 i ttl da2 51 i ttl da0 52 i ttl pdiagb 53 i/o ttl 12 ma internal pull up resistor da1 54 i ttl iocs16b 55 od 12 ma intrq 56 ot 12 ma dmackb 57 i ttl iordy 58 ot 12 ma diorb 59 i ttl diowb 60 i ttl dmarq 61 ot 12 ma vss 62 i dd15 63 i/o ttl 12 ma dd0 64 i/o ttl 12 ma dd14 65 i/o ttl 12 ma dd1 66 i/o ttl 12 ma dd13 67 i/o ttl 12 ma dd2 68 i/o ttl 12 ma
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 9- 5 signal pin i/o input level output current remark dd12 69 i/o ttl 12 ma dd3 70 i/o ttl 12 ma vss 71 i dd11 72 i/o ttl 12 ma dd4 73 i/o ttl 12 ma dd10 74 i/o ttl 12 ma dd5 75 i/o ttl 12 ma dd9 76 i/o ttl 12 ma dd6 77 i/o ttl 12 ma dd8 79 i/o ttl 12 ma dd7 79 i/o ttl 12 ma hrstb 80 i ttl schmitt trigger badd4 81 o 4 ma badd3 82 o 4 ma badd5 83 i/o 4 ma badd2 84 o 4 ma vss 85 i badd6/xsel 86 i/o 4 ma external jumper badd1 87 o 4 ma badd7/isel 88 i/o 4 ma external jumper badd0 89 o 4 ma vcc 90 i badd8/msel 91 i/o 8 ma external jumper rasb 92 o 8 ma casb 93 o 4 ma web 94 o 4 ma bdat8 95 i/o ttl 4 ma internal pull up resistor vss 96 i bdat7 97 i/o ttl 4 ma internal pull up resistor bdat9 98 i/o ttl 4 ma internal pull up resistor bdat6 99 i/o ttl 4 ma internal pull up resistor bdat10 100 i/o ttl 4 ma internal pull up resistor
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 1 chapter 10 general timing 10.1 microprocessor interface 10.1.1multiplexed intel mode register read/write timing microcontroller read cycle tale tale trd tas trdly trc tah tcs trdh tdar trp trp tch trds address data in address data in ale rdb ad[7:0] csb microcontroller write cycle tale tale trdly tdly tah tcs twds twdh twp twp tch address address data out data out ale wrb ad[7:0] csb
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 2 parameter symbol min. max. unit ale pulse width tale 1 sysclk ns address setup time tas 10 address hold time tah 5 ns chip select setup for read / write command tcs 10 ns chip select hold for read / write command tch 0 ns ale active from read / write rising edge delay tdly 0 ns write pulse width twp 2 sysclk ns read pulse width trp 3 sysclk ns read pulse to next address valid tdar 10 ns data setup time for write twds 10 ns data hold time for write twdh 10 ns ale falling to rdb/ wrb falling trdly 15 ns read data setup time trds 1 sysclk ns read data hold time trdh 0 ns
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 3 10.1.2 multiplexed motorola mode register read/write timing tah tdh tas tale tdely tcsh tarw tcs trws tdsp tdsl tds thrw tda trdh add in out ad(7:0) - in ale cs dsb r/wb (write) ad(7:0) - out r/wb (read) parameter symbol min. max. unit ale pulse width tale 1 sysclk ns address setup time tas 10 ns address hold time tah 10 ns address valid before read/write command tarw 15 ns chip select setup for read/write tcs 10 ns chip select hold for read/write tch 0 ns r/wb- setup before ds trws 5 ns r/wb- hold after ds thrw 5 ns dsb pulse width tdsp 3 sysclk ns dsb recover time tdsl 1 sysclk ns data setup time for write tds 10 ns data hold time for write tdh 10 ns read access time tda 1 sysclk 2 sysclk ns dsb to ale falling edge delay tdely 1.5 sysclk ns read data hold time trdh 0 ns
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 4 10.1.3 indirect access register mode read/write timing valid data valid data tas tas trwh tda thz trwb trp tdh trwb twp tds l : address port , h : data port ad(7:0) - in rdb ad(7:0) - out wrb rsb cs parameter symbol min. max. unit wrb recover time to next rdb or wrb trwb 2 sysclk ns cs or rsb setup for read/write tas 10 ns wrb pulse width twp 40 ns rdb pulse width trp 40 ns cs or rsb hold time trwh 5 ns data setup time for write tds 10 ns data hold time for write tdh 10 ns read access time tda 10 20 ns read data hold time thz 0 ns
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 5 10.2 dram interface 10.2.1 dram single clock cycle read/write timing t t tdis trd trh tcd tch tcp tcads tcas tradd tcadd tcadd toed toeh twed tweh tdih tdd tddh row col 1 col 2 indata data out data out indata sysclk rasb casb badd oeb web bdat - read bdat - write
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 6 10.2.2 dram non-single clock cycle read/write timing tdis trd trh tcd tch tradd tcadd toed toeh twed tweh tdih tdd tddh row col 1 col 2 indata data out data out indata sysclk rasb casb badd oeb web bdat - read bdat - write 10.2.3 dram refresh timing trd trh tcd tch sysclk rasb casb oeb - "1" web - "1"
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 7 10.2.4 dram ac timing parameter symbol min. max. unit sysclk cycle time t 20.8 ns sysclk to rasb low delay trd 15 ns sysclk to rasb high delay trh 15 ns sysclk to casb low delay tcd 15 ns sysclk to casb high delay tch 15 ns sysclk to row add valid delay tradd 15 ns sysclk to column add valid delay tcadd 15 ns sysclk to oeb low delay toed 15 ns sysclk to oeb high delay toeh 15 ns sysclk to web low delay twed 15 ns sysclk to web high delay tweh 15 ns casb high to data in setup time tdis 0 ns casb high to data in hold time tdih 6 ns sysclk to valid data delay for write tdd 20 ns sysclk to invalid delay for write tddh 20 ns cas high pulse width tcp 5 ns cas low pulse width tcas t/2 + 1.5 ns column address set up tcads 4 ns
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 8 10.3 ata interface 10.3.1 single word dma data transfer hdreqhs hdrwhs hdrwss hdrwps hddss hdras hdrhs hddhs dmarq dmackb diorb/diowb hdat - read hdat - write parameter symbol min. max. unit dmackb to dmarq delay hdreqhs 80 ns dmackb to dior(w)b setup hdrwss 0 ns diorb/diowb pulse width hdrwps 120 ns dior(w)b to dmackb hold hdrwhs 0 ns diorb read access time hdras 60 ns diorb data hold hdrhs 5 ns diowb data setup hddss 35 ns diowb data hold hddhs 20 ns
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 9 10.3.2 multiword word dma data transfer hdreqh hdrwh hdrws hdrwp hdds hdrwc hdrwh hdra hdrh hddh dmarq dmackb diorb/diowb hdat - read hdat - write parameter symbol min. max. unit dior(w)b to dmackb delay hdreqh 35 ns dior(w)b to dmackb hold hdrwh 5 ns dmackb to dior(w) setup hdrws 0 ns diorb/diowb pulse width hdrwp 70 ns diorb/diowb negated pulse width hdrwh 25 ns diorb/diowb cycle time hdrwc 120 ns diorb read access time hdra 60 ns diorb data hold hdrhs 5 ns diowb data setup hdds 20 ns diowb data hold hddh 10 ns
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 10 10.3.3 ultra dma data transfer tui tenv tack tfs tziordy taz tzad tdvs tdvh data drive initiating dma burst read dmarq (drive dmarq) dmackb (host dmackb) diowb (host stop) diorb (host dmardyb) iordy (drive strobe) dd[15:0] (data-out) da0, da1, da2 cs1fxb, cs3fxb iocs16b
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 11 tui tack tenv tli tziordy tui tdvs tdvh data drive initiating dma burst write dmarq (drive dmarq) dmackb (host dmackb) diowb (host stop) iordy (drive dmardyb) diorb (host strobe) dd[15:0] (data-in) da0, da1, da2 cs1fxb, cs3fxb iocs16b tcyc t2cyc tcyc tcyc t2cyc tcyc tcyc t2cyc t2cyc tcyc tdvh tdvs tdvh tdvs tdvh tdvs tdvh t2cyc tcyc t2cyc tcyc tcyc t2cyc tcyc tcyc t2cyc tcyc tdh tds tdh tds tdh tds tdh sustaining ultra dma burst data data data data data data data data iordy (drive strobe during reads) dd[15:0] (data-out during reads) diorb (host strobe during writes) dd[15:0] (data-in during writes)
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 12 tsr trp trfs drive pausing dma burst write data data syncnronous pause: if dmardyb is deasserted within tsr time. asynchronous pause: if dmardyb is deasserted outside tsr time. dmarq (drive dmarq) dmackb (host dmackb) diowb (host stop) iordy (drive dmardyb) diorb (host strobe) dd[15:0] (data-in) da0, da1, da2 cs1fxb, cs3fxb iocs16b l h h l tdvs tdvh tdvs tdvh drive pausing dma burst read data data burst read paused iordy (drive strobe) dd[15:0] (data-out) burst read is paused by holding strobe constant.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 13 tli tmli tack tli tiordvz taz tzah tdvs tdvh crc drive terminating dma burst read dmarq (drive dmarq) dmackb (host dmackb) diowb (host stop) diorb (host dmardyb) iordy (drive strobe) dd[15:0] (data-out) da0, da1, da2 cs1fxb, cs3fxb iocs16b tli tmli tack tiordyz tdvs tdvh crc drive terminating dma burst write dmarq (drive dmarq) dmackb (host dmackb) diowb (host stop) iordy (drive dmardyb) diorb (host strobe) dd[15:0] (data-in) da0, da1, da2 cs1fxb, cs3fxb iocs16b
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 14 tli tmli tack tli tiordyz taz tzah tdvs tdvh host terminating dma burst read crc dmarq (drive dmarq) dmackb (host dmackb) diowb (host stop) diorb (host dmardyb) iordy (drive strobe) dd[15:0] (data-out) da0, da1, da2 cs1fxb, cs3fxb iocs16b tli tmli tack tli tli tiordyz tdvs tdvh host terminating dma burst write crc dmarq (drive dmarq) dmackb (host dmackb) diowb (host stop) iordy (drive dmardyb) diorb (host strobe) dd[15:0] (data-in) da0, da1, da2 cs1fxb, cs3fxb iocs16b
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 15 tss drive stop request during read iordy (drive strobe) dmarq (drive dmarq) ultra dma timing parameters (mode-2) parameter symbol min. max . unit cycle time tcyc 55 ns two cycle time t2cyc 117 ns data setup time at receiver tds 7 ns data hold time at receiver tdh 3 ns data valid setup time at sender tdvs 34 ns data valid hold time at sender tdvh 6 ns first strobe time - time allowed for drive to send first strobe tfs 0 170 ns limited interlock time tli 0 150 ns limited interlock time with minimum tmli 20 ns unlimited interlock time tui 0 ns maximum time allowed for outputs to tristate taz 10 ns minimum delay required for output drivers to turn on from high z tzah tzad 20 0 ns ns envelope time tenv 20 70 ns strobe-to-dmardy response time to ensure synchronous pause tsr 20 ns ready-to-final-strobe time trfs 50 ns ready-to-pause time trp 100 ns pull-up time before allowing iordy to go high z tiordyz 20 ns minimum time drive must wait before driving iordy tziordy 0 ns setup and hold times before assertion and deassertion of /dmack tack 20 ns time from strobe edge to stop assertion when sender is stopping tss 50 ns
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 16 10.3.4 programmed i/o read/write timing hah has hrwp hds hdh hrac trdh hcs16s tcs16h hrdys hrda hrdyp da,cs1(3)fxb diorb/diowb hdat - write hdat - read iocs16b iordy parameter symbol min. max. units address setup time has 25 ns address hold time hah 10 ns dior-/diow- pulse width : 16 bits hrwp 70 ns diow- data setup time hds 20 ns diow- data hold time hdh 10 ns dior- read access time hrac 25 ns dior- read data hold time hrdh 5 ns address valid to iocs16b delay hcs16s 40 ns address valid to iocs16b hold hcs16h 25 ns iordy setup time hrdys 35 ns read data valid to iordy selected hrda 0 ns iordy pulse width hrdyp 1250 ns
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 17 10.4 cd dsp interface 10.4.1 sbclk falling edge strobe ddh dds c2poi, sdata, lrclk sbclk parameter symbol min. max. unit c2poi, sdata, lrclk setup before sbclk dds 5 ns c2poi, sdata, lrclk hold after sbclk ddh 5 ns 10.4.2 sbclk raising edge strobe ddh dds c2poi, sdata, lrclk sbclk parameter symbo l min. max. unit c2poi, sdata, lrclk setup before sbclk dds 5 ns c2poi, sdata, lrclk hold after sbclk ddh 5 ns
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 18 10.4.3 audio output edge strobe ddh dds adat, awck abck parameter symbol min. max. unit adat, awck setup before abck dds 5 ns adat, awck hold after abck ddh 5 ns 10.4.4 dsp interface format philips iis dsp interface format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 h - right channel , l - left channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb upper byte flag lower byte flag msb 15 sbclk lrclk sdata c2poi toshiba dsp interface format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 h - left channel , l - right channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb upper byte flag lower byte flag msb 0 sbclk lrclk sdata c2poi sony 24-clock dsp interface format-1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 h - left channel , l - right channel msb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb upper byte flag lower byte flag sbclk lrclk sdata c2poi sony 24-clock dsp interface format-2
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 19 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 h - left channel , l - right channel msb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb upper byte flag lower byte flag sbclk lrclk sdata c2poi sony 32-clock dsp interface format-3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 h - right channel , l - left channel lsb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 msb 30 31 0 sbclk lrclk sdata 10.4.5 audio output interface format eiaj (16-bit) audio data interface format 0 15 14 12 8 5 0 15 23 0 1 3 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 13 11 10 9 7 6 4 3 1 2 22 1 left channel data abck adat awck eiaj (18-bit) audio data interface format 0 17 16 14 12 8 5 0 17 left channel data 15 13 11 10 7 6 9 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 23 22 1 2 abck adat awck philips i2s (16-bit) audio data interface format 15 10 5 1 0 15 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 22 21 23 14 13 12 11 9 8 7 6 4 3 2 14 left channel data abck adat awck philips i2s (18-bit) audio data interface format
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 10- 20 17 0 1 17 1 0 9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 16 16 15 14 13 12 11 10 8 7 6 5 4 3 2 23 22 21 left channel data abck adat awck 10.5 power on reset interface timing trstp trstp trstp trstp rstb hrstb parameter symbol min. max. units reset pulse width trstp 10 us
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 11- 1 chapter 11 package and dimensions
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 12- 1 chapter 12 hardware application notes 12.1 pio/dma support modes the following tables list the various disk speed and pio/dma mode which are supported in our specification. pio mode summary/disk speed pio mode burst speed cycle time support remark mode 0 3.33 mb/sec 600 nsec yes without flow control mode 1 5.33 mb/sec 383 nsec yes without flow control mode 2 8.33 mb/sec 240 nsec yes without flow control mode 3 11.1 mb/sec 180 nsec yes without flow control mode 4 16.7 mb/sec 120 nsec yes without flow control dma mode summary/disk speed single/multi word burst speed cycle time support remark single word mode 0 2.08 mb/sec 960 nsec yes single word mode 1 4.17 mb/sec 480 nsec yes single word mode 2 8.33 mb/sec 240 nsec yes multiword mode 0 4.17 mb/sec 480 nsec yes multiword mode 1 13.3 mb/sec 150 nsec yes multiword mode 2 16.7 mb/sec 120 nsec yes 12.2 firmware sector process time the following tables list the various disk rate against the worst case time left for firmware to process a sector after decoder interrupt is generated by hardware. firmware sector process time disk speed sector period dsp rate worst f/w sector time 1x 13.333 ms 150kb/sec 6.666 msec 2x 6.666 ms 300kb/sec 3.333 msec 4x 3.333 ms 600kb/sec 1.666 msec 6x 2.222 ms 900kb/sec 1.111 msec 8x 1.666 ms 1.2mb/sec .833 msec 10x 1.333 ms 1.5mb/sec .666 msec 12x 1.111 ms 1.8mb/sec .555 msec 14x .952 ms 2.1mb/sec .476 msec 16x .833 ms 2.4mb/sec .416 msec 24x .555 ms 3.6mb/sec .277 msec
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 12- 2 12.3 sleep mode how to enter sleep mode KS9245 can be programmed into sleep mode for saving power and most of hardware will be cut off by clock. the only way into sleep mode is the register 2f bit 7 must be set to high. how to quit sleep mode there are two ways to quit from sleep mode. one done by firmware is clear bit 7 of register 2f directly and the other is new ata command received or ata software reset command received in this case KS9245 hardware will automatically wake up. something important before enter sleep mode in the sleep mode, dsp interface will be shut off automatically, so make sure KS9245 is in dsp stop mode. ecc engine and buffer manager are totally turned off. in dram control logic, the refresh time will still work to keep the buffer data is valid. following table is for each block function affected by sleep mode. dram refresh dsp subcod e microp ecc edc buffer manager ide sleep on on off off on off off on how much power is saved in sleep mode in the sleep mode, it is about 75%-80% less than the normal operation mode. 12.4 automatic power-savings mode besides sleep mode, the KS9245 has an automatic power-savings feature for the cd- dsp/ subcode interface, ecc, and cav audio playback modules. in this mode, the clocks driving these modules are stopped when the modules are not active. the following describes the automatic power-savings feature: 1) the clock to the cd-dsp/ subcode interface is automatically shut off while the cd-decoder is in stop mode. 2) the clock to the ecc module is normally stopped until there is a header, a correction or repeat correction request occurs. after the request is serviced, the ecc clock will again be automatically shut off. 3) the clock to the cav audio playback module is shut off until the spa (start play audio) bit 0 in register 4dh is set.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 12- 3 12.5 intel & motorola microprocessor direct access the KS9245 is designed to be directly interfaced with intel and motorola type microprocessors without any external glue logic (refer to the microprocessor interface timing in section 9.1.1 and 9.1.2). the following diagrams show the connections for an intel-type and motorola-type microprocessor connected to the KS9245 in a direct access configuration. note: isel and msel can still used as badd7 and badd8 to connect to dram addresses. KS9245 intel microprocessor intel direct access interface diagram rdb wrb rdb wrb ad[7:0] ad[7:0] ale ale csb csb msel/badd8 isel/badd7 10k 10k KS9245 motorola microprocessor motorola direct access interface diagram dsb r/wb dsb r/wb ad[7:0] ad[7:0] ale ale csb csb msel/badd8 isel/badd7 22k 10k +5v
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 12- 4 12.6 intel & motorola microprocessor indirect access the KS9245 is designed to be directly interfaced with intel and motorola type microprocessors without any external glue logic (refer to the microprocessor interface timing in section 9.1.1 and 9.1.2). however, if the timing specifications 9.1.1 and 9.1.2 cannot be satisfied, then an indirect access method must be used. for this case, the timing of section 9.1.3 is used. the following shows an interface scheme for using indirect access on the KS9245 with intel and motorola type microprocessors. note: for indirect access mode, isel needs to be sampled high by the KS9245 immediately after power-on. after this, both isel and msel can be used as badd7 and badd8 to interface with the dram, respectively. KS9245 intel microprocessor intel indirect access interface diagram rdb wrb rdb wrb ad[7:0] ad[7:0] 74hc373 ale rsb address port: a0 = 0 data port: a0 = 1 a0 g oc d0 q0 csb ad0 22k +5v msel/badd8 isel/badd7
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 12- 5 KS9245 motorola microprocessor motorola indirect access interface diagram rdb wrb r/wb dsb ad[7:0] ad[7:0] 74hc373 ale rsb address port: a0 = 0 data port: a0 = 1 a0 g oc d0 q0 csb ad0 22k +5v msel/badd8 isel/badd7 in this scheme, two access are required if the previous access is to a different location. the first access writes the address port to select a register in the KS9245 while the second access reads/writes the selected KS9245 register. for example, to read from register 10h of the KS9245, the first access should write 10h to any even address (a0=0) to program the address port with 10h. the next access must then be a read to any odd address (a0=1) to obtain the data from register location 10h.
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 12- 6 12.7 cav audio playback and digital audio support introduction in traditional clv (constant linear velocity) applications, the cd disc speed must constantly be changed in order to maintain a constant linear velocity as the pickup head moves from inner track to outer track or vice versa. as a result, cd-rom access times are severely impacted, especially when audio tracks must be played at single speed rates. to overcome this limitation, the KS9245 automated atapi cd-rom controller integrates an audio buffer manager and dedicated pins for support of cav (constant angular velocity) mode playback. in this mode, the KS9245 allows audio data to be buffered at up to 50x and played back at a constant 1x speed. thus, cd-rom access times are not impacted as a result of speed changes. additionally, since the audio data is buffered, the KS9245 easily provides support for iec-958 digital audio output at no extra cost. this applications note describes the audio buffer manager , the cav pins and register sets along with its digital audio support, and shows how to configure those pins and registers for cav and digital audio mode playback. audio buffer manager the KS9245 integrates an audio buffer manager in order to simplify firmware efforts and efficiently control the cav audio playback sequence. this hardware automatically keeps track of the available audio block(s) in the buffer dram and monitors buffer full and empty conditions. audio blocks that are stored in dram are tracked by the valid audio block count register (reg48h). in the event of buffer full conditions, the firmware must stop the dsp buffering operation. in the event of buffer under-run conditions, the hardware automatically mutes the audio channels to mask any undesired noise. note that buffer full is determined by firmware keeping track of available dram space. thus, firmware should stop the audio buffering before the dram actually becomes full to account for any response delays. cav pin description table 1 lists the pins used for cav mode playback. in cav mode, these pins are dedicated outputs from the KS9245 to the audio dac and carry audio data that have been buffered to dram by the KS9245. note: when not in cav mode, these pins are general purpose i/o pins. physical pin assignment signal pin i/o description source / destination awck 13 o audio word clock output KS9245 / dac abck 14 o audio bit clock output KS9245 / dac adat 15 o audio data output KS9245 / dac table 1: cav pins cav register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 48h r/ w vabc valid audio block count register b7:b0 4ah r/ w daba dac block address low register b7:b0 4ch r/w dofs adat18 abck d1 afps abckl alsb f alch abckf 4dh r/w dacr lcm rcm rsvd reserved acc spa 4eh r/w accr rsvd abps daue rsvd xina div table 2: KS9245 audio mode register set
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 12- 7 table 2 lists a subset of the KS9245 ? s registers used for configuring cav mode playback. detailed descriptions of these registers can be referenced in the KS9245 atapi automated cd- rom controller engineering specification, available from iml. valid audio block count registers (vabc at 48h) : this register specifies the number of valid audio blocks buffered into dram which are available for audio playback. firmware must increment this register by one (to keep track of the audio block count) by writing a ? 1 ? to the incaudcnt bit in the buffer access control register (reg29h, bit7) after a decoder interrupt occurs in audio buffering mode. this register is automatically decremented by one after one audio block has been output to the awck/abck/adat pins during cav playback. note that a dac interrupt is generated after one audio block is output to the awck/abck/adat pins. aslo, when this occurs, the dacint bit in the decoder interrupt status register (reg11h, bit2) is set if the dacinte bit in the decoder interrupt mask register (reg13h, bit2) is set. dac block address register (daba at 4ah) : this register points to the audio block in dram to be output or currently being output to the audio dac. this register is automatically incremented to point to the next audio block to be played once the current block is completely outputted. note that this pointer will wrap around after the bottom of the buffer is reached. dac output format selection register (dofs at 4ch) : this register is used to select various audio output interface formats for cav mode playback only. table 3 lists the available formats using this register. audio output format selection summary audio format adat18 abckd1 afps abckl alsbf alch abckf hex eiaj 16 bit 0 0 0 10 0 1 0 12h eiaj 18 bit 1 0 0 10 0 1 0 92h i2s 16 bit 0 1 1 10 0 0 0 70h i2s 18 bit 1 1 1 10 0 0 0 f0h table 3: audio output format selection in addition, the KS9245 also supports an audio bypass mode where it allows inputs from dsp devices (such as toshiba, sanyo, and sony) to be directly output to the awck / abck / adat pins without any conversions. this mode is set when the abps (audio bypass mode) bit is set to ? 1 ? in the audio clock control register (reg4eh, bit 6). dac control register (dacr at 4dh) : this register is used to control various dac output operations such as muting, mono / stereo / swap modes, and start play audio. bit 7 and bit 6 control the left and right audio channel muting for cav and audio bypass modes, except for dau audio bypass. when any of these bits are set to ? 1 ? in cav or audio bypass modes, the corresponding audio channel is muted. when any of these bits are reset to ? 0 ? , the corresponding audio channel is enabled. following power-on, software reset, or atapi reset conditions, the state of these bits are set to ? 1 ? and both audio channels are muted. table 4 summarizes the mono / stereo / swapped modes selected by bits 2 and 1. audio channel mode selection bit 2, bit 1 channel mode description valid 00 stereo output both left and right channels cav & audio bypass 01 mono right output right channel data to both channels cav only 10 mono left output left channel data to both channels cav only 11 channel swap left and right channels data swap cav & audio bypass table 4: audio channel mode selection
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 12- 8 spa (bit 0) is used to start playing (outputting) the buffered audio blocks to the awck / abck / adat / dauo pins. when spa is set to ? 1 ? and the abps is reset to ? 0 ? , buffered audio data will be output to the awck / abck / adat pins. note: if the daue is also set to ? 1 ? in the audio clock control register (reg4eh, bit5), the buffered audio data will also be output to the dauo (digital audio output pin 4) simultaneously audio clock control register (accr at 4eh) : this register is used to select the audio clock source and audio bypass mode. table 6 summarizes the audio clock selection for cav mode only. note: the audio clock source is derived directly from the KS9245 system clock and is not internally configurable. thus, the system clock should be driven from either a 33.8688mhz / 50.8 mhz source in order to match the audio clock requirements. audio clock select bit [ 1, 0] system clock inputs audio word clock length digital output 16-bck 24-bck 32-bck dauo 01 33.8688 mhz valid valid valid valid 11 50.8032 mhz valid valid valid valid x0 reserved table 5: audio clock selection additionally, bits 6 and 5 of this register control the enabling / disabling of audio bypass mode and digital audio mode (described above) respectively. table 6 shows the audio mode configuration truth table. abps spa daue audio mode selected channel controls allowed 1 x x dsp inputs bypass to dac swap, mute l/r dauo outputs none 0 0 x none none 0 1 0 dac outputs swap, mute l/r, mono, stereo 0 1 1 dac and dau outputs simultaneously swap, mute l/r, mono, stereo table 6: audio mode selection table cav mode configuration the following sequence shows how to configure the KS9245 for cav mode playback: 1. set the apce (audio port configuration enable) bit to ? 1 ? in the global control register (reg2f, bit3) to configure the awck, abck, and adat pins as output for cav mode. 2. select the KS9245 ? s dsp interface format in the dsp device type selection register (reg3eh). note that this selection must match the requirements of the dsp format for correction operation of audio playback. 3. select the audio output format (either eiaj 16/18 bits or i2s 16/18 bits) in the dac output format selection register (reg4c). note that this selection must match the requirements of the audio dac to be interfaced with for correction operation of audio playback. 4. configure the audio sample rate and channel mode for stereo, mono, or swapped in the dac control register (reg4d).
samsung version: tm 2.4 KS9245 atapi automated cd-rom controller preliminary technical manual _____________________________________________________________ do not copy or release 12- 9 5. select the appropriate audio word clock length in the audio clock control register (reg4e). 6. set the address pointer in the dac block address registers (reg4a) to point to the start of audio data in dram to be played. 7. set the spa (start play audio) bit to ? 1 ? in the dac control register (reg4d) to start outputting the audio data pointed to by the dac block address register . iec-958 digital audio support digital audio support has traditionally been provided by the cd-dsp controllers and not the cd- decoders. however, since decoders such as the KS9245 now provide support for cav mode playback by buffering the audio data, digital audio on the dsp controllers cannot be used while the decoders are in cav mode. thus, to take advantage of both cav and digital audio, the KS9245 implements on-board digital audio support (eiaj iec-958 standard) using the sony/philips digital signal format. this implementation comprises an dauo pin (output pin 4) and an dauin pin (input pin 16), as well as an daue (enable) bit in the audio clock control register (reg4eh, bit5). iec-958 digital audio configuration to configure the digital audio channel for outputting audio data, cav mode and the dac interface must first be properly configured (refer to cav mode configuration described above and note that a 33.8mhz system clock must be used). once cav mode and the dac interface are configured, setting both the daue bit (reg4eh) and the spa bit (reg4dh) to ? 1 ? will allow iec-958 sony/phillips digital audio formatted data to be output on the dauo pin. note that the abps bit (reg4eh) must be reset to ? 0 ? . additionally, when the audio bypass mode is selected, the KS9245 allows the digital audio data to come from an outside source such as the cd-dsp. in this case, the cd- dsp ? s dauo pin would be connected to the KS9245 ? s dauin pin, and the audio data would be directly bypassed to the dauo pin of the KS9245. the benefit of the feature is that it allows for the same board design to support both cav and clv mode playback . note that in the digital audio (dau) bypass mode, all audio channel mode controls such as channel muting, channel swapping, and mono left and right channels have no affect on the digital audio data being output on the dauo. thus, this data is always played back in stereo on the dauo pin in dau bypass mode.

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