i - 14 ? 1998 ixys all rights reserved inverter interface and digital deadtime generator for 3-phase pwm controls ixys reserves the right to change limits, test conditions and dimensions. type package configuration temp. range ixdp630 pi 18-pin plastic dip rc oscillator -40 c to +85 c ixdp631 pi 18-pin plastic dip crystal oscillator -40 c to +85 c features l 5 v hcmos logic implementation maintains low power at high speed l schmitt trigger inputs and cmos logic levels improve noise immunity l simultaneously injects equal dead- time in up to three output phases l replaces 10-12 standard ssi/msi logic devices l allows a wide range of pwm modulation strategies l directly drives high speed optocouplers applications l 1- and 3- phase motion controls l 1- and 3- phase ups systems l general power conversion circuits l pulse timing and waveform generation l general purpose delay and filter l general purpose three channel "one shot" in the ixdp630, deadtime programming is achieved by an internal rc oscillator. in the ixdp631, programming is achieved by use of a crystal oscillator. an alternative for both the ixdp630/ 631 is with an external clock signal. because of its flexibility, the ixdp630/ 631 is easily utilized in a variety of brushed dc, trapezoidally commutated brushless dc, hybrid and variable reluctance step and other more exotic pwm motor drive power and control circuit designs. this 5 v hcmos integrated circuit is intended primarily for application in three-phase, sinusoidally commutated brushless motor, induction motor, ac servomotor or ups pwm modulator control systems. it injects the required deadtime to convert a single phase leg pwm command into the two separate logic signals required to drive the upper and lower semiconductor switches in a pwm inverter. it also provides facilities for output disable and fast overcurrent and fault condition shutdown. block diagram ixdp 630/ixdp 631
i - 15 ? 1998 ixys all rights reserved ixdp630 ixdp631 symbol definition maximum ratings min. max. v cc supply voltage -0.5 7 v v in dc input voltage -0.5 v cc + 0.5 v i in dc input current -1 1 ma v 0 dc output voltage 0.5 v cc + 0.5 v i 0 dc output current -25 25 ma t stg storage temperature -55 150 c t l lead soldering (max. 10 s) 300 c recommended operating conditions v cc supply voltage 4.5 5.5 v t j operating temperature -40 85 c l 0 output current -8 8 ma f osc oscillator frequency 0.001 16/24 mhz symbol definition/condition characteristic values min. typ. max. v t+ input hi threshold 3.6 2.7 v v t- input lo threshold 1.6 0.8 v v hys hysteresis 1.1 v i in input leakage current -10 10 m a c in input capacitance 5 10 pf v oh output high voltage l o = -8 ma 2.4 v v ol output low voltage l o = 8 ma 0.4 v i cc supply current outputs unloaded 5 ma i ccq quiescent current outputs 0.4 1 ma unloaded ixdp630 i ccq quiescent current outputs 1 10 m a unloaded ixdp631 dp630 oscillator section c osc capacitor (rcin to gnd) 0.047 10 nf r osc resistor (oscout to rcin) 1 1000 k w f osc frequency range 0.001 - 16 mhz initial tolerance (f osc 1mhz) 5 % temperature coefficient -400 ppm/ c dp631 oscillator section f osc frequency range 0.1-24 mhz v inh oscillator thresholds (ixtlin) 3.9 v v inl 0.8 v external oscillator f in frequency range (odcout open) 0-24 mhz t sx set up time data-to-xtlin 14 n s t sc set up time data-to-oscin 22 ns t hold hold time clock-data 0 ns t pdro propagation delay reset-to-output 15 20 ns t pdeo propagation delay enable-to-output 8 16 ns dimensions in inch (1" = 25.4 mm) 16-pin plastic dip t pdeo t pdro t hold t sc t sx
i - 16 ? 1998 ixys all rights reserved ixdp630 ixdp631 sym. pin description gnd 9 circuit ground - 0 volts rcin 10 the first node of the clock or network. for the ixdp630, the xtlin rc input is applied to rcin. for the ixdp 631, the crystal oscil- lator is applied to xtlin. if an external clock is to be supplied to the chip it should be connec- ted to this pin. osc 11 this is the output node of the out oscillator. it is connected indi- rectly to the rcin or xtlin pins when using the internal oscillator as described in the applications information. it is not recommen- ded for external use. tl 12 after the appropriate delay, the tu 13 external drive outputs (r,s, t) u sl 14 are in phase with their corres- su 15 ponding inputs; (r,s, t) l are rl 16 the complementary outputs. ru 17 v cc 18 voltage supply +5 v 10 % sym. pin description r 1 r, s and t are the three single- s 3 phase inputs. each input is t 5 expanded into two outputs to generate non-overlapping drive signals, ru/rl, su/sl, and tu/ tl. the delay from the falling edge of one line to the rising edge of the other is a function of the clock. enar 2 high logic input will enable the enas 4 outputs, as set by the proper enat 6 input phase. the ena (r,s,t) signals control the drive output lines. a low logic input will force both controlled outputs to a low logic level out 7 high logic level will enable all ena outputs to their related phase. the outena simultaneously controls all outputs. low input logic level will inhibit all outputs (low). reset 8 the reset signal is active low. when a logic low reset is applied, all outputs will go low. after releasing the reset command within the generated delay, the outputs will align with the phase input level after the programmed delay internal. pin description ixdp630 pin description ixdp631 waveforms deadtime deadtime deadtime deadtime this diagram shows the normal operation of the ixdp630/631 after the reset input is released. the deadtime is the 8 clock periods between xu and xl when both xu and xl are a "0". the length of the deadtime is fixed at 8 times the period of clk. the diagram shows outena and enax asynchronously forcing the xu output and the xl output to the off state. outena will force all three channels to the off state. enax (where x is one of the three channels) will only force the xu and xl outputs of that channel to the off state. note that because enax is asynchronous with respect to the internal clock and deadtime counters, when enax goes hi whatever state the deadtime counter was in immediately propagates to the output. this figure also shows that noise at the xin input will be filtered before the xu output or xl output will become active, which may extend the deadtime. note: x = any input, r, s or t. noise deadtime deadtime
i - 17 ? 1998 ixys all rights reserved ixdp630 ixdp631 application information basic operation the ixdp630/631 deadtime genera- tors are intended to simplify the implementation of a single- or three- phase digitally controlled power conversion circuit. it replaces one to three digital event counters (timer/ counters) in a microcontroller or dsp implementation of a motor control, ups or other power system. in most cases these timers are at a premium. they must be used to calculate pulse width on one to three independent modula- tors, set interrupt service times, generate a real-time clock, handle communica- tions timing functions, etc. the input command on the r, s and t inputs is first synchronized with the internal oscillator. when an input changes state, the on output is switched off, and after a deadtime of exactly 8 clock periods, the complimen- tary output is switched on. for exam- ple, if input r is hi, output ru is hi. at the first rising edge of clk out after input r is brought low, the ru output goes low. after exactly 8 more clock periods the rl output goes high. this injected delay is the deadtime. this method of synchronizing is utilized to guarantee that the deadtime is always exactly the same (to the accu- racy of the clk frequency). this can be very important in certain applications. unbalanced deadtime creates an offset in the pwm output stage transfer func- tion, and can cause saturation of the induction machine control or the driven transformer if not corrected within a few cycles. fig. 1: totem pole configuration of transistor switches; reason for dead- time requirements deadtime in power circuits why is deadtime required? fig. 1 is typical of a switching power conversion equipment output stage. it has two (or typically more) switches. a simple logic error - turning a transistor on at the wrong instant - can cause catastrophic failure in the right (or wrong ) circumstances. in normal operation, when the state of the output totem pole must change, the conducting transistor is turned off. then, after a delay (usually called the deadtime), the other transistor is turned on. the delay is added to ensure that there is no possibility of both transistors conducting at the same time (this would cause a short circuit of the dc link - a "shoot through" - and would likely fail both transistors in a few microseconds). when the control logic commands a switch to change to the off state, several parasitics may delay/modify this command. the propagation delay of the control logic and gate drive buffer, td (off) of the power transistor, storage time (for bipolars) or tail time (for igbts), voltage rise and current fall times, etc., may be significant. problems caused by excessive deadtime if a little is good, a lot should be better - except with deadtime. unfortunately, deadband in the switching output stage causes a nonlinearity in the power circuit transfer function that may be difficult for the control loop to remove. fig. 2 illustrates the problem. the switching period t is: t = t 1 + t 2 + dt t 1 is the time q1 is commanded on, t 2 is the time q2 is commanded on, and dt is the deadtime. assuming continuous condition, and with current in the direction of i l1 : t hi = t 1 + dt t lo = t 2 with current in the direction of i l2 : t hi = t 1 + dt t lo = t 2 + dt. the change in "apparent duty cycle" is then twice the deadtime (2dt). if deadtime is 5% of the cycle period, the duty cycle, as load current crosses zero, instantly changes by 10 %. this is a significant nonlinearity that causes zero crossing distortions in load current and voltage that must be removed by the feedback loop around the pwm stage. if these nonlinearities get large enough, the loop may not have the gain or the speed to remove them. this may cause problems in the behavior of the end product that are unacceptable. zero crossing distortion in the current of a microstepped step motor, for examp- le, causes very serious position errors, velocity ripple, and audible noise in operation - all undesirable. calculating appropriate deadtime values the designer must determine, under worst case conditions, the absolute maximum delay between the logic off command and the actual cessation of transistor conduction. this includes all appropriate stages of logic, transistor storage and delay times, etc. it is very important to include special effects due to the switch technology chosen. storage time of a bipolar transistor with constant base drive can vary 10:1 as collector current varies (storage time increases dramatically at low collector current, such as at light load). these effects must be considered when determining "worst case" delay time requirements. a power circuit must not only work at full rated load, but must not fail under light or no load condi- tions. a delay of at least this time (plus a guardband) must be injected in the command to the series transistor so as to absolutely prohibit its turn-on during this interval. fig. 2: problems caused by excessive deadtime. i l1 i l2
i - 18 ? 1998 ixys all rights reserved ixdp630 ixdp631 selecting components for a specific requirement deadtime in the ixdp630/631 is exactly 8 clock periods: dt= 8/fclk. once the worst case (minimum) deadtime has been determined (from power switching component manufacturer data sheets, drive circuit analysis, breadboard measurements, etc.) the clock frequency is calculated: fclk(max) = 8/ dt(min). this is the highest allowable clock frequency, including the effects of initial accuracy, tolerance, temperature coeffi- cient, etc. when choosing oscillator components, special attention to resistor and capacitor construction is mandatory. oscillator design there are two versions of the deadtime generator. they have distinctly different internal oscillator designs to serve different application. in either case, however, the internal oscillator can be disabled by simply leaving its external components off. an hcmos compatible clock up to 24 mhz can be fed directly into the rcin or xtlin pin. ixdp630 rc oscillator design the ixdp630 uses a schmitt trigger inverter oscillator (fig. 3). two external components, r osc and c osc , determine the clock frequency and consequently the deadtime. this design allows a significant cost reduction over a standard crystal oscillator, but entails a trade-off in frequency accuracy. the initial accuracy and drift are a function of the external component tolerance and temperature coefficients, supply voltage, and ixdp630 internal para- meters. at frequencies under 1 mhz, assuming the external components were perfect, the ixdp630 would introduce an initial accuracy error of 5 %, and a temperature dependence of -400 ppm. the shift in frequency over the v cc range 4.5 v to 5.5 v is typically less than 5 %. at higher frequencies and with resistor values below 1 k w , the ixdp630 internal parameters become more influential factors. this results in greater frequency variation from one device to another, as well as with temperature and supply voltage variations. if high accuracy is a requirement, the ixdp631 with a crystal oscillator would be the better choice. oscillator frequency vs. rosc and cosc is shown in fig. 4. for an analytical method of setting the oscillator, the design equation is for operation below 1 mhz approximately: 0.95 f osc ? cosc rosc for operation above 1 mhz, 0.95 f osc ? cosc (rosc+30) + 3 ? 10 - 8 ixdp631 precision crystal oscillator design the ixdp631 uses a more common standard internal crystal oscillator design. for proper operation the crys- tal must be of the parallel resonant type, resonating at the crystal's funda- mental frequency. fig. 5 illustrates the recommended oscillator configuration. note the external components required. the capacitors are needed to achieve the calibrated crystal frequency (their value is determined by the crystal manufacturer), and the resistor is necessary to assure that the circuit starts in every case. while the circuit will usually operate without these extra parts, this is not recommended. the crystal oscillator in the ixdp631 is significantly more accurate than the rc oscillator in the ixdp630. the total tolerance (including effects of initial accuracy, temperature, supply voltage, drift, etc.) is better than 100 ppm. this improves the accuracy and repeatability of the desired deadtime, but at the added expense of a crystal. which version is appropriate for your application? that depends on how you are willing to trade off component cost for deadtime accuracy. fig. 4. oscillator frequency component selection for ixdp630. fig. 3: ixdp630 internal schmitt trigger inverter oscillator (r osc , c osc are external) c osc = 470 pf c osc = 270 pf c osc = 100 pf c osc = 47 pf c osc = 1 nf c osc = 2.2 nf c osc = 4.7 nf c osc = 10 nf 0.1 1 10 100 100 0 10 000 oscillator - khz
i - 19 ? 1998 ixys all rights reserved ixdp630 ixdp631 ixdp630 rc oscillator component details the ixdp630 oscillator has only two external components. rosc should be a precision, high frequency resistor. the material used in carbon compo- sition resistors is hydroscopic (it absorbs water), causing resistors above 100 k w to 1 m w to change value with relative humidity. this is on top of initial tolerance and temperature coefficient deviations, and so is not recommended. instead, precision metal film or carbon film resistor construction is preferred, with initial tolerances of 1 % and better with temperature coefficients of 100 ppm. the construction of cosc is also critical to circuit operation. cosc should be a good quality monolithic ceramic (single or multilayer) or a metallized polypropy- lene timing capacitor. if ceramic techno- logy is chosen, be sure to consider temperature coefficient and tolerance. it is the minimum capacitor value that is critical, not the part number rated capacitance. a z5u ceramic has an initial tolerance of +80/-20 %, and a temperature variation of +30/-80 % over temperature. an x7r is 10 % initial tolerance, 10 % over temperature. an npo is 5 % initial tolerance, 5 % over temperature (although tighter selections are readily available in npo). if film technology is chosen, polypropy- lene is one of the best choices. tolerances down to 1 % and 2 % are standard and temperature coefficient is 100 ppm. the layout of the external components is also critical. the components should be as close to the device as possible, minimizing stray capacitance and inductance. fig. 5. recommended crystal oscillator components ixdp631 crystal oscillator component details the ixdp631 oscillator requires three external passive components, in addition to the crystal. the crystal is chosen with a frequency below fclk (min). the capacitors and resistor (illustrated earlier in fig. 5) follow rules similar to the rc oscillator option. the resistor should be metal or carbon film, although its accuracy and stability do not significantly affect oscillator frequency accuracy. the capacitors should be monolithic ceramic construction (ck05, or similar) with x7r or better characteristics. grounding, interfacing and noise immunity due to the very high level of currents that are switched at high speed in a typical motor control power circuit, voltage transients (v = l ? di/dt) can cause serious problems. fast digital circuits respond to transients instead of legitimate inputs, disturbing inverter operation or causing outright failure. bypassing and decoupling as with any high speed logic compo- nent, the ixdp630/631 should be bypassed with a good quality (mono- lithic ceramic or film) capacitor designed specifically for bypass application. decoupling is normally not required. the ixdp630 does not generate sufficient supply line current ripple to be a significant noise source when properly bypassed, and it is capable of rejecting normal supply line noise. logic levels all inputs to the ixdp630 and ixdp631 (except xtlin on the ixdp631) are hcmos schmitt trigger compatible. on the ixdp631, the xtlin pin is different because the crystal oscillator circuit cannot tolerate a schmitt input. the hysteresis inherent in schmitt trigger inputs greatly improves the reliability of digital communications. it can reject ground bounce of up to 2 v, and induced voltages in digital signal traces of 1 v. power circuit noise generation in a typical transistor inverter, the output mosfet may switch on or off with di/dt 3 500a/ m s. referring to fig. 6, and assuming that the mosfet source terminal has a 1 inch path on the pcb to system ground, a voltage as high as 13.5 v can be developed: v = 27 nh ? 500a/ m s = 13.5 v if the mosfet switches 25 a, the transient will last as long as (25/500) m s or 50 ns, which is much more than the typical 6 or 7 ns propagation delay of a 74 hc series gate. caution : if one set of digital circuits is tied to system ground, and one to local ground, it is clear that such a transient would cause spurious outputs. in an inverter, the consequences of such an error could be catastrophic. turning a transistor on at the wrong time could easily cause it to explode, with the potential for equipment damage and operator injury -- clearly undesirable. fig. 6. power circuit noise generation methods of correcting these problems the first step is to use a logic family with inherent noise immunity. standard ttl (or any of its derivatives, including 74hct cmos) is a poor choice because of the logic levels these fami- lies employ. in particular, v ol, v il are too close to ground to reject the levels of ground noise common to power circuits. 74hc logic is significantly superior, and the older 4000 series cmos is even better. unfortunately, in modern motor controls, especially those that employ microprocessors, the speeds of the 4000 series cmos are no longer adequate. in most cases 74hc logic is the only viable alternative. layout the second, and most important step is the printed circuit board (pcb) layout. the pcb is a very important compo- nent in any power circuit, and there is a
i - 20 ? 1998 ixys all rights reserved ixdp630 ixdp631 tendency to leave it off the schematic. during the layout process, the engineer must consider each and every connec- tion from the standpoint of its contribu- tion to system operation. how sensitive is it? what noise producing lines are routed near it? what transients can occur between circuits tied to each end of this trace...? with few exceptions, modern autorouters cannot deal with these requirements. if autorouters are used, they produce layouts that will not function. remember that the ixdp630/631 is the interface between the control circuits and the power circuits. nowhere else on the pcb are these problems more likely to occur. nowhere else will one need to pay more attention. fig. 7 illustrates an example layout problem. the power circuit consists of three the mosfet is 6 v), the di/dt at turn-on will be regulated by the driver/mosfet/ l s1 loop to about 200 a/ m s - quite a surprise when your circuit requires 500 a/ m s to operate correctly. it is possible to make use of this beha- vior to create a turn-on or turn-off di/dt limiter (perhaps to snub the upper freewheeling diode reverse recovery). while possible, this is normally not desirable or practical where two or more transistors are controlled. equalizing the parasitic impedances of three traces while positioning the transistors next to their heat sink and meeting ul/vde voltage spacings is just too difficult. grounding the gate drive buffer as in option (a) solves the mosfet turn on problem by eliminating l s1 from the to eliminate this problem, a ground level transformation circuit must be added that rejects this common mode transient. the simplest is a decoupling circuit, also illustrated in fig. 7. the capacitor voltage (on c d ) remains constant while the transient voltage is dropped across r d and the buffer detects no input transition, eliminating the oscillation. this circuit does add significantly to turn-on and turn-off delay time, and cannot be used if the transient lasts as long as these delays are allowed to extend. delay times must be considered in selection of system deadtime. it is also important to consider the layout of the bypass capacitor as well as the oscillator components in order to keep these as close to the device as possible. isolation the most complex (and most effective) method of eliminating the effects of transients between grounds is isolation. optocouplers and pulse transformers are the most commonly used isolation techniques, and work very well in this case. the ixdp630/631 has been specifically designed to directly drive a high speed optocoupler like the hewlett packard hcpl22xx family or the general instrument 740l60xx optologic family. these optos are especially well suited to motor control and power conversion equipment due to their very high common-mode dv/dt rejection capabilities. the major problem associated with using an optocoupler in a power circuit is its common-mode dv/dt capability. when a lower transistor is turned on, its collector (or drain) is pulled to ground very quickly. the optocoupler that drives the upper transistor has its local output stage referenced to the emitter (source) of this upper device, which is tied to the collector of the lower device. as this node moves, the dv/dt between here and input circuit common is im- pressed across the upper optocoupler. this causes displacement currents to flow in sensitive nodes in the optical receiver circuitry, and may cause false triggering of the output. always pay strict attention to the manufacturer's recommended dv/dt ratings - exceeding them could be disastrous. power transistors (mosfets in this example) controlled by a common digital ic (the ixdp630). with the gate drive amplifier (a discrete circuit or possibly an ic driver like the ixbd4410) grounded as in option (b), the communication path from the ixdp630 will operate without errors. the pc trace induced voltages are not common with the digital path so the input of the gate drive buffer will not see or respond to them. unfortunately, the mosfet will not operate properly. the voltage induced across l s1 when q1 is turned on, acts as source dege- neration, modifying the turn-on behavior of the mosfet. if l s1 = 27 nh, and v cc is 12 v (assuming the gate plateau of fig. 7. potential layout problems that create functional problems. source feedback loop. now, unfortuna- tely, the gate driver will oscillate every time you turn it on or off. as the ixdp630 output goes high, the gate driver output follows (after its propaga- tion delay) and the mosfet starts to conduct. the voltage transient induced across l s1 (v = ls1/di/dt) raises the local ground (point a) until it exceeds v oh (630)-v il (gate buffer) and the buffer (after its prop. delay) turns the mosfet off. now the mosfet current falls, v(ls1) drops, point (a) drops to (or slightly below) system ground, and the buffer detects a "1" at its input. after its propagation delay, it again turns the mosfet on, continuing the oscillation for one more cycle.
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