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slls067g ? august 1990 ? revised april 2006 1 post office box 655303 ? dallas, texas 75265 bidirectional transceiver meets or exceeds the requirements of ansi standard tia/eia?485?a and iso 8482:1987(e) high-speed low-power linbicmos ? circuitry designed for high-speed operation in both serial and parallel applications low skew designed for multipoint transmission on long bus lines in noisy environments very low disabled supply current ...200 a maximum wide positive and negative input/output bus voltage ranges thermal-shutdown protection driver positive-and negative-current limiting open-circuit failsafe receiver design receiver input sensitivit y... 200 mv max receiver input hysteresis . . . 50 mv typ operates from a single 5-v supply glitch-free power-up and power-down protection available in q-temp automotive highrel automotive applications configuration control / print support qualification to automotive standards description the sn55lbc176, sn65lbc176, sn65lbc176q, and sn75lbc176 differential bus transceivers are monolithic, integrated circuits designed for bidirectional data communi- cation on multipoint bus-transmission lines. they are designed for balanced transmission lines and meet ansi standard tia/eia?485?a (rs-485) and iso 8482:1987(e). please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications o f texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 8 7 6 5 r re de d v cc b a gnd d, jg, or p package (top view) 3212019 910111213 4 5 6 7 8 18 17 16 15 14 nc b nc a nc nc re nc de nc fk package (top view) nc r nc gnd nc v nc nc d nc nc ?no internal connection cc copyright ? 2000?2006, t exas instruments incorporated linbicmos and linasic are trademarks of texas instruments incorporated. input d h l x enable de h h l outputs a b h l l h z z driver differential inputs v id = v ia ?v ib v id 0.2 v ?0.2 v < v id < 0.2 v v id ? 0.2 v x open enable re l l l h l output r h ? l z h receiver h = high level, l = low level, ? = indeterminate, x = irrelevant, z = high impedance (off) function tables
slls067g ? august 1990 ? revised april 2006 2 post office box 655303 ? dallas, texas 75265 description (continued) the sn55lbc176, sn65lbc176, sn65lbc176q, and sn75lbc176 combine a 3-state, differential li ne driver and a differential input line receiver, both of which operate from a single 5-v power supply. the driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. the driver differential outputs and the receiver differential inputs connect internally to form a differential input /output (i/o) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or v cc = 0. this port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. very low device supply current can be achieved by disabling the driver and the receiver. these transceivers are suitable for ansi standard tia/eia?485 (rs-485) and iso 8482 applications to the extent that they are specified in the operating conditions and characteristics section of this data sheet. certain limits contained in tia/eia?485?a and iso 8482:1987 (e) are not met or cannot be tested over the entire military temperature range. the sn55lbc176 is characterized for operation from ? 55 c to 125 c. the sn65lbc176 is characterized for operation from ?40 c to 85 c, and the sn65lbc176q is characterized for operation from ? 40 c to 125 c. the sn75lbc176 is characterized for operation from 0 c to 70 c. logic symbol ? logic diagram (positive logic) 2 en1 b a 1 4 2 r d re 7 6 d re r 7 6 4 1 2 b a bus 3 en2 1 1 de 3 de ? this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. available options t a package part number part marking 0 c to 70 c sop sn75lbc176d 7lb176 0 c to 70 c pdip sn75lbc176p 75lbc176 ?40 c to 85 c sop sn65lbc176d 6LB176 ?40 c to 85 c pdip sn65lbc176p 65lbc176 ?40 c to 110 c sop sn65lbc176qd lb176q ?40 c to 110 c sop sn65lbc176qdr lb176q ?55 c to 125 c lccc snj55lbc176fk snj55lbc176fk ?55 c to 125 c cdip snj55lbc176jg snj55lbc176
slls067g ? august 1990 ? revised april 2006 3 post office box 655303 ? dallas, texas 75265 schematics of inputs and outputs input v cc equivalent of d, re , and de inputs typical of receiver output output v cc v cc 100 k ? nom a port only 18 k ? nom 3 k ? nom a or b 100 k ? nom b port only 1.1 k ? nom typical of a and b i/o ports absolute maximum ratings ? supply voltage, v cc (see note 1) 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range at any bus terminal ?10 v to 15 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v i (d, de, r, or re ) ?0.3 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . receiver output current, i o 10 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values, except differential i/o bus voltage, are with respect to network ground terminal. dissipation rating table package thermal model t a < 25 c power rating derating factor above t a = 25 c t a = 70 c power rating t a = 85 c power rating t a = 110 c power rating d low k ? 526 mw 5.0 mw/ c 301 mw 226 mw ? d high k ? 882 mw 8.4 mw/ c 504 mw 378 mw ? p 840 mw 8.0 mw/ c 480 mw 360 mw ? jg 1050 mw 8.4 mw/ c 672 mw 546 mw 210 mw fk 1375 mw 11.0 mw/ c 880 mw 715 mw 440 mw ? in accordance with the low effective thermal conductivity metric definitions of eia/jesd 51?3. ? in accordance with the high effective thermal conductivity metric definitions of eia/jesd 51?7.
slls067g ? august 1990 ? revised april 2006 4 post office box 655303 ? dallas, texas 75265 recommended operating conditions min nom max unit supply voltage, v cc 4.75 5 5.25 v voltage at any bus terminal (separately or common mode), v i or v ic ?7 12 v high-level input voltage, v ih d, de, and re 2 v low-level input voltage, v il d, de, and re 0.8 v differential input voltage, v id (see note 2) ?12 12 v high-level output current, i oh driver ?60 ma high-level output current, i oh receiver ?400 a low-level output current, i ol driver 60 ma low-level output current, i ol receiver 8 ma junction temperature, t j 140 c sn55lbc176 ?55 125 operating free-air temperature, t a sn65lbc176 ?40 85 c operating free-air temperature, t a sn65lbc176q ?40 125 c sn75lbc176 0 70 note 2: differential input /output bus voltage is measured at the noninverting terminal a with respect to the inverting terminal b.
slls067g ? august 1990 ? revised april 2006 5 post office box 655303 ? dallas, texas 75265 driver section electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v ik input clamp voltage i i = ? 18 ma ?1.5 v v o output voltage i o = 0 0 6 v | v od1 | differential output voltage i o = 0 1.5 6 v 55lbc176, | v od2 | differential output voltage r l = 54 ? , see figure 1, 55lbc176, 65lbc176, 1.1 v | v od2 | differential output voltage r l = 54 ? , see note 3 see figure 1, 65lbc176, 65lbc176q 1.1 v od2 see note 3 75lbc176 1.5 5 v = ? 7 v to 12 v, see figure 2, 55lcb176, 65lcb176, 1.1 v od3 differential output voltage v test = ? 7 v to 12 v, see note 3 see figure 2, 65lcb176, 65lbc176q 1.1 v od3 see note 3 75lbc176 1.5 5 ? | v od | change in magnitude of differential output voltage ? ?0.2 0.2 v v oc common-mode output voltage r l = 54 ? or 100 ? , see figure 1 ?1 3 v ? | v oc | change in magnitude of common-mode output voltage ? r l = 54 ? or 100 ? , see figure 1 ?0.2 0.2 v i o output current output disabled, v o = 12 v 1 ma i o output current output disabled, see note 4 v o = ? 7 v ?0.8 ma i ih high-level input current v i = 2.4 v ?100 a i il low-level input current v i = 0.4 v ?100 a v o = ? 7 v ?250 i os short-circuit output current v o = 0 ?150 ma i os short-circuit output current v o = v cc 250 ma v o = 12 v 250 receiver disabled 55lbc176, 65lbc176q 1.75 i cc supply current v i = 0 or v cc , receiver disabled and driver enabled 65lbc176, 75lbc176 1.5 ma i cc supply current v i = 0 or v cc , no load receiver and driver 55lbc176, 65lbc176q 0.25 ma receiver and driver disabled 65lbc176, 75lbc176 0.2 ? ? | v od | and ? | v oc | are the changes in magnitude of v od and v oc , respectively, that occur when the input changes from a high level to a low level. notes: 3. this device meets the v od requirements of tia/eia?485?a above 0 c only. 4. this applies for both power on and off; refer to tia/eia?485?a for exact conditions.
slls067g ? august 1990 ? revised april 2006 6 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature parameter test conditions sn55lbc176 sn65lbc176q sn65lbc176 sn75lbc176 unit parameter test conditions min typ max min typ ? max unit t d(od) differential output delay time r l = 54 ? , ?, see figure 3 c l = 50 pf, 12 12 ns t sk(p) pulse skew ( | t d(odh) ? t d(odl) |) see figure 3 6 0 6 ns t pzh output enable time to high level r l = 110 ? , see figure 4 65 35 ns t pzl output enable time to low level r l = 110 ? , see figure 5 65 35 ns t phz output disable time from high level r l = 110 ? , see figure 4 105 60 ns t plz output disable time from low level r l = 110 ? , see figure 5 105 35 ns ? all typical values are at v cc = 5 v, t a = 25 c. symbol equivalents data sheet parameter rs-485 v o v oa , v ob | v od1 | v o | v od2 | v t (r l = 54 ? ) | v od3 | v t (test termination measurement 2) ? | v od | || v t | ? | v t || v oc | v os | ? | v oc | | v os ? v os | i os none i o i ia , i ib
slls067g ? august 1990 ? revised april 2006 7 post office box 655303 ? dallas, texas 75265 receiver section electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) parameter test conditions min typ ? max unit v it + positive-going input threshold voltage v o = 2.7 v, i o = ? 0.4 ma 0.2 v v it ? negative-going input threshold voltage v o = 0.5 v, i o = 8 ma ?0.2 ? v v hys hysteresis voltage (v it + ? v it ? ) (see figure 4) 50 mv v ik enable-input clamp voltage i i = ? 18 ma ?1.5 v v oh high-level output voltage v id = 200 mv, i oh = ? 400 a, 2.7 v v oh high-level output voltage v id = 200 mv, see figure 6 i oh = ? 400 a, 2.7 v v ol low-level output voltage v id = ?200 mv, i ol = 8 ma, 0.45 v v ol low-level output voltage v id = ?200 mv, see figure 6 i ol = 8 ma, 0.45 v i oz high-impedance-state output current v o = 0.4 v to 2.4 v ?20 20 a i i line input current other input = 0 v, v i = 12 v 1 ma i i line input current other input = 0 v, see note 5 v i = ? 7 v ?0.8 ma i ih high-level enable-input current v ih = 2.7 v ?100 a i il low-level enable-input current v il = 0.4 v ?100 a r i input resistance 12 k ? receiver enabled and driver disabled 3.9 ma i cc supply current v i = 0 or v cc , no load receiver and sn55lbc176, sn65lbc176, 0.25 i cc supply current no load receiver and driver disabled sn65lbc176, sn65lbc176q 0.25 ma driver disabled sn75lbc176 0.2 ? all typical values are at v cc = 5 v, t a = 25 c. ? the algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet. note 5: this applies for both power on and power off. refer to ansi standard rs-485 for exact conditions. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 15 pf parameter test conditions sn55lbc176 sn65lbc176q sn65lbc176 sn75lbc176 unit parameter test conditions min max min typ ? max unit t plh propagation delay time, low- to high-level single-ended output v id = ? 1.5 v to 1.5 v, 11 37 11 33 ns t phl propagation delay time, high- to low-level single-ended output v id = ? 1.5 v to 1.5 v , see figure 7 11 37 11 33 ns t sk(p) pulse skew ( | t plh ? t phl |) 10 3 6 ns t pzh output enable time to high level see figure 8 35 35 ns t pzl output enable time to low level see figure 8 35 30 ns t phz output disable time from high level see figure 8 35 35 ns t plz output disable time from low level see figure 8 35 30 ns ? all typical values are at v cc = 5 v, t a = 25 c.
slls067g ? august 1990 ? revised april 2006 8 post office box 655303 ? dallas, texas 75265 parameter measurement information v oc 2 r l v od2 v test v od3 60 ? 375 375 ? 2 r l figure 1. driver v od and v oc figure 2. driver v od3 voltage waveforms 50% t t(od) t d(odl) 10% t t(od) 2.5 v ? 2.5 v 90% 50% output t d(odh) 0 v 3 v 1.5 v input test circuit output c l = 50 pf (see note b) r l = 54 ? 50 ? 3 v generator (see note a) 1.5 v figure 3. driver test circuit and voltage waveforms voltage waveforms t phz 1.5 v 2.3 v 0.5 v 0 v 3 v t pzh output input 1.5 v s1 0 v or 3 v output test circuit 50 ? v oh v off 0 v r l = 110 ? generator (see note a) c l = 50 pf (see note b) figure 4. driver test circuit and voltage waveforms test circuit output r l = 110 ? 5 v s1 50 ? 3 v or 0 v voltage waveforms 5 v v ol 0.5 v t pzl 3 v 0 v t plz 2.3 v 1.5 v output input c l = 50 pf (see note b) generator (see note a) 1.5 v figure 5. driver test circuit and voltage waveforms notes: a. the input pulse is supplied by a generator having the following characteristics: prr 1 mhz, 50% duty cycle, t r 6 ns, t f 6 ns, z o =50 ? . b. c l includes probe and jig capacitance.
slls067g ? august 1990 ? revised april 2006 9 post office box 655303 ? dallas, texas 75265 parameter measurement information ?i oh +i ol v ol v id v oh figure 6. receiver v oh and v ol 51 ? c l = 15 pf (see note b) output 1.5 v 0 v test circuit voltage waveforms 1.5 v 3 v 0 v input output 1.3 v v oh v ol t phl t plh generator (see note a) 1.5 v 1.3 v notes: a. the input pulse is supplied by a generator having the following characteristics: prr 1 mhz, 50% duty cycle, t r 6 ns, t f 6 ns, z o =50 ? . b. c l includes probe and jig capacitance. figure 7. receiver test circuit and voltage waveforms thermal characteristics ? d package parameter test conditions min typ max unit junction?to?ambient thermal reisistance, ja ? low-k board, no air flow 199.4 junction?to?ambient thermal reisistance, ja ? high-k board, no air flow 119 c/w junction?to?board thermal reisistance, jb high-k board, no air flow 67 c/w junction?to?case thermal reisistance, jc 46.6 average power dissipation, p (avg) r l = 54 ?, input to d is 10 mbps 50% duty cycle square wave, v cc = 5.25 v, t j = 130 c. 330 mw thermal shutdown junction temperature, t sd 165 c ? see ti application note literature number szza003, package thermal characterization methodologies, for an explanation of this p arameter.
slls067g ? august 1990 ? revised april 2006 10 post office box 655303 ? dallas, texas 75265 parameter measurement information input 3 v t pzh 1.5 v 1.5 v 0 v v oh 0 v 0 v 1.5 v 3 v input 1.3 v v oh 0.5 v output t phz output 0 v 1.5 v 3 v input t plz input 3 v 1.5 v 0 v output 1.5 v output v ol 1.3 v t pzl 4.5 v v ol 0.5 v s1 to 1.5 v s2 open s3 closed s3 opened s2 closed s1 to ?1.5 v s1 to 1.5 v s2 closed s3 closed s3 closed s2 closed s1 to ?1.5 v voltage waveforms test circuit 50 ? s3 5 v s2 2 k ? 5 k ? s1 ?1.5 v 1.5 v 1n916 or equivalent generator (see note a) c l = 15 pf (see note b) figure 8. receiver test circuit and voltage waveforms notes: a. the input pulse is supplied by a generator having the following characteristics: prr 1 mhz, 50% duty cycle, t r 6 ns, t f 6 ns, z o =50 ? . b. c l includes probe and jig capacitance.
slls067g ? august 1990 ? revised april 2006 11 post office box 655303 ? dallas, texas 75265 thermal characteristics of ic packages ja (junction-to-ambient thermal resistance) is defined as the difference in ju nction temperature to ambient temperature divided by the operating power ja is not a constant and is a strong function of the pcb design (50% variation) altitude (20% variation) device power (5% variation) ja can be used to compare the thermal performance of packages if the specific test conditions are defined and used. standardized testing includes specification of pcb construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. ja is often misused when it is used to calculate junction temperatures for other installations. ti uses two test pcbs as defined by jedec specifications. the low-k board gives average in-use condition thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. the high-k board gives best case in?use condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. a 4% to 50% difference in ja can be measured between these two test cards jc (junction-to-case thermal resistance) is defined as difference in junction temperature to case divided by the operating power. it is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. jc is a useful thermal characteristic when a heatsink is applied to package. it is not a useful characteristic to predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and junction temperatures are backed out. it can be used with jb in 1-dimensional thermal simulation of a package system. jb (junction-to-board thermal resistance) is defined to be the difference in the junction temperature and the pcb temperature at the center of the package (closest to the die) when the pcb is clamped in a cold?plate structure. jb is only defined for the high-k test card. jb provides an overall thermal resistance between the die and the pcb. it includes a bit of the pcb thermal resistance (especially for bga?s with thermal balls) and can be used for simple 1-dimensional network analysis of package system (see figure 1). surface node jc calculated/measured junction jb calculated/measured pc board ca calculated ambient node figure 1. thermal resistance
slls067g ? august 1990 ? revised april 2006 12 post office box 655303 ? dallas, texas 75265 mechanical information d (r-pdso-g**) plastic small-outline package 14 pins shown 4040047 / d 10/96 0.228 (5,80) 0.244 (6,20) 0.069 (1,75) max 0.010 (0,25) 0.004 (0,10) 1 14 0.014 (0,35) 0.020 (0,51) a 0.157 (4,00) 0.150 (3,81) 7 8 0.044 (1,12) 0.016 (0,40) seating plane 0.010 (0,25) pins ** 0.008 (0,20) nom a min a max dim gage plane 0.189 (4,80) (5,00) 0.197 8 (8,55) (8,75) 0.337 14 0.344 (9,80) 16 0.394 (10,00) 0.386 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 ? 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
slls067g ? august 1990 ? revised april 2006 13 post office box 655303 ? dallas, texas 75265 mechanical information fk (s-cqcc-n**) leadless ceramic chip carrier 4040140 / c 11/95 28 terminals shown b 0.358 (9,09) max (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) a no. of min max 0.358 0.660 0.761 0.458 0.342 (8,69) min (11,23) (16,26) 0.640 0.740 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) ** 20 28 52 44 68 84 0.020 (0,51) terminals 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 12 13 14 15 16 18 17 11 10 8 9 7 5 4 3 2 0.020 (0,51) 0.010 (0,25) 6 1 28 26 27 19 21 b sq a sq 22 23 24 25 20 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a metal lid. d. the terminals are gold-plated. e. falls within jedec ms-004
slls067g ? august 1990 ? revised april 2006 14 post office box 655303 ? dallas, texas 75265 mechanical information jg (r-gdip-t8) ceramic dual-in-line package 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) seating plane 4040107/c 08/96 5 4 0.065 (1,65) 0.045 (1,14) 8 1 0.020 (0,51) min 0.400 (10,20) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) max 0.130 (3,30) min 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0 ?15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification only on press ceramic glass frit seal only. e. falls within mil-std-1835 gdip1-t8
mpdi001a ? january 1995 ? revised june 1999 15 post office box 655303 ? dallas, texas 75265 mechanical information p (r-pdip-t8) plastic dual-in-line 8 4 0.015 (0,38) gage plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) nom max 0.430 (10,92) 4040082/d 05/98 0.200 (5,08) max 0.125 (3,18) min 5 0.355 (9,02) 0.020 (0,51) min 0.070 (1,78) max 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 1 0.015 (0,38) 0.021 (0,53) seating plane m 0.010 (0,25) 0.100 (2,54) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001 for the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-9318301q2a active lccc fk 20 1 tbd post-plate n / a for pkg type 5962-9318301qpa active cdip jg 8 1 tbd a42 snpb n / a for pkg type sn65lbc176d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn65lbc176dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn65lbc176dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn65lbc176drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn65lbc176p active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type sn65lbc176pe4 active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type sn65lbc176qd active soic d 8 75 tbd cu nipdau level-1-220c-unlim sn65lbc176qdr active soic d 8 2500 tbd cu nipdau level-1-220c-unlim sn75lbc176d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn75lbc176dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn75lbc176dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn75lbc176drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn75lbc176p active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type sn75lbc176pe4 active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type snj55lbc176fk active lccc fk 20 1 tbd post-plate n / a for pkg type snj55lbc176jg active cdip jg 8 1 tbd a42 snpb n / a for pkg type (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder package option addendum www.ti.com 12-jan-2007 addendum-page 1
temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 12-jan-2007 addendum-page 2
mechanical data mcer001a january 1995 revised january 1997 post office box 655303 ? dallas, texas 75265 jg (r-gdip-t8) ceramic dual-in-line 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) seating plane 4040107/c 08/96 5 4 0.065 (1,65) 0.045 (1,14) 8 1 0.020 (0,51) min 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) max 0.130 (3,30) min 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification. e. falls within mil std 1835 gdip1-t8
mechanical data mlcc006b october 1996 post office box 655303 ? dallas, texas 75265 fk (s-cqcc-n**) leadless ceramic chip carrier 4040140 / d 10/96 28 terminal shown b 0.358 (9,09) max (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) a no. of min max 0.358 0.660 0.761 0.458 0.342 (8,69) min (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) ** 20 28 52 44 68 84 0.020 (0,51) terminals 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 12 13 14 15 16 18 17 11 10 8 9 7 5 4 3 2 0.020 (0,51) 0.010 (0,25) 6 1 28 26 27 19 21 b sq a sq 22 23 24 25 20 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a metal lid. d. the terminals are gold plated. e. falls within jedec ms-004
mechanical data mpdi001a january 1995 revised june 1999 post office box 655303 ? dallas, texas 75265 p (r-pdip-t8) plastic dual-in-line 8 4 0.015 (0,38) gage plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) nom max 0.430 (10,92) 4040082/d 05/98 0.200 (5,08) max 0.125 (3,18) min 5 0.355 (9,02) 0.020 (0,51) min 0.070 (1,78) max 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 1 0.015 (0,38) 0.021 (0,53) seating plane m 0.010 (0,25) 0.100 (2,54) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001 for the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

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