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mos integrated circuit m pd9611 the information in this document is subject to change without notice. document no. s11018ej2v0ds00 (2nd edition) date published october 1996 p printed in japan the m pd9611 incorporates 4-channel a-law/ m -law pcm codecs compliant with itu-t recommendation g.711/ g.714 and is suitable for applications such as pbx analog subscriber line circuits. its gain setting circuit allows transmit/receive gain to be set for 4 channels independently by externally inputting digital signals. features ? single-chip cmos monolithic lsi ? itu-t recommendation g.711/g.714 compliant ? four-channel pcm codecs integrated on a single chip ? compatible with a-law and m -law ? digital gain setting for each channel ? transmit : +7.5 to C8.0 db (0.5 db step) ? receive : 0 to C15.5 db (0.5 db step) ? data transfer system: transmit/receive synchronization ? data rate: 2048 khz ? +5 v single power supply ? power down function for each channel ? low power consumption ordering information part number package m pd9611gt 48-pin shrink sop (375 mil) four-channel pcm codec 1996 preliminary data sheet
m pd9611 2 pin configuration (top view) 48-pin shrink sop (375 mil) acom in 1-acom in 4 : analog common voltage in acom out 1-acom out 4 : analog common voltage out agnd1-agnd4 : analog ground a in 1-a in 4 : analog signal in a out 1-a out 4 : analog signal out av dd 1-av dd 4 : analog power supply dclk : data clock in dgnd : digital ground d r : receive pcm data in dv dd : digital power supply d x : transmit pcm data out fsc : frame synchronous clock in law : a-law/ m -law control in nc : no connection pd1-pd4 : power down control rst : reset in sp clk : serial port data clock in sp data : serial port data in sp sync : serial port synchronous clock in subgnd : sub ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a in 1 a out 1 nc a in 2 a out 2 nc acom in 1 acom out 1 acom in 2 acom out 2 av dd 1 av dd 2 av dd 3 av dd 4 dv dd nc pd1 pd2 pd3 pd4 fsc dclk d x d r a in 4 a out 4 nc a in 3 a out 3 nc acom in 3 acom out 3 acom in 4 acom out 4 agnd1 agnd2 agnd3 agnd4 subgnd dgnd nc nc nc rst law sp data sp sync sp clk pd9611gt m
m pd9611 3 block diagram av dd 1av dd 2av dd 3av dd 4dv dd a in 1 a out 1 a in 2 a out 2 a in 3 a out 3 a in 4 a out 4 acom in 1 acom in 2 agnd1 ch3 ch4 fsc dclk i/o linear a, dgs mux, demux clock generator voltage reference apd1 apd2 m d x d r rst sp sync sp clk sp data law pd1 pd2 pd3 pd4 dsp channel fiiter ch2 acom in 3 apd3 acom in 4 apd4 apd1 apd2 apd3 apd4 acom in 1 acom out 1 acom in 2 acom out 2 acom in 3 acom out 3 acom in 4 acom out 4 agnd2 agnd3 agnd4 dgnd subgnd ch1 a/d d/a
m pd9611 4 1. pin description pin no. symbol i/o name and function 1a in 1 i transmit analog input pin for channel 1 when not used, connect to acom out 1 pin. 2a out 1 o receive analog output pin for channel 1 3 nc C leave this pin open. 4a in 2 i receive analog input pin for channel 2 when not used, connect to acom out 1 pin. 5a out 2 o transmit analog output pin for channel 2 6 nc C leave this pin open. 7 acom in 1 i signal reference voltage input for channel 1 8 acom out 1 o signal reference voltage output for channel 1 9 acom in 2 i signal reference voltage input for channel 2 10 acom out 2 o signal reference voltage output for channel 2 11 av dd 1 C analog power supply pin for channel 1 +5 0.25 v 12 av dd 2 C analog power supply pin for channel 2 +5 0.25 v 13 av dd 3 C analog power supply pin for channel 3 +5 0.25 v 14 av dd 4 C analog power supply pin for channel 4 +5 0.25 v 15 dv dd C digital power supply pin +5 0.25 v 16 nc C leave this pin open. 17 pd1 i power-down control input pin for channel 1 channel 1 enters power-down mode when this signal is low level. the output of d x pin for channel 1 becomes high-impedance and a out 1 becomes signal reference voltage in the power-down mode. 18 pd2 i power-down control input pin for channel 2 channel 2 enters power-down mode when this signal is low level. the output of d x pin for channel 2 becomes high-impedance and a out 2 becomes signal reference voltage in the power-down mode. 19 pd3 i power-down control input pin for channel 3 channel 3 enters power-down mode when this signal is low level. the output of d x pin for channel 3 becomes high-impedance and a out 3 becomes signal reference voltage in the power-down mode. 20 pd4 i power-down control input pin for channel 4 channel 4 enters power-down mode when this signal is low level. the output of d x pin for channel 4 becomes high-impedance and a out 4 becomes signal reference voltage in the power-down mode. 21 fsc i frame synchronous clock input pin (8 khz) 22 dclk i data clock input pin (2048 khz) 23 d x o transmit pcm data output pin this pin outputs pcm data for channel 1 to 4 in synchronization with rising edges of dclk after rising edges of fsc. it becomes high-impedance for other timings. 24 d r i receive pcm data input pin this pin inputs pcm data for channel 1 to 4 in synchronization with falling edges of dclk after rising edges of fsc. 25 sp clk i setting data clock input pin 26 sp sync i setting synchronous clock input pin 27 sp data i setting data input pin
m pd9611 5 pin no. symbol i/o name and function 28 law i a-law/ m -law select pin in common to four channels l: a-law, h: m -law 29 rst C reset input, power-on reset pin h: normal operation l : internal registers are in the default status. 30-32 nc C leave this pin open. 33 dgnd C digital ground pin 34 subgnd C substrate ground pin 35 agnd4 C analog ground pin for channel 4 36 agnd3 C analog ground pin for channel 3 37 agnd2 C analog ground pin for channel 2 38 agnd1 C analog ground pin for channel 1 39 acom out 4 o signal reference voltage output for channel 4 40 acom in 4 i signal reference voltage input for channel 4 41 acom out 3 o signal reference voltage output for channel 3 42 acom in 3 i signal reference voltage input for channel 3 43 nc C leave this pin open. 44 a out 3 o receive analog output pin for channel 3 45 a in 3 i transmit analog input pin for channel 3 when not used, connect to acom out 1 pin. 46 nc C leave this pin open. 47 a out 4 o receive analog output pin for channel 4 48 a in 4 i transmit analog input pin for channel 4 when not used, connect to acom out 1 pin.
m pd9611 6 2. cautions on use (1) absolute maximum ratings application of voltage or current in excess of the absolute maximum ratings to the m pd9611 may result in damage due to latch up, etc. be especially cautions about power supply noise, etc. (2) wiring pattern the design of the ground pattern is extremely important for operating the m pd9611 with high precision. connect the analog ground pins (agnd1 to agnd4), digital ground pin (dgnd) and substrate ground pin (subgnd) close to the ic pins, and connect to a wide analog ground line on the board. (3) addition of bypass capacitors for power supply pins because the m pd9611 uses many internal high-frequency operational amplifiers, high power supply impedance can cause instability (such as oscillation) in these internal operational amplifiers. to suppress such instability and eliminate power supply noise, connect all power supply pins (av dd 1 to av dd 4, dv dd ) close to the ic pins, and put bypass capacitors (c vdd = approximately 0.1 m f) having superior high-frequency characteristics very close to the pins. (4) addition of bypass capacitors for acom pins the m pd9611 incorporates references voltages for signal sources. superposing of noise on these reference voltages may have adverse effects on transmission characteristics, etc. therefore, connect the acom out pin and acom in pin close to the ic pins, and put bypass capacitors (c acom = approximately 0.1 m f) having superior high-frequency characteristics very close to the pins. (5) control or sp data pin on reset when inputting the setting data from the sp data pin after the m pd9611 is reset, first input the following patterns to reset to 0 the couter used to fetch data from the sp data pin. 16 clocks or more 1 clocks or more rst sp clk sp sync sp data after ther rst pin has been set to the high level, input 1 clock or more to the sp clk pin, set the sp sync pin to the high level and input 16 clocks more to the sp clk pin. during this operation, the sp data pin is held at the low level. afterwards, input the setting data.
m pd9611 7 3. general operation (1) pcm data transfer in the transmit section, if fsc pin is set to the high level in synchronization with the rising edge ( ) of the data clock applied to the dclk pin, the d x pin becomes active and sign bit data (msb) of channel 1 is output. the following data of 7 bits is clocked out in synchronization with the rising edge ( ) of each data clock. sign bit data (msb) of channel 2 is output in synchronization with the rising edge ( ) of the 9th data clock. in the same manner, each data up to channel 4 is output and the rising edge ( ) of the 33rd data clock then sets the d x pin to high-impedance state. similarly, in the receive section, if the fsc pin is set to the high level in synchronization with the rising edge ( ) of the data clock applied to the dclk pin, data of d r pin is latched by the falling edges ( ? ) of the data clock and consecutively clocked in. (2) power down control the m pd9611 has the following two methods for power down control and is able to control power-down independently for each channel. ? sets pins pd1 to pd4 to high or low level. ? inputs 8-bit setting data from sp data pin (see (5) control of sp data pin ). internal data is the logical sum of pd1 to pd4 pin state and 8-bit setting data input. if the internal data is 0, the channel enters the power-down state. if the internal data is 1, the channel enters the power-up state. in the power down state, pcm data in the channel goes to high-impedance state and analog output becomes the signal reference voltage level. 8-bit setting data pd1 pin internal data (channel 1) 000 101 011 111 remarks 1. 0: power down, 1: power up 2. the settings are the same for channel 2 to channel 4.
m pd9611 8 (3) a-law/ m -law control the m pd9611 has the following two methods for a-law/ m -law control. ? sets law pin to high or low level. ? inputs 8-bit setting data from sp data pin (see (5) control of sp data pin ). internal data is the logical sum of law pin state and 8-bit setting data input. if the internal data is 0, the m pd9611 enters a-law mode. if the internal data is 1, the m pd9611 enters m -law mode. 8-bit setting data law pin internal data 000 101 011 111 remark 0: a-law, 1: m -law (4) gain setting control for transmit/receive the m pd9611 can control gain settings independently for the transmit/receive by inputting 8-bit setting data (see (5) control of sp data pin ) from the sp data pin for four channels. gain can be set from +7.5 to C8.0 db for the transmit and +0.0 db t o C15.5 db for the receive in 0.5 db steps. 8-bit setting data input from sp data pin specifies the channel set in the first 8 bits, and performs selection of transmit/receive and gain setting in the second 8 bits.
m pd9611 9 (5) control of sp data pin if sp sync pin is set to the high level in synchronization with the rising edge ( ) of the data clock applied to the sp clk pin, data of the sp data pin is latched by the falling edge ( ? ) of the data clock and consecutively fetched in. after the 8-bit data has been fetched, the setting operation is performed according to the data. this setting operation is performed during the 8 clocks after fetching the data and the next data is valid at the 17th clock. therefore, when setting 1 word (8 bits) of data, input 17 clocks or more to the sp clk pin. ensure that 17 clocks or more are input to the sp clk pin between the rising of sp sync and the rising of the next sp sync . 123456789101112131415161718 sp sync sp clk sp data setting completed (the next data is valid.) setting operation data fetch dont care 17 clocks or more sp sync sp clk
m pd9611 10 ? a/ m -law, power down control notes 1. default setting is power down mode. 2. default setting is a-law mode. ? transmit/receive gain setting control (1st word) d7 0 d6 1 d5 d4 d3 ch1 d2 ch2 d1 ch3 d0 ch4 0/1 gain non-setting/setting for channel 4 0/1 gain non-setting/setting for channel 3 0/1 gain non-setting/setting for channel 2 0/1 gain non-setting/setting for channel 1 ? don t care ? don t care 1 identification code 0 identification code transmit/receive gain setting control (2nd word) d7 1 d6 1 d5 x/r d4 d3 d1 d0 0/1 gain setting 0/1 gain setting 0/1 gain setting 0/1 gain setting 0/1 gain setting 0/1 transmit/receive setting 1 identification code 1 identification code d2 setting data d7 1 d6 0 d5 d4 a/ d3 pd1 d2 pd2 d1 pd3 d0 pd4 0/1 power down/power up for channel 4 note 1 0/1 power down/power up for channel 3 note 1 0/1 power down/power up for channel 2 note 1 0/1 power down/power up for channel 1 note 1 0/1 setting of a-law/ -law note 2 ? don t care 0 identification code 1 identification code m m
m pd9611 11 table of gain setting codes (1/2) setting item setting 1st word 2nd word level d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 gain setting for transmit +7.5 db 01CCch1ch2ch3ch411010000 +7.0 db 11010001 +6.5 db 11010010 +6.0 db 11010011 +5.5 db 11010100 +5.0 db 11010101 +4.5 db 11010110 +4.0 db 11010111 +3.5 db 11011000 +3.0 db 11011001 +2.5 db 11011010 +2.0 db 11011011 +1.5 db 11011100 +1.0 db 11011101 +0.5 db 11011110 0.0 db note 11011111 C0.5 db 11000000 C1.0 db 11000001 C1.5 db 11000010 C2.0 db 11000011 C2.5 db 11000100 C3.0 db 11000101 C3.5 db 11000110 C4.0 db 11000111 C4.5 db 11001000 C5.0 db 11001001 C5.5 db 11001010 C6.0 db 11001011 C6.5 db 11001100 C7.0 db 11001101 C7.5 db 11001110 C8.0 db 11001111 note default setting
m pd9611 12 (2/2) setting item setting 1st word 2nd word level d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 gain setting for receive 0.0 db note 01CCch1ch2ch3ch411111111 C0.5 db 11111110 C1.0 db 11111101 C1.5 db 11111100 C2.0 db 11111011 C2.5 db 11111010 C3.0 db 11111001 C3.5 db 11111000 C4.0 db 11110111 C4.5 db 11110110 C5.0 db 11110101 C5.5 db 11110100 C6.0 db 11110011 C6.5 db 11110010 C7.0 db 11110001 C7.5 db 11110000 C8.0 db 11101111 C8.5 db 11101110 C9.0 db 11101101 C9.5 db 11101100 C10.0 db 11101011 C10.5 db 11101010 C11.0 db 11101001 C11.5 db 11101000 C12.0 db 11100111 C12.5 db 11100110 C13.0 db 11100101 C13.5 db 11100100 C14.0 db 11100011 C14.5 db 11100010 C15.0 db 11100001 C15.5 db 11100000 note default setting
m pd9611 13 gain setting control is set by inputting 8-bit data fo the 1st word first and inputting 8-bit data of the 2nd word in synchronization with the next rising edge of sp sync . however, if data other than the identification code of the 2nd word is input after the input of the 1st word, the contents of the 1st word are ignored. (i) when gain setting control is valid remark because a/ m -law, power down control is input after input of gain setting control (1st word), gain setting control (1st word) becomes invalid and gain setting control (2nd word) also becomes invalid. (iii) when gain setting control is invalid C2 remark because gain setting control (2nd word) is input before gain setting control (1st word), gain setting control (1st word) becomes invalid. then, because a/ m -law, power down control is input even if gain setting control (1st word) is input, gain setting control (1st word) becomes invalid. (ii) when gain setting control is invalid C1 sp clk sp sync sp data 0 1 0 0 1 1 1 1 11011111 10001111 a/ -law, power down control (valid) gain setting control (1st word) (valid) gain setting control (2nd word) (valid) m sp clk sp sync sp data 1 0 0 0 1 1 1 1 11011111 01001111 a/ -law, power down control (valid) gain setting control (2nd word) (invalid) gain setting control (1st word) (invalid) m sp clk sp sync sp data 0 1 0 0 1 1 1 1 10001111 11011111 gain setting control (1st word) (invalid) a/ -law, power down control (valid) gain setting control (2nd word) (invalid) m
m pd9611 14 4. electrical specifications (preliminary) absolute maximum ratings (t a = 25 c) item symbol condition rating unit supply voltage v dd av dd 1, av dd 2, av dd 3, av dd 4, dv dd C0.3 to +7.0 v analog input voltage v ain a in 1, a in 2, a in 3, a in 4, acom in 1, C0.3 to v dd +0.3 acom in 2, acom in 3, acom in 4 digital input voltage v din d r , dclr, fsc, law, pd1, pd2, pd3, C0.3 to v dd +0.3 pd4, sp clk , sp sync , sp data , rst voltage applied to analog output v aout a out 1, a out 2, a out 3, a out 4, acom out 1, C0.3 to v dd +0.3 pin acom out 2, acom out 3, acom out 4 voltage applied to digital output pin v dout d x C0.3 to v dd +0.3 power dissipation p t 500 mw ambient operating temperature t a C20 to +85 c storage temperature t stg C65 to +150 caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. recommended operation conditions (t a = C20 to +85 c, v dd = 5 v 5 %, gnd = 0 v, f dclk = 2048 khz) (1) dc condition item symbol condition min. typ. max. unit ambient operating temperature t a C20 +25 +85 c supply voltage v dd av dd 1, av dd 2, av dd 3, av dd 4, dv dd 4.75 5.0 5.25 v analog input voltage v ai a in 1, a in 2, a in 3, a in 4 (acom as reference) C1.0 +1.0 analog output load resistance r load a out 1, a out 2, a out 3, a out 450 k w analog output load capacitance c load 50 pf high level input voltage v ih1 d r , dclk, fsc, law, pd1, pd2, pd3, 2.0 v dd v pd4, sp clk , sp sync , sp data v ih2 rst 0.8 v dd v dd low level input voltage v il1 d r , dclk, fsc, law, pd1, pd2, pd3, 0 0.8 pd4, sp clk , sp sync , sp data v il2 rst 0 0.2 v dd
m pd9611 15 (2) ac condition item symbol condition min. typ. max. unit data clock frequency f clk (= 1/t cy ) 50 ppm 2048 khz data clock pulse width t clk 200 ns frame synchronous clock frequency fs 50 ppm 8.0 khz high level frame synchronous t whs 200 ns pulse width low level frame synchronous t wls 8 m s pulse width clock rise time t r 50 ns clock fall time t f 50 ns float in synchronous timing t csd1 100 ns t csd2 40 ns frame synchronous clock and t whsc 100 ns data clock high level width d r setup time t dsr note 65 ns d r hold time t dhr note 120 ns sp data clock frequency f spclk 2048 khz sp data setup time t gsr note 100 ns sp data hold time t ghr note 100 ns float in sp synchronous timing t fsd 40 ns note set the rise time and fall time of the digital input waveform and clock signal used for measuring timings to 5 ns.
m pd9611 16 dc characteristics (t a = C20 to +85 c, v dd = 5 0.25 v, gnd = 0 v, f dclk = 2048 khz, and all output pins are unloaded.) (1) power consumption item symbol condition min. typ. max. unit circuit current i dd all channels in normal operation 23 30 ma power-down circuit current i ddpd all channels in power-down mode 5 6 (2) digital interface item symbol condition min. typ. max. unit digital input current i id d r , dclk, fsc, law, pd1, pd2, pd3, C10 +10 m a pd4, sp clk , sp sync , sp data , rst each pin 0 v din v dd 3-state leakage current i l d x pin 0 v din v dd C10 +10 high level output voltage v oh d x pin i oh = C150 m a v dd C0.3 v low level output voltage v ol d x pin i ol = 0.8 ma 0.4 digital output pin output capacitance c od f = 1 mhz, 0 v other than unmeasured pins 15 pf digital input pin input capacitance c id f = 1 mhz, 0 v other than unmeasured pins 10 (3) transmit amplifier (a in 1, a in 2, a in 3, a in 4 pins) item symbol condition min. typ. max. unit input bias current i b C10 +10 m a input resistance r in 1m w input capacitance c in 10 pf (4) receive power amplifier (a out 1, a out 2, a out 3, a out 4 pins) item symbol condition min. typ. max. unit output offset voltage v oa d r = +0 code C50 +50 mv acom as reference maximum output voltage v om acom as reference C1.02 +1.02 v output resistance r out 1 w (5) signal reference voltage output (acom out 1, acom out 2, acom out 3, acom out 4 pins) item symbol condition min. typ. max. unit output voltage v acom 2.35 2.4 2.45 v
m pd9611 17 ac characteristics (t a = C20 to +85 c, v dd = 5 0.25 v, gnd = 0 v, f dclk = 2048 khz) item symbol condition min. typ. max. unit data enable delay time t dzx1 d x when fsc is behind dclk 100 ns t dzx2 d x when fsc is ahead of dclk 100 ns data delay time t ddx d x pin 100 ns data hold time t hzx d x pin 25 ns
m pd9611 18 timing charts (1) transmit timing (a) when fsc is ahead of dclk fsc dclk msb d x lsb 7th 2nd hi-z hi-z 12 8 t r t whs t f t wls t whsc t csd2 t cy t r t clk t f t clk t dzx2 t ddx t hzx (b) when fsc is behind dclk fsc dclk msb d x lsb 7th 2nd hi-z hi-z 12 8 t csd1 t dzx1 t whsc
m pd9611 19 (2) receive timing (a) when fsc is ahead of dclk (b) when fsc is behind dclk fsc dclk t csd1 t whsc fsc dclk msb d r 7th 2nd 12 8 9 t r t whs t f t wls t whsc t csd2 t cy t r t clk t f t dsr t dhr don t care 8th don t care don t care t r , t f t clk t r , t f
m pd9611 20 (3) gain setting timing remark the relationship between sp sync and sp clk is the same as in the receive timing. d x output measuring circuit timing test waveform d7 d6 d5 d1 don t care don t care don t care don t care don t care d0 don t care 123 89 sp sync sp clk sp data t gsr t fsd t ghr (4) transmit, receive pcm data input/output timing charts 2.0 v 0.8 v 2.0 v 0.8 v test points all inputs/outputs other than d x pin 2.4 v 0.4 v 2.4 v 0.4 v test points d x pin output d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d4 d3 d2 d1 d0 d7 d6 d5 d4 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d4 d3 d2 d1 d0 d7 d6 d5 d4 12345678910111213 282930313233 2561234 dclk (2.048 mhz) fsc (8.0 khz) d x d r msb msb msb msb sb msb lsb lsb lsb lsb channel 1 data channel 1 data channel 2 data channel 2 data channel 1 data channel 1 data channel 4 data channel 4 data hi-z hi-z don t care don t care v dd 2 k w output 165 pf d x
m pd9611 21 (5) setting data input timing sp sync sp clk dont care setting data dont care msb lsb d7 d6 d5 d4 d3 d2 d1 d0 sp data d7 d6 d5 d4 msb setting data 1234567891011121314151617 1234
m pd9611 22 transmission characteristics (t a = C20 to +85 c, v dd = 5 0.25 v, gnd = 0 v, f dclk = 2048 khz) item symbol condition setting value unit zero transmission level point (transmit) otlp x referenced to 600 w C3.8 dbm zero transmission level point (receive) otlp x referenced to 600 w C3.8 dbm item symbol condition min. typ. max. unit insertion loss il a/d input signal C0.3 +0.3 db 0 dbm0 1 khz d/a input signal C0.3 +0.3 0 dbm0 1 khz transmission loss frequency f rx a/d 60 hz 24.0 C db characteristics reference input signal 200 hz 0 2.0 1015 hz 0 dbm0 300 to 3000 hz C0.15 +0.15 3200 hz C0.15 +0.65 3400 hz 0 0.8 3780 hz +6.5 f rr d/a 0 to 3000 hz C0.15 +0.15 reference input signal 3200 hz C0.15 +0.65 1015 hz 0 dbm0 3400 hz 0 +0.8 3780 hz +6.5 gain tracking (tone method) gt x a/d +3 to C40 dbm0 C0.2 +0.2 db reference input signal C50 dbm0 C0.5 +0.5 C10 dbm0 C55 dbm0 C1.0 +1.0 f = 700 to 1100 hz gt r d/a +3 to C40 dbm0 C0.2 +0.2 reference input signal C50 dbm0 C0.5 +0.5 C10 dbm0 C55 dbm0 C1.0 +1.0 f = 700 to 1100 hz transmit/receive channel sd x a/d +3 to C30 dbm0 36 db overall power distortion ratio input signal C40 dbm0 30 (tone method) f = 700 to 1100 hz C45 dbm0 25 sd r d/a +3 to C30 dbm0 36 input signal C40 dbm0 30 f = 700 to 1100 hz C45 dbm0 25 absolute delay characteristic d a a/a 540 m s input signal = 0 dbm0 absolute delay distortion d o a/a 500 hz 1400 m s frequency characteristics 600 hz 700 1000 to 2600 hz 200 2800 hz 1400 idle channel noise icn ada a/d a-law psophometric weighted C72 dbm0p icn daa d/a a-law psophometric weighted C80 icn ad m a/d m -law c-message weighted 18 dbrnc0 icn da m d/a m -law c-message weighted 10
m pd9611 23 item symbol condition min. typ. max. unit cross talk between channels ct a/a C70 db input signal = 0 dbm0 power supply rejection ratio psrr av dd 1, av dd 2, av dd 3, av dd 4, C25 db dv dd = 5 v 100 mv p-p coder offset a/d C5 +5 C input signal 0 v mutual modulation (2 tones) imd a/d 44.0 db input signal: f1, f2; 300 to 3400 hz, C4 to C21 dbm0 measuring signal: 2 f1 C f2 level (2 f1 C f2) vs level (f1, f2) d/a 44.0 db input signal: f1, f2; 300 to 3400hz, C4 to C21 dbm0 measuring signal: 2 f1 C f2 level (2 f1 C f2) vs level (f1, f2) discrimination a/d C27 db input signal: f; 4396 to 7796 hz 0 dbm0 measuring signal: 8000 C fhz out-of-band spurious d/a C27 db input signal: f; 204 to 3604 hz 0 dbm0 measuring signal: 8000 C fhz in-band spurious a/d C45 db input signal: f; 700 to 1100 hz 0 dbm0 measuring signal: any frequency d/a C45 db input signal: f; 700 to 1100 hz 0 dbm0 measuring signal: any frequency single frequency noise n sf d/a C54 dbm0 gain setting = 0 db measuring signal: f = up to 256 khz transmit gain setting d dgs x a/d difference from reference setting value C0.15 +0.15 db receive gain setting d dgs r d/a difference from reference setting value C0.15 +0.15
m pd9611 24 5. application circuit example av dd 1av dd 2av dd 3av dd 4dv dd a in 1 a out 1 a in 2 a out 2 a in 3 a out 3 a in 4 a out 4 acom in 1 acom in 2 agnd1 ch1 ch4 a/d i/o linear a, dgs mux, demux apd1 apd2 m d x d r rst sp sync sp clk sp data law pd1 pd2 pd3 pd4 dsp channel fiiter acom in 3 apd3 acom in 4 apd4 apd1 apd2 apd3 apd4 acom in 1 acom out 1 acom in 2 acom out 2 acom in 3 acom out 3 acom in 4 acom out 4 agnd2 agnd3 agnd4 dgnd subgnd v dd 0.1 f 100 k w acom out 1 m ch3 d/a pd1 pd2 pd3 pd4 law sp data d x d r rst fsc dclk clock generator sp sync sp clk fsc dclk 0.1 f m 0.1 f m 0.1 f m 0.1 f m voltage reference v dd 2 k w 0.1 f m acom out 1 acom out 1 0.1 f m ch2 100 k w acom in 1
m pd9611 25 6. package drawings 48 pin plastic shrink sop (375 mil) c b d e f g a 124 48 25 l i h j k detail of lead end 3 m m n +7 ? p48gt-65-375b-1 item millimeters inches a b c d e f g h i j k 16.21 max. 0.65 (t.p.) 2.0 max. 1.7 0.1 10.0 0.3 0.63 max. 0.639 max. 0.005 0.003 0.079 max. 0.394 0.315 0.008 0.025 max. note l m 0.5 0.2 0.15 1.0 0.2 8.0 0.2 0.004 0.020 +0.008 ?.009 each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 0.067 0.004 0.026 (t.p.) 0.006 n 0.10 0.004 0.012 0.30 0.10 0.125 0.075 +0.004 ?.002 0.10 +0.10 ?.05 +0.004 ?.005 +0.012 ?.013 0.039 +0.009 ?.008
m pd9611 26 7. recommended soldering conditions this product should be soldered and mounted under the conditions recommended below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, please contact your nec sales representative. surface mount type m pd9611gt: 48-pin shrink sop (375 mil) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c ir-35-103-2 duration: 30 sec. max. (210 c or above) number of times: 2 max. time limit: 3 days note (thereafter, 10-hour prebaking at 125 c required.) (1) wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) do not perform flux cleaning with water after the first reflow. pin heating pin temperature: 300 c max. duration: 3 sec. max. (per side of device) note for the storage period after unpacking from the dry-pack, storage conditions are max. 25 c, 65 % rh.
m pd9611 27 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd9611 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

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