dc C 16 ghz packaged divide-by-2 prescaler technical data HMMC-3102 features ? wide frequency range: 0.2 - 16 ghz ? high input power sensitivity: on-chip pre- and post-amps -20 to +10 dbm (1 - 10 ghz) -15 to +10 dbm (10 - 12 ghz) -10 to +5 dbm (12 - 15 ghz) ?p out : +6 dbm (0.99 v p-p ) will drive ecl ? low phase noise: -153 dbc/hz @ 100 khz offset ? (+) or (-) single supply bias with wide range: 4.5 to 6.5 v ? differential i/0 with on-chip 50 w matching description the HMMC-3102 is a packaged gaas hbt mmic prescaler which offers dc to 16 ghz frequency translation for use in communica- tions and ew systems incorporat- ing high-frequency pll oscillator circuits and signal-path down conversion applications. the prescaler provides a large input power sensitivity window and low phase noise. package type: 8-lead ssop plastic package dimensions: 4.9 x 3.9 mm typ. package thickness: 1.55 mm typ. lead pitch: 1.25 mm nom. lead width: 0.42 mm nom. absolute maximum ratings [1] (@ t a = 25 c, unless otherwise indicated) symbol parameters/conditions units min. max. v cc bias supply voltage volts +7 v ee bias supply voltage volts -7 |v cc - v ee | bias supply delta volts +7 v logic logic threshold voltage volts v cc -1.5 v cc -1.2 p in(cw) cw rf input power dbm +10 v rfin dc input voltage volts v cc 0.5 (@ rf in or rf in ports) t bs [2] backside operating temp. c -40 +85 t stg storage temperature c -65 +165 t max maximum assembly temp. c 310 (60 seconds max.) notes: 1. operation in excess of any parameter limit (except t bs ) may cause permanent damage to the device. 2. mttf > 5 x 10 5 hours @ t bs < 85 c. operation in excess of maximum operating temperature (t bs ) will degrade mttf.
2 HMMC-3102 dc specifications/physical properties, (t a = 25 c, v cc - v ee = 5.0 v unless otherwise listed) symbol parameters and test conditions units min. typ. max. v cc - v ee operating bias supply difference [1] volts 4.5 5.0 6.5 |i cc | or |i ee | bias supply current ma 68 80 92 v rfin(q) quiescent dc voltage appearing at all rf ports volts v cc v logic nominal ecl logic level volts v cc - 1.45 v cc - 1.35 v cc - 1.25 (v logic contact self-bias voltage, generated on-chip) note: 1. prescaler will operate over full specified supply voltage range. v cc or v ee not to exceed limits specified in absolute maximum ratings section. rf specifications, (t a = 25 c, z o = 50 w , v cc - v ee = 5.0 v) symbol parameters and test conditions units min. typ. max. | in(max) maximum input frequency of operation ghz 16 18 | in(min) minimum input frequency of operation [1] (p in = -10 dbm) ghz 0.2 0.5 | self-osc. output self-oscillation frequency [2] ghz 3.4 @ dc, (square-wave input) dbm -15 >-25 +10 @ | in = 500 mhz, (sine-wave input) dbm -15 >-20 +10 p in | in = 1 to 10 ghz dbm -15 >-25 +10 | in = 10 to 12 ghz dbm -10 >-15 +10 | in = 12 to 15 ghz dbm -4 >-10 +4 rl small-signal input/output return loss (@ | in < 12 ghz) db 15 s 12 small-signal reverse isolation (@ | in < 12 ghz) db 30 j n ssb phase noise (@ p in = 0 dbm, 100 khz offset dbc/hz -153 from a | out = 1.2 ghz carrier) jitter input signal time variation @ zero-crossing ps 1 ( | in = 10 ghz, p in = -10 dbm) t r or t f output transition time (10% to 90% rise/fall time) ps 70 @ | out < 1 ghz dbm 4 6 p out [3] | out = 2.5 ghz dbm 3.5 5.5 | out = 3.5 ghz dbm 0 2.0 @ | out < 1 ghz volts 0.99 |v out(p-p) | [4] | out = 2.5 ghz volts 0.94 | out = 3.5 ghz volts 0.63 | out power level appearing at rf in or rf in (@ | in = 12 ghz, dbm -40 p spitback unused rf out or rf out unterminated ) | out power level appearing at rf in or rf in (@ | in = 12 ghz, dbm -47 both rf out & rf out terminated ) p feedthru power level of | in appearing at rf out or rf out dbc -23 (@ | in = 12 ghz, p in = 0 dbm, referred to p in ( | in )) h 2 second harmonic distortion output level dbc -25 (@ | out = 3.0 ghz, referred to p out ( | out )) notes: 1. for sine-wave input signal. prescaler will operate down to d.c. for square-wave input signal. minimum divide frequency limite d by input slew-rate. 2. prescaler can exhibit this output signal under bias in the absence of an rf input signal. this condition may be eliminated by use of the input dc offset technique described on page 3. 3. fundamental of output square waves fourier series. 4. square wave amplitude calculated from p out . v rfout (q)
3 figure 1. HMMC-3102 simplified schematic. applications the HMMC-3102 is designed for use in high frequency communi- cations, microwave instrumenta- tion, and ew radar systems where low phase-noise pll control circuitry or broad-band frequency translation is required. operation the device is designed to operate when driven with either a single- ended or differential sinusoidal input signal over a 200 mhz to 16 ghz bandwidth. below 200 mhz the prescaler input is slew-rate limited, requiring fast rising and falling edge speeds to properly divide. the device will operate at frequencies down to dc when driven with a square- wave. ac coupling at p in 5 (rf in ) is recommended for most applications. the device can be operated from either a single positive or single negative supply. for positive supply operation v cc pins are nominally biased at any voltage in the +4.5 to +6.5 volt range with p in 8 (v ee ) grounded. for nega- tive bias operation v cc pins are typically grounded and a negative voltage between -4.5 to -6.5 volts is applied to p in 8 (v ee ). input dc offset to prevent false triggers or self- oscillation conditions, apply a 20 to 100 mv dc offset voltage between the rf in and rf in ports. this prevents noise or spurious low level signals from triggering the divider. gaas mmics are esd sensitive. proper precautions should be used when handling these devices. v cc bypass in in 642 v cc v cc v cc 5 50 in v cc v ee v pwr sel v cc 50 soic w/backside gnd 150p v ee out out 50 50 7 8 in 3 out pin 1 out
4 figure 3. assembly diagram. (single-supply, positive-bias configuration shown) figure 2. package and dimensions. v ee pin 1 v cc v cc v cc rf in rf in 3.80/4.00 5.80/6.20 4.80/5.00 rf out rf out 1.35/1.75 0 /8 0.10/0.25 0.19/.025 pin 8 0.33/0.51 0.40/1.27 1.27 bsc notes: all dimensions are min./max. in millimeters. refer to jedec outline ms-012 for additional tolerances. exposed heat slug area on pkg bottom = 2.67 x 1.65 v ee v cc rfin rfin v cc v cc rfout rfout v cc (+4.5 to +6.5 volts) ~1 f monoblock capacitor to operate component from a negative supply, ground each v cc connection and supply v ee with a negative voltage (-4.5 to -6.5 v) bypassed to ground with ~1 f capacitor. rf out should be terminated in 50 to ground (dc blocking capacitor required for positive bias configuration.)
5 HMMC-3102 supplemental data 024 input frequency, in (ghz) v cc ? ee = +5 v, t a = 25 c 20 10 0 -10 -20 -30 -40 input power, p in (dbm) 12 8 610 161820 14 100 90 80 70 60 50 40 30 20 10 0 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 i supply (ma) v logic ?v cc (v) 01 2 5 34 78 69 v cc ? ee (v) t a = 25 c high power mode low power mode figure 6. typical output voltage waveform. 8 6 4 2 0 -2 -4 -6 -8 p out (@ p in = 0 dbm) (dbm) 01 2 5 34 78 6 output frequency (ghz) v cc ? ee = +5 v, t a = 25 c input frequency, in (ghz) v cc ? ee = +5 v, p in = 0 dbm, t a = 25 c 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 p spitback (dbm) unterminated rf out port both rf out ports terminated 024 12 8 610 161820 14 figure 8. typical phase noise performance. figure 4. typical input sensitivity window. figure 5. typical supply current & v logic vs. supply voltage. figure 7. typical output power vs. output frequency, ? out (ghz). figure 9. typical spitback power. p(? out ) appearing at rf input port. period, (200 ps/div.) low p out mode, t r = ~70 ps, output freq: 882 mhz, t a = 25 c output voltage (80 mv/div.) -3 -23 -43 -63 -83 -103 -123 -143 -163 10 100 1k 10k 100k 1m 10m offset from carrier (hz) ssb phase noise (dbc/hz) p in = 0 dbm, f carrier = 6.0 ghz
this data sheet contains a variety of typical performance data. the information supplied should not be interpreted as a complete list of circuit specifications. in this data sheet the term typical refers to the 50th percentile performance. for additional information contact your local agilent sales representative. supplemental information input dc offset as long as an rf signal is always present and within the input power specifications, there will not be any problems with false triggering or self-oscillations. if this is not the case, you can put ? 10k w to ground from the unused input and this, when combined with the on-chip 50 w resistor to v cc = 5, will put an offset of ? 25 mv between the rf inputs (i.e., if rf in has 10kq to ground, it will be at ? 4.975 v and rf in will be at ? 5v). if you want a 20 to 100 mv offset per the note on page 3, the resistor value to ground will be 12.45k w to 2.45k w when v cc = 5. biasing and dc-blocking the backside of the divider chip is gold plated and attached to the heat slug in the package. also in the package is a capacitor con- nected between the chips topside v cc rail and the heat slug making the heat slug an rf ground. in the majority of cases, you would tie the exposed heat slug on the bottom of the package to ground. in a typical positive bias setup with v cc = 5, v ee is dc ground along with the packages heat slug. the rf input and rf output nodes are each tied to v cc through 50 w and will be floating nominally at that bias level (depending, of course, on the input drive level and the appropri- ate output state) so blocking capacitors will usually be re- quired. for a typical negative bias setup with v ee = -5, v cc is dc ground along with the packages heat slug. in some cases, such as level shifting to subsequent stages, you might want to float the package and apply bias as the difference between v cc and v ee . for such applications, the packages heat slug must be attached to a point that is both a good heat sink and a good rf ground. heat slug/bonding pad the exposed area of the packages backside heat slug (or pad) measures 2.67 x 1.65 mm (0.105" x 0.065"). anything larger than this on a pcb would be at the customers preference or convenience. on our test pcbs, we use a 0.200" x 0.082" pad with eight 0.020" diameter solder-filler thermal vias. www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies 5968-4885e (11/99)
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