View ISD14B20_3370904.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ISD14B20 publication release date: october 9, 2007 - 1 - revision 0 ISD14B20 single-chip, multiple-message voice record/playback device 10.6- to 32-seconds duration
ISD14B20 publication release date: october 9, 2007 - 2 - revision 0 table of contents 1. general description ............................................................................................................... 3 2. features ....................................................................................................................................... 3 3. block diagram ............................................................................................................................ 5 4. pad description ......................................................................................................................... 6 5. functional description ......................................................................................................... 8 5.1. address trigger ( norm ) operation ........................................................................................... 8 5.1.1. record ( rec ) operation ........................................................................................................ 8 5.1.2. edge-triggered playback ( playe ) operation ........................................................................ 10 5.1.3. level- triggered playback ( playl )operation ........................................................................ 10 5.1.4. playback (supersedes record) operation .......................................................................... 11 5.1.5. xclk feature ....................................................................................................................... 12 5.2. direct trigger ( mode ) operation ............................................................................................. 12 5.3. other operations ...................................................................................................................... 14 5.3.1. rosc operation .................................................................................................................... 14 5.3.2. led operation ...................................................................................................................... 15 5.3.3. feed-through mode operation ........................................................................................... 15 5.3.4. power-on playback operation ............................................................................................ 15 5.3.5. automatic single message playback ................................................................................... 15 5.3.6. power is interrupted abruptly ............................................................................................... 15 6. absolute maximum ratings [1] .............................................................................................. 16 6.1 operating conditions ................................................................................................................... 16 7. electrical characteristics ............................................................................................... 17 7.1. dc parameters ........................................................................................................................... 17 7.2. ac parameters ........................................................................................................................... 18 8. typical application circuit ................................................................................................ 19 9. packaging ............................................................................................................................... .... 21 9.1 die information .......................................................................................................................... 21 10. ordering information .......................................................................................................... 22 11. version history ....................................................................................................................... 23
ISD14B20 publication release date: october 9, 2007 - 3 - revision 0 1. general description winbond?s ISD14B20 chipcorder ? is a new single-chip multiple-message record/playback series with dual operating modes (address trigger and direct trigger) with wide operating voltage ranging from 2.4v to 5.5v. the sampling frequency can be selected from 4 to 12 khz via an external resistor, which also determines the duration from 10.6 to 32 seconds. the device is designed for mostly standalone applications, and of course, it can be manipulated by a microcontroller, if necessary. the two operating modes are address trigger and direct tr igger. while in address trigger mode, both record and playback operations are manipulated according to the start address and e nd address specified through the start address and end address pins. however, in direct tri gger mode, the device can configure the memory up to as many as eight equal messages, pe nding upon the fixed message configura tion settings. with the record or playback feature being pre-selected , each message can be randomly accesse d via its message control pin. the device has a selectable differential micr ophone input with agc feature or single-ended analog input, anain, under feed-through mode. its differential class d pwm speaker driver can directly drive a typical speaker or buzzer. 2. features the ISD14B20 is a multiple messages record/pla yback device with two operational modes: address trigger ( ) and direct trigger ( norm mode ). the analog inputs and the outputs are: ? supply voltage: 2.4v to 5.5v. ? external resistor, rosc, sele cts sampling frequency and duration. sampling frequency 12 khz 8 khz 6.4 khz 5.3 khz 4 khz rosc 53.3 k ? 80 k ? 100 k ? 120 k ? 160 k ? ? mic+/mic- : differential microphone inputs. ? agc : automatic gain control for microphone preamp circuit. ? ft : feed-through the anain signal to the speaker outputs while anain is converted from mic+. ? when both ft and recording are active, device will record anain signal into memory with anain signal output to speaker simultaneously. ? sp+/sp- : class-d pwm diffe rential speaker drivers. ? led : during recording, led is on. ? automatically power down after each operation cycle. ? playback takes precedence over the recording operation. y temperature option: 0 c to +50 c (die) y packaging: die only
ISD14B20 publication release date: october 9, 2007 - 4 - revision 0 2.1. address trigger operational mode ? while in mode, flexible message duration is defined by start address and end address. norm ? utilize four start addresses ( , , & ) and four end addresses ( , , & ) to specific the message duration. s0 s1 s2 s3 e0 e1 e2 e3 ? rec : level-hold or edge-trigger (toggle on-off) recording from start to end addresses. ? playe : edge-trigger playback from start to end addresses and stops at eom marker, if eom is prior to end address. toggle on-off. ? playl : level-hold playback from start to end addre sses. also, if constantly low, device will loop playback from start to end addresses. 2.2. direct trigger operational mode ? while mode is active, utilizing, fmc1 , & fmc3 , the device reconfigures some pins to adapt various (1 to 8) fixed equal message conf igurations for random access and pre-defines the fixed message duration accordingly. fmc2 ? the control pins are: m1 ~ m8 (message activation) and /pr (record or playback selection). ? the record or playback operation is pre-defined by the /pr pin. ? each message can be randomly accessed via its message control pin ( m1 ~ m8 ) and the desired operation is facilitated accordingly.
ISD14B20 publication release date: october 9, 2007 - 5 - revision 0 3. block diagram clock control non-volatile multi level storage array automatic gain control (agc) antialiasing filter smoothing filter amp pre- amp sp + sp - playl playe agc mic+_ anain amp s0 s1 s2 s3 e0 e1 e2 e3 rosc v cca v ssa v ssd v ccd v ssp2 v ccp v ssp1 power conditioning norm xclk device & address control rec led ft switch address trigger: direct trigger: fmc2 fmc3 m1 m2 m3 r/p m8 m6 m7 fmc1 mode m5 m4 led ft
ISD14B20 publication release date: october 9, 2007 - 6 - revision 0 4. pad description pad name i / o function v ssd i digital ground : ground path for digital circuits. i s0 [1] : in norm mode, start address bit 0. m1 : when mode is active, l ow active operation on 1 st message. internal pull-up & debounce existed. s0 / m1 i s1 [1] : in norm mode, start address bit 1. m2 : when mode is active, l ow active operation on 2 nd message. internal pull-up & debounce existed. s1 / m2 i s2 [1] : in norm mode, start address bit 2. m3 : when mode is active, l ow active operation on 3 rd message. internal pull-up & debounce existed. s2 / m3 i s3 [1] : in norm mode, start address bit 3. m4 : when mode is active, l ow active operation on 4 th message. internal pull-up & debounce existed. s3 / m4 i playl : in norm mode, low active input, level-hold playback start to end addresses, debounce & internal pull-up existed. holding playl low constantly will perform looping playback function from star t to end addresses with insignificant dead time between messages regardl ess of sampling frequencies. fmc1 : when mode is active, , t ogether with fmc2 & , setup various fixed-message configurations. fmc1 fmc3 playl / fmc1 e0 / m5 i e0 [1] : in norm mode, end address bit 0. m5 : when mode is active, l ow active operation on 5 th message. internal pull-up & debounce existed. v ssa i analog ground : ground path for analog circuits. i e1 [1] : in norm mode, end address bit 1. m6 : when mode is active, l ow active operation on 6 th message. internal pull-up & debounce existed. e1 / m6 i e2 [1] : in norm mode, end address bit 2. m7 : when mode is active, l ow active operation on 7 th message. internal pull-up & debounce existed. e2 / m7 e3 / m8 i e3 [1] : in norm mode, end address bit 3. m8 : when mode is active, l ow active operation on 8 th message. internal pull-up & debounce existed. v ssp2 i ground : ground for negative pwm speaker driver. sp- o sp- : negative signal of the differential cla ss-d pwm speaker outputs. this output, together with the sp+, is used to drive an 8 ? speaker directly. v ccp i speaker power supply : power supply for pwm speaker drivers. sp+ o sp+ : positive signal of the differential class-d pwm speaker outputs. this output, together with the sp-, is used to drive an 8 ? speaker directly. v ssp1 i ground : ground for positive pwm speaker driver. agc i automatic gain control (agc) : the agc adjusts the gain of the microphone preamplifier circuitry. mic+ / anain i ? mic+ : non-inverting input of t he differential microphone signal. ? anain : when ft is selected, the mic+ input is configured to a single-ended input with 1vp-p maximum input am plitude and feed-through to the speaker outputs.
ISD14B20 publication release date: october 9, 2007 - 7 - revision 0 pad name i / o function mic- i mic- : inverting input of the differential microphone signal. while ft is enabled, mic- pin is disabled and must be floated. rosc i oscillator resistor : connect an external resistor from this pin to v ssa to select the internal sampling frequency. v cca i analog power supply : power supply for analog circuits. led o led output : during recording, this output is low. also, led pulses low momentarily at the end of playback. i playe : in norm mode, low active input, edge-trigger playback from start to end addresses & toggle on-off. debounce & internal pull-up existed. fmc2 : when mode is active, , t ogether with & , setup various fixed-message configurations. fmc2 fmc1 fmc3 playe / fmc2 i rec / /pr rec : in norm mode, level-hold (after 1 sec holdi ng) or edge-trigger (toggle on-off), low active, recording from start to end addresses. debounce & internal pull-up existed. /pr ( when mode is active ): ? when /pr is set to low, level-hold record operation is selected. ? when /pr is set to high, edge-trigger & toggle on-off playback operation is selected. i external clock : in norm mode, low active and level-hold input. as xclk activated, rosc pin accepts external clo ck input signal, provided resistor at rosc must be removed. connecting this pin to high enables device running on internal clock via rosc resistor. if not used, xclk must be at high level. when mode is active, fmc3 , t ogether with & fmc2 , setup various fixed- message configurations. fmc1 xclk / fmc3 ft i feed-through : low active input, level-hold, debounce & internal pull-up required. when ft is selected, the mic+ input is configured to a single-ended input with 1vp-p maximum input amplitude and feed- through to the speaker outputs. i level-hold input. norm / mode ? norm : when set to high, the device operates under address trigger condition. ? mode : when set to low, the device operates under direct trigger condition. the device reconfigures its pin definitions to fit various fixed-message configurations utilizing , fmc2 & pins as below table. fmc1 fmc3 fmc3 fmc2 fmc1 # of fixed messages 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 v ccd i digital power supply : power supply for digital circuits. notes: [1] : address bits , , , , , , & e3 are used to access the memory location. s0 s1 s2 s3 e0 e1 e2
ISD14B20 publication release date: october 9, 2007 - 8 - revision 0 5. functional description there are two operational modes: address trigger ( ) and direct trigger ( norm mode ). after a new condition is selected on / norm mode , the power must be cycled to enable it. 5.1. a ddress t rigger ( ) o peration norm the start address bits ( , , & ) and end address bits ( , , & ) are used to access the memory location and they can divide the memory into a maximum of 16 slots. as an example of i14b20, they are defined as follows: s0 s1 s2 s3 e0 e1 e2 e3 s3 ( ) e3 s2 ( ) e2 s1 ( e1 ) s0 ( e0 ) row # 14b20 duration [s] 0 0 0 0 0 0 0 0 0 1 8 1.25 0 0 1 0 16 2.50 0 0 1 1 24 3.75 0 1 0 0 32 5.00 0 1 0 1 40 6.25 0 1 1 0 48 7.50 0 1 1 1 56 8.75 1 0 0 0 64 10.00 1 0 0 1 72 11.25 1 0 1 0 80 12.50 1 0 1 1 88 13.75 1 1 0 0 96 15.00 1 1 0 1 104 16.25 1 1 1 0 112 17.50 1 1 1 1 120 18.75 5.1.1. record ( rec ) operation ? low active input, level-hold for level-trigger or falling edge for edge-trigger with debounce required. ? for 8khz sampling frequency, if rec is held at low for a period equal to 1 sec or more, then level recording is activated. however, if rec is pulsed low for less than 1 sec, then edge-trigger recording is initiated. ? for 6.4khz sampling frequency, if rec is held at low for a period equal to 1.25 sec or more, then level recording is activated. however, if rec is pulsed low for less t han 1.25 sec, then edge-trigger recording is initiated. ? recording begins from the start address to end address and led is on. ? recording ceases whenever rec returns to high in level-hold mode or a subsequent lower going pulse appears while in edge-trigger mode or when end address is reached. then an eom marker is written at the end of message. and led is off. ? then the device will autom atically power down. ? this pin has an internal pull-up device. ? once rec is active, input on ft , / norm mode , , , , , , , or is illegal. s0 s1 s2 s3 e0 e1 e2 e3
ISD14B20 publication release date: october 9, 2007 - 9 - revision 0 fig. 1: record?level ( rec ) function till end address rec mic+/- or anain end address led norm/mode t deb t aset t stop1 t ahold fig. 2: record?level ( rec ) function with start and stop actions rec mic+/- or anain end address led norm/mode t deb t aset t stop1 stop start start t settle1 t ahold t ahold t aset t deb t deb fig. 3: record?edge ( rec ) function with on-off rec mic+/- or anain end address led norm/mode t deb t aset t stop1 stop start start t settle1 t ahold t deb t ahold t aset t deb
ISD14B20 publication release date: october 9, 2007 - 10 - revision 0 5.1.2. edge-triggered playback ( playe ) operation ? low active input, edge-trigger, toggle on-off, debounce required. ? playback begins from the start address to end addr ess or eom, whichever is occurred first. ? at the end of message, led pulses low momentarily. ? then device will automat ically power down. ? during playback, a subsequent trigger terminates the playback operation. if eom marker is not encountered, then led will not pulses low momentarily. ? this pin has an internal pull-up device. ? once playe is active, input on playl , rec , ft , / norm mode , , , , , , , or is banned. s0 s1 s2 s3 e0 e1 e2 e3 fig. 4 : playback?edge ( playe ) function playe sp+ sp- end of message led norm/mode t deb t aset stop start start t settle2 t ahold t deb t eom t ahold t aset t deb 5.1.3. level- triggered playback ( playl )operation ? low active input, level-hold, debounce required. ? once active, playback begins from the start address and stops whenever playl returns to high. when an eom is encountered, led pulses low momentarily. ? then device will automat ically power down. ? this pin has an internal pull-up device. ? once playl is active, input on playe , rec , ft , / norm mode , , , , , , , or is prohibited. s0 s1 s2 s3 e0 e1 e2 e3 fig. 5: playback?level ( playl ) function
ISD14B20 publication release date: october 9, 2007 - 11 - revision 0 part of message playl sp+ sp- end of message led norm/mode t deb t aset stop start start t settle2 t ahold t ahold t aset t eom t deb t deb ? however, holding playl low constantly will perform looping pl ayback function, wi thout power down, from start address to end address. fig. 6: looping playback function via playl playl norm/mode t deb t aset t ahold sp+ sp- led t eom t eom 5.1.4. playback (supersedes record) operation ? playback takes precedence over the recording operation. ? if either playe or playl is activated during a recording cycle, the recording immediately ceases with an eom marker attached, and wit hout power down, playback of t he just-recorded message performs accordingly. then device powers down. fig. 7: an example of playback supersedes record
ISD14B20 publication release date: october 9, 2007 - 12 - revision 0 led mic+/- or anain playe sp+ sp- rec norm/mode t deb t ahold t aset t settle1 t deb t eom t settle3 5.1.5. xclk feature ? when precision sampling frequency is required, ex ternal clock mode can be activated by setting xclk to low. under such condition, the resistor at ro sc pin must be removed and the external clock signal must be applied to the rosc pin. these conditions must be satisfied prior to any operations. ? however, when internal clock is used, xclk must be linked to high. ? the external clock frequencies required for various sampling frequencies are listed in below table. sampling freq [khz] 12 8 6.4 5.3 4 xclk [mhz] 3.072 2.048 1. 638 1.356 1.024 5.2. d irect t rigger ( mode ) o peration ? the direct trigger is selected by the mode pin. once chosen, the suppl y voltage must be reset to allow the device to construct itself to the appropriate configuration by re-defining the function on the related control pins. also, the mode change is only a llowed while the device is in power down state and inhibited during an operat ion is in progress. ? once direct trigger is activated, , & are utilized to select various (1 to 8) fixed message configurations fmc1 fmc2 fmc3 [1] . pending upon the arrangement on , & fmc3 , each divided message has approximate equal length of duration, which is related to the number of rows assigned as in below table. fmc1 fmc2 ? the record or playback oper ation is pre-defined by the /pr pin. setting this pin to low allows record operation while setting it to high enables playback operation. ? each message can be randomly acce ssed via its message control pin ( m1 ~ m8 ) and the desired operations are facilitated accordi ngly. non-configured pins are aut omatically disabled and must be floated. notes: [1] : number of fixed message arrangement with respect to , & fmc3 . fmc1 fmc2 fmc3 fmc2 fmc1 # of fixed messages [1] 0 0 0 1 0 0 1 2 0 1 0 3
ISD14B20 publication release date: october 9, 2007 - 13 - revision 0 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 [2 ] : number of memory row arrangement with respect to different number of fixed messages for ISD14B20 (128 rows). the non-configured message control pins (mx) will be disabled. # of msg m1 m2 m3 m4 m5 m6 m7 m8 1 128 2 64 64 3 44 42 42 4 32 32 32 32 5 26 26 26 26 24 6 23 21 21 21 21 21 7 20 18 18 18 18 18 18 8 16 16 16 16 16 16 16 16 [3 ] : the durations for various fixed message configur ations on i14b20 device at 8 khz sampling frequency are shown in below table. # of msg m1 m2 m3 m4 m5 m6 m7 m8 1 20 2 10 10 3 6.875 6.563 6.563 4 5.0 5.0 5.0 5.0 5 4.063 4.063 4.063 4.063 3.750 6 3.594 3.281 3.281 3.281 3.281 3.281 7 3.125 2.813 2.813 2. 813 2.813 2.813 2.813 8 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5
ISD14B20 publication release date: october 9, 2007 - 14 - revision 0 example of four fixed-message configuration: fig. 8: record operation under fmc mode mic+/- or anain led fm3 norm/mode fm2 fm1 m1 ~ m4 start start stop end of duration r / p t fset t deb t settle1 t deb t deb t stop1 fig. 9: playback operation under fmc mode sp+ sp- led fm3 norm/mode fm2 fm1 m1 ~ m4 stop start end of message r / p start t fset t deb t deb t deb t eom t settle2 5.3. o ther o perations 5.3.1. rosc operation ? when the r osc varies from 53.3 k ? to 160 k ? , the sampling frequency changes from 12 to 4 khz accordingly.
ISD14B20 publication release date: october 9, 2007 - 15 - revision 0 ? when r osc resistor value is changed during playback, t he tone of a recorded message will alter either faster or slower. ? if the ground side of r osc resistor is floated or tied to v cc , then the current operat ion will be freezed. ? the operation will resume when the re sistor is connected back to ground. 5.3.2. led operation ? led turns on during recording. also, led pulses low at the end of me ssage. the low period must be sufficiently greater than debounce time. 5.3.3. feed-through mode operation ? as ft is held low, the mic+ pin will be reconfigured as anain input then the anain signal will be transmitted to the speaker output s. under this mode, mic- pi n is not used (must be floated). ? after ft is enabled, if rec is triggered, then anain signal will be recorded into memory while the feed-through path remains on. ? if ft is already enabled, activating either playe or playl will first disable the ft path then play the recorded message. once playback comp letes, ft path will be resumed. ? during an operation, activating the ft pin is not allowed. 5.3.4. power-on playback operation ? if playe is kept at low during power turns on, t he device plays message onc e, then powers down. ? if playl is held at low during power turns on and constantly maintained at low, the device will play the message repeatedly, with insignificant dead ti me between messages regardless of sampling frequencies. this status will sustai n unless power is turned off or playl somehow returns to high. 5.3.5. automatic single message playback ? if led is connected to playe , once playe is triggered, then the dev ice plays message repeatedly without power down between the l ooping playback. however, if playe is triggered again during playback, then playback will stop. 5.3.6. power is interrupted abruptly ? during the device is in operat ion, it is strongly recommended that the supply power cannot be interrupted. otherwise, it may cause the device to become malfunctioning.
ISD14B20 publication release date: october 9, 2007 - 16 - revision 0 6. absolute maximum ratings [1] absolute maximum ratings condition value junction temperature 150c storage temperature range -65c to +150c voltage applied to any pins (v ss ? 0.3v) to (v cc + 0.3v) voltage applied to input pins (current limited to +/-20 ma) (v ss ? 1.0v) to (v cc + 1.0v) voltage applied to output pins (current limited to +/-20 ma) (v ss ? 1.0v) to (v cc + 1.0v) v cc ? v ss -0.3v to +7.0v [1] stresses above those listed may cause perm anent damage to the devic e. exposure to the absolute maximum ratings may affect device re liability and performance. functional operation is not implied at these conditions. 6.1 o perating c onditions operating conditions condition value operating temperature range 0c to +50c operating voltage (v cc ) [1] +2.4v to +5.5v ground voltage (v ss ) [2] 0v [1] v cc = v cca = v ccd [2] v ss = v ssa = v ssd
ISD14B20 publication release date: october 9, 2007 - 17 - revision 0 7. electrical characteristics 7.1. dc p arameters parameter symbol min [2] typ [1] max [2] units conditions input low voltage v il 0.3xvcc v input high voltage v ih 0.7xvcc v output low voltage v ol 0.3xvcc v i ol = 4.0 ma [3] output high voltage v oh 0.7xvcc v i oh = -1.6 ma [3] standby current i stby 1 10 a [4] [5] record current i rec 20 30 ma v cc = 5.5v [4] [5] playback current i play 20 30 ma v cc = 5.5v, no load [4] [5] pull-up device for rec , playe , playl , ft & m1 ~ m8 pins r pu1 600 k mic+ input resistance r micp 18 k ? mic- input resistance r micn 18 k ? anain input resistance r anain 42 k ? mic differential input v in1 15 300 mv peak-to-peak anain input v in2 1 v peak-to-peak gain from mic to sp+/- a msp 6~40 db v in = 15~300 mvp-p, agc = 4.7 f, v cc = 2.4v~5.5v output load impedance r spk 8 ? speaker load speaker output power pout 313 mw v dd = 4.4 v 1vp-p, 1 khz sine wave at anain. r spk = 8 ? speaker output voltage v out1 v dd v r spk = 8 ? speaker, typical buzzer notes: [1] typical values @ v cc = 5.5v, t a = 25 and sampling frequency (fs) at 8 khz, unless stated. [2] not all specifications are 100 percent tested. all min/max limit s are guaranteed by winbond via design, electrical testing and/or characterization. [3] led output during recording. [4] v cca , v ccd and v ccp are connected together. also, v ssa , v ssd , v ssp1 and v ssp2 are linked together. [5] all required control pins must be at appropriate status. external components are biased under a separated power supply.
ISD14B20 publication release date: october 9, 2007 - 18 - revision 0 7.2. ac p arameters characteristic [1] symbol min [2] typ max [2] unit s conditions sampling frequency fs 4 12 khz [3] record duration t rec 10.6 32 sec [3] playback duration t play 10.6 32 sec [3] debounce time t deb 225k/f s msec [3] [4] address setup time t aset 30 nsec address hold time t ahold 225k/f s msec [3] [4] fmc setup time t fset 30 nsec record settle time t settle1 32k/fs msec [3] [4] play settle time t settle2 256k/f s msec [3] [4] delay from record to play t settle3 128k/f s msec [3] [4] record stop time t stop1 30 nsec led pulse low time t eom 256k/f s msec [3] [4] notes: [1] conditions are v cc = 5.5v, t a = 25 c and sampling frequency (f s ) at 8khz, unless specified. [2] not all specifications are 100 percent tested. all min/max limit s are guaranteed by winbond via design, electrical testing and/or characterization. [3] when different f s is applied, the value will change accordingly. also, stability of internal oscillator may vary as much as + 10% over the operating tem perature and voltage ranges. [4] k = 1000. 8.
ISD14B20 publication release date: october 9, 2007 - 19 - revision 0 8. typical application circuit the following typical application examples on isd14b 20 series are for references only. they make no representation or warranty that such applicati ons shall be suitable for the use specified. it?s customer?s obligation to verify the design in its own system for the functi onalities, voice quality, current consumption, and etc. in addition, the below notes apply to the following application examples: * the suggested values are for references onl y. depending on system r equirements, they can be adjusted for functionalities, voice quality and degree of performance. it is important to have a separate path for each ground and power back to the related terminals to minimize the noise. besides, the power supplie s should be decoupled as close to the device as possible. also, it is crucial to follow good audio design practices in layout and power supply decoupling. see recommendations in application notes from our websites. example #1: operations via start and end addresses under address trigger mode ( ) norm rosc* speaker v cc 4.7 f* ? 4.7 k 0.1 f* 0.1 f* 4.7 k ? 4.7 k ? 4.7 f* 1 k d1 0.1 f 10 f* v ccd 0.1 f 10 f* v cca 10 f* v ccp 0.1 f 10 f* 0.1 f v cca v ccd v ccp vcc gnd isd1916 v ssd mic+_anain mic- sp- v ccd agc rosc v cca sp+ v ssa playe playl s2 s1 s0 e2 e1 e0 v ccp v ssp1 v ssp2 norm ft xclk led rec e3 s3 to switches or address i/os
ISD14B20 publication release date: october 9, 2007 - 20 - revision 0 example #2: fixed message configuration operations under direct trigger mode ( mode ) rosc* speaker v cc 4.7 f* ? 4.7 k 0.1 f* 0.1 f* 4.7 k ? 4.7 k ? 4.7 f* 1 k d1 0.1 f 10 f v cca 10 f* v ccp 0.1 f 10 f* 0.1 f v cca v ccd v ccp vcc gnd ISD14B20 fmc1 fmc3 fmc2 m3 m4 m5 m6 m7 m8 m2 r/p m1 mic+_anain mic- sp- agc rosc sp+ v ssp1 v ssp2 ft v ssd v ccd v cca v ssa v ccp mode 0.1 f 10 f* v ccd led v cc good audio design practices winbond?s chipcorder are very high-quality single- chip voice recording and playback devices. to ensure the highest quality voice reproduction, it is important that good audio design practices on layout and power supply decoupling are followed. see application information links below for details. good audio design practices http://www.wi nbond-usa.com/products/isd_products/chi pcorder/applicat ioninfo/apin11.pdf single-chip board layout diagrams http://www.wi nbond-usa.com/products/isd_products/chi pcorder/applicat ioninfo/apin12.pdf it is strongly recommended that before any design or la yout project starts, t he designer should contact winbond sales rep for the most update tec hnical information and layout advice.
ISD14B20 publication release date: october 9, 2007 - 21 - revision 0 9. packaging 9.1 d ie i nformation ISD14B20 v ccd v ssd s1 / m2 s2 / m3 norm / mode ft xclk / fmc3 rec / r/p s0 / m1 rosc mic- agc playe / fmc2 led playl / fmc1 sp+ sp- v ccp v ssp2 mic+_anain v cca v ssp1 v cca s3 / m4 e0 / m5 e1 / m6 e2 / m7 v ssa e3 / m8 contact winbond sales representativ es for other information.
ISD14B20 publication release date: october 9, 2007 - 22 - revision 0 10. ordering information product number descriptor key product name: i = isd product series: 14b = 14b00 duration: 20 : 10.6 ? 32 secs i14bxxx x temperature : blank = commercial ? die (0 c to +50 c) package type : x = die when ordering ISD14B20 devices, please refer to the above ordering scheme. contact the local winbond sales representatives for any questions and the availability. for the latest product information, please contact the winbond sales/rep or access winbond?s worldwide web site at http://www.winbond-usa.com
ISD14B20 publication release date: october 9, 2007 - 23 - revision 0 11. version history version date description 0 oct 9, 2007 initial revision
ISD14B20 publication release date: october 9, 2007 - 24 - revision 0 winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or fo r other applications intended to support or sustain life. furthermore, winbond products are not intended fo r applications wherein failure of winbond products could result or lead to a situation wherein personal injury, deat h or severe property or environmental damage could occur. winbond customers using or selling these products for use in su ch applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. the contents of this document are provided only as a guide for the applications of winbond products. winbond makes no representation or warranties with respect to the accuracy or completeness of the c ontents of this publication and reserves the right to discontinue or make changes to specif ications and product descriptions at any time without notice. no license, whether express or implied, to any intellectual property or other right of winbond or others is granted by this publication. except as set forth in winbond's standard terms and conditions of sale, winbond assumes no liability whatsoever and disclaims any express or implied warrant y of merchantability, fitness for a particular purpose or infringement of any intellectual property. the contents of this document are pr ovided ?as is?, and winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchant ability, fitness for a particular purpose or infringement of any intellectual property. in no event, shall winbond be liable for any damages w hatsoever (including, wit hout limitation, damages for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this documents, even if winbond has been advised of the possibility of such damages. application examples and alternative uses of any integrated circuit contained in this publication are for illustration only and winbond makes no representation or warranty that such applications shall be suitable for the use specified. the 100-year retention and 100k record cycle projections are based upon accelerated reliability tests, as published in the winbond reliability report, and are nei ther warranted nor guaranteed by wi nbond. this product incorporates superflash ? . information contained in this isd ? chipcorder ? datasheet supersedes all data fo r the isd chipcorder products published by isd ? prior to august, 1998. this datasheet and any future addendum to this datasheet is(are) the complete and controlling isd ? chipcorder ? product specifications. in the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentat ion contains information in addition to the information in this, the information contained herein supersedes and governs su ch other information in its entirety. this datasheet is subject to change without notice. copyright ? 2005, winbond electronics corporation. all rights reserved. chipcorder ? and isd ? are trademarks of winbond electronics corporation. superflash ? is the trademark of silicon storage technology, inc. all other trademarks are p ro p erties of their res p ective owners. please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

▲Up To Search▲

Price & Availability of ISD14B20

	To Download ISD14B20 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .