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december 2006 hyb18t512161bf 512-mbit x16 ddr2 sdram ddr2 sdram rohs compliant internet data sheet rev. 1.43
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram qag_techdoc_rev400 / 3.2 qag / 2006-08-01 2 03292006-l40n-l04g hyb18t512161bf revision history: 2006-11, rev. 1.43 page subjects (major chan ges since last revision) all adapted internet edtion 94-101 added chapter 7 explaining ac timing measurement condition (reference load ; slew rate ; set up & hold timing references ; derating values for input /command ,data ) 82-86 setup & hold timings are changed with refe rence to industrial standard definition all removed all the occurances of rdqs as it in not used in graphics (x16) previous revision: 2006-09, rev. 1.32 all qimonda update previous revision: 2006-03, rev. 1.31 9 added power supply info for [-20 and -22] 86 table 41: change i dd max to i dd typ 77 - 80 corrected ac timing values for -20 speedsort in table 35 and table 36 previous revision: 2006-02, rev. 1.21 67 table 18: added speed sort -20 71 table 24: added speed sort -20 76 table 33 and table 34: added speed sort -20 77 table 35: change cl=7 2.0 tck (speed sort -20) 78 table 36: added all values for speed sort -20 86 table 41: added all idd values (all speed sorts)
internet data sheet rev. 1.43, 2006-11 3 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 1overview this chapter gives an overview of the 512-mbit double-da ta-rate-two sdram product fam ily for graphics application and describes its main characteristics. 1.1 features the 512-mbit double-data-rate-two sdra m offers the following key features: ? 1.8 v 0.1v v dd for [?25/?28/?33] ? 2.0 v 0.1v v dd for [?20/?22] ? 1.8 v 0.1v v ddq for [?25/?28/?33] ? 2.0 v 0.1v v ddq for [?20/?22] ? dram organizations with 16 data in/outputs ? double data rate architecture: ? two data transfers per clock cycle ? four internal banks for concurrent operation ? programmable cas latency: 3, 4, 5, 6, 7 ? programmable burst length: 4 and 8 ? differential clock inputs (ck and ck ) ? bi-directional, differentia l data strobes (dqs and dqs ) are transmitted / received with da ta. edge aligned with read data and center-aligned with write data. ? dll aligns dq and dqs transitions with clock ?dqs can be disabled for single-ended data strobe operation ? commands entered on each positive clock edge, data and data mask are referenced to both edges of dqs ? data masks (dm) for write data ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance adjustment (ocd) and on- die-termination (odt) for better signal quality. ? auto-precharge operation for read and write bursts ? auto-refresh, self-refresh and power saving power- down modes ? average refresh period 7.8 s at a t case lower than 85 c, 3.9 s between 85 c and 95 c ? full strength and reduced strength (60%) data-output drivers ? 2kb page size ? packages: p-tfbga-84 for 16 components ? rohs compliant products 1) table 1 ordering information for rohs compliant products 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product number org. clock (mhz) package hyb18t512161bf?20/22/25/28/33 16 500/450/400/350/300 p-tfbga-84
internet data sheet rev. 1.43, 2006-11 4 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 1.2 description the 512-mb ddr2 dram is a high-speed double-data- rate-two cmos dram device containing 536,870,912 bits and internally configured as a quad-bank dram. the 512-mb device is organized as 8 mbit 16 i/o 4 banks chip. these devices achieve high speed transfer rates starting at 400 mb/sec/pin for general applications. the device is designed to comply with all ddr2 dram key features: 1. posted cas with additive latency, 2. write latency = read latency - 1, 3. normal and weak strengt h data-output driver, 4. off-chip driver (ocd) impedance adjustment 5. on-die termination (odt) function. all of the control and address inputs are synchronized with a pair of externally supplied diff erential clocks. inputs are latched at the cross point of di fferential clocks (ck rising and ck falling). all i/os are synchronized with a single ended dqs or differential dqs-dqs pair in a source synchronous fashion. a 15-bit address bus for 16 components is used to convey row, column and bank address information in a ras -cas multiplexing style. an auto-refresh and self-refresh mode is provided along with various power-saving power-down modes. the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. the ddr2 sdram is available in p-tfbga package.
internet data sheet rev. 1.43, 2006-11 5 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 2 pin configuration 2.1 pin configuration the pin configuration of a ddr2 s dram is listed by function in table 2 . the abbreviations used in the pin#/buffer type columns are explained in table 3 and table 4 respectively. the pin numbering for the fbga package is depicted in figure 1 for 16 . table 2 pin configuration of ddr sdram ball#/pin# name pin type buffer type function clock signals 16 organization j8 ck i sstl clock signal ck, complementary clock signal ck k8 ck i sstl k2 cke i sstl clock enable control signals 16 organization k7 ras i sstl row address strobe (ras), column address strobe (cas), write enable (we) l7 cas i sstl k3 we i sstl l8 cs i sstl chip select address signals 16 organization l2 ba0 i sstl bank address bus 1:0 l3 ba1 i sstl l1 nc ? ?
internet data sheet rev. 1.43, 2006-11 6 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram m8 a0 i sstl address signal 12:0,address signal 10/autoprecharge m3 a1 i sstl m7 a2 i sstl n2 a3 i sstl n8 a4 i sstl n3 a5 i sstl n7 a6 i sstl p2 a7 i sstl p8 a8 i sstl p3 a9 i sstl m2 a10 i sstl ap i sstl p7 a11 i sstl r2 a12 i sstl data signals 16 organization g8 dq0 i/o sstl data signal 15:0 note: bi-directional data bus. dq[15:0] for 16 components g2 dq1 i/o sstl h7 dq2 i/o sstl h3 dq3 i/o sstl h1 dq4 i/o sstl h9 dq5 i/o sstl f1 dq6 i/o sstl f9 dq7 i/o sstl c8 dq8 i/o sstl c2 dq9 i/o sstl d7 dq10 i/o sstl d3 dq11 i/o sstl d1 dq12 i/o sstl d9 dq13 i/o sstl b1 dq14 i/o sstl b9 dq15 i/o sstl data strobe 16 organization b7 udqs i/o sstl data strobe upper byte a8 udqs i/o sstl f7 ldqs i/o sstl data strobe lower byte e8 ldqs i/o sstl ball#/pin# name pin type buffer type function
internet data sheet rev. 1.43, 2006-11 7 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 3 abbreviations for pin type data mask 16 organization b3 udm i sstl data mask upper byte f3 ldm i sstl data mask lower byte power supplies 16 organizations a9,c1,c3,c7,c 9 v ddq pwr ? i/o driver power supply a1 v dd pwr ? power supply a7,b2,b8,d2,d 8 v ssq pwr ? power supply a3,e3 v ss pwr ? power supply power supplies 16 organization j2 v ref ai ? i/o reference voltage e9, g1, g3, g7, g9 v ddq pwr ? i/o driver power supply j1 v ddl pwr ? power supply e1, j9, m9, r1 v dd pwr ? power supply e7, f2, f8, h2, h8 v ssq pwr ? power supply j7 v ssdl pwr ? power supply j3,n1,p9 v ss pwr ? power supply not connected 16 organization a2, e2, l1, r3, r7, r8 nc nc ? not connected other pins 16 organization k9 odt i sstl on-die termination control abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nc not connected ball#/pin# name pin type buffer type function
internet data sheet rev. 1.43, 2006-11 8 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 4 abbreviations for buffer type figure 1 pin configuration for 16 components, p-tfbga-84 (top view) note: 1. udqs/udqs is data strobe for dq[15:8], ldqs/ldqs is data strobe for dq[7:0] 2. ldm is the data mask signal for dq[7:0], udm is the data mask signal for dq[15:8] 3. v ddl and v ddsl are power and ground for the dll. they are isolated on the device from v dd , v ddq , v ss and v ssq. abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tristate, and allows multiple devices to share as a wire-or. 0 3 3 7 6 ' ' 1 & $ 6 6 6 4 .# 6 6 6 & . ( & . 6 6 6 8 ' 0 ' 4 6 ' ' 4 ' 4 ' 4 6 6 6 6 ' ' / $ 6 6 6 4 ' 4 /' 4 6 5 $6 6 ' ' $ % & ' ) * + - ( / 0 . 1 ' 4 6 ' ' % $ % $ $ $3 $ 6 6 6 6 ' ' 4 ' 4 ' 4 9 6 6 ' / $ $ $ '4 1 & 6 ' ' 1 & 3 5 $ $ $ $ 1 & 6 6 6 ' 4 6 ' ' 4 6 6 6 4 ' 4 / ' 0 6 ' ' 4 6 ' ' 4 '4 6 6 6 4 '4 6 5 ( ) : ( 1 & $ $ 8' 4 6 8 ' 4 6 ' 4 6 ' ' 4 6 ' ' 4 ' 4 6 6 6 4 ' 4 6 6 6 4 6 ' ' 4 / ' 4 6 6 6 6 4 6 ' ' 4 ' 4 6 ' ' 4 6 6 6 4 & . 6 ' ' 2 ' 7 & $6 & 6 6 6 6 4 6 6 6 4
internet data sheet rev. 1.43, 2006-11 9 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 2.2 512 mbit ddr2 addressing table 5 512-mbit ddr2 addressing configuration 32-mbit x 16 note bank address ba[1:0] number of banks 4 auto-precharge a10 / ap row address a[12:0] column address a[9:0] number of column address bits 10 1) 1) referred to as ?colbits? number of i/os 16 2) 2) referred to as ?org? page size [bytes] 2048 (2k) 3) 3) pagesize = 2 colbits org/8 [bytes
internet data sheet rev. 1.43, 2006-11 10 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 3 functional description table 6 mode register defini tion (ba[1:0] = 00b) field bits type 1) description ba1 14 reg. addr. bank address [1] 0 b ba1 bank address ba0 13 bank address [0] 0 b ba0 bank address pd 12 w active power-down mode select 0 b pd fast exit 1 b pd slow exit wr [11:9] w write recovery 2) note: all other bit combinations are illegal. 001 b wr 2 010 b wr 3 011 b wr 4 100 b wr 5 101 b wr 6 dll 8 w dll reset 0 b dll no 1 b dll yes tm 7 w test mode 0 b tm normal mode 1 b tm vendor specific test mode cl [6:4] w cas latency note: all other bit combinations are illegal. 010 b cl reserved 011 b cl 3 100 b cl 4 101 b cl 5 110 b cl 6 111 b cl 7 % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ 3 ' : 5 % / u h j d g g u z zz z z z ' / / 7 0 & / % 7 z
internet data sheet rev. 1.43, 2006-11 11 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram bt 3 w burst type 0 b bt sequential 1 b bt interleaved bl [2:0] w burst length note: all other bit combinations are illegal. 010 b bl 4 011 b bl 8 1) w = write only register bits 2) number of clock cycles for write recovery during auto- precharge. wr in clock cycles is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up to the next integer: wr [cycles] t wr (ns) / t ck (ns). the mode register must be programmed to fulfill the minimum requirement for the analogue t wr timing wr min is determined by t ck.max and wr max is determined by t ck.min . field bits type 1) description
internet data sheet rev. 1.43, 2006-11 12 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 7 extended mode register definition (ba[1:0] = 01b) field bits type 1) 1) w = write only register bits description ba1 14 reg. addr. bank address [1] 0 b ba1 bank address ba0 13 bank address [0] 0 b ba0 bank address qoff 12 w output disable 0 b qoff output buffers enabled 1 b qoff output buffers disabled dqs 10 complement data st robe (dqs output) 0 b dqs enable 1 b dqs disable ocd program [9:7] off-chip driver calibration program 000 b ocd ocd calibration mode exit, maintain setting 001 b ocd drive (1) 010 b ocd drive (0) 100 b ocd adjust mode 111 b ocd ocd calibration default al [5:3] additive latency note: all other bit combinations are illegal. 000 b al 0 001 b al 1 010 b al 2 011 b al 3 100 b al 4 101 b al 5 110 b al 6 r tt 2,6 nominal termination resistance of odt 00 b rtt (odt disabled) 01 b rtt 75 ohm 10 b rtt 150 ohm 11 b rtt 50 ohm dic 1 off-chip driver impedance control 0 b dic full (driver size = 100%) 1 b dic reduced dll 0 dll enable 0 b dll enable 1 b dll disable % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ 4 r i i ' 4 6 2 & ' 3 u r j u d p 5 w w $ / 5 w w ' , & ' / / u h j d g g u z z z z z z z
internet data sheet rev. 1.43, 2006-11 13 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 8 emrs(2) programming extended mode register definition (ba[1:0]=10 b ) field bits type 1) 1) w = write only description ba [14:13] w bank adress[14:13] 00 b ba mrs 01 b ba emrs(1) 10 b ba emrs(2) 11 b ba emrs(3): reserved a[12:8]w address bus[12:8] 0 b a[12:8] address bits a7 w address bus[7] note: adapted self refresh rate for tcase > 85 c 0 b a7 disable 1 b a7 enable 2)3) 2) when dram is operated at 85c t case 95c the extended self refresh rate must be enabled by setting bit a7 to "1" before the self refresh mode can be entered. 3) if pasr (partial array self refresh) is enabled, data located in areas of the array beyond the specified location will be los t if self refresh is entered. data integrity will be maintained if tref conditions are met and no self refresh command is issued a [6:3] w address bus[6:3] 0 b a[6:3] address bits partial self refresh for 4 banks a [2:0] w address bus[2:0], partial array self refresh for 4 banks 000 b pasr0 full array 001 b pasr1 half array (ba[1:0]=00, 01) 010 b pasr2 quarter array (ba[1:0]=00) 011 b pasr3 not defined 100 b pasr4 3/4 array (ba[1:0]=01, 10, 11) 101 b pasr5 half array (ba[1:0]=10, 11) 110 b pasr6 quarter array (ba[1:0]=11) 111 b pasr7 not defined %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ uhjdggu 65) 3$65
internet data sheet rev. 1.43, 2006-11 14 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 9 emr(3) programming extended mode register definition (ba[1:0]=10 b ) table 10 odt truth table note: x = don?t care; 0 = bit set to low; 1 = bit set to high field bits type 1) 1) w = write only description ba1 14 bank adress[1] 1 b ba1 bank address ba0 13 bank adress[0] 1 b ba0 bank address a [12:0] w address bus[12:0] 0 b a[12:0] address bits input pin emrs(1) address bit a10 emrs(1) address bit a11 x16 components dq[7:0] x dq[15:8] x ldqs x ldqs 0x udqs x udqs 0x ldm x udm x 0 3 % 7 % $ % $ $ $ $ $ $ $ $ $ $ $ $ $ $ u h j d g g u
internet data sheet rev. 1.43, 2006-11 15 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 11 burst length and sequence notes 1. pagesize and length is a function of i/o organization:32mb x 16 organiz ation (ca[9:0]); page size = 2 kbyte; page length = 1024 2. order of burst access for sequential addressing is ?nibble- based? and therefore diff erent from sdr or ddr components burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
internet data sheet rev. 1.43, 2006-11 16 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 4 truth tables table 12 command truth table function cke cs ras cas we ba0 ba1 a[13:11] a10 a[9:0] note 1)2)3) 1) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 2) ?x? means ?h or l (but a defined logic level)?. 3) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initializa tion sequence before normal operation can continue. previous cycle current cycle (extended) mode register set hhllllbaop code 4)5) 4) all ddr2 sdram commands are defined by states of cs , we , ras , cas , and cke at the rising edge of the clock. 5) bank addresses ba[1:0] determine which bank is to be operated upon. for (e)mrs ba[1:0] selects an (extended) mode register. auto-refresh h h l l l h x x x x 4) self-refresh entry h l l l l h x x x x 4)6) 6) v ref must be maintained during self refresh operation. self-refresh exit l h h x x x x x x x 4)6)7) 7) self refresh exit is asynchronous. lh h h single bank precharge h h l l h l ba x l x 4)5) precharge all banks h h l l h l x x h x 4) bank activate h h l l h h ba row address 4)5) write h h l h l l ba column l column 4)5)8) 8) burst reads or writes at bl = 4 cannot be terminated. write with auto- precharge h h l h l l ba column h column 4)5)8) read h h l h l h ba column l column 4)5)8) read with auto- precharge h h l h l h ba column h column 4)5)8) no operation h x l h h h x x x x 4) device deselect h x h x x x x x x x 4) power down entry h l h x x x x x x x 4)9) 9) the power down mode does not perform any refresh operations. the duration of power down is therefore limited by the refresh requirements. lh h h power down exit l h h x x x x x x x 4)9) lh h h
internet data sheet rev. 1.43, 2006-11 17 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 13 clock enable (cke) truth table for synchronous transitions table 14 data mask (dm) truth table current state 1) 1) current state is the state of the ddr2 sdram immediately prior to clock edge n. cke command (n) 2)3) ras, cas, we, cs 2) command (n) is the command registered at clock e dge n, and action (n) is a result of command (n) 3) the state of odt does not affect the states described in this table. the odt function is not available during self refresh. action (n) 2) note 4)5) 4) cke must be maintained high while the device is in ocd calibration mode. 5) operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initializa tion sequence before normal operation can continue. previous cycle 6) (n-1) 6) cke (n) is the logic state of cke at clock edge n; c ke (n-1) was the state of cke at the previous clock edge. current cycle 6) (n) power-down l l x maintain power-down 7)8)11) 7) the power-down mode does not perform any refresh operations. the duration of power-down mode is therefor limited by the refre sh requirements 8) ?x? means ?don?t care (including floating around v ref )? in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to ?1? in emrs(1)). l h deselect or nop power-down exit 7)9)10)11) 9) all states and sequences not shown ar e illegal or reserved unless explicitly described else where in this document. 10) valid commands for power-down entry and exit are nop and deselect only. 11) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 cloc ks of registration. thus, after any cke trans ition, cke may not transition from its v alid level during the time period of t is + 2 t cke + t ih . self refresh l l x maintain self refresh 8)11)12) 12) v ref must be maintained during self refresh operation. l h deselect or nop self refresh exit 9)12)13)14) 13) on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the txsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 14) valid commands for self refresh exit are nop and deselct only. bank(s)active h l deselect or nop active power-down entry 7)9)10)11)15) 15) power-down and self refresh can not be entered while read or write operations, (extended) mode register operations, precharg e or refresh operations are in progress. all banks idle h l deselect or nop precharge power-down entry 9)10)11)15) h l autorefresh self refresh entry 7)11)14)16) 16) self refresh mode can only be entered from the all banks idle state. any state other than listed above h h refer to the command truth table 17) 17) must be a legal command as defined in the command truth table. name (function) dm dqs note write enable l valid 1) 1) used to mask write data; provided coincident with the corresponding data. write inhibit h x 1)
internet data sheet rev. 1.43, 2006-11 18 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 5 electrical characteristics table 15 dram component operating temperature range 5.1 absolute maximum ratings table 16 absolute maximum ratings symbol parameter rating unit note t case operating temperature 0 to 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dr am specification will be suppor ted. during operation, the dr am case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s. 4) when operating this product in the 85 c to 95 c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. note, when the high temperature self refresh is enabled there is an increase of i dd6 by approximately 50% symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?1.0 2.3 v 1) 1) stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may a ffect reliability. v ddq voltage on v ddq pin relative to v ss ?0.5 2.3 v 1) v ddl voltage on v ddl pin relative to v ss ?0.5 2.3 v 1) v in , v out voltage on any pin relative to v ss ?0.5 2.3 v 1) t j junction temperature ? 125 c 1) t stg storage temperature ?55 150 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram.
internet data sheet rev. 1.43, 2006-11 19 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 5.2 dc characteristics table 17 recommended dc operating conditions (sstl_18) table 18 odt dc electrical characteristics symbol parameter rating unit note min. typ. max. v dd supply voltage 1.7 1.8 1.9 v 1)2) 1) hyb18t512161bf?[25/28/33] 2) v ddq tracks with v dd , v dddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together. v dddl supply voltage for dll 1.7 1.8 1.9 v 1)2) v ddq supply voltage for output 1.7 1.8 1.9 v 1)2) v dd supply voltage 1.9 2.0 2.1 v 2)3) 3) hyb18t512161bf?[20/22] v dddl supply voltage for dll 1.9 2.0 2.1 v 2)3) v ddq supply voltage for output 1.9 2.0 2.1 v 2)3) v ref input reference voltage 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4)5) 4) the value of v ref may be selected by the user to provide optimum noi se margin in the system. typically the value of v ref is expected to be about 0.5 v ddq of the transmitting device and v ref is expected to track variations in v ddq . 5) peak to peak ac noise on v ref may not exceed 2% v ref (dc) v tt termination voltage v ref ? 0.04 v ref v ref + 0.04 v 6) 6) v tt is not applied directly to the device. v tt is a system supply for signal terminati on resistors, is expected to be set equal to v ref , and must track variations in die dc level of v ref . parameter / condition symbol min. nom. max. unit note termination resistor impedance value for emrs(1)[a6,a2] = [0,1]; 75 ohm rtt1(eff) 60 75 90 ? 1) 1) measurement definition for rtt(eff): apply v ih(ac) and v il(ac) to test pin separately, then measure current i(v ihac ) and i(v ilac ) respectively. rtt(eff) = (v ih(ac) ? v il(ac) ) /(i(v ihac ) ? i(v ilac )). termination resistor impedance value for emrs(1)[a6,a2] =[1,0]; 150 ohm rtt2(eff) 120 150 180 ? 1) termination resistor impedance value for emrs(1)(a6,a2)=[1,1]; 50 ohm rtt3(eff) 40 50 60 ? 1) deviation of v m with respect to v ddq / 2 delta v m ?6.00 ? + 6.00 % 2) 2) measurement definition for v m : turn odt on and measure voltage (v m ) at test pin (midpoint) with no load: delta v m =((2 xv m /v ddq )? 1) x 100%
internet data sheet rev. 1.43, 2006-11 20 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 19 input and output leakage currents 5.3 dc & ac characteristics ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) ?enable dqs ? mode bit; timing advantages of differential mode are realized in system des ign. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these ti ming relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is verified by design and characterization but not subject to production test. in single ended mode, the dqs signals are internally disabled and don?t care. table 20 dc & ac logic input levels table 21 single-ended ac input test conditions symbol parameter / condition min. max. unit note iil input leakage current; any input 0 v < v in < v dd ?2 +2 a 1) 1) all other pins not under test = 0 v iol output leakage current; 0 v < v out < v ddq ?5 +5 a 2) 2) dq?s, ldqs, ldqs , udqs, udqs , dqs, dqs are disabled and odt is turned off symbol parameter min. max. units v ih(dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il(dc) dc input low ?0.3 v ref ? 0.125 v v ih(ac) ac input logic high v ref + 0.250 ? v v il(ac) ac input low ? v ref ? 0.250 v symbol condition value unit note v ref input reference voltage 0.5 v ddq v 1) 1) input waveform timing is referenced to the input signal crossing through the v ref level applied to the device under test. v swing.max input signal maximum peak to peak swing 1.0 v 1) slew input signal minimum slew rate 1.0 v / ns 2)3) 2) the input signal minimum slew rate is to be maintained over the range from v ih(ac).min to v ref for rising edges and the range from v ref to v il(ac).max for falling edges as shown in figure 2 3) ac timings are referenced with input waveforms switching from v il(ac) to v ih(ac) on the positive transitions and v ih(ac) to v il(ac) on the negative transitions.
internet data sheet rev. 1.43, 2006-11 21 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram figure 2 single-ended ac input test conditions diagram table 22 differential dc and ac in put and output logic levels figure 3 differential dc and ac input and output logic levels diagram symbol parameter min. max. unit note v in(dc) dc input signal voltage ?0.3 v ddq + 0.3 ? 1) 1) v in(dc) specifies the allowable dc execution of eac h input of differential pair such as ck, ck , dqs, dqs etc. v id(dc) dc differential input voltage 0.25 v ddq + 0.6 ? 2) 2) v id(dc) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(dc) ? v il(dc) . v id(ac) ac differential input voltage 0.5 v ddq + 0.6 v 3) 3) v id(ac) specifies the input differential voltage v tr ? v cp required for switching. the minimum value is equal to v ih(ac) ? v il(ac) . v ix(ac) ac differential cross point input voltage 0.5 v ddq ? 0.175 0.5 v ddq + 0.175 v 4) 4) the value of v ix(ac) is expected to equal 0.5 v ddq of the transmitting device and v ix(ac) is expected to track variations in v ddq . v ix(ac) indicates the voltage at which differential input signals must cross. v ox(ac) ac differential cross point output voltage 0.5 v ddq ? 0.125 0.5 v ddq + 0.125 v 5) 5) the value of v ox(ac) is expected to equal 0.5 v ddq of the transmitting device and v ox(ac) is expected to track variations in v ddq . v ox(ac) indicates the voltage at which differential input signals must cross. 9 ' ' 4 9 , + d f p l q 9 , + g f p l q 9 5 ( ) 9 , / g f p d [ 9 , / d f p d [ 9 6 6 9 6 :, 1 * 0 $; g h o w d 7 5 g h o w d 7 ) 9 , / d f p d [ g h o w d 7 ) ) d o o l q j 6 o h z 5 l v l q j 6 o h z 9 , + d f p l q g h o w d 7 5 9 5 ( ) 9 5 ( ) & u r v v l q j 3 r l q w 9 ' ' 4 9 6 6 4 9 , ' 9 , ; r u 9 2 ; 9 7 5 9 & 3
internet data sheet rev. 1.43, 2006-11 22 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 5.4 output buffer characteristics table 23 full strength calibrated pull-up driver characteristics table 24 full strength calibrated pull -down driver characteristics voltage (v) calibrated pull -up driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics ev aluation conditions are nominal low and nominal high 25 c ( t case ), v ddq = 1.8 v, any process nominal(18 ohms) 3) 3) the driver characteristics evaluat ion conditions are nominal 25 c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluation conditions are nominal maximum 0 c ( t case ), v ddq = 1.9 v, any process 0.2 ?9.5 ?10.7 ?11.4 ?11.8 ?13.3 0.3 ?14.3 ?16.0 ?16.5 ?17.4 ?20.0 0.4 ?18.3 ?21.0 ?21.2 ?23.0 ?27.0 voltage (v) calibrated pull -down driver current [ma] nominal minimum 1) (21 ohms) 1) the driver characteristics evaluation conditions are nominal minimum 95 c ( t case ). v ddq = 1.7 v, any process nominal low 2) (18.75 ohms) 2) the driver characteristics ev aluation conditions are nominal low and nominal high 25 c ( t case ), v ddq = 1.8v, any process nominal 3) (18 ohms) 3) the driver characteristics evaluat ion conditions are nominal 25 c ( t case ), v ddq = 1.8 v, typical process nominal high 2) (17.25 ohms) nominal maximum 4) (15 ohms) 4) the driver characteristics evaluation conditions are nominal maximum 0 c ( t case ), v ddq = 1.9 v, any process 0.2 9.5 10.7 11.5 11.8 13.3 0.3 14.3 16.0 16.6 17.4 20.0 0.4 18.7 21.0 21.6 23.0 27.0
internet data sheet rev. 1.43, 2006-11 23 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 5.5 input / output capacitance table 25 input / output capacitance symbol parameter min. max. unit cck input capacitance, ck and ck 1.0 2.0 pf cdck input capacitance delta, ck and ck ?0.25 pf ci input capacitance, all other input-only pins 1.0 1.75 pf cdi input capacitance delta, all other input-only pins ? 0.25 pf cio input/output capacitance, dq, dm, dqs, dqs 2.5 3.5 pf cdio input/output capacitance delta, dq, dm, dqs, dqs ?0.5 pf
internet data sheet rev. 1.43, 2006-11 24 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 5.6 overshoot and undershoot specification table 26 ac overshoot / undershoot specification for address and control pins figure 4 ac overshoot / undershoot diagram for address and control pins parameter ?20 ?22 ?25 ?28 ?33 unit maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 0.5 0.5 v maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 0.5 0.5 v maximum overshoot area above v dd 0.80 0.80 0.80 0.80 0.80 v.ns maximum undershoot area below v ss 0.80 0.80 0.80 0.80 0.80 v.ns 9 ' ' 9 6 6 2 y h u v k r r w $u h d 8 q g h u v k r r w $u h d 0 d [ l p x p $p s o l w x g h 0 d [ l p x p $p s o l w x g h 7l p h q v 9 r o w v 9
internet data sheet rev. 1.43, 2006-11 25 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 27 ac overshoot / undershoot specification for clock, data, strobe and mask pins figure 5 ac overshoot / undershoot diagram for clock, data, strobe and mask pins parameter ?20 ?22 ?25 ?28 ?33 unit maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 0.9 0.9 v maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 0.9 0.9 v maximum overshoot area above v ddq 0.23 0.23 0.23 0.23 0.23 v.ns maximum undershoot area below v ssq 0.23 0.23 0.23 0.23 0.23 v.ns 9 ' ' 4 9 6 6 4 2 y h u v k r r w $u h d 8 q g h u v k r r w $u h d 0 d [ l p x p $p s o l w x g h 0 d [ l p x p $p s o l w x g h 7l p h q v 9 r o w v 9
internet data sheet rev. 1.43, 2006-11 26 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 5.7 ac characteristics 5.7.1 speed grade definitions table 28 speed grade definition speed grade ?20 ?22 ?25 ?28 ?33 unit note parameter symbol min. max. min. max. min. max. min. max. min. max. clock frequency @ cl = 3 t ck 3.75 8 3.75 8 3.75 8 3.75 8 3.75 8 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 7 .timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0). 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , input reference level is the crosspoint when in differential strobe mode. 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 3.75 8 3.75 8 3.75 8 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 38 38 38 38 3.338 ns 1)2)3)4) @ cl = 6 t ck 2.5 8 2.5 8 2.5 8 2.8 8 3.33 8 ns 1)2)3)4) @ cl = 7 t ck 2.0 8 2.2 8 ? ? ? ? ? ? ns 1)2)3)4) row active time t ras 45 70k 45 70k 45 70k 45 70k 45 70k ns 1)2)3)4) 5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? 60 ? 60 ? 60 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? 15 ? 15 ? 15 ? 15 ? ns 1)2)3)4) row precharge time t rp 15 ? 15 ? 15 ? 15 ? 15 ? ns 1)2)3)4)
internet data sheet rev. 1.43, 2006-11 27 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 5.7.2 ac timing parameters list of timing parameters table 29 timing parameter by speed grade parameter symbol ?20 ?22 ?25 unit note 1) 2)3)4)5)6) min. max. min. max. min. max. dq output access time from ck / ck t ac ?450 +450 ?450 +450 ?500 +500 ps cas a to cas b command period t ccd 2?2?2? t ck ck, ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck cke minimum high and low pulse width t cke 3?3?3? t ck ck, ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ?wr+ t rp ?wr+ t rp ? t ck 7)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? t is + t ck + t ih ?? t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh 145 ?? 220 ?? 250 ?? ps 9) dq and dm input hold time (single ended data strobe) t dh1 -105 ?? -30 ?? 0 ?? ps 9) dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? 0.35 ? t ck dqs output access time from ck / ck t dqsck ?450 + 450 ?450 + 450 ?500 + 500 ps 9) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 450 ? 450 ? 450 ps 10) write command to 1st dqs latching transition t dqss wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 t ck dq and dm input setup time (differential data strobe) t ds 20 ? 95 ?? 125 ?? ps 9) dq and dm input setup time (single ended data strobe) t ds1 -105 ? -30 ?? 0 ?? ps 9) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? 0.2 ? t ck dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? 0.2 ? t ck clock half period t hp min. ( t cl, t ch )min. ( t cl, t ch ) min. ( t cl, t ch )? 11) data-out high-impedance time from ck / ck t hz ? t ac.max ? t ac.max ? t ac.max ps 12)
internet data sheet rev. 1.43, 2006-11 28 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram address and control input hold time t ih 525 525 ? 575 ? ps address and control input pulse width (each input) t ipw 0.6 ? 0.6 ? 0.6 ? t ck address and control input setup time t is 400 ? 400 ? 450 ? ps dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max 2 t ac.min t ac.max 2 t ac.min t ac.max ps 12) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max t ac.min t ac.max t ac.min t ac.max ps 12) mode register set command cycle time t mrd 2?2?2? t ck ocd drive mode output delay t oit 012012012ns data output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ? t hp ? t qhs ?? data hold skew factor t qhs ? 600 ? 600 ? 600 ps average periodic refresh interval t refi ? 7.8 ? 7.8 ? 7.8 s 13)14) ? 3.9 ? 3.9 ? 3.9 s 13)15) auto-refresh to active/auto- refresh command period t rfc 105 ? 105 ? 105 ? ns 16) read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 12) read postamble t rpst 0.40 0.60 0.40 0.60 0.40 0.60 t ck 12) active bank a to active bank b command period t rrd 10 ? 10 ? 10 ? ns 14)17) internal read to precharge command delay t rtp 7.5 ? 7.5 ? 7.5 ? ns write preamble t wpre 0.35 x t ck ? 0.35 x t ck ?0.35 x t ck ? t ck write postamble t wpst 0.40 0.60 0.40 0.60 0.40 0.60 t ck 17) write recovery time for write without auto-precharge t wr 13 ? 13 ? 15 ? ns write recovery time for write with auto-precharge wr t wr / t ck ? t wr / t ck ? t wr / t ck ? t ck 18) internal write to read command delay t wtr 7.5 ? 7.5 ? 7.5 ? ns 19) exit power down to any valid command (other than nop or deselect) t xard 2?2?2? t ck 20) exit active power-down mode to read command (slow exit, lower power) t xards 10 ? al ? 9 ? al ? 8 ? al ? t ck 20) exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2?2? t ck parameter symbol ?20 ?22 ?25 unit note 1) 2)3)4)5)6) min. max. min. max. min. max.
internet data sheet rev. 1.43, 2006-11 29 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram exit self-refresh to non-read command t xsnr t rfc +10 ? t rfc +10 ? t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? 200 ? 200 ? t ck 1) v ddq , v dd refer to chapter 1 . 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 5 of this data sheet. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross.the dqs / dqs , input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs / dqs is defined in chapter 5.3 of this data sheet. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . see chapter 5 for the reference load for timing measurements. 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. in case of clock frequency ch ange during power-down, a specif ic procedure is required. 9) timing is referenced to industrial standard definition 10) consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14) 0 c t case 85 c 15) 85 c < t case 95 c 16) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 17) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 18) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 19) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 20) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. parameter symbol ?20 ?22 ?25 unit note 1) 2)3)4)5)6) min. max. min. max. min. max.
internet data sheet rev. 1.43, 2006-11 30 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 30 timing parameter by speed grade parameter symbol ?28 ?33 unit note 1) 2)3)4)5)6) min. max. min. max. dq output access time from ck / ck t ac ?550 +550 ?600 +600 ps cas a to cas b command period t ccd 2?2? t ck ck, ck high-level width t ch 0.45 0.55 0.45 0.55 t ck cke minimum high and low pulse width t cke 3?3? t ck ck, ck low-level width t cl 0.45 0.55 0.45 0.55 t ck auto-precharge write recovery + precharge time t dal wr + t rp ?wr+ t rp ? t ck 7)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? t is + t ck + t ih ?? ns 8) dq and dm input hold time (differential data strobe) t dh 275 ?? 295 ?? ps 9) dq and dm input hold time (single ended data strobe) t dh1 25 ?? 45 ?? ps 9) dq and dm input pulse width (each input) t dipw 0.35 ? 0.35 ? t ck dqs output access time from ck / ck t dqsck ?550 + 550 ?600 + 600 ps 9) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck dqs-dq skew (for dqs & associated dq signals) t dqsq ? 450 ? 450 ps 10) write command to 1st dqs latching transition t dqss wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 t ck dq and dm input setup time (differential data strobe) t ds 150 ?? 170 ?? ps 9) dq and dm input setup time (single ended data strobe) t ds1 25 ?? 45 ?? ps 9) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck dqs falling edge to ck se tup time (write cycle) t dss 0.2 ? 0.2 ? t ck clock half period t hp min. ( t cl, t ch )min. ( t cl, t ch )? 11) data-out high-impedance time from ck / ck t hz ? t ac.max ? t ac.max ps 12) address and control input hold time t ih 625 ? 675 ? ps address and control input pulse width (each input) t ipw 0.6 ? 0.6 ? t ck address and control input setup time t is 500 ? 550 ? ps dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max 2 t ac.min t ac.max ps 12) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max t ac.min t ac.max ps 12) mode register set command cycle time t mrd 2?2? t ck ocd drive mode output delay t oit 0 12 0 12 ns data output hold time from dqs t qh t hp ? t qhs ? t hp ? t qhs ?? data hold skew factor t qhs ? 600 ? 600 ps average periodic refresh interval t refi ?7.8?7.8 s 13)14) ?3.9?3.9 s 13)15)
internet data sheet rev. 1.43, 2006-11 31 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram auto-refresh to active/auto-refresh command period t rfc 105 ? 105 ? ns 16) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 12) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 12) active bank a to active bank b command period t rrd 10 ? 10 ? ns 14)17) internal read to precharge command delay t rtp 7.5 ? 7.5 ? ns write preamble t wpre 0.35 x t ck ?0.35 x t ck ? t ck write postamble t wpst 0.40 0.60 0.40 0.60 t ck 17) write recovery time for write without auto- precharge t wr 15 ? 15 ? ns write recovery time for write with auto-precharge wr t wr / t ck ? t wr / t ck ? t ck 18) internal write to read command delay t wtr 7.5 ? 7.5 ? ns 19) exit power down to any valid command (other than nop or deselect) t xard 2?2? t ck 20) exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? 6 ? al ? t ck 20) exit precharge power-down to any valid command (other than nop or deselect) t xp 2?2? t ck exit self-refresh to non-read command t xsnr t rfc +10 ? t rfc +10 ? ns exit self-refresh to read command t xsrd 200 ? 200 ? t ck 1) v ddq , v dd refer to chapter 1 . 2) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 3) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. for other slew rates see chapter 5 of this data sheet. 4) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross.the dqs / dqs input reference level is the crosspoint when in differential strobe mode; the input reference level for signals other than ck/ck , dqs / dqs is defined in chapter 5.3 of this data sheet. 5) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 6) the output timing reference voltage level is v tt . see chapter 5 for the reference load for timing measurements. 7) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 8) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. in case of clock frequency ch ange during power-down, a specif ic procedure is required. 9) timing is referenced to industrial standard definition 10) consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 11) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 12) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 13) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 14) 0 c t case 85 c 15) 85 c < t case 95 c 16) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. parameter symbol ?28 ?33 unit note 1) 2)3)4)5)6) min. max. min. max.
internet data sheet rev. 1.43, 2006-11 32 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 5.7.3 odt ac electrical characteristics table 31 odt ac electrical characteristics a nd operating conditions for all bins 17) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 18) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 19) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 mhz. 20) user can choose two different active pow er-down modes for additional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. symbol parameter / condition unit note min. max. t aond odt turn-on delay 2 2 t ck t aon odt turn-on t ac.min t ac.max + 0.7 ns ns 1) 1) odt turn on time min. is when the devic e leaves high impedance and odt re sistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (pow er-down modes) t ac.min +2 ns 2 t ck + t ac.max +1 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (pow er-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns t anpd odt to power down mode entry latency 3 ? t ck t axpd odt power down exit latency 8 ? t ck
internet data sheet rev. 1.43, 2006-11 33 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 6 specifications and conditions table 32 i dd measurement conditions parameter symbol note operating current - one bank active - precharge t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching. i dd0 1)2)3)4) 5)6) operating current - one bank active - read - precharge i out = 0 ma, bl = 4, t ck = t ck(idd) , t rc = t rc(idd) , t ras = t ras.min(idd) , t rcd = t rcd(idd) , al = 0, cl = cl(idd); cke is high, cs is high between valid commands. address and control inputs are switching; databus inputs are switching. i dd1 1)2)3)4) 5)6) precharge power-down current all banks idle; cke is low; t ck = t ck(idd) ;other control and address inputs ar e stable; data bus inputs are floating . i dd2p 1)2)3)4) 5)6) precharge standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are switching, data bus inputs are switching . i dd2n 1)2)3)4) 5)6) precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck(idd) ; other control and address inputs are stable, data bus inputs are floating. i dd2q 1)2)3)4) 5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other control and address inputs are stable; data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit). i dd3p(0) 1)2)3)4) 5)6) active power-down current all banks open; t ck = t ck(idd) , cke is low; other cont rol and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to 1 (slow power-down exit); i dd3p(1) 1)2)3)4) 5)6) active standby current all banks open; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd3n 1)2)3)4) 5)6) operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max.(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r 1)2)3)4) 5)6) operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl (idd) ; t ck = t ck(idd) ; t ras = t ras.max(idd) , t rp = t rp(idd) ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w 1)2)3)4) 5)6) burst refresh current t ck = t ck(idd) , refresh command every t rfc = t rfc(idd) interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b 1)2)3)4) 5)6) distributed refresh current t ck = t ck(idd) , refresh command every t refi = 7.8 s interval, cke is low and cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5d 1)2)3)4) 5)6)
internet data sheet rev. 1.43, 2006-11 34 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 33 definition for i dd self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and addr ess inputs are floating, data bus inputs are floating. i dd6 1)2)3)4) 5)6) operating bank interleave read current 1. all banks interleaving reads, i out = 0 ma; bl = 4, cl = cl (idd) , al = t rcd(idd) -1 t ck(idd) ; t ck = t ck(idd) , t rc = t rc(idd) , t rrd = t rrd(idd) ; cke is high, cs is high between valid commands. address bus inputs are stable during deselects; data bus is switching. i dd7 1)2)3)4) 5)6)7) 1) v ddq = 2.0 v 0.1 v; v dd = 2.0 v 0.1 v 2) i dd specifications are tested after the device is properly initialized. 3) i dd parameter are specified with odt disabled. 4) data bus consists of dq, dm, dqs, dqs , ldqs, ldqs , udqs and udqs . 5) definitions for i dd : see table 33 6) timing parameter minimum and maximum values for i dd current measurements are defined in chapter 7.. 7) a = activate, ra = read with auto-precharge, d=deselect parameter description low defined as v in v il(ac).max high defined as v in v ih(ac).min stable defined as inputs are stable at a high or low level floating defined as inputs are v ref = v ddq / 2 switching defined as: inputs are changing between high and lo w every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for dq signals not including mask or strobes parameter symbol note
internet data sheet rev. 1.43, 2006-11 35 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 34 i dd specification speed grade ?20 ?22 ?25 -28 -33 unit note symbol typ. typ. typ. typ. typ. i dd0 92 87 81 77 70 ma i dd1 99 94 89 85 78 ma i dd2p 44444ma i dd2n 46 43 41 38 33 ma i dd2q 40 38 38 35 31 ma i dd3p(0) 30 29 28 27 23 ma 1) 1) mrs(12)=0 i dd3p(1) 55554ma 2) 2) mrs(12)=1 i dd3n 52 48 47 43 37 ma i dd4r 166 158 153 145 127 ma i dd4w 189 173 163 149 129 ma i dd5b 127 122 119 115 109 ma i dd5d 55554ma 3) 3) 0 t case 85c i dd6 44443ma 3) i dd7 204 204 193 193 179 ma
internet data sheet rev. 1.43, 2006-11 36 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 7 package 7.1 package dimension figure 6 package outline p-tfbga-84 (top view)
internet data sheet rev. 1.43, 2006-11 37 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 7.2 package thermal characteristics table 35 package thermal characteristics jesd51 theta_ja 1) 1) junction to ambient thermal resistance. the value has been obtained by simulation us ing the conditions stated in the industri al standard jesd-51 standard. theta_jc 2) 2) junction to case thermal resistance. the value has been obtained by simulation. industrial standard board 1s0p 2s0p air flow 0 m/s 1 m/s 3 m/s 0 m/s 1 m/s 3 m/s ? rth[k/w] 69 53 47 41 35 33 5
internet data sheet rev. 1.43, 2006-11 38 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram figure 1 pin configuration for 16 components, p-tfbga-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2 single-ended ac input test conditions diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 3 differential dc and ac input and output logic levels diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4 ac overshoot / undershoot diagram for address and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5 ac overshoot / undershoot diagram for clock, data, strobe and mask pins . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6 package outline p-tfbga-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 list of figures
internet data sheet rev. 1.43, 2006-11 39 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram table 1 ordering information for rohs compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2 pin configuration of ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3 abbreviations for pin type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4 abbreviations for buffer type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5 512-mbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6 mode register definition (ba[1:0] = 00b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7 extended mode register definition (ba[1:0] = 01b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8 emrs(2) programming extended mode register definition (ba[1:0]=10 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9 emr(3) programming extended m ode register definition (ba[1:0]=10 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10 odt truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 11 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12 command truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13 clock enable (cke) truth table for synchronous transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14 data mask (dm) truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15 dram component operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 16 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 17 recommended dc operating conditions (sstl_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 18 odt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 19 input and output leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 20 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 21 single-ended ac input test condition s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 22 differential dc and ac input and output logic levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 23 full strength calibrated pull-up driv er characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 24 full strength calibrated pull-down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 25 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 26 ac overshoot / undershoot specification for address and co ntrol pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 27 ac overshoot / undershoot specification for clock, data, strobe and mask pins . . . . . . . . . . . . . . . . . . . . . 25 table 28 speed grade definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 29 timing parameter by speed grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 30 timing parameter by speed grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 31 odt ac electrical characteristics and operating condition s for all bins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 32 i dd measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 33 definition for i dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 34 i dd specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 35 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 list of tables
internet data sheet rev. 1.43, 2006-11 40 03292006-l40n-l04g hyb18t512161bf?20/22/25/28/33 512-mbit double-data-rate-two sdram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 512 mbit ddr2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4truthtables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 dc & ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 output buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 input / output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.6 overshoot and undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7.1 speed grade definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7.2 ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.7.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table of contents
edition 2006-11 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2006. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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