View TMDS141_3294772.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features applications description TMDS141 slls737b ? june 2006 ? revised april 2007 hdmi hider high impedance outputs when disabled supports 2.25 gbps signaling rate for 480i/p, tmds inputs hbm esd protection exceeds 6 720i/p, and 1080i/p resolution to 12-bit color kv depth 3.3-v supply operation compatible with hdmi 1.3a 40-pin qfn package (rha) integrated receiver termination rohs compatible and 260 c reflow rated 8-db equalizer compensates losses from 5-m or longer hdmi cables digital tv selectable output de-emphasis supports 1-m hdmi transmission dvd player set-top-box i 2 c repeater isolates bus capacitance at both ends audio video receiver digital projector dvi or hdmi cable the TMDS141 hdmi hider is designed to accommodate a 1-m hdmi cable between a hdmi connector and a receiver. the internal cable causes signal distortion to high-speed tmds signals, as well as increasing capacitance to the ddc channel. each TMDS141 contains four tmds repeaters to transmit digital content with signaling rates of up to 2.25-gbps, and an i 2 c repeater to link extended display identification data (edid) reading and high-bandwidth digital content protection (hdcp) key exchange under i 2 c standard mode operations. the device includes four tmds compliant differential receivers with 50- w termination resistors and 3.3-v termination voltage integrated at each receiver input pin. external terminations are not required. a built-in frequency response equalization circuit, 8 db at 825 mhz, compensates inter-symbol interference (isi) losses from a 5-m or longer input cable link. the device also includes four tmds compliant differential drivers. a precision resistor is connected externally from the vsadj pin to ground for setting the differential output voltage to be compliant with the tmds standard. a selectable de-emphasis circuit is available via the pre input to drive long pcb traces or cables. when pre is high, the 3.5-db high frequency gain offsets the losses due to the fr4 trace. pre can be left open or kept low when the de-emphasis function is not desired. typical application please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2006?2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www.ti.com tmds 141 interface unit audiovisual processing unit hdmi rx digital tv
TMDS141 slls737b ? june 2006 ? revised april 2007 with standard tmds terminations at the outputs, all tmds outputs are forced high-impedance when oe is set high. the i 2 c repeater isolates the buses without accumulating the capacitance of both sides. it allows ddc capacitance to be controlled under the desired load. the i 2 c outputs are high-impedance when device supply voltage is less than 1.5 v or i2cen is low. the ovs pin, output voltage select, provides the flexibility of adjusting the output voltage level of the tscl and tsda side to optimize noise margins while interfacing to different hdmi receivers. the device is characterized for operation from 0 c to 70 c. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. functional block diagram 2 submit documentation feedback www.ti.com v cc r int tmdsreceiver w/eq tmds driver tx2 tx2 rx2 rx2 tmdsreceiver w/eq tmds driver tx1 tx1 rx1 rx1 tmdsreceiver w/eq tmds driver tx0 tx0 rx0 rx0 tmdsreceiver w/eq tmds driver txc txc rxc rxc r int r int r int v cc v cc v cc vsadj pre rscl rsda tscl tsda i2cen oe ovs
TMDS141 slls737b ? june 2006 ? revised april 2007 rha package (top view) terminal functions terminal i/o description name no. rx2, rx1, rx0, rxc 1, 38, 35, 32 i tmds negative inputs rx2, rx1, rx0, rxc 2, 39, 36, 33 i tmds positive inputs tx2, tx1, tx0, txc 10, 13, 16, 19 o tmds negative outputs tx2, tx1, tx0, txc 9, 12, 15, 18 o tmds positive outputs rscl 29 i/o ddc bus clock line to source rsda 28 i/o ddc bus data line to source tscl 22 i/o ddc bus clock line to sink tsda 23 i/o ddc bus data line to sink vsadj 30 i tmds compliant voltage swing control i 2 c repeater enable i2cen 5 i low: high-z high: active ovs 25 i tscl/tsda output voltage select tmds output enable oe 6 i low: active high: high-z tmds output de-emphasis adjustment pre 7 i low: 0 db high: 3.5 db 4, 11, 17, 24, 27, v cc power supply 34, 40 3, 8, 14, 20, 21, gnd ground 26, 31, 37 3 submit documentation feedback www.ti.com vsadjrscl rsda v cc gndovs v cc tsdatscl gnd gnd rxc rxc v cc rx0 rx0 gnd rx1 rx1 v cc rx2 rx2 gnd v cc i2cen oe pre gnd tx2tx2 gndtxc txcv cc tx0 tx0gnd tx1 tx1v cc 12 3 4 5 6 7 8 9 10 3132 33 34 35 36 37 38 39 40 20 1918 17 16 15 14 13 12 11 3029 28 27 26 25 24 23 22 21
equivalent input and output schematic diagrams TMDS141 slls737b ? june 2006 ? revised april 2007 ordering information (1) part number part marking package TMDS141rhar TMDS141 40-pin qfn tape/reel (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com. 4 submit documentation feedback www.ti.com z tmds output stage y 25 w 25 w 10ma tmds input stage a b 50 w 50 w control input stage ovs 400 w control input stage pre oe i2cen 400 w t-side i c input/output stage 2 tscl tsda v cc 400 w v ol r-side i c input/output stage 2 rscl rsda 400 w v cc v cc v cc v cc v cc v cc
absolute maximum ratings dissipation ratings thermal characteristics recommended operating conditions TMDS141 slls737b ? june 2006 ? revised april 2007 over operating free-air temperature range (unless otherwise noted) (1) unit v cc supply voltage range (2) ?0.5 v to 4 v rx, rx 2.0 v to 4 v voltage range tx, tx, pre, vsadj, oe, i2cen, ovs, hpdn ?0.5v to 4 v rscl, rsda, tscl, tsda ?0.5 v to 6 v rx, rx 6 kv human body model (3) all pins 4 kv electrostatic discharge charged-device model (4) (all pins) 1500 v machine model (5) (all pins) 200 v continuous power dissipation see dissipation rating table (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values, except differential i/o bus voltages, are with respect to network ground terminal. (3) tested in accordance with jedec standard 22, test method a114-b (4) tested in accordance with jedec standard 22, test method c101-a (5) tested in accordance with jedec standard 22, test method a115-a derating factor (1) t a = 70 c package pcb jedec standard t a 25 c above t a = 25 c power rating 40-qfn rha low-k (2) 839.7 mw 8.39 mw/ c 461.8 mw 40-qfn rha high-k (3) 3030.3 mw 30.3 mw/ c 1666.6mw (1) this is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. (2) in accordance with the low-k thermal metric definitions of eia/jesd51-3 (3) in accordance with the high-k thermal metric definitions of eia/jesd51-7 over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit r q jb junction-to-board thermal 30.9 c/w resistance 6 r q jc junction- to-case thermal 32.4 c/w resistance 2 v ih = v cc , v il = v cc - 0.5 v, r t = 50 w , pre = low 344 370 mw v cc = av cc = 3.3v, r vsadj = 4.64 k w pre = high 381 407 p d device power dissipation v ih = v cc , v il = v cc - 0.6 v, r t = 50 w , pre = low 484 mw v cc = 3.6 v, av cc = 3.3v, r vsadj = 4.6 k w pre = high 526 min nom max unit v cc supply voltage 3 3.3 3.6 v t a operating free-air temperature 0 70 c tmds differential pins (rx/ rxc) v ic input common mode voltage v cc ?400 v cc +10 mv v id receiver peak-to-peak differential input voltage 150 1560 mvp-p r vsadj resistor for tmds compliant voltage swing range 4.6 4.64 4.68 k w av cc tmds output termination voltage, see figure 1 3 3.3 3.6 v r t termination resistance, see figure 1 45 50 55 w signaling rate 0 2.25 gbps 5 submit documentation feedback www.ti.com
electrical characteristics TMDS141 slls737b ? june 2006 ? revised april 2007 recommended operating conditions (continued) min nom max unit control pins (pre, oe, i2cen) v ih lvttl high-level input voltage 2 v cc v v il lvttl low-level input voltage gnd 0.8 v control pins (ovs) v ih lvttl high-level input voltage 3 3.6 v v il lvttl low-level input voltage -0.5 0.5 v i 2 c pins (tscl, tsda) v ih high-level input voltage 0.7v cc 5.5 v v il low-level input voltage -0.5 0.3v cc v v icl low-level input voltage contention (1) -0.5 0.4 v i 2 c pins (rscl, rsda) v ih high-level input voltage 2.1 5.5 v v il low-level input voltage -0.5 1.5 v (1) v il specification is for the first low level seen by the scl/sda lines. v icl is for the second and subsequent low levels seen by the tscl/tsda lines. over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit v ih = v cc , v il = v cc ? 0.4 v, r t = 50 w , av cc = 3.3 v, r vsadj = 4.64 k w , i cc supply current 108 130 (2) ma 1.65-gbps hdmi data pattern, 165-mhz pixel clock, pre = low v ih = v cc , v il = v cc ? 0.4 v, r t = 50 w , av cc = 3.3 v, r vsadj = 4.64 k w , p d power dissipation 497 (2) mw 1.65-gbps hdmi data pattern, 165-mhz pixel clock, pre = low tmds differential pins (tx, txc) v oh single-ended high-level output voltage av cc ?10 av cc +10 mv v ol single-ended low-level output voltage av cc ?600 av cc ?400 mv v swing single-ended output swing voltage 400 600 mv see figure 2 , av cc = 3.3 v, v od(o) overshoot of output differential voltage 15% 2 v swing r t = 50 w v od(u) undershoot of output differential voltage 25% 2 v swing change in steady-state common-mode d v oc(ss) 5 mv output voltage between logic states 0 v v cc 1.5 v, i (o)off single-ended standby output current ?10 10 a av cc = 3.3 v, r t = 50 w v od(pp) peak-to-peak output differential voltage 800 1200 see figure 3 , pre = high, mvp-p steady state output differential voltage av cc = 3.3 v, r t = 50 w v ode(ss) 600 820 with de-emphasis i (os) short circuit output current see figure 4 -12 12 ma single-ended input voltage under high v i(open) i i = 10 a v cc ?10 v cc +10 mv impedance input or open input r int input termination resistance v in = 2.9 v 45 50 55 w control pins (pre, oe, i2cen, ovs) |i ih | high-level digital input current v ih = 2 v or v cc -10 10 a |i il | low-level digital input current v il = gnd or 0.8 v -10 10 a i 2 c pins (tscl, tsda) v i = 5.5 v -50 50 |i lkg | input leakage current a v i = v cc -10 10 |i oh | high-level output current v o = 3.6 v -10 10 a (1) all typical values are at 25 c and with a 3.3-v supply. (2) the maximum rating is characterized under 3.6 v v cc and 600 mv v id . 6 submit documentation feedback www.ti.com
switching characteristics TMDS141 slls737b ? june 2006 ? revised april 2007 electrical characteristics (continued) over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit |i il | low-level input current v il = gnd -40 40 a ovs = nc (3) 0.47 0.6 v ol low-level output voltage i ol = 400 m a or 4 ma ovs = gnd (3) 0.6 0.75 v ovs = v cc (3) 0.75 0.95 ovs = nc (3) 70 low-level input voltage below output v ol -v ilc ensured by design ovs = gnd (3) 220 mv low-level voltage level ovs = v cc (3) 370 v i = 5.0 v or 0 v, freq = 100 khz 25 c io input/output capacitance pf v i = 3.0 v or 0 v, freq = 100 khz 10 i 2 c pins (rscl, rsda) v i = 5.5 v -50 50 |i lkg | input leakage current m a v i = v cc -10 10 |i oh | high-level output current v o = 3.6 v -10 10 a |i il | low-level input current v il = gnd -10 10 a v ol low-level output voltage i ol = 4 ma 0.2 v v i = 5.0 v or 0 v, freq = 100 khz 25 c i input capacitance pf v i = 3.0 v or 0 v, freq = 100 khz 10 (3) the patent of the ovs pin is filed. over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit tmds differential pins (tx/txc) t plh propagation delay time, low-to-high-level output 100 500 ps t phl propagation delay time, high-to-low-level output 100 500 ps t r differential output signal rise time (20% - 80%) 75 240 ps t f differential output signal fall time (20% - 80%) 75 240 ps see figure 2 , av cc = 3.3 v, r t = 50 w t sk(p) pulse skew (|t phl ? t plh |) (2) 50 ps t sk(d) intra-pair differential skew, see figure 5 60 ps t sk(o) inter-pair channel-to-channel output skew (3) 80 ps t sk(pp) part-to-part skew (4) 200 ps t en enable time 10 ns see figure 6 t dis disable time 10 ns t jit(pp) peak-to-peak output jitter from txc, residual jitter (5) see figure 7 , rxc = 165-mhz clock, 14 30 ps rx = 1.65-gbps hdmi pattern, input: 5m 28awg hdmi cable, t jit(pp) peak-to-peak output jitter from tx0 - tx2, residual jitter (5) 30 88 ps output: 1m 28awg hdmi cable, pre = high t jit(pp) peak-to-peak output jitter from txc, residual jitter (5) see figure 7 , rxc = 225-mhz clock, 25 rx = 2.25-gbps hdmi pattern, ps input: 5m 28awg hdmi cable, t jit(pp) peak-to-peak output jitter from tx0 - tx2, residual jitter (5) 42 88 output: 1m 28awg hdmi cable, pre = high (1) all typical values are at 25 c and with a 3.3-v supply. (2) t sk(p) is the magnitude of the time difference between t plh and t phl of a specified terminal. (3) t sk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when inputs are tied together. (4) t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of two devices, or between channel 1 of two devices, when both devices operate with the same source, the same supply voltages, at the same temperature, and have identical packages and test circuits. (5) jitter specifications are ensured by design and characterization and measured in ber -12 7 submit documentation feedback www.ti.com
TMDS141 slls737b ? june 2006 ? revised april 2007 switching characteristics (continued) over recommended operating conditions (unless otherwise noted) parameter test conditions min typ (1) max unit i2c pins (rscl, rsda, tscl, tsda) propagation delay time, low-to-high-level output 204 t plh 459 ns tscl/tsda to rscl/rsda propagation delay time, high-to-low-level output 35 t phl 120 ns tscl/tsda to rscl/rsda propagation delay time, low-to-high-level output 194 t plh 351 ns rscl/rsda to tscl/tsda see figure 8 , ovs = nc propagation delay time, high-to-low-level output 35 t phl 120 ns rscl/rsda to tscl/tsda t r tscl/tsda output signal rise time 500 800 ns t f tscl/tsda output signal fall time 30 72 ns t r rscl/rsda output signal rise time 796 999 ns t f rscl/rsda output signal fall time 20 72 ns t set enable to start condition 100 ns see figure 9 t hold enable after stop condition 100 ns 8 submit documentation feedback www.ti.com
parameter measurement information TMDS141 slls737b ? june 2006 ? revised april 2007 figure 1. typical termination for tmds output driver note: pre = low. all input pulses are supplied by a generator having the following characteristics: t r or t f < 100 ps, 100 mhz from agilent 81250. c l includes instrumentation and fixture capacitance within 0.06 m of the d.u.t. measurement equipment provides a bandwidth of 20 ghz minimum. figure 2. tmds timing test circuit and definitions 9 submit documentation feedback www.ti.com tmds driver avcc r t r t tmds receiver z o = r t z o = r t t phl t plh 100% 0v differential 0% 80% 20% t f t r 0.4 v 0 v ?0.4 v vcc tmds receiver tmds driver tx rx avcc c l 0.5 pf vccvcc?0.4 v dc coupled vcc+0.2 vvcc?0.2 v ac coupled rx v ic = | v rx ? v rx | v swing = | v tx ? v tx | v rx v rx v ic v tx v tx tx v rx v rx v ic v ic r int r int r t r t v oc v id(pp) v od(pp) v swing v od(o) v oc(ss) v od(u)
TMDS141 slls737b ? june 2006 ? revised april 2007 parameter measurement information (continued) figure 3. de-emphasis output voltage waveforms and duration measurement definitions figure 4. short circuit output current test circuit figure 5. definition of intra-pair differential skew figure 6. tmds enable and disable timing definitions 10 submit documentation feedback www.ti.com oe v cc 1.5 v 0 v txtx t en t dis hi-z v = 75 mv od v od = -75 mv 0 v v = 400 mv od v od = -400 mv v od(pp) v ode(ss) 20% 80% t pre 1 bit 1 to n bit tmds driver 0 v or 3.6 v 50 50 _ + i os v tx v tx t sk(d) 50%
TMDS141 slls737b ? june 2006 ? revised april 2007 parameter measurement information (continued) a. all jitters are measured in ber of 10 -12 b. the residual jitter reflects the total jitter measured at xtp4, subtract the total jitter at xtp1 figure 7. jitter test circuit figure 8. i 2 c timing test circuit and definition 11 submit documentation feedback www.ti.com data + data - clk+clk- video patterm generator 800mvpp or 1200mvpp differential coaxcoax coaxcoax coaxcoax coaxcoax TMDS141 smasma sma sma avcc r t r t avcc r t r t jitter test instrument jitter test instrument xtp4 xtp2 xtp1 28awg hdmi cable transmission media hdmi cable or fr4 pcb trace rx +eq out rx +eq out smasma sma sma xtp3 pulse generator d.u.t. r t r l =4.7k w c l =100pf v in v out 3.3v + 10% v cc vcc vcc/2 0.1v 3.3v + 10% 1.5v v ol t r t f t plh t phl rscl/rsda input 20% 20% 80% 80% tscl/tsda output pulse generator d.u.t. r t r l =1.67k w c l =400pf v in v out 5v + 10% v cc vcc 1.5v0.1v 5v + 10% vcc/2 v ol t r t f t phl tscl/tsda input 20% 20% 80% 80% rscl/rsda output tscl/tsda input rscl/rsda output vcc 0.5v 5v + 10% vcc/2 t plh
TMDS141 slls737b ? june 2006 ? revised april 2007 parameter measurement information (continued) figure 9. i 2 c setup and hold definition 12 submit documentation feedback www.ti.com scl sda i2cen v dd 0v v dd 1.5v 0v v dd 1.5v 0v t set t hold start stop
typical characteristics TMDS141 slls737b ? june 2006 ? revised april 2007 supply current supply current vs vs frequency free-air temperature figure 10. figure 11. residual peak-to-peak jitter residual peak-to-peak jitter vs vs data rate data rate (dc coupled input: 5m 28awg, output: 1m 28awg) (dc coupled input: 3m 30awg, output: 1m 28awg) figure 12. figure 13. 13 submit documentation feedback www.ti.com data rate - mbps residual peak-peak jitter - % of tbit 0 2 4 6 8 10 12 14 16 18 20 750 1450 1650 1850 2250 pre = high, 800 mv pp pre = high, 1200 mv pp pre = low, 1200 mv pp pre = low, 800 mv pp v = av = 3.3 v, r = 50 , t = 25c, = low, hdmi data pattern cc cc t a w r = 4.64 k , vsadj w oe 0 2 4 6 8 10 12 14 16 18 20 750 1450 1650 1850 2250 data rate - mbps residual peak-peak jitter - % of tbit pre = high, 800 mv pp pre = low, 800 mv pp pre = high, 1200 mv pp pre = low, 1200 mv pp v = av = 3.3 v, r = 50 , t = 25c, cc cc t a w r = 4.64 k , = low, hdmi data pattern vsadj w oe 0 10 20 30 40 50 60 70 80 90 100 110 120 t - free- air temperature - c a i - supply current - ma c c 1 2 3 4 5 6 oe = low, pre = high v = av = 3.3 v, r = 50 , v = 1200 mv , rx0 - rx2 hdmi data pattern,2.25 gbps rxc, 225 mhz cc cc t id(pp) p-p w r = 4.64 k , vsadj w 0 10 20 30 40 50 60 70 80 90 100 110 120 f - frequency - mhz i - supply current - ma cc 75 165 185 205 225 oe = low, pre = high oe = low, pre = low oe = high, pre = low v = av = 3.3 v, r = 50 , t = 25c, v = 1200 mv cc cc t a id(pp) p-p w r = 4.64 k vsadj w,
TMDS141 slls737b ? june 2006 ? revised april 2007 typical characteristics (continued) residual peak-to-peak jitter residual peak-to-peak jitter vs vs data rate 8-mil fr4 trace output (ac coupled input: 3m 30awg, output: 1m 28awg) (dc coupled input: 5m 28awg) figure 14. figure 15. residual peak-to-peak jitter vs peak-to-peak differential input voltage (at xtp2) figure 16. 14 submit documentation feedback www.ti.com data rate - mbps residual peak-peak jitter - % of tbit 0 2 4 6 8 10 12 14 16 18 20 750 1450 1650 1850 2250 pre = low, 800 mv pp pre = low, 1200 mv pp pre = high, 1200 mv pp pre = high, 800 mv pp v = av = 3.3 v, t = 25c, cc cc a r = 50 r = 4.64 k = low, hdmi data pattern t vsadj w, w, oe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 5 7 11 15 18 8-mil fr4 trace length - inch residual peak-peak jitter - % of tbit xtp1 v = 800 mv id pp xtp1 v = 1200 mv id pp v = av = 3.3 v, r = 50 , t = 25c, cc cc t a w pre = high, = low, 1.65 gbps hdmi pattern, 165-mhz pixel clock, v at xtp1, source jitter < 0.3 ui, see figure 7 oe id(pp) r = 4.64 k , vsadj w 4 4.5 5 5.5 6 6.5 7 7.5 8 300 500 700 900 1100 1300 1500 1700 peak-to-peak differential input voltage - mvp-p residual peak-peak jitter - % of tbit output = 1m, pre = high output = 0m, pre = low v = av = 3.3 v, r = 50 t = 25c, cc cc a t w, r = 4.64 k = low, 28awg hdmi cable, 1.65 gbps hdmi data pattern, 165 mhz pixel clock, v at xtp1, source jitter < 0.3 ui, see figure 7 vsadj id(pp) w, oe
application information supply voltage tmds inputs tmds outputs i 2 c function description TMDS141 slls737b ? june 2006 ? revised april 2007 all v cc pins can be tied to a single 3.3-v power source. a 0.01- m f capacitor is connected from each v cc pin directly to ground to filter supply noise. standard tmds terminations are integrated on all tmds inputs. external terminations are not required. each input channel contains an 8-db equalization circuit to compensate for cable losses. the voltage at the tmds input pins must be limited per the absolute maximum ratings. an unused input should not be connected to ground as this would result in excessive current flow damaging the device. tmds input pins do not incorporate failsafe circuits. an unused input channel can be externally biased to prevent output oscillation. the complementary input pin is recommended to be grounded through a 1-k w resistor and the other pin left open. a 1% precision resister, 4.64-k w , connected from vsadj to ground is recommended to allow the differential output swing to comply with tmds signal levels. the differential output driver provides a typical 10-ma current sink capability, which provides a typical 500-mv voltage drop across a 50- w termination resistor. figure 17. tmds driver and termination circuit referring to figure 17 , if both v cc (TMDS141 supply) and av cc (sink termination supply) are both powered, the tmds output signals is high impedance when oeb = high. both supplies being active is the normal operating condition. again refer to figure 17 , if v cc is on and av cc is off, the tmds outputs source a typical 5-ma current through each termination resistor to ground. a total of 10-mw of power is consumed by the terminations independent of the oeb logical selection. when av cc is powered on, normal operation (oeb controls output impedance) is resumed. when the power source of the device is off and the power source to termination is on, the i o(off) , output leakage current, specification ensures the leakage current is limited 10- m a or less. the pre pin provides 3db de-emphasis, allowing output signal pre-conditioning to offset interconnect losses from the TMDS141 outputs to a tmds receiver. pre is recommended to be set low while connecting to a receiver throw short pcb route. the rscl/rsda and tscl/tsda pins are 5-v tolerant when the device is powered off and high impedance under low supply voltage, 1.5 v or below. if the device is powered up and the i 2 c circuits are enabled, and i2cen = high, the driver t (see figure 18 ) is turned on or off depending up on the corresponding r side voltage level. when the r side is pulled low below 1.5 v, the corresponding t side driver turns on and pulls the t side down to a low level output voltage, v ol . the value of v ol depends on the input to the ovs pin. when ovs is left floating 15 submit documentation feedback www.ti.com TMDS141 v cc gnd tmdsdriver av cc z o = r t z o = r t r t r t tmdsreceiver
i 2 c enable i 2 c behavior TMDS141 slls737b ? june 2006 ? revised april 2007 application information (continued) or not connected, v ol is typically 0.5 v. when ovs is connected to gnd, v ol is typically 0.65 v. when ovs is connected to v cc , v ol is typically 0.8 v. v ol is always higher than the driver r input threshold, v il , which is typically 0.4 v, preventing lockup of the repeater loop. the v ol value can be selected to improve or optimize noise margins between v ol and the v il of the repeater itself or the v il of some external device connected on the t side. when the r side is pulled up, above 1.5 v, the t side driver turns off and the t side pin is high impedance. figure 18. i 2 c drivers in TMDS141 when the t side is pulled below 0.4 v by an external i 2 c driver, both drivers r and t are turned on. driver r pulls the r side to near 0 v, and driver t is on, but is overridden by the external i 2 c driver. if driver t is already on, due to a low on the r side, driver r just turns on. when the t side is released by the external i 2 c driver, driver t is still on, so the t side is only able to rise to the v ol of driver t. driver r turns off, since v ol is above its 0.4-v v il threshold, releasing the r side. if no external i 2 c driver is keeping the r side low, the r side rises, and driver t turns off once the r side rises above 1.5 v, see figure 19 . figure 19. waveform of turning driver t off it is important that any external i 2 c driver on the t side is able to pull the bus below 0.4 v to ensure full operation. if the t side cannot be pulled below 0.4 v, driver r may not recognize and transmit the low value to the r side. the i2cen pin is active high with an internal pull-up to v cc . it can be used to isolate a badly behaved slave during power up. it should never change state during an i 2 c operation because disabling during a bus operation may hang the bus and enabling part way through a bus cycle could confuse the i 2 c parts being enabled. the typical application of the TMDS141 is as a repeater in a tv connecting the hdmi input connector and an internal hdmi rx through flat cables. the i 2 c repeater is 5-v tolerant, and no additional circuitry is required to translate between 3.3-v to 5-v bus voltages. in the following example, the system master is running on an r-side i 2 c-bus while the slave is connected to a t-side bus. both buses run at 100 khz supporting standard-mode i 2 c operation. master devices can be placed on either bus. 16 submit documentation feedback www.ti.com rsclrsda tscl tsda i2cen ovs r t tscl/tsda rscl/rsda vcc 0.5v 5v + 10% vcc/2 t plh
TMDS141 slls737b ? june 2006 ? revised april 2007 application information (continued) figure 20. typical application figure 21 illustrates the waveforms seen on the r-side i 2 c-bus when the master writes to the slave through the i 2 c repeater circuit of the TMDS141. this looks like a normal i 2 c transmission, and the turn on and turn off of the acknowledge signals are slightly delayed. figure 21. bus r waveform figure 22 illustrates the waveforms seen on the t-side i 2 c-bus under the same operation in figure 21 . on the t-side of the i 2 c repeater, the clock and data lines would have a positive offset from ground equal to the v ol of the driver t. after the 8th clock pulse, the data line is pulled to the v ol of the slave device which is very close to ground in this example. at the end of the acknowledge, the slave device releases and the bus level rises back to the v ol set by the driver until the r-side rises above v cc /2, after which it continues to high. it is important to note that any arbitration or clock stretching events require that the low level on the t-side bus at the input of the TMDS141 i 2 c repeater is below 0.4 v to be recognized by the device and then transmitted to the r-side i 2 c bus. figure 22. bus t waveform the i 2 c circuitry inside the TMDS141 allows multiple stage operation as shown in figure 23 . i 2 c-bus slave devices can be connected to any of the bus segments. the number of devices that can be connected in series is limited by repeater delay/time of flight considerations for the maximum bus speed requirements. 17 submit documentation feedback www.ti.com master slave driver r driver t v rdd r rup c cable c source c i c o c slave v tdd r tup c medium rscl rsda 9th clock pulse - acknowledge from slave tscl tsda 9th clock pulse - acknowledge from slave v ol of slave v ol of driver t
i 2 c pull-up resistors (1) (2) (3) TMDS141 slls737b ? june 2006 ? revised april 2007 application information (continued) figure 23. typical series application the pull-up resistor value is determined by two requirements: 1. the maximum sink current of the i 2 c buffer: the maximum sink current is 3 ma or slightly higher for an i 2 c driver supporting standard-mode i 2 c operation. 2. the maximum transition time on the bus: the maximum transition time, t, of an i 2 c bus is set by an rc time constant, where r is the pull-up resistor value, and c is the total load capacitance. the parameter, k, can be calculated from equation 3 by solving for t, the times at which certain voltage thresholds are reached. different input threshold combinations introduce different values of t. table 1 summarizes the possible values of k under different threshold combinations. table 1. value k upon different input threshold voltages v th- \v th+ 0.7v dd 0.65v dd 0.6v dd 0.55v dd 0.5v dd 0.45v dd 0.4v dd 0.35v dd 0.3v dd 0.1v dd 1.0986 0.9445 0.8109 0.6931 0.5878 0.4925 0.4055 0.3254 0.2513 0.15v dd 1.0415 0.8873 0.7538 0.6360 0.5306 0.4353 0.3483 0.2683 0.1942 0.2v dd 0.9808 0.8267 0.6931 0.5754 0.4700 0.3747 0.2877 0.2076 0.1335 0.25v dd 0.9163 0.7621 0.6286 0.5108 0.4055 0.3102 0.2231 0.1431 0.0690 0.3v dd 0.8473 0.6931 0.5596 0.4418 0.3365 0.2412 0.1542 0.0741 - from equation 1, r up(min) = 5.5v/3ma = 1.83 k w to operate the bus under a 5-v pull-up voltage and provide less than 3 ma when the i 2 c device is driving the bus to a low state. if a higher sink current, for example 4 ma, is allowed, r up(min) can be as low as 1.375 k w . given a 5-v i 2 c device with input low and high threshold voltages at 0.3 v dd and 0.7 v dd , the valued of k is 0.8473 from table 1 . taking into account the 1.83-k w pull-up resistor, the maximum total load capacitance is c (total-5v) = 645 pf. c cable(max) should be restricted to be less than 545 pf if c source and c i can be as heavy as 50 pf. here the c i is treated as c sink , the load capacitance of a sink device. fixing the maximum transition time from table 1 , t = 1 m s, and using the k values from table 1 , the recommended maximum total resistance of the pull-up resistors on an i 2 c bus can be calculated for different system setups. to support the maximum load capacitance specified in the hdmi spec, c cable(max) = 700pf/c source = 50pf/c i = 50pf, r (max) can be calculated as shown in table 2 . 18 submit documentation feedback www.ti.com t k rc v(t) v dd (1 e t rc ) tsda tscl TMDS141 rsda rscl en tsdatscl TMDS141 rsda rscl en sda scl bus master sda scl bus slave tsdatscl TMDS141 rsdarscl en 3.3v 3.3v 3.3v source sink repeater rup source rup 2 rup 1 c 1 c 2 c 3 c 3 c 1 5v 5v c 2 5v rup sink c 2 5v rup sink c 2 rup source r up(min) v dd lsink
thermal dissipation TMDS141 slls737b ? june 2006 ? revised april 2007 table 2. pull-up resistor upon different threshold voltages and 800-pf loads v th- \v th+ 0.7v dd 0.65v dd 0.6v dd 0.55v dd 0.5v dd 0.45v dd 0.4v dd 0.35v dd 0.3v dd unit 0.1v dd 1.14 1.32 1.54 1.80 2.13 2.54 3.08 3.84 4.97 k w 0.15v dd 1.20 1.41 1.66 1.97 2.36 2.87 3.59 4.66 6.44 k w 0.2v dd 1.27 1.51 1.80 2.17 2.66 3.34 4.35 6.02 9.36 k w 0.25v dd 1.36 1.64 1.99 2.45 3.08 4.03 5.60 8.74 18.12 k w 0.3v dd 1.48 1.80 2.23 2.83 3.72 5.18 8.11 16.87 - k w or, limiting the maximum load capacitance of each cable to be 400 pf to accommodate with i 2 c spec version 2.1. c cable(max) = 400pf/c source =50pf/c i = 50pf, the maximum values of r (max) are calculated as shown in table 3 . table 3. pull-up resistor upon different threshold voltages and 500-pf loads v th- \v th+ 0.7v dd 0.65v dd 0.6v dd 0.55v dd 0.5v dd 0.45v dd 0.4v dd 0.35v dd 0.3v dd unit 0.1v dd 1.82 2.12 2.47 2.89 3.40 4.06 4.93 6.15 7.96 k w 0.15v dd 1.92 2.25 2.65 3.14 3.77 4.59 5.74 7.46 10.30 k w 0.2v dd 2.04 2.42 2.89 3.48 4.26 5.34 6.95 9.63 14.98 k w 0.25v dd 2.18 2.62 3.18 3.92 4.93 6.45 8.96 13.98 28.99 k w 0.3v dd 2.36 2.89 3.57 4.53 5.94 8.29 12.97 26.99 - k w obviously, to accommodate the 3-ma drive current specification, a narrower threshold voltage range is required to support a maximum 800-pf load capacitance for a standard-mode i 2 c bus. when the input low and high level threshold voltages, v th- and v th+ , are 0.7 v and 1.9 v, which is 0.15 v dd and 0.4 v dd approximately with v dd = 5 v, from table 2 , the maximum pull-up resistor is 3.59 k w . the allowable pull-up resistor is in the range of 1.83 k w and 3.59 k w . on a high-k board ? it is always recommended to solder the powerpad onto the thermal land. a thermal land is the area of solder-tinned-copper underneath the powerpad package. on a high-k board the TMDS141 can operate over the full temperature range by soldering the powerpad onto the thermal land without vias. on a low-k board ? in order for the device to operate across the temperature range on a low-k board, a 1-oz cu trace connecting the gnd pins to the thermal land must be used. a simulation shows r q ja = 100.84 c/w allowing 545 mw power dissipation at 70 c ambient temperature. a general pcb design guide for powerpad packages is provided in the document slma002 - powerpad thermally enhanced package. 19 submit documentation feedback www.ti.com
package option addendum packaging information 11-august-2006 TMDS141 slls737b ? june 2006 ? revised april 2007 orderable device package package pins package lead/ball finish status (1) eco plan (2) msl peak temp (3) type drawing qty TMDS141rhar active qfn rha 40 2500 green (rohs & cu nipdau level-3-260c-168 hr no sb/ br) TMDS141rharg4 active qfn rha 40 2500 green (rohs & cu nipdau level-3-260c-168 hr no sb/ br) 1. the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. 2. eco plan -the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) -please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) 3. msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. 20 submit documentation feedback www.ti.com
TMDS141 slls737b ? june 2006 ? revised april 2007 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from a revision (august 2006) to b revision ............................................................................................... page changed features ................................................................................................................................................................ 1 changed signaling rate from 1.65 gbps to 2.25 gbps ........................................................................................................ 5 added pre = low to supply current test conditions ............................................................................................................ 6 added pre = low to power dissipation test conditions ....................................................................................................... 6 deleted ttl high- and low-level output voltages ................................................................................................................. 7 changed peak-to-peak output jitter from tx0 - tx2, residual jitter from 90 to 88 ps .......................................................... 7 added peak-to-peak output jitter from txc, residual jitter ................................................................................................... 7 added peak-to-peak output jitter from tx0 - tx2, residual jitter .......................................................................................... 7 changed figure 10 ............................................................................................................................................................ 13 changed figure 11 ............................................................................................................................................................ 13 changed figure 12 ............................................................................................................................................................ 13 changed figure 13 ............................................................................................................................................................ 13 changed figure 14 ............................................................................................................................................................ 14 21 submit documentation feedback www.ti.com
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TMDS141rhar active qfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr TMDS141rharg4 active qfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 14-apr-2007 addendum-page 1
tape and reel information package materials information www.ti.com 17-may-2007 pack materials-page 1
device package pins site reel diameter (mm) reel width (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TMDS141rhar rha 40 mla 330 16 6.3 6.3 1.5 12 16 pkgorn t2tr-ms p tape and reel box information device package pins site length (mm) width (mm) height (mm) TMDS141rhar rha 40 mla 346.0 346.0 33.0 package materials information www.ti.com 17-may-2007 pack materials-page 2

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com telephony www.ti.com/telephony low power www.ti.com/lpw video & imaging www.ti.com/video wireless wireless www.ti.com/wireless mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2007, texas instruments incorporated

▲Up To Search▲

Price & Availability of TMDS141

	To Download TMDS141 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .