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ICS9P935 idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ddr i/ddr ii phase lock loop zero delay buffer datasheet 1 fb_in sclk sdata clk_int clk_inc control logic fb_out ddrt0 ddrc0 ddrt1 ddrc1 ddrt2 ddrc2 ddrt3 ddrc3 ddrt4 ddrc4 ddrt5 ddrc5 pll description output features ddr i/ddr ii zero delay clock buffer ? low skew, low jitter pll clock driver max frequency supported = 400mhz (ddrii 800) i 2 c for functional and output control feedback pins for input to output synchronization spread spectrum tolerant inputs programmable skew through smbus frequency defect control thorugh smbus individual output control programmable through smbus funtional block diagram key specifications cycle - cycle jitter: <100ps output - output skew: <100ps duty cycle: 48% - 52% 28-pin ssop package available in rohs compliant packaging operates @ 2.5v or 1.8v pin configuration ddrc0 1 28 gnd ddrt0 2 27 ddrc5 vdd2.5/1.8 3 26 ddrt5 ddrt1 4 25 vdd2.5/1.8 ddrc1 5 24 gnd gnd 6 23 ddrc4 vdda2.5/1.8 7 22 ddrt4 gnd 8 21 vdd2.5/1.8 clk_int 9 20 sdata clk_inc 10 19 sclk vdd2.5/1.8 11 18 fb_in ddrt2 12 17 fb_out ddrc2 13 16 ddrt3 gnd 14 15 ddrc3 28-ssop/tssop ICS9P935
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 2 pin description pin# pin name type pin description 1 ddrc0 out "complementary" clock of differential pair output. 2 ddrt0 out "true" clock of differential pair output. 3 vdd2.5/1.8 pwr power supply, nominal 2.5v or 1.8v 4 ddrt1 out "true" clock of differential pair output. 5 ddrc1 out "complementary" clock of differential pair output. 6 gnd pwr ground pin. 7 vdda2.5/1.8 pwr output power supply, nominal 2.5v or 1.8v 8 gnd pwr ground pin. 9 clk_int in "true" reference clock input. 10 clk_inc in "complementary" reference clock input. 11 vdd2.5/1.8 pwr power supply, nominal 2.5v or 1.8v 12 ddrt2 out "true" clock of differential pair output. 13 ddrc2 out "complementary" clock of differential pair output. 14 gnd pwr ground pin. 15 ddrc3 out "complementary" clock of differential pair output. 16 ddrt3 out "true" clock of differential pair output. 17 fb_out out feedback output, dedicated for external feedback. 18 fb_in in single-ended feedback input, provides feedback signal to internal pll to eliminate phase error with the input clock. 19 sclk in clock pin of smbus circuitry, 3.3v tolerant. 20 sdata i/o data pin for smbus circuitry, 3.3v tolerant. 21 vdd2.5/1.8 pwr power supply, nominal 2.5v or 1.8v 22 ddrt4 out "true" clock of differential pair output. 23 ddrc4 out "complementary" clock of differential pair output. 24 gnd pwr ground pin. 25 vdd2.5/1.8 pwr power supply, nominal 2.5v or 1.8v 26 ddrt5 out "true" clock of differential pair output. 27 ddrc5 out "complementary" clock of differential pair output. 28 gnd pwr ground pin.
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 3 absolute max supply voltage -0.5v to 2.7v logic inputs gnd ?0.5 v to v dd +0.5 v ambient operating temperature 0c to +70c case temperature 115c storage temperature ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage avdd, vdd = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 250 a input low current i il v i = v dd or gnd 10 a output disabled low current i odl oe = l, v odl = 100mv 100 a i dd1.8 c l = 0pf @ 100mhz 300 ma i ddld c l = 0pf 500 a input clamp voltage v ik v ddq = 1.8v iin = -18ma -1.2 v i oh = -100a v dd -0.2 v i oh = -9ma 1.1 v i ol =100a 0.1 v i ol =9ma 0.6 v input capacitance 1 c in v i = gnd or v dd 23pf output capacitance 1 c out v out = gnd or v dd 23pf operating supply current high-level output voltage v oh low-level output voltage v ol
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 4 notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vtr is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v dd and is the voltage at which the differential signal must be crossing. recommended operating condition ( see note1 ) t a = 0 - 70c; supply voltage avdd, vdd = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v ddq , a vd d 1.7 1.8 1.9 v low level input voltage v il clk_int, clk_inc, fb_in 0.35 x v d d v high level input voltage v ih clk_int, clk_inc, fb_in 0.65 x v dd v dc input signal voltage (note 2) v in -0.3 v dd + 0.3 v dc input si g nal volta g e swin g v in-diff clk_int, clk_inc gnd - 0.3 1.5 v d d + 0.3 v dc - clk_int, clk_inc, fb_in 0.3 v dd + 0.4 v ac - clk_int, clk_inc, fb_in 0.6 v dd + 0.4 v output differential cross-voltage (note 4) v ox v dd / 2 - 0.1 v dd / 2 + 0.1 v input differential cross-voltage (note 4) v ix v dd /2 - 0.15 v dd /2 v dd / 2 + 0.15 v high level output current i oh -9 ma low level output current i ol 9ma high impedance output current i oz v dd =1.9v, v out =v dd or gnd 10 ma operating free-air temperature t a 070c differential input signal voltage (note 3) v id
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 5 notes: 1. refers to transition on noninverting output in pll bypass mode. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle=t wh /t c , were the cycle (t c ) decreases as the frequency goes up. 3. switching characteristics guaranteed for application frequency range. 4. static phase offset shifted by design. timing requirements t a = 0 - 70c supply voltage avdd, vdd = 1.8 v +/- 0.1v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 1.8v+ 0.1v @ 25c 125 500 mhz application frequency range freq app 1.8v+ 0.1v @ 25c 160 400 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 15 s switching characteristics 1 parameter symbol condition min typ max units output enable time t en oe to any output 8 ns output disable time t dis oe to any output 8 ns period jitter t j it (p er ) -40 40 ps half-period jitter t j it ( h p er ) -75 75 ps input clock 1 2.5 4 v/ns output enable (oe), (os) 0.5 v/ns output clock slew rate slr1 ( o ) 1.5 2.5 3 v/ns t j it ( cc+ ) 040ps t j it ( cc- ) 0 -40 ps dynamic phase offset t ( ) d y n -50 50 ps phase error t (p hase error ) 2 -50 0 50 ps output to output skew t skew 40 ps ssc modulation frequency 30.00 33 khz ssc clock input frequency deviation 0.00 -0.50 % cycle-to-cycle period jitter input slew rate slr1(i)
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 6 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage a vdd , v dd = 2.5v 0.2v parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 5 a input low current i il v i = v dd or gnd 5 a i dd2. 5 c l = 0pf @ 200mhz 250 ma i ddpd c l = 0pf 100 a output high current i oh v dd = 2.3v, v ou t = 1v -18 -32 ma output low current i ol v dd = 2.3v, v out = 1.2v 26 35 ma high impedance out p ut current i oz v dd =2.7v, vout=v dd or gnd 10 ma input clamp voltage v ik v ddq = 2.3v iin = -18ma -1.2 v v dd = min to max, i oh = -1 ma v ddq - 0.1 v v ddq = 2.3v, i oh = -12 ma 1.7 v v dd = min to max i ol =1 ma 0.1 v v ddq = 2.3v i oh =12 ma 0.6 v input capacitance 1 c in v i = gnd or v dd 3pf output capacitance 1 c out v out = gnd or v dd 3pf operating supply current high-level output voltage v oh low-level output voltage v ol
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 7 recommended operating condition (see note 1) notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vt is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v dd and is the voltage at which the differential signal must be crossing. t a = 0 - 70c; supply voltage avdd, vdd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v dd , a vdd 2.3 2.5 2.7 v ddrt,ddrc 0.4 v dd /2 - 0.18 v ddrt,ddrc v dd /2 + 0.18 2.1 v dc input signal voltage (note 2) v in -0.3 v dd + 0.3 v dc - ddrt 0.36 v dd + 0.6 v ac - ddrt 0.7 v dd + 0.6 v output differential cross - volta g e (note 4) v ox v dd /2 - 0.15 v dd /2 + 0.15 v input differential cross- volta g e (note 4) v ix v dd /2 - 0.2 v dd /2 v dd /2 + 0.2 v high level output current i oh -30 ma low level output current i ol -30 ma operating free-air temperature t a 085c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 8 timing requirements switching characteristics 3 notes: 1. refers to transition on noninverting output in pll bypass mode. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle=t wh /t c , were the cycle (t c ) decreases as the frequency goes up. 3. switching characteristics guaranteed for application frequency range. 4. static phase offset shifted by design. t a = 0 - =70c; supply voltage a vdd , v dd = 2.5 v +/- 0.2v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 2.5v+ 0.2v @ 25 o c 45 600 mhz application frequency range freq app 2.5v+ 0.2v @ 25 o c 95 233 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 15 s parameter symbol condition min typ max units low-to high level propagation delay time t plh 1 buf_in to any output 3.5 ns high-to low level propagation delay time t pll 1 buf_in to any output 3.5 ns period jitter t j it (p er ) 100mhz to 200mhz -30 30 ps half-period jitter t(jit_hper) 100mhz to 200mhz -100 100 ps input clock slew rate t sl ( i ) 14v/ns output clock slew rate t sl ( o ) 12v/ns cycle to cycle jitter 1 t c y c -t c y c 100mhz to 200mhz -50 50 ps static phase offset t ( static p hase offset ) 4 -50 0 50 ps output to output skew t skew 40 ps
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 9 1. the idt clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support smbus block read protocol. 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferr ed. the command code and byte count shown above must be sent, the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. notes: general i 2 c serial interface information for the ICS9P935 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d4 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d4 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d5 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address d4 (h) beginning byte = n write start bit controller (host) tstart bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d5 (h) index block read operation slave address d4 (h) beginning byte = n ack ack
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 10 table 1: 7-steps skew programming table 7 step 11 10 01 00 lsb 11 600 ps 500 ps 400 ps 300 ps 10 n/a n/a n/a 200 ps 01 n/a n/a n/a 100 ps 00 n/a n/a n/a 0.0 ps msb table 2: 7-steps skew programming table 7 step 11 10 01 00 lsb 11 -600 ps -500 ps -400 ps -300 ps 10 n/a n/a n/a -200 ps 01 n/a n/a n/a -100 ps 00 n/a n/a n/a 0.0 ps msb i 2 c table: output control register pin # name control function type 0 1 pwd bit 7 freq detect low frequency detect pll off control rw off on 1 bit 6 fb_in/out fb_out control rw disable enable 1 bit 5 ddr_t5/c5 output control rw disable enable 1 bit 4 ddr_t4/c4 output control rw disable enable 1 bit 3 ddr_t3/c3 output control rw disable enable 1 bit 2 ddr_t2/c2 output control rw disable enable 1 bit 1 ddr_t1/c1 output control rw disable enable 1 bit 0 ddr_t0/c0 output control rw disable enable 1 i 2 c table: group skew control register b y te 8 pin # name control function t yp e0 1pwd bit 7 - ddr skw3 rw 0 bit 6 - ddr skw2 rw 0 bit 5 - ddr skw1 rw 0 bit 4 - ddr skw0 rw 0 bit 3 - ddr skw3 rw 0 bit 2 - ddr skw2 rw 0 bit 1 - ddr skw1 rw 0 bit 0 - ddr skw0 rw 0 i 2 c table: revision id and vendor id register b y te 10 pin # name control function t yp e0 1pwd bit 7 - revision_id bit 3 rw - - x bit 6 - revision_id bit 2 rw - - x bit 5 - revision_id bit 1 rw - - x bit 4 - revision_id bit 0 rw - - x bit 3 - vendor_id bit3 rw - - 0 bit 2 - vendor_id bit2 rw -- 0 bit 1 - vendor_id bit1 rw -- 0 bit 0 - vendor_id bit0 rw -- 1 i 2 c table: byte count register byte 15 pin # name control function type 0 1 pwd bit 7 -bc7 rw 0 bit 6 -bc6 rw 0 bit 5 -bc5 rw 0 bit 4 -bc4 rw 0 bit 3 -bc3 rw 1 bit 2 -bc2 rw 1 bit 1 -bc1 rw 1 bit 0 -bc0 rw 1 i2c table: all other i2c registers are reserved see table 2: 7-step skew programming table clkin to ddr skew control byte 6 - - - - byte count programming b(7:0) writing to this register will configure how many bytes will be read back, default is 0f = 15 bytes - - clkin to ddr skew control - - rev id vendor id see table 1: 7-step skew programming table
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 11 ordering information ICS9P935 y flf-t seating plane seating plane a1 a a2 e -c- - c - b .10 (.004) c .10 (.004) c c l index area index area 12 1 2 n d e1 e 209 mil ssop min max min max a -- 2.00 -- .079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 v ariations min max min max 28 9.90 10.50 .390 .413 10-0033 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.65 basic 0.0256 basic reference doc.: jedec publication 95, mo-150 see variations see variations n d mm. d (inch) example: designation for tape and reel packaging rohs compliant (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf- t
idt tm /ics tm ddr i/ddr ii phase lock loop zero delay buffer ICS9P935 rev h 12/1/08 ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 12 ordering information ICS9P935 y glf-t example: designation for tape and reel packaging rohs compliant (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0035 see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol
ICS9P935 ddr i/ddr ii phase lock loop zero delay buffer 13 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # a 2/8/2007 final release. - b 6/4/2007 fixed various typos. - c 6/14/2007 added tssop ordering information. 12 d 6/20/2007 1. updated output features: max frequency supported. 2. updated ddri/ddrii max clock frequency. 1 5, 8 e 8/16/2007 1. updated supply voltage. 2. updated input high/low current max. 3 f 9/5/2007 updated electrical specifications. 3-5 g 11/19/2007 updated serial interface information. 9 h 12/1/2008 updated pin description. 2

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