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1/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. power management switch ics for pcs and digital consumer products power switch ic for expresscard tm BD4154FV description BD4154FV is a power management switch ic for the next generation pc card (expresscard tm ) developed by the pcmcia. it conforms to the pcmcia expresscard tm standard, expresscard tm compliance checklist, and expresscard tm implementation guideline, and obtains the compliance id ?ec100040? from pcmcia . the power switch offers a number of functions - card detector, and system status detector - which are ideally suited for laptop and desktop computers. features 1) incorporates three low on-resistance fets for expresscard tm . 2) incorporates an fet for output discharge. 3) incorporates an enabler. 4) incorporates under voltage lockout (uvlo) protection. 5) employs an ssop-b20 package. 6) built-in thermal shutdown protector (tsd). 7) built-in soft start function. 8) incorporates an over current protection (ocp). 9) built-in enable signal for pll 10) built-in pull up resistance for detecting expresscard tm 11) conforms to the expresscard tm standard. 12) conforms to the expresscard tm compliance checklist. 13) conforms to the expresscard tm implementation guideline. applications laptop and desktop computer s, and other expresscard tm equipped digital devices. product lineup parameter BD4154FV package ssop-b20 ?expresscard tm ? is a registered trademark registered of the pcmcia (per sonal computer memory card international association). no.10029ebt09
BD4154FV technical note 2/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. absolute maximum ratings parameter symbol limit unit input voltage v3aux_in, v3_in, v15_in -0.3 5.0 *1 v logic input voltage 1 en,cppe#,cpusb#,sysr, perst_in#,rclken -0.3 v3aux_in+0.3 *1 v logic output voltage 1 rclken -0.3 v3aux_in+0.3 *1 v logic output voltage 2 perst# -0.3 v3aux_in+0.3 v output voltage v3aux,v3, v15 -0.3 5.0 * 1 v output current 1 iov3aux 1.0 a output current 2 iov3 2.0 a output current 3 iov15 2.0 a power dissipation 1 pd1 500.0 *2 mw power dissipation 2 pd2 812.5 *3 mw operating temperature range topr -40 +100 storage temperature range tstg -55 +150 maximum junction temperature tjmax +150 *1 not to exceed pd. *2 reduced by 4.0mw for each increase in ta of 1 over 25 *3 reduced by 6.5mw for each increase in ta of 1 over 25 (when mounted on a board 70m mx70mmx1.6mm glass-epoxy pcb) operating conditions (ta=25 ) parameter symbol min max unit input voltage 1 v3aux_in 3.0 3.6 v input voltage 2 v3_in 3.0 3.6 v input voltage 3 v15_in 1.35 1.65 v logic input voltage 1 en -0.3 3.6 v logic input voltage 2 cppe#,cpusb#,sysr, perst_in#,rclken 0 v3aux_in v logic output voltage 1 rclken 0 v3aux_in v logic output voltage 2 perst# 0 v3aux_in v output current 1 iov3aux 0 275 ma output current 2 iov3 0 1.3 a output current 3 iov15 0 650 ma * this product is not designed to offer protection against radioactive rays.
BD4154FV technical note 3/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. electrical characteristics (unless otherwise noted, ta=25 ven=3.3v v3aux_in =v3_in=3.3v,v15_in=1.5v) parameter symbol standard value unit condition min typ max standby current ist - 40 80 a ven=0v (include ien, irclken) bias current 1 icc1 - 120 250 a vsysr=0v bias current 2 icc2 - 250 500 a vsysr=3.3v [enable] high level enable input voltage venhi 2.0 - 5.5 v low level enable input voltage venlow -0.2 - 0.8 v enable pin input current ien 10 - 30 a ven=0v [logic] high level logic input voltage vlhi 2.0 - - v low level logic input voltage vllow - - 0.8 v logic pin input current icppe# - 0 1 a cppe#=3.6v 10 - 30 a cppe#=0v icpusb# - 0 1 a cpusb#=3.6v 10 - 30 a cpusb#=0v isysr - 0 1 a sysr=3.6v 10 - 30 a sysr=0v iprt_in# - 0 1 a perst_in#=3.6v 10 - 30 a perst_in#=0v irclken - 0 1 a rclken=3.6v 10 - 30 a rclken=0v rclken low voltage vrclken - 0.1 0.3 v irclken=0.5ma rclken leak current irclken - - 1 a vrclken=3.65v [switch v3aux] on resistance r v3aux - 120 220 m ? tj=-10 100 * discharge on resistance r v3aux dis - 60 150 ? [switch v3] on resistance r v3 - 42 90 m ? tj=-10 100 * discharge on resistance r v3 dis - 60 150 ? [switch v15] on resistance r v15 - 45 90 m ? tj=-10 100 * discharge on resistance r v15 dis - 60 150 ? [over current protection] v3 over current ocp v3 1.3 - - a v3aux over current ocp v3aux 0.275 - - a v15 over current ocp v15 0.65 - - a [under voltage lockout] v3_in uvlo off voltage vuvlo v3_in 2.70 2.80 2.90 v sweep up v3_in hysteresis voltage Svuvlo v3_in 50 100 150 mv sweep down v3aux_in uvlo off voltage vuvlo v3aux_in 2.70 2.80 2.90 v sweep up v3aux_in hysteresis voltage S vuvlo v3aux_in 50 100 150 mv sweep down v15_in uvlo off voltage vuvlo v15_in 1.15 1.20 1.25 v sweep up v15_in hysteresis voltage Svuvlo v15_in 50 100 150 mv sweep down [power good] v3 power good voltage pg v3 2.700 2.850 3.000 v v3aux power good voltage pg v3aux 2.700 2.850 3.000 v v15 power good voltage pg v15 1.200 1.275 1.350 v perst# low voltage vperst# low - 0.1 0.3 v i perst =0.5ma perst# high voltage vperst# high 3.0 - - v perst# delay time t perst# 4 - 20 ms perst# assertion time tast - - 500 ns [output rise time] v3_in to v3 t v3 0.1 - 3 ms v3aux_in to v3aux t v3aux 0.1 - 3 ms v15_in to v15 t v15 0.1 - 3 ms * design target
BD4154FV technical note 4/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. reference data fig.5 wakeup wave form (card assert) fig.6 wakeup wave form (usb2.0 assert) fig.7 wakeup wave form (shut down active) fig.1 card assert/ de-assert (active) fig.2 card assert/de-assert (standby) fig.4 system active ? standby ( no card ) fig.3 system active ? standby ( card present) fig.8 wakeup wave form (standby active) fig.10 power down wave form (usb2.0 de-assert) fig.9 power down wave form (card de-assert) fig.11 power down wave form (active shut down) fig.12 power down wave form (active standby) cppe#(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) sysr(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) en(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) r v3 =3.3 r v3aux =13.2 r v15 =3 cppe#(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) cppe#(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) sysr(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) cppe#(2v/div) v3(2v/div) v15(1v/div) v3aux(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) sysr(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) cpusb#(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) sysr(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) cpusb#(2v/div) en(2v/div) 500 s/div 500s/div 500s/div 5.0ms/div 5.0ms/div 5.0ms/div 500 s/div 500 s/div 500 s/div 5.0ms/div 5.0ms/div 500s/div
BD4154FV technical note 5/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. fig.17 perst# wave form (perst_in# input) fig.18 rclken wave form (perst_in# input) fig.19 output voltage (v3_in:off on) fig.20 output voltage (v3aux_in:off on) fig.14 rclken wave form (card assert/ de-assert) fig.15 perst# wave form (usb2.0 assert/ de-assert) fig.16 rclken wave form (usb2.0 assert/ de-assert) fig.22 output voltage (v3_in:on off) fig.21 output voltage (v15_in:off on) fig.13 perst# wave form (card assert/ de-assert) v3(2v/div) v3aux(2v/div) perst#(2v/div) cppe#(2v/div) v3(2v/div) v3aux(2v/div) perst#(2v/div) cppe#(2v/div) v3(2v/div) v3aux(2v/div) rclken(2v/div) cppe#(2v/div) cpusb#(2v/div) v3aux(2v/div) v3(2v/div) v3aux(2v/div) perst#(2v/div) v3(2v/div) v3aux(2v/div) rclken(2v/div) v3(2v/div) rclken(2v/div) perst_in#(2v/div) perst_in#(2v/div) v3(2v/div) v15_in(2v/div) v3(2v/div) v3aux(2v/div) v3_in(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) v15(1v/div) v3aux_in(2v/di v3aux(2v/div) v15(1v/div) v3(2v/div) r v3 =3.3 r v3aux =13.2 r v15 =3 v3_in(2v/div) v3aux(2v/div) v15(1v/div) r v3 =3.3 r v3aux =13.2 r v15 =3 v3aux_in(2v/di v3(2v/div) v3aux(2v/div) v15(1v/div) r v3 =3.3 r v3aux =13.2 r v15 =3 v15_in(2v/div) v3(2v/div) v3aux(2v/div) v15(1v/div) fig.23 output voltage (v3aux_in:on off) fig.24 output voltage (v15_in:on off) 5.0ms/div 5.0ms/div 500 s/div 1.0ms/div 1.0ms/div 500 s/div 5.0ms/div 5.0ms/div 500 s/div 500 s/div 500 s/div 500 s/div
BD4154FV technical note 6/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. block diagram pin configration pin function pin no pin name pin function 1 perst_in# perst# control input pin (sysreset#) 2 en enable input pin 3 sysr logic input pin 4 v3_in1 v3 input pin 1 5 v3_in2 v3 input pin 2 6 v3_1 v3 output pin 1 7 v3_2 v3 output pin 2 8 perst# logic output pin 9 test test pin 10 gnd gnd pin 11 cpusb# logic input pin 12 cppe# logic input pin 13 v15_1 v15 output pin 1 14 v15_2 v15 output pin 2 15 v15_in1 v15 input pin 1 16 v15_in2 v15 input pin 2 17 v3aux v3aux output pin 18 v3aux_in v3aux input pin 1 19 rclken reference clock enable signal/ power good signal (no delay) 20 nc non connection 3.3v aux/275ma 1.5v/625ma v3_in1 sysr v3_in v3aux_in uvlo cppe# cpusb# v15_in1 v15-2 input logic reference block v3aux_in v15_in vd v3_in,v3aux_in,v15_in v3,v3aux,v15 3.3v/1.30a pump charge protection thermal tsd en vd vd v3-2 v3aux vd 3.3v tsd,cl,uvlo v3-1 power good tsd,cl,uvlo tsd,cl,uvlo_aux cl v3_in2 v15_in2 v15-1 rclken en,sysr,cpusb#,cppe# 1.5v uvlo_aux 3.3v perst# v3aux_in v3aux_in perst_in# 4 5 18 16 12 11 3 2 gnd 10 1 8 19 17 7 6 under voltage lock out 15 14 ssop-b20 package 1 2 3 4 5 6 7 8 9 10 perst_in# en sysr v3_in1 v3_in2 v3_1 v3_2 perst# test gnd cpusb# cppe# v15_1 v15_2 v15_in1 v15_in2 v3aux v3aux_in rclken nc 20 19 18 17 16 15 14 13 12 11
BD4154FV technical note 7/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. description of block operation en with an input of 2.0 volts or higher, this terminal goes high to activate the circuit, and goes low to deactivate the circuit (with the standby circuit current of 40 a), it discharges each output and lowers output voltage when the input falls to 0.8 volts or less. v3_in, v15_in, and v3aux_in these are the input terminals for each channel of a 3ch switch. v3 _ in and v15 _ in terminals have two pins each, which should be short-circuited on the pc board with a thick co nductor. a large current runs through these three terminals : (v3 _ in: 1.35a; v3aux _ in: 0.275 a; and v15 _ in: 0.625 a). in order to lower the output impedance of the connected power supply, it is recommended that ceramic capacitors (with b-type characteristics or better) be provided between these terminals and the ground. specifically, the capacitors should be on the order of 1 f between v3 _ in and gnd, and between v15 _ in and gnd; and on the order of 0.1 f between v3aux _ in and gnd. v3, v15, and v3aux these are the output terminals for each switch. the v3 and v15 terminals have two pins each, which should be short-circuited on the pc board and connected to an expresscard connector with a thick conductor, as short as possible. in order to stabilize the output, it is recommended that ceramic capacitors (with b-type characteristics or better) be provided between these terminals and the gro und. specifically, the capacitors should be on the order of 10 f between v3 and gnd, and between v15 and gnd; and on the order of 1 f between v3aux and gnd. cppe# this pin is used to find whether or not a pci-express signal comp atible card is present. turns to ?high? level with an input of 2.0 volts or higher, which means that no card is provided, while it turns to ?low? level when the input is lowered to 0.8 vo lts or less, which means that a card is prov ided. controls the on/off, switch sele cting the proper mode based on the status of the system. pull up resistance (100k ? 200k ) is built into, so the number of components is reduced. cpusb# this pin is used to find whether or not a usb2.0 signal compatib le card is present. turns to ?high? level with an input of 2.0 volts or higher, which means that no card is provided, while it turns to ?low? level when the input is lowered to 0.8 volts or less, which means that a card is provid ed. controls the on/off switch, select ing the proper mode based on the system status. pull up resistance (100k ? 200k ) is built into, so the number of components is reduced. sysr this pin is used to detect the system stat us. turns to ?high? level with an input of 2.0 volts or higher, which means that the system is activated, while it turns to ?low? level when the inpu t is lowered to 0.8 volts or less, which means that the system is on standby. perst_in# t his pin is used to control the reset signal (perst#) to a ca rd from the system side. (also referred to as ?sysreset#? by pcmcia.) turns to ?high? level with an input of 2.0 volts or higher, and sets perst# to ?high? and with a ?power good? output. turns to ?low? level and sets perst# to ?l ow? when the input falls to 0.8 volts or less. perst# this pin is used to send a reset signal to a pci-express comp atible card. reset status is determined by the outputs, perst_in#, cppe# system status, and en on/off status. turns to ?high? level and activates the pci-express compatible card only if each output is within the ?power good? threshold, with the card inserted and perst_in# turned to ?high? level. rclken this pin is used to send an enable signal to the reference clock. activation status is determined by the outputs, cppe# system status, and en on/off status. turns to ?high? level and activates the reference clock pll only if each output is within the ?power good? threshold, with the card kept inserted. test this pin is used to test, which should be short-circuited to th e gnd. when it is short-circuited to v3aux_in, uvlo (v3_in, v15_in) turns off.
BD4154FV technical note 8/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. timing chart power on/off status of expresscard tm system status expresscard tm module status power switch status primary auxiliary primary(+3.3v and +1.5v) auxiliary(3.3v aux) off off don?t care off off on on de-asserted off off asserted on on on on de-asserted off off asserted before this off on asserted after this off off expresscard tm states transition diagram system status card status stand-by status :sysr=l card asserted status :cp#=l on status :sysr=h card de-asserted status :cp#=h from on to stand-by status :sysr=h l from de-asserted to asserted status :cp#=hl from stand-by to on status :sysr=l h from asserted to de-a sserted status :cp#=l h v3aux=off v15=v3=off cp#=h ?l ? sysr=l h cp#=l h sysr=h l sysr=h ?l cp#=h sysr=l cp#=l sysr=l cp#=h sysr=h cp#=l sysr=h cp#=l sysr=l h cp#=h l sysr=h cp#=l sysr=h l cp#=l sysr=l cp#=l h v3aux=on v15=v3=on v3aux=on v15=v3=off
BD4154FV technical note 9/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. BD4154FV evaluation board BD4154FV evaluation board application components part no value company part name r1 0 ? rohm mcr03series r2 0 ? rohm mcr03series r3 0 ? rohm mcr03series r11 0 ? rohm mcr03series r12 0 ? rohm mcr03series c1 - - - c2 - - - c3 - - - c4 1 f murata gmr21 series c6 10 f murata gmr21 series c11 - - - c12 - - - c13 10 f murata gmr21 series c15 1 f murata gmr21 series c17 1 f murata gmr21 series c18 0.1 f murata gmr18 series perst_in# en sysr v3_in1 v3_in2 v3_1 v3_2 perst# test gnd rclken v3aux_in1 v3aux v15_in2 v15_in1 v15_2 v15_1 cppe# cpusb# BD4154FV 1 2 3 4 5 6 7 8 9 10 r1 r2 r3 c1 gnd c2 gnd c4 gnd c6 c3 gnd gnd v3_in(s) v3(s) gnd sw1 sw2 sw3 sw7 perst_in# gnd gnd gnd en sysr v3_in v3 perst # v3aux_in 19 18 17 16 15 14 13 12 11 ssop-b20 c18 gnd c17 gnd c15 gnd c12 gnd c11 gnd c13 gnd v3aux_in v3aux_in v3aux v15_in v15 rclken sw4 gnd v3aux_in(s) v3aux(s) v15_in(s) v15(s) r12 r11 cppe# cpusb# sw5 gnd sw6 gnd u1 20
BD4154FV technical note 10/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. BD4154FV evaluation board layout silk screen top layer bottom layer mid layer 1 mid layer 2
BD4154FV technical note 11/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. application circuit (circuit for expresscard tm compliance checklist) heat loss thermal design should allow the device to operate within the follo wing conditions. note that the temperatures listed are the allowed temperature limits. thermal design should allow sufficient margin from these limits. 1. ambient temperature ta c an be no higher than 100c. 2. chip junction temperature tj can be no higher more than 150c. chip junction temperature tj can be determined as follows: chip junction temperature tj is calculated from ic su rface temperature tc under actual application conditions: tj=tc+ j-cxw reference value j-c:ssop-b20 35/w chip junction temperature tj is ca lculated from ambient temperature ta: tj=tc+ j-axw reference value j-a:ssop-b20 250 /w (ic only) 153.8 /w single-layer substrate (substrate surface copper foil area: less than 3%) most of heat loss in the BD4154FV occurs at the output switch. the power lost is determined by multiplying the on-resistance by the square of output current of each switch. cppe#(12pin) cpusb#(11pin) v3(6,7pin) v3aux(17pin) v15(13,14pin) perst#(8pin) rclken(19pin) v3_in(4,5pin) v3aux_in(18pin) v15_in(15,16pin) perst_in#(1pin) en(2pin) sysr(3pin) cppe#(1) cpusb#(2) 3.3v(3) 3.3vaux(4) 1.5v(5) perst#(6) 3.3v(7) 3.3vaux(8) 1.5v(9) sysreset#(10) BD4154FV gnd(10pin)
BD4154FV technical note 12/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. equivalent circuit 1pin 2pi n 3pin 4,5pin 6,7pin 8pin 9pin 11pin 12pin 13,14pin 15,16pin< v15_in1,v15_in2> 17pin 18pin 19pin v3aux_in v3aux_in v3 v3_in v3aux_in v3_in v15 v3aux_in v3aux v3aux_in v3aux_in v3aux_in v3aux_in v3aux_in v3aux_in v3aux_in v3aux_in v3aux_in
BD4154FV technical note 13/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. notes for use 1.absolute maximum ratings although quality is rigorously controll ed, the device may be destroyed when applie d voltage, operating temperature, etc. exceeds its absolute maximum rating. because the source (short mode or open mode) cannot be identified once the ic is destroyed, it is important to take physical safety meas ures such as fusing when implementing any special mode that operates in excess of absolute rating limits. 2.thermal design consider allowable loss (pd) under actual operating conditions and provide sufficient margin in the thermal design. 3.terminal-to-terminal short-circuit and mis-mounting when the mounting the ic to a printed circuit board, take utmost care to assure the position and orientation of the ic are corr ect. in the event that the ic is mounted err oneously, it may be destroyed. the ic may also be destroyed when a short-circuit is caused by foreign matter introduced into the clearance between outputs, or between an output and power-gnd. 4.operation in strong el ectromagnetic fields using the ic in strong electromagnetic fields may cause malfunct ions. exercise caution in respect to electromagnetic fields. 5.built-in thermal shutdown protection circuit this ic incorporates a thermal shutdown protection circuit (tsd circuit). the working temperature is 175c (standard value) with a -15c (standard value) hysteresis width. when the ic chip temperature rises the tsd circuit is activated, while the output terminal is brought to the off state. the built-in tsd ci rcuit is intended exclusively to shut down the ic in a thermal runaway event, and is not intended to protect the ic or guarantee performance in these conditions. therefore, do not operate the ic after with the expectation of continued use or subsequent operation once this circuit is activated. 6.capacitor across output and gnd when a large capacitor is connected across the output and gnd, and the v3aux_in is short-circuited with 0v or gnd for any reason, current charged in the capacitor flows into the output and may destroy the ic. therefore, use a capacitor smaller than 1000 f between the output and gnd. 7.set substrate inspection connecting a low-impedance capacitor to a pin when running an inspection with a set substrate may produce stress on the ic. therefore, be certain to discharge electr icity at each process of the operation. to prevent elec trostatic accumulation and discharge in the assembly process, thoroughly ground your self and any equipment that could sustain esd damage, and continue observing esd-prevention procedures in all handling, transfer and storage operation s. before a ttempting to connect the set substrate to the test setup, make certain that the power supply is off. likewise, be sure the power supply is off before removing the subs trate from the test setup. 8.ic terminal input this integrated circuit is a monolithic ic, with p substrate and p + isolation between elements. the p layer and n layer of each element form a, pn junction. when the potential relation is gnd>terminal a>terminal b, the pn junction works as a diode, and when terminal b>gnd termina l a, the pn junction operates as a parasitic transistor. parasitic elements inevitably form, due to the nature of the ic construction. the operation of the parasitic element gives rise to mutual interference between circuits and results in malfunction, and eventually, breakdown. consequently, take utmost care not to use the ic in a way that would cause the parasitic element to ac tively operate, such as applying voltage lower than gnd (p substrate) to the input terminal. 9. gnd wiring pattern if both a small signal gnd and a high current gnd are presen t, it is recommended that the patterns for the high current gnd and the small signal gnd be separated. proper grounding to the reference point of the set should also be provided. in this way, the small signal gnd voltage will by unaffect ed by the change in voltage stemming from the pattern wiring resistance and the high current. also, pay special attentio n to avoid undesirable wiring pattern fluctuations in any externally connected gnd component. pin a p+ p+ n n n p p substrate gnd gnd n p n c b e gnd p+ p+ n n resistor npn transistor structure (npn) pin b parasitic diode gnd pin a c e b gnd nearby other device pin b parasitic diode parasitic diode parasitic diode p substrate
BD4154FV technical note 14/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. 10. electrical characteristics the electrical characteristics in the s pecifications may vary, depending on ambi ent temperature, power supply voltage, circuit(s) externally applied, and/or ot her conditions. therefore, please check all such factors, including transient characteristics, that could affect the electrical characteristics. 11. capacitors applie d to input terminals the capacitors applied to the input terminals (v3_in, v3aux_ in and v15_in) are used to lower the output impedance of the connected power supply. an increase in the output impedance of the power supply may result in destabilization of input voltages (v3_in, v3aux_in and v15_in). it is re commended that a low-esr capacitor be used, with a lower temperature coefficient (change in capacitance vs. change in temperature), recommended capa citors are on the order of 0.1 f for v3aux_in, and1 f for v3_in and v15_in. however, they must be thoroughly checked at the temperature and with the load range expected in act ual use, because capacitor selection depends to a significant degree on the characteristics of the input power supply to be used and the conductor pattern of the pc board. 12. capacitors applied to output terminals capacitors for the output terminals (v3, v3_aux, and v15) , should be connected between ea ch of the output terminals and gnd. a low-esr, low temperature coefficient out put capacitor is recommended-on the order of 1 f for v3 and v15 terminals, and 1 f less for v3_aux. however, they must be thoroughl y checked at the temper ature and with the load range expected in actual use, because capacitor selection depends to a significant degree on the temperature and the load conditions. 13. not of a radiation-resistant design. 14. allowable loss (pd) with respect to the allowable loss, please refer to the therma l derating characteristics shown in the exhibit, which serves as a rule of thumb. when the system design causes the ic to operate in excess of the allo wable loss, chip temperature will rise, reducing the current capacity and decreasing other basic ic functionality. t herefore, design should always enable ic operation within the allowable loss only. 15. operating range basic circuit functions and operations are warranted within t he specified operating range the working ambient temperature range. although reference values for electrical characteri stics are not warranted, no rapid or extraordinary changes in these characteristics are expected, provided operation is within the normal operating and temperature range. 16. the applied circuit example diagrams presented here ar e recommended configurations. however, actual design depends on ic characteristics, which shou ld be confirmed before operation. also, note that modifying external circuits may impact static, noise and other ic characteristics, includin g transient characteristics. be sure to allow sufficient margin in the design to accommodate these factors. 17. wiring to the input terminals (v3 in, v3aux in, and v15 in) and output terminals (v3, v3aux and v15) of the built-in fet should be carried out with special care. using unnecessar ily long and/or thin conductors may decrease output voltage and degrade other characteristics. 18. heatsink the heatsink is connected to the sub, wh ich should be short-circuited to the gnd. proper heatsink soldering to the pc board should enable lower thermal resistance. power dissipation ambient temperature (ta) mounted on board 70mmx70mmx1.6mm glass-epoxy pcb j-a=153.8 /w 0 25 75 100 125 150 50 400 200 0 [ ] 800 1000 600 [mw] 100 812.5mw power dissipation (pd) 500mw without heat sink j-a=250.0 /w
BD4154FV technical note 15/15 www.rohm.com 2010.04 - rev.b ? 2010 rohm co., ltd. all rights reserved. ordering part number b d 4 1 5 4 f v - e 2 part number part number package fv : ssop-b20 packaging and forming specification e2: embossed tape and reel (ssop-b20) (unit : mm) ssop-b20 0.1 11 10 20 1 0.1 0.1 6.4 0.3 4.4 0.2 6.5 0.2 0.15 0.1 0.22 0.1 0.65 1.15 0.1 0.3min. ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin
r1010 a www.rohm.com ? 2010 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redunda ncy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospac e machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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