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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2005, zarlink semiconductor inc. all rights reserved. features ? highly integrated mixer/oscillator pll and if agc amplifier for multi band analog/digital terrestrial tuners and/or cable tuners ? low phase noise pll frequency synthesizer ? agc output level detect with digital controlled top threshold ? >50 db desired/undesired ratio without pre filtering ? separate analog and digital if outputs ? >41 db if agc control range ? power down modes to support power reduction initiatives ? four independent gpo ? 48 pin qfn package applications ? dvb-t receiver systems ? isdb-t receiver systems ? dvb-c cable receiver systems ? terrestrial analog receivers description the zl10060 is a 3 band mopll with if agc amplifier. it down-converts the rf channel to a standard if followed by filtering and if agc amplification for the digital channel. each band consists of a low noise preamplifier/mixer and local oscillator with an external varactor tuned tank circuit. an if level detector is included for control of the rf agc. the take over point and time constant are both programmable. the zl10060 has high signal level handling performance providing exce llent performance in the presence of high level unwanted signals. all chip control is via i 2 c bus. if higher performance is required, an alternative part, zl10063 is available with image reject down conversion. november 2005 ordering information ZL10060LDG1 48 pin qfn* trays zl10060ldf1 48 pin qfn* tape and reel *pb free matte tin -20 c to +85 c zl10060 mopll with if agc amplifier data sheet figure 1 - basic block diagram pll agc det i 2 c control loop filter vco tank circuits band pass filter digital digital lna and tracking filters zl10060 rf input demod analog demod gpo if saw analog if saw i 2 c if agc digital if analog if rf agc tuning
zl10060 data sheet table of contents 2 zarlink semiconductor inc. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 rf converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 saw driver amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 agc detector and adc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 if agc amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 vco. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 pll frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 general purpose switching ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.8 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.0 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 programmable features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 pll registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 control register - byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 control register - byte 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 control register - byte 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.0 applications information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.0 pin circuit information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.0 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.0 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
zl10060 data sheet list of figures 3 zarlink semiconductor inc. figure 1 - basic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3 - detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4 - low band (vhf1) external tank circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5 - mid band (vhf3) external tank circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6 - high band (uhf) external tank circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7 - typical application circuit (dvb-t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8 - crystal oscillator circuit (4 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9 - interstage filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10 - noise figure measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
zl10060 data sheet list of tables 4 zarlink semiconductor inc. table 1 - pin names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2 - programmable features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3 - control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4 - address bit ma1 and ma0 settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5 - byte 2- lo divider (msb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6 - byte 3 lo divider (lsb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7 - byte 4 pll control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8 - charge pump current selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9 - reference divide ratio settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10 - byte 5 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11 - band selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12 - internal circuit block control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 13 - gppo output port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 14 - byte 6 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 15 - agc decay current setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 16 - agc threshold selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 17 - byte 7 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 18 - adc input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 19 - test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 20 - read data format (msb is transmitted first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 21 - agc activity flag settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 22 - adc output values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 23 - optimum cp and lo trim settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
zl10060 data sheet 5 zarlink semiconductor inc. figure 2 - pin diagram pin no. port name function 1 ifagc if amplifier agc input 2 sab saw filter driver output (analog) 3 sa saw filter driver output (analog) 4 adc external adc input 5sda i 2 c bus serial data input/output 6scl i 2 c bus serial clock input 7 add i 2 c bus address selection input 8 agcop agc output 9 cnopb analog converter output 10 cnop analog converter output 11 cont paddle (ground) 12 vccrf rf section supply 13 sipb saw filter driver input 14 sip saw filter driver input 15 gpp0 general purpose switching port 16 gpp1 general purpose switching port table 1 - pin names agcop zl10060 cnop cnopb adc scl sda lhopb lhipb veeosc lmopb lhop lhip lmop veerf gpp2 ipref gpp0 gpp1 sipb sip loip sa ifagc sab vccosc ifip ifipb veeif ifopb ifop xtal vccif sdb vccif sd pump vccdig 1 vccrf cont llopb llop hiipb gpp3 xcap drive hiip midip add vee (package paddle)
zl10060 data sheet 6 zarlink semiconductor inc. 17 gpp2 general purpose switching port 18 veerf rf section ground 19 loip low band input 20 ipref reference input for low and mid bands 21 midip mid band input 22 hiip high band input 23 hiipb high band inverse input 24 gpp3 general purpose switching port 25 llop low band local oscillator output 26 llopb low band local oscillator inverse output 27 lmop mid band local oscillator output 28 lmopb mid band local oscillator inverse output 29 lhip high band local oscillator input 30 lhop high band local oscillator output 31 lhopb high band local oscillator inverse output 32 lhipb high band local o scillator inverse input 33 veeosc oscillator section ground 34 vccosc oscillator supply 35 ifip if amplifier input 36 ifipb if amplifier inverse input 37 drive loop amplifier drive output 38 pump loop amplifier charge pump output 39 vccdig digital section supply 40 sd saw filter driver output (digital) 41 sdb saw filter driver output (digital) 42 vccif if amplifier section supply 43 xcap reference osc illator feedback input 44 xtal reference oscillator crystal drive 45 vccif if amplifier section supply 46 veeif if section ground 47 ifop if amplifier output 48 ifopb if amplifier inverse output paddle vee global ground pin no. port name function table 1 - pin names (continued)
zl10060 data sheet 7 zarlink semiconductor inc. figure 3 - detailed block diagram 1.0 functional description the zl10060 is a three-band rf mixer oscillator with on-board frequency sy nthesizer and if agc amplifier, integrating all tuner active circuitry after the tracking f ilter in a single package. it is intended for use in all band terrestrial tuners, and requires a minimum external co mponent count. it contains all elements required for rf down conversion to a standard if with the exception of external vco tank circuits. in normal application the rf input is interfaced to the selected mixer oscillator preamplifier through the tuner pre- filter and agc stages. the zl10060 provides an rf agc co ntrol signal, which can be used to control the rf gain. the preamplifier output feeds the mixer stage where the required channel is down converted to the if frequency. the local oscillator fr equency for the down conver sion is obtained from the on board pll and local oscillator, with an external varactor tuned tank. the downconverted signal is then passed through an external filter into a saw filter driv er amplifier. this provides two output channels for hybrid ana log and digital applications.
zl10060 data sheet 8 zarlink semiconductor inc. an agc if amplifier is included which provid es an output signal to a digital demodulator. the device is controlled through an i 2 c compatible interface. 1.1 rf converter the zl10060 contains three input stages to cover the vhf1, vhf3 and uhf frequency bands. the inputs would normally be driven by front end amplifiers and tracking fi lters. all three inputs are di fferential, however, the vhf1 and vhf3 inputs would normally be single ended. these inputs therefore can share a common input reference pin. the uhf input should be driven with a differential si gnal. the inputs are all high impedance. the differential converter if output is then passed through an external in terstage filter. this can be tuned for 36 mhz for dvb-t applications but can also be used at 44 mhz and 57 mhz to be compatible with other tv standards. the recommended filter circuit is shown in figure 9. the de sign of this filter provides an impedance transformation as well as rejection of adjacent channels. a 0.5 db cheb ychev filter with 10 mhz bandwidth is recommended. this gives a flat response across the pass band and ta kes into account normal component tolerances. 1.2 saw driver amplifier the output of the interstage filter then passes to the saw f ilter drive amplifier. this pr ovides further amplification and interfaces to the saw filter. two saw filter drive ou tputs are provided for hybrid analog and digital applications. both output stages are identical however the digital outp ut (sd, sdb) should always be used for digital applications as the pin out of the device has been optimized to give the best isolation perfo rmance in this configuration. output selection is programmable however it should be noted that the uns elected output is not powered off but operates at a lower power level which means that a signal will still be present on the output. the differential outputs will drive a balanced saw filter wi th a tuning inductor to resonate with the saw filter input capacitance. the saw filter can also be driven without the tuning inductor but with the addition of 350 ohm resistors to ground on the saw driver outputs to increase the ou tput drive capability. this will increase total current consumption by 14 ma. 1.3 agc detector and adc the zl10060 contains a broadband agc detector circuit whic h provides an output to provide gain control for the rf frontend gain stages. the detector inpu t signal is derived from the signal level in the saw driver amplifier. the composite signal at this point is the wanted signal plus adjacent channels (n +/- 1, n +/- 2, n +/- 3). the agc detector threshold point at which the agc output becomes active can be programmed to one of eight levels via the i 2 c interface. when the composite level reaches the agc th reshold, the agc output pin will be active. the agc attack current is fixed, however, the decay current can be programmed to two levels. the agc output can only drive a high impedance e.g., a dual gate fet. if rf gain co ntrol uses a pin diode then a simple buffer circuit will be required. an agc flag output is also available through the i 2 c interface. this indicates when the agc output is active i.e., less than 4 volts. the agc output level can also be monitored by an on chip 3 bit adc. although the adc is 3 bits, only 5 levels are available. alternativ ely the adc can be programmed to measure the voltage on an external pin (adc pin 4). 1.4 if agc amplifier the agc amplifier amplifies the output of the saw filter for the digital channel and prov ides a differential output to the demodulator. the analog gain control signal is normally derived from the demodulator. at least 41 db of gain control is provided. the agc amplifier can be powered down independently of the re st of the device if not r equired. this mode could be used in analog applications to reduce overall power consumption.
zl10060 data sheet 9 zarlink semiconductor inc. 1.5 vco separate vco?s are provided for each band. the oscillator circui ts are on chip howeve r the tank circuitry is external. all three oscillators are differen tial. the typical external tank circuits are shown in figures 4, 5 and 6. it is essential to take care to minimize track lengths and parasitics when designing the pcb layout to obtain best performance. the close-in phase noise of the local os cillator can be optimized at the programmed operating frequency by a programming bit which increases bias current in the vco. . figure 4 - low band (vhf1) external tank circuit figure 5 - mid band (vhf3) external tank circuit llopb llop vva r r_bias r_bias cs pf l1 nh lmopb lmop vvar r_bias r_bias cs pf l1 nh
zl10060 data sheet 10 zarlink semiconductor inc. figure 6 - high band (uhf) external tank circuit 1.6 pll frequency synthesizer the pll frequency synthesizer section contains all the el ements necessary, with the exception of a frequency reference and loop filter to control a varicap tuned local oscillator, to form a complete pll frequency synthesized source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noi se performance. it can be operated with comparison frequencies appropriate for frequency offsets as re quired in digital terrestrial (dtt) receivers. the lo input signal from the selected o scillator section is routed to an internal preamplif ier, which provides gain and reverse isolation from the divider signals. the output of the preamplifie r interfaces directly to the 15-bit programmable divider, which is of mn+a architecture, with a 16/17 dual modulus prescaler. the a counter is 4-bits, and the m counter is 11 bits. the output of the programm able divider is fed to the phase comparat or where it is compared in both phase and frequency domain with the comparison frequency which is derived either from the on-board crystal controlled oscillator, or from an external reference source. in bo th cases the reference frequency is divided down to the comparison frequency by the reference divider, which is programmable into 1 of 16 ratios. the output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external loop filter, integrates the curren t pulses into the varactor control voltage. the programmable divider output, f pd , divided by two and the re ference divider output, f comp , can be switched to port p0 by programming the device into a test mode. the pll includes a lock detect circuit. the lock detect out put is available by reading the status byte on the i 2 c interface 1.7 general purpose switching ports the zl10060 has four output switching ports. three of these ports (gpp[3:1]) incorporate a 10 kohm pull up resistor. the remaining port (gpp0) is an open collector switch. these ports can be used for switching external rf input stages for example. ports gpp[1:0] can also be used as test outputs for debug purposes. 1.8 i 2 c interface the zl10060 is controlled by an i 2 c data bus and is compatible with both 3.3 v and 5 v control levels. data and clock are fed in on the sda and sc l lines respectively as defined by i 2 c bus format. the device can either accept data (write mo de), or send data (read mode). the lsb of t he address byte (r/w) sets the device into write mode if it is low, and read mode if it is high. the device can be programmed to respond to 1 of 4 addresses, lhipb lhopb lhop lhip vva r r_bias r_bias cs pf l1 nh cp r_damp cp cp cp
zl10060 data sheet 11 zarlink semiconductor inc. which enables the use of more than one device in an i 2 c bus system. the address is selected by applying a voltage to the ?add? input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes ar e received. when the devic e is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this peri od, the device generates an internal stop condition, whic h inhibits further reading. 2.0 programming the zl10060 is fully programmable through the i 2 c interface. the device can also output data to the controller. 2.1 programmable features 2.2 register map there are a total of 7 write registers, the first of which is the address register. the control registers are described in detail in the following section. the m sb of each register is written first. after reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0 ' indicating byte 2, and a logic '1' indicating byte 4. having feature description rf programmable divider programs pll main divider reference programmable divider programs pll reference divider to set required frequency step band selection selects rf input and appropriate lo oscillator. agc threshold sets the input power level threshold at which the agc detector starts to generate a control level. agc decay sets the agc decay current. charge pump current selects one of t he four charge pump current settings. if amplifier function the if amplifier can be enabled independently of other circuit blocks. sawf output select select the analog or digital saw driver output. ports gpp[3:1] these are configured as npn buf fers with 10 kohm pull-up resistors to v cc . logic ?1? = on logic ?0? = off; default on power up port gpp0 this is configured as a np n open collector buffer. logic ?1? = on logic ?0? = off; default on power up vco trim adjusts the vco bias current to provide optimum phase noise performance. adc input select select either the internal agc detec t output level or the external level applied to the adc input pin. programmable power the zl10060 has various power saving modes. test modes test modes to monitor and control internal pll signals. table 2 - programmable features
zl10060 data sheet 12 zarlink semiconductor inc. interpreted this byte as either byte 2 or 4 the following dat a byte will be interpreted as byte 3 or 5 respectively. byte 5 will be followed by byte 6 or a stop condition. byte 6 wi ll be followed by byte 7 or a stop condition. byte 7 will be followed by a stop condition or a byte 2 or byte 4 as described above. further da ta bytes can be programmed following the above-described protocol . a stop condition can be generated after any data byte, if however it occurs during a byte transmission, the pr evious byte data is retained. to fa cilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a stop condition. msb lsb ack 76543210 address 11000ma1ma00a byte 1 programmable divider 0 d14 d13 d12 d11 d10 d9 d8 a byte 2w programmable divider d7 d6 d5 d4 d3 d2 d1 d0 a byte 3w control data 1 c1c0r4r3r2r1r0 a byte 4w control data bs1 bs0 sl1 sl0 p3 p2 p1 p0 a byte 5w control data lo1 lo0 atc ife x at2 at1 at0 a byte 6w control data sasxagdadst3t2t1t0 a byte 7w table 3 - control registers a acknowledge bit ma1, ma0 address bits d14-d0 programmable divisi on ratio control bits r4-r0 reference division ratio select c1, c0 charge pump current select bs1-bs0 band select bits sl1-sl0 power down modes sas sawf drive output select p3-p0 p3-p0 port output states ads adc input select atc agc decay current agd agc disable at2:at0 agc onset threshold control lo1:lo0 lo trim control bits t3-t0 test mode control bits ife if agc amplifier enable x don?t care
zl10060 data sheet 13 zarlink semiconductor inc. details of the programming registers are shown in the following sections. default values on power up are also shown. 2.3 address register the zl10060 address (ma1, ma0) are determined by the volt age set at the address pin (a dd) as shown in table 4. 2.4 pll registers bytes 2,3 and 4 are used to program the pll. the lo frequency will not be updated until both byte 1 and byte 2 have been programmed. the charge pump current values are selected from the following table: address select (byte 1) ma1 ma0 address input voltage level 0 0 0 - 0.1vcc (connect to v ee ) 0 1 0.2v cc ? 0.3v cc (open circuit) 10 0.4 v cc ? 0.6 v cc (30k ? to v cc ) 110.9 v cc - 1.0 v cc (connect to v cc ) table 4 - address bit ma1 and ma0 settings bit field name default description 7 - 0 must be set to 0 6:0 d[14:8] 0 msb bits of lo divider register. table 5 - byte 2- lo divider (msb) bit field name default description 7:0 d[7:0] 0 lsb bits of lo divider register. table 6 - byte 3 lo divider (lsb) bit field name default description 7 - 1 must be set to 1 6:5 c[1:0] 0 charge pump current. 4:0 r[4:0] 10011 referenc e divider control. table 7 - byte 4 pll control c1 c0 current a 0 0 +-155 table 8 - charge pump current selection
zl10060 data sheet 14 zarlink semiconductor inc. the reference divider ratio can be selected from the following table: 0 1 +-330 1 0 +-690 1 1 +-1450 default state on power up = 00 r4 r3 r2 r1 r0 ratio 0001116 0010032 0010164 00110128 0101120 0110040 0110180 01110160 1001124 1010048 1010196 10110192 1101128 1110056 11101112 11110224 default state on power up = 10011 table 9 - reference divide ratio settings c1 c0 current a table 8 - charge pump current selection
zl10060 data sheet 15 zarlink semiconductor inc. 2.5 control register - byte 5 the band switching is controlled as shown below: the various power-up modes are shown below. the if agc amplifier is controlled separately the i 2 c interface and crystal oscillator circuit is active in all modes . the zl10060 has four output ports. port s [3:1] have an internal 10 kohm pull up resistor to vcc. gpp0 is open collector. bit field name default description 7:6 bs[1:0] 11 band switching 5:4 sl[1:0] 01 power-up modes 3:0 p[3:0] 0 general purpose output ports table 10 - byte 5 control bs1 bs0 band selected 0 0 lo band 0 1 mid band 1 0 hi band 1 1 all off default state on power up = 11 table 11 - band selection power mode section status sl1 sl0 i 2 c interface and registers crystal oscillator pll & vco converter and if stages 0 x sleep enabled enabled disabled disabled 1 0 pll and vco enabled enabled enabled enabled disabled 1 1 full enabled enabled enabled enabled table 12 - internal circuit block control function bit 0 1 gpp0 output enable p0 off (high impedance) on (current sink) gpp1 output enable p1 off on (current sink) gpp2 output enable p2 off on (current sink) gpp3 output enable p3 off on (current sink) table 13 - gppo output port control
zl10060 data sheet 16 zarlink semiconductor inc. 2.6 control register - byte 6 the vco bias trim adjusts the vco bias to give optimum cl ose-in phase noise. in general this should be set to 1 for the lower third of the vco frequency range. the agc attack curr ent is fixed at 100 a however the agc decay current ca n be programmed to one of two values as shown below. if the pll is unlocked (fl = 0), then the atc control is over-ridden and the agc decay current is set to 10 a. when the pll locks (fl = 1) the decay current reverts to the programmed atc value. bit field name default description 7lo10vco bias trim 6 lo0 0 not used 5 atc 0 agc decay current select 4 ife 0 if agc amplifier enable (1 = on) 3 x 0 not used 2:0 at[2:0] 0 agc threshold select table 14 - byte 6 control atc agc decay current ( a) 010.0 10.3 table 15 - agc decay current setting
zl10060 data sheet 17 zarlink semiconductor inc. the agc threshold can be programmed using the at[2 :0] bits. note that the programmed value is db v peak. 2.7 control register - byte 7 the adc input selection is shown in the table below the test bits t[3:0] allow internal pll signals to be monitored and also to manually control charge pump current and agc detector output. this facilities may be useful during debug. the te st bit selection is shown below. the reserved test modes should not be used. at2 at1 at0 agc threshold (peak signal in db v into detector) 000 120 001 118 010 116 011 114 100 112 101 110 110 107 111 104 default state on power up = 000 table 16 - agc threshold selection bit field name default description 7 sas 1 digital saw drive output select (1 = digital) 6 x 0 not used 5 agd 1 agc detector enable (0 = enabled) 4 ads 0 adc input select 3:0 t[3:0] 0 test bits table 17 - byte 7 control ads adc function 0 agc output 1 external adc input table 18 - adc input selection t3 t2 t1 t0 test mode description 0 0 0 0 normal operation 0 0 0 1 reserved test mode 0010agc sink, force i agc = -100 a 0 0 1 1 agc source, force i agc = 10 a p0 = output of agc bias dac table 19 - test modes
zl10060 data sheet 18 zarlink semiconductor inc. 2.8 read mode when the device is in read mode, t he status byte read from the device takes the form shown in table 20. the following describes data read through the read byte; ? bit 7 (por) is the power-on reset indicator, and this is set to a logic '1' if the v cc supply to the device has dropped below 3 v (at 25 c), e.g., when the device is initially turned on. the por is reset to '0' when the read sequence is terminated by a stop command. when por is set high this indicates that the programmed information may have been corrupted and the device reset to power up condition. ? bit 6 (f l ) is the pll lock flag and indicates whether the device is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked. the fl bit is set after 64 consecutive comparison cycles in lock. 0 1 0 0 reserved test mode 0 1 0 1 reserved test mode 0 1 1 0 reserved test mode 0 1 1 1 reserved test mode 1 0 0 0 reserved test mode 1 0 0 1 charge pump sink * status byte fl set to logic ?0? 1 0 1 0 charge pump source * status byte fl set to logic ?0? 1 0 1 1 charge pump disabled * status byte fl set to logic ?1? 1100port p0 = f pd /2 1 1 0 1 charge pump sink * status byte fl set to logic ?0? port p0 = f comp 1 1 1 0 charge pump source * status byte fl set to logic ?0? port p0 = f comp 1 1 1 1 charge pump disabled * status byte fl set to logic ?1? port p0 = f comp msb lsb ack 76543210 address 11000ma1ma01a byte 1 status byte por fl 1 1 agf v2 v1 v0 a byte 2r table 20 - read data format (msb is transmitted first) t3 t2 t1 t0 test mode description table 19 - test modes (continued)
zl10060 data sheet 19 zarlink semiconductor inc. ? bit 3 (agf) is the agc detector flag and indicate s whether the agc detector is active. ? bits 2:0 (v2:v0) contain the adc output data. the adc output is sampled on the ack clock of the read address byte. agf agc activity flag 0 agc active, v agc < 4 v external rf lna gain is reduced 1 agc not active, v agc >4 v external rf lna gain is at maximum table 21 - agc activity flag settings input level (v) v2 v1 v0 < 0.32 vcc 000 0.32vcc to 0.48vcc 0 0 1 0.48vcc to 0.64vcc 0 1 0 0.64vcc to 0.80vcc 0 1 1 > 0.80vcc 100 table 22 - adc output values
zl10060 data sheet 20 zarlink semiconductor inc. 3.0 applications information a typical applications circuit is shown in the following diagram. figure 7 - typical application circuit (dvb-t) c14 2p2f c13 2p2f c12 2p2f c11 2p2f l6 2n5h (air) c16 27pf r6 3k3 c17a 10nf c20 220pf r7 10k gnd r8 20k +30v r9 1k c21 8.2nf gnd +5v +5v l4 12n5h (air ) d2 bb640 c10 68pf l2 100nh (air ) c2 100pf d1 bb640 r1 1k r4 3k3 r5 1k c3 100pf c4 18pf c5 1nf c6 18pf c7 1nf c8 1nf r3 1k gnd gnd c30 10nf c32 100pf c33 10nf c34 10nf c35 10nf +30v + c56 10uf +5v c22 10nf c23 10nf r2 3k3 gnd gnd d3 bb555 gnd gnd gnd rf i n ( uhf) rf i n ( v hf 3 ) rf i n ( v hf 1 ) gnd l9 680nf gnd +5v c38 12pf l10 680nh c25 12pf c39 12pf in+ 2 in- 1 op + 4 gnd 3 op- 5 sf1 x6874d gnd c37 10nf l13 1.5uh c24 1nf c26 1nf c27 1nf gnd r13 0r pll loop f ilt er c15 10nf l11 680nf gnd gnd c40 100pf tp3 tp gnd + c36 2u2f gnd c51 10nf gnd c46 100nf c47 100pf +5v gnd lhip 29 lhop 30 lhopb 31 lhipb 32 vccosc 34 vccif 45 ifop 47 ifopb 48 ifagc 1 vccifo 42 vccrf 12 vccdig 39 continuity 11 dri ve 37 pump 38 sda 5 xcap 43 xtal 44 gpp0 15 scl 6 hi ipb 23 sab 2 sd 40 adc 4 if in 35 gpp3 24 agcout 8 add 7 veeif 46 sdb 41 cnop 10 cnopb 9 veerf 18 loip 19 mi di p 21 rfinb 20 hi ip 22 llop 25 llopb 26 veeosc 33 gnd 0 gpp1 16 sa 3 gpp2 17 ifinb 36 sipb 13 sip 14 lmop 27 lmopb 28 zl1006x ic1 zl10060 c48 12pf c49 10nf r15 6r8 r14 6r8 c50 10nf c19 47pf c18 150pf gnd x1 4.000mhz +5v c1 10nf c28 27pf gnd gnd gnd x3 nm x5 nm x7 0r gnd gnd x2 nm x4 nm x6 0r gnd 1 2 3 4 ifagc adc ifagc c53 10nf gnd r26 nm r27 nm gnd coil dat a l2: 100nh as 8.5 turns 24 swg (0.56mm) en cu on 2.5mm di a l4: 12.5nh as 30mm 24 swg en cu formed into 2.5 turns on 2mm dia l6: 2n5h as 16mm 24 swg en cu formed into 5/4 turns on 2mm di a space wound close wound space wound tr1 bcw33 c54 100pf gnd +5v 1 2 3 4 6 r16 18k scl sda i2c agc out gpp3 gpp2 gpp1 gpp0 interstage filter if output to digit al demod ulat or an alo g saw driver out put
zl10060 data sheet 21 zarlink semiconductor inc. the low (vhf1) and mid (vhf3) bands are single ended how ever the high band (uhf) s hould be differential. all if signals are differential. it is essential to have good rf layout around the rf sta ges, i.e., rf inputs and the vc os. track lengths around the vco?s should be minimized to reduce track inductance. the layout should be organized to give good isolation bet ween the if signal paths. in particular good isolation is required between the outputs and inputs of the if agc amplifier. isolation across the saw filter is also important to ensure rejection of unwanted adjacent signals. this can be achieved by r outing input and output tracks on opposite sides of the board. it is also important to have good is olation between the high leve l if signal and the crys tal oscillator circuit to minimize any interactions. care should be taken when loca ting if tuning inductors to en sure there is no radiation to other parts of the circuit. the crystal oscillator can also provide a clock signal to the demodulator. this can be done by taking the oscillator signal from the crystal series capacitor (27 pf) as shown in the following diagram. figure 8 - crystal oscillator circuit (4 mhz)
zl10060 data sheet 22 zarlink semiconductor inc. the interstage filter between the converter outputs provi des some rejection of adjacent channels (n +/- 2).the recommended values are shown in figure 9. the choice of compone nts is important not only to give a flat response but also to provide an impedance transformation. the specified noise figure for the low and mid bands assumes t hat there will be a network be fore the device to provide image rejection. in a tuner this would be part of the inpu t tracking filters but for test purposes a network is shown in figure 10. figure 9 - interstage filter cnopb cnop sipb sip l1 l1 cc cc l2 c1 c1 rterm rterm sawf drive amplifier input c2 r source r source vcc c1 type if 0.5 db bw component values mhz mhz r source r term l1 l2 c1 cc c2 0.5 db chebycheff 36 12 700 350 560 560 18 12 8.2
zl10060 data sheet 23 zarlink semiconductor inc. the optimum charge pump and lo trim settings for the appli cation circuit shown in figure 8 are shown in the table below. these give the optimum phase noise performanc e for the circuit shown. the changes in charge pump current compensate for frequency and vco gain variations. figure 10 - noise figure measurement conditions frequency range charge pump setting cp lo trim lo1 vhf1 50 -110 mhz 01 1 vhf1 100 -160 mhz 10 1 vhf3 160 - 250 mhz 10 1 vhf3 250 - 350 mhz 01 0 vhf3 350 - 450 mhz 10 0 uhf 450 - 500 mhz 00 1 uhf 500 - 700 mhz 01 1 uhf 700 - 800 mhz 10 1 uhf 800 - 850 mhz 11 1 table 23 - optimum cp and lo trim settings 50 c1 l1 c2 ipref midip/loip gnd 1nf 1nf dut v s band frequency c1 l1 c2 lo rf in mhz mhz pf nh pf low 90 46 20 299 20 low 200 156 8 65 8 mid 240 196 8 41 8 mid 500 446 2.1 21 4
zl10060 data sheet 24 zarlink semiconductor inc. 4.0 pin circuit information pin no. pin name port sense function schematic 1 ifagc input if agc control 2, 3 sab, sa output, output saw filter driver output a inverse saw filter driver output a 4 adc input adc input 5 sda bi-directional i 2 c bus serial data input/output 6 scl input i 2 c bus serial clock input v re f 3k 3k ifagc 50 vcc sa sa b v cc a dc vcc sda vcc sda vcc scl
zl10060 data sheet 25 zarlink semiconductor inc. 7 add input i 2 c address select 8 agcop output agc output 9, 10 cnopb, cnop output, output converter output inverse converter output 11 cont - paddle - 12 vccrf supply rf section supply - 13, 14 sipb sip input, input saw filter driver input inverse, saw filter driver input 15 gpp0 output switching port/test output 1 pin no. pin name port sense function schematic vcc a dd 3k 63k 21k vcc agco p 100 1k vcc cnopb cnop 500 500 sip 250 1.1k vcc sipb gpp0
zl10060 data sheet 26 zarlink semiconductor inc. 16 gpp1 output switching port/test output 2 17 gpp2 output switching port as gpp1 (pin16) 18 veerf supply rf section ground - 19, 20, 21 loip ipref midip input, input, input low band input, mid- and low-band i/p reference, mid-band input 22, 23 hiip, hiipb input, input hi-band input, hi-band input inverse 24 gpp3 output switching port as gpp1 (pin16) 25, 26 llop, llopb output low band oscillator output, low-band oscillator output inverse 27, 28 lmop, lmopb output, output mid-band oscillator output, mid-band oscillator output inverse pin no. pin name port sense function schematic gpp1 gpp 2 gpp 3 10k vcc ipre f loip midip hiipb hiip llop llop b lmop lmopb
zl10060 data sheet 27 zarlink semiconductor inc. 29, 30, 31, 32 lhip, lhop, lhopb, lhipb input, output, output, input high band osc illator input, high-band oscillator output, high-band oscillator output inverse, high-band oscillato r input inverse 33 veeosc supply lo ground - 34 vccosc supply lo supply - 35, 36 ifip, ifipb input, input if agc amp input, if agc amp input inverse 37, 38 drive, pump output, output loop amplifier drive output, loop amp charge pump output 39 vccdig supply digital section supply - 40, 41 sd, sdb output, output saw filter driver output d, saw filter driver o/p d inverse 42 vccif supply sawf output supply - 43 xcap input reference osc feedback input 44 xtal output reference osc crystal drive see xcap (pin 43) pin no. pin name port sense function schematic vcc lhip lhipb 350 350 lhopb lhop ifip b ifip pump 340 vcc drive 50 vcc sd sd b 0.2 m a 110 xtal xca p vcc
zl10060 data sheet 28 zarlink semiconductor inc. 45 vccif supply if agc supply - 46 veeif supply if agc ground - 47, 48 ifop, ifopb output, output if agc amp output, if agc amp inverse output paddle vee - - - pin no. pin name port sense function schematic if o p vcc
zl10060 data sheet 29 zarlink semiconductor inc. 5.0 absolute maximum ratings all voltages are referred to v ee at 0 v. 6.0 operating range all voltages are referred to v ee at 0 v. characteristic min. max. units conditions supply voltage -0.3 6 v rf input voltage 117 db v transient condition only maximum voltage on sda, scl 5.5 v v cc = 0 to 5.5v max voltage on all remaining signal pins -0.3 v cc +0.3 v the voltage on any pin must not exceed 6 v to t a l p o r t c u r r e n t 2 0 m a storage temperature -55 150 o c junction temperature 125 o c power applied package thermal resistance (chip to ambient) 27 o c/w package paddle soldered to ground esd protection 2.0 kv all pins except 9,10 mil-std 883b method 3015 cat1 1.25 kv pins 9, 10 only characteristic min. max. units. conditions supply voltage 4.5 5.5 v functional operation, specification not guaranteed supply voltage 4.75 5.25 v full specification ambient temperature -20 85 o c low band input frequency 50 170 mhz mid band input frequency 140 460 mhz high band input frequency 400 900 mhz
zl10060 data sheet 30 zarlink semiconductor inc. 7.0 electrical characteristics test conditions (unless otherwise stated). t = 25 o c, v ee = 0 v, v cc = 5 v, if frequency = 36 mhz. all signals are differential with the exception of vhf1 and vhf3 inputs. characteristic min. typ. max. units conditions supply current normal operation 117 140 ma total current ? uhf band all switching ports off all sections active 110 134 ma total current - vhf bands all switching ports off all sections active except agc if amplifier 92 ma uhf band. switching ports off 85 ma vhf bands. switching ports off sleep mode 9 ma crystal oscillator and data interface enabled 33 ma pll and crystal oscillator enabled composite system to saw filter driver outputs vhf1 band conversion gain 29 32 35 db rfin = 54 mhz. single ended input conversion gain 29 32 35 db rfin = 155 mhz. single ended input noise figure 9 11 db rs = 50 ?, ssb with input matching network. see figure 10. opip3 135 146 db v two output tones at 110 db v output level causing 1% cross modulation 113 120 db vnote 2 output level causing 1.5 khz fm 113 120 db vnote 3 i 2 c bus transmission induced lo frequency modulation 2.5 khz transmission repetition rate of 20 msec minimum with no change to previously loaded data, at 100 khz scl rate n+5 direct modulation of vco -40 dbc local oscillator sidebands induced by an input carrier at 80 db v offset from local oscillator by 100 khz supply ripple spurious -40 dbc residual fm induced on local oscillator by 20 mv p-p ripple on v cc at 500 khz local oscillator leakage to any band input 30 db v
zl10060 data sheet 31 zarlink semiconductor inc. ipip2 134 143 db v two input tones at 87 db v at 90 mhz and 66 mhz with local oscillator at 114 mhz ipip3 112 120 db v desired = 54 mhz at 45 db v undesired = 60 and 72 mhz at 87 db v ipip3 112 119 db v desired = 155 mhz at 45 db v undesired = 161 and 173 mhz at 87 db v p1db 93 106 db v output impedance 100 ? 10 nh phase noise, ssb pll loop bandwidth ~ 3 khz f comp = 166.7 khz 1 khz -90 -70 dbc/hz 10 khz -95 -86 dbc/hz 100 khz -115 -106 dbc/hz 10 mhz -135 dbc/hz noise floor reference spurs -90 -50 dbc phase noise, ssb narrow pll loop bandwidth f comp = 62.5 khz 10 khz -97 dbc/hz 100 khz -115 dbc/hz composite system to saw filter driver outputs vhf3 band conversion gain 29 32 35 db rfin = 164 mhz single ended input conversion gain 29 32 35 db rfin = 442 mhz single ended input noise figure 9 11 db rs = 50 ?, ssb with input matching network. see figure 10. opip3 135 146 db v two output tones at 110 db v output level causing 1% cross modulation 113 120 db vnote 2 output level causing 1.5 khz fm 113 120 db vnote 3 characteristic min. typ. max. units conditions
zl10060 data sheet 32 zarlink semiconductor inc. i 2 c bus transmission induced lo frequency modulation 2.5 khz transmission repetition rate of 20 msec minimum with no change to previously loaded data, at 100 khz scl rate n+5 direct modulation of vco - -40 dbc local oscillator sidebands induced by an input 750 mhz carrier at 80 db v offset from local oscillator by 100 khz. supply ripple spurious -40 dbc residual fm induced on local oscillator by 20 mv p-p ripple on v cc at 500 khz local oscillator leakage to any band input 30 db v ipip2 134 143 db v two input tones at 89 db v at 198 mhz and 398 mhz with local oscillator at 240 mhz ipip3 112 122 db v desired = 165 mhz at 45 db v undesired = 171 and 183 mhz at 89 db v ipip3 112 119 db v desired = 438 mhz at 45 db v undesired = 444 and 456 mhz at 89 db v p1db -95 107 db v output impedance 100 ? 10 nh phase noise, ssb pll loop bandwidth ~ 3 khz f comp = 166.7 khz 1 khz -87 -70 dbc/hz 10 khz -92 -86 dbc/hz 100 khz -114 -106 dbc/hz 10 mhz -135 dbc/hz noise floor reference spurs -90 -50 dbc phase noise, ssb narrow pll loop bandwidth f comp = 62.5 khz 10 khz -94 dbc/hz 100 khz -114 dbc/hz composite system to saw filter driver outputs uhf band conversion gain 35 38 41 db rfin = 450 mhz characteristic min. typ. max. units conditions
zl10060 data sheet 33 zarlink semiconductor inc. conversion gain 35 38 41 db rfin = 866 mhz noise figure 6 8 db rs = 50 ?, no image correction opip3 135 146 db v two output tones at 110 db v output level causing 1% cross modulation 113 120 db vnote 2 output level causing 1.5 khz fm 113 120 db vnote 3 i 2 c bus transmission induced lo frequency modulation 2.5 khz transmission repetition rate of 20 msec minimum with no change to previously loaded data, at 100 khz scl rate n+5 direct modulation of vco -30 dbc local oscillator sidebands induced by an input 750 mhz carrier at 80 db v offset from local oscillator by 100 khz supply ripple spurious -40 dbc residual fm induced on local oscillator by 20 mv p-p ripple on v cc at 500 khz local oscillator leakage to any band input 60 db v ipip2 125 159 db v two input tones at 89 db v at 198 mhz and 398 mhz with local oscillator at 240 mhz ipip3 108 115 db v desired = 438 mhz at 45 db v undesired = 444 and 456 mhz at 85 db v ipip3 108 112 db v desired = 858 mhz at 45 db v undesired = 864 and 876 mhz at 85 db v p1db 91 99 db v output impedance 100 ? 10 nh phase noise, ssb pll loop bandwidth ~ 3 khz f comp = 166.7 khz 1 khz -78 -70 dbc/hz 10 khz -89 -84 dbc/hz 100 khz -113 -106 dbc/hz 10 mhz -135 dbc/hz noise floor reference spurs -80 -50 dbc characteristic min. typ. max. units conditions
zl10060 data sheet 34 zarlink semiconductor inc. phase noise, ssb narrow pll loop bandwidth f comp = 62.5 khz 10 khz -91 dbc/hz 100 khz -113 dbc/hz agc detector and adc operating frequency range 16 72 mhz agc threshold level 120 db v at[2:0] = 0 adc leakage current 60 na v adc = 4.0 v -60 na v adc = 0.5v agc source current 6.8 10 13.3 a see table 15 0.25 0.33 0.43 a agc sink current -65 -100 -145 a agc attack current, triggered by detected level exceeding agc attack point agc sink current 90% rise and fall time 1 sec agc input level response 1 db change in input level for agc sink current to change from high impedance to 90% of maximum value, with agc operative agcop output impedance 20 m ? agc inactive agcop output voltage range 0.5 v minimum gain required 4 v maximum gain required external agc voltage 0.5 v cc -0.4 v maximum external voltage range which can be applied to agcop when disabled agcop leakage current -50 50 n a over normal operating range adc step size, lsb 0.16v c c v see table 22 adc step size accuracy 0.01v c c v see table 22 agcout_flag high threshold v cc - 0.66 v agf flag set to 1 agcout_flag low threshold v cc - 0.76 agf flag set to 0 characteristic min. typ. max. units conditions
zl10060 data sheet 35 zarlink semiconductor inc. if amplifier supply current 25 ma frequency range 16 72 mhz input impedance 1.5 2 2.8 k ? 1.5 pf gain (voltage conversion gain, differential source to maximum load as defined below) 61 66 70 db v ifagc = 3.0 v 48 57 65 db v ifagc = 2.2 v 21 25 29 db v ifagc = 1.2 v 81722dbv ifagc = 0.5 v noise figure 6.3 8.5 rs=50 ? agc range 41 48 db agc control slope 25 31 38 db/v 1.2 v agc 2.2 agc input current 50 a gain variation within channel 0.25 db channel bandwidth 8 mhz within operating frequency range, with maximum load as defined below opip3 130 141 db v two output tones at 109 db v within output channel gain range = 21 db to maximum output impedance 120 ? maximum load condition 4.7 k ? differential load 15 pf i 2 c bus sda scl input high voltage 2.55 5.5 v input low voltage 0 1.4 v input current high 10 av in =5.5 v, v cc =5.25 v 10 av in =5.5 v, v cc =0 v input current low -10 av in = 0 v, v cc =5.25 v hysteresis 0.4 v sda output voltage 0.4 v i sink =3 ma 0.6 v i sink =6 ma scl clock rate 100 khz characteristic min. typ. max. units conditions
zl10060 data sheet 36 zarlink semiconductor inc. note 1: 0 dbm =107 db v. all input levels are specified as voltage that would be present if input signal generator was terminated in 50 ohms note 2: wanted signal (picture carrier) = 101 dbmv at output. undesired signal (sound carrier) at 5.25 mhz offset modulated with 1 khz 80% am. increase undesired signal to give 1% am on wanted signal. note 3: wanted signal at 101 dbmv. unwanted signal at 5.25 mhz offset modulated with 1 khz 50% am. increase undesired signal to give 1.5 khz fm on wanted signal note 4: current into pump pin with 20 a current from drive pin add (address) select see table 4 input high current 1 ma v in =v ccd input low current -0.5 ma v in =v ee pll synthesizer charge pump output current see table 8 v pump =2 v charge pump output leakage +-3 10 na note 4 charge pump drive output current 0.5 ma v drive =0.7 v crystal frequency 4 16 mhz application as in figure 13 with 4 mhz crystal recommended crystal series esr 25 70 150 ? 4 mhz parallel resonant crystal external reference input frequency 4 20 mhz sine wave coupled through 10 nf capacitor external reference drive level 0.2 2 v pp sine wave coupled through 10nf capacitor 0.5 v pp recommended level for optimum phase noise at 4 mhz phase detector comparison frequency 31.25 250 khz rf division ratio 240 32767 switching ports gpp3-gpp0 sink current 10 ma v port = 0.4 pull up resistor gpp3- gpp1 10 k ? leakage current 10 av port = v cc, port p0 only characteristic min. typ. max. units conditions
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes seating plane 1 25-02-2004 e1 e e2 a1 a d d1 d2 b e l
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