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1 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation lo w p o wer micr opr ocessor supervisory with battery switc h-over sp691a/693a/800l/800m the sp691a/693a/800l/800m is a microprocessor ( p) supervisory circuit that integrates a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in p and digital systems. the sp691a/693a/800l/800m offers complete p monitoring and watchdog functions. the sp691a/693a/800l/800m is ideal for a low-cost battery management solution and is well suited for portable, battery-powered applications with its supply current of 35 a. the 6ns chip-enable propagation delay, the 25ma current output in battery-backup mode, and the 250ma current output in standard operation also makes the sp691a/693a/800l/800m suitable for larger scale, high-performance equipment. precision 4.65v/4.40v v oltage monitoring 200ms or adjustable reset time 100ms, 1.6s or adjustable watchdog time 60 a maximum operating supply current 2.0 a maximum batter y backup current 0.1 a maximum batter y standby current p ower switching 250ma output in vcc mode (0.6 ? ) 25ma output in batter y mode (5 ? ) on-board gating of chip-enable signals memor y write-cycle completion 6ns ce gate propagation delay v oltage monitor for p ower-f ail or low batter y backup-batter y monitor reset v alid to vcc=1v 1% accuracy guaranteed ( sp800l / 800m ) pin compatible upgrade to max691a/693a/ 800l/800m r e b m u n t r a p d l o h s e r h t t e s e r y c a r u c c a t e s e r y c a r u c c a i f p h c t i w s y r e t t a b - p u k c a b a 1 9 6 p s v 5 6 . 4 + v m 5 2 1 + % 4 s e y a 3 9 6 p s v 0 4 . 4 + v m 5 2 1 + % 4 s e y l 0 0 8 p s v 5 6 . 4 + v m 0 5 + % 1 s e y m 0 0 8 p s v 0 4 . 4 + v m 0 5 + % 1 s e y description features v ba tt v out vcc gnd ba tt on pfo pfi osc in reset wdo ce in ce out wdi lowline 16 dip/so top view 15 14 13 12 1 1 10 9 1 2 3 4 5 6 7 8 corporation reset osc sel now available in lead free packaging ?
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 2 these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. terminal voltages (with respect to gnd) v cc .......................................................................................-0.3v to +6v v batt .....................................................................................-0.3v to +6v all other inputs........................................................-0.3v to (v cc +0.3v) input currents v cc peak...........................................................................................1.0a v cc continuous.............................................................................250ma v batt peak....................................................................................250ma v batt continuous............................................................................25ma gnd, batt on............................................................................100ma all other inputs..............................................................................25ma v cc = +4.75v to +5.5v for the sp691a/800l , v cc = +4.5v to +5.5v for the sp693a/800m , v batt = +2.8v, and t amb = t min to t max unless otherwise noted. typical values apply at t amb =+25 o c. s r e t e m a r a p . n i m . p y t . x a m s t i n u s n o i t i d n o c , e g n a r e g a t l o v g n i t a r e p o v c c v r o t t a b 1 e t o n , 0 5 . 5 v v , e g a t l o v t u p t u o t u o e d o m g n i t a r e p o l a m r o n n i v c c 5 0 . 0 - v c c 3 . 0 - v c c 2 . 0 - v c c 5 1 0 . 0 - v c c 5 1 . 0 - v c c 9 0 . 0 - v v c c i , v 5 . 4 = t u o a m 5 2 = v c c i , v 5 . 4 = t u o a m 0 5 2 = v c c v , v 0 . 3 = t t a b i , v 8 . 2 = t u o a m 0 0 1 = v c c v - o t - t u o e c n a t s i s e r - n o 6 . 0 9 . 0 2 . 1 0 . 2 ? v c c v 5 . 4 = v c c v 0 . 3 = v t u o e d o m p u k c a b - y r e t t a b n i v t t a b 3 . 0 - v t t a b 5 2 . 0 - v t t a b 5 1 . 0 - v t t a b 1 . 0 - v t t a b 7 0 . 0 - v t t a b 5 0 . 0 - v v t t a b i , v 5 . 4 = t u o a m 0 2 = v t t a b i , v 8 . 2 = t u o a m 0 1 = v t t a b i , v 0 . 2 = t u o a m 5 = v t t a b v - o t - t u o e c n a t s i s e r - n o 5 7 0 1 5 1 5 2 0 3 ? v t t a b v 5 . 4 = v t t a b v 8 . 2 = v t t a b v 0 . 2 = l a m r o n n i t n e r r u c y l p p u s i , e d o m g n i t a r e p o c c v 5 3 0 6 a v c c v ( > t t a b i g n i d u l c x e , ) v 1 - t u o - y r e t t a b n i t n e r r u c y l p p u s i , e d o m p u k c a b t t a b 2 e t o n , 1 0 0 . 0 0 . 2 a v c c v ( < t t a b v , ) v 2 . 1 - t t a b i g n i d u l c x e , v 8 . 2 = t u o v t t a b i , t n e r r u c y b d n a t s t t a b , 3 e t o n 1 . 0 - 2 0 . 0 a v c c > v ( t t a b i g n i d u l c x e , ) v 2 . 0 + t u o d l o h s e r h t r e v o h c t i w s y r e t t a b v t t a b 3 0 . 0 + v t t a b 3 0 . 0 - v p u - r e w o p n w o d - r e w o p s i s e r e t s y h r e v o h c t i w s y r e t t a b 0 6 v m k a e p o t k a e p absolute maximum ratings electrical characteristics enhanced esd specifications........................ +4kv human body model power dissipation per package 16-pin pdip (derate 14.3mw/ o c above +70 o c).......................1150mw 16-pin narrow soic (derate 13.6mw/ o c above 70 o c)............1090mw 16-pin wide soic (derate 11.2mw/ o c above 70 o c).................900mw storage temperature....................................................-65 o c to +150 o c lead temperature (soldering,10 sec).........................................+300 o c
3 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation s r e t e m a r a p . n i m . p y t . x a m s t i n u s n o i t i d n o c w o l t u p t u o n o t t a b e g a t l o v 1 . 0 7 . 0 4 . 0 5 . 1 v i k n i s a m 2 . 3 = i k n i s a m 5 2 = t r o h s t u p t u o n o t t a b t n e r r u c t i u c r i c 1 0 6 5 1 0 0 1 a m a t n e r r u c k n i s t n e r r u c e c r u o s r e m i t g o d h c t a w d n a , e n i l w o l , t e s e r e g a t l o v d l o h s e r h t t e s e r 0 5 . 4 5 2 . 4 0 6 . 4 5 3 . 4 5 6 . 4 0 4 . 4 5 6 . 4 0 4 . 4 5 7 . 4 0 5 . 4 0 7 . 4 5 4 . 4 v a 1 9 6 p s a 3 9 6 p s l 0 0 8 p s m 0 0 8 p s s i s e r e t s y h d l o h s e r h t t e s e r 5 1 v m k a e p - o t - r e t n e c v c c y a l e d t e s e r o t 0 8 s n w o d r e w o p y a l e d t e s e r o t e n i l w o l 0 0 8 s n n w o d r e w o p d o i r e p t u o e m i t e v i t c a t e s e r r o t a l l i c s o l a n r e t n i e h t r o f 0 4 1 0 0 2 0 8 2 s m p u - r e w o p d o i r e p t u o e m i t e v i t c a t e s e r , k c o l c l a n r e t x e e h t r o f 4 e t o n 8 4 0 2 k c o l c s e l c y c p u - r e w o p r o f d o i r e p t u o e m i t g o d h c t a w r o t a l l i c s o l a n r e t n i e h t 0 . 1 0 7 6 . 1 0 0 1 5 2 . 2 0 4 1 c e s s m d o i r e p g n o l d o i r e p t r o h s r o f d o i r e p t u o e m i t g o d h c t a w 4 e t o n , k c o l c l a n r e t x e e h t 6 9 0 4 4 2 0 1 k c o l c s e l c y c d o i r e p g n o l d o i r e p t r o h s t u p n i g o d h c t a w m u m i n i m h t d i w e s l u p 0 0 1 s n v l i v , v 8 . 0 = h i v x 5 7 . 0 = c c e g a t l o v t u p t u o t e s e r 5 . 3 4 0 0 . 0 1 . 0 3 . 0 4 . 0 v i k n i s 0 5 = v , a c c v , v 1 = c c g n i l l a f i k n i s v , a m 2 . 3 = c c v 5 2 . 4 = i e c r u o s v , a m 6 . 1 = c c v 5 = t i u c r i c - t r o h s t u p t u o t e s e r t n e r r u c 7 0 2 a m t n e r r u c e c r u o s t u p t u o , w o l e g a t l o v t u p t u o t e s e r 5 e t o n 1 . 0 4 . 0 v i k n i s a m 2 . 3 = e g a t l o v t u p t u o e n i l w o l 5 . 3 1 . 0 4 . 0 v i k n i s v , a m 2 . 3 = c c v 5 2 . 4 = i e c r u o s 1 = v , a c c v 5 = t r o h s t u p t u o e n i l w o l t n e r r u c t i u c r i c 5 1 0 0 1 a t n e r r u c e c r u o s t u p t u o e g a t l o v t u p t u o o d w 5 . 3 1 . 0 4 . 0 v i k n i s a m 2 . 3 = i e c r u o s 0 0 5 = v , a c c v 5 = t i u c r i c - t r o h s t u p t u o o d w t n e r r u c 3 0 1 a m t n e r r u c e c r u o s t u p t u o v cc = +4.75v to +5.5v for the sp691a/800l , v cc = +4.5v to +5.5v for the sp693a/800m , v batt = +2.8v, and t amb = t min to t max unless otherwise noted. typical values apply at t amb =+25 o c. electrical characteristics
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 4 s r e t e m a r a p . n i m . p y t . x a m s t i n u s n o i t i d n o c , e g a t l o v d l o h s e r h t i d w 6 e t o n v x 5 7 . 0 c c 8 . 0 v v h i v l i t n e r r u c t u p n i i d w 0 5 - 0 1 - 0 2 0 5 a v 0 = i d w v = i d w t u o r o t a r a p m o c l i a f - r e w o p d l o h s e r h t t u p n i i f p 0 0 2 . 1 5 2 2 . 1 5 2 . 1 5 2 . 1 0 0 3 . 1 5 7 2 . 1 v a 3 9 6 / a 1 9 6 p s v , c c v 5 = m 0 0 8 / l 0 0 8 p s v , c c v 5 = t n e r r u c e g a k a e l i f p + 1 0 . 0 + 5 2 a n e g a t l o v t u p t u o o f p 5 . 3 1 . 0 4 . 0 v i k n i s a m 2 . 3 = i e c r u o s 1 = v , a c c v 5 = t n e r r u c t i u c r i c t r o h s o f p 1 0 6 5 1 0 0 1 a m a t n e r r u c k n i s t u p t u o t n e r r u c e c r u o s t u p t u o y a l e d o f p - o t - i f p 5 2 0 6 s v d o v m 5 1 = v d o v m 5 1 = g n i t a g e l b a n e - p i h c e c n i t n e r r u c e g a k a e l + 5 0 0 . 0 + 1 a e d o m e l b a s i d e c n i e c o t t u o , e c n a t s i s e r 7 e t o n 5 6 0 5 1 ? e d o m e l b a n e e c t u o t n e r r u c t i u c r i c - t r o h s ) e v i t c a t e s e r ( 1 . 0 5 7 . 0 0 . 2 a m e c , e d o m e l b a s i d t u o v 0 = e c n i e c o t t u o n o i t a g a p o r p 8 e t o n , y a l e d 6 0 1 s n 0 5 ? c , r e v i r d e c n a d e p m i e c r u o s d a o l f p 0 5 = e c t u o h g i h e g a t l o v t u p t u o ) e v i t c a t e s e r ( 5 . 3 7 . 2 v v c c i , v 5 = t u o 0 0 1 = a v c c v , v 0 = t t a b i , v 8 . 2 = t u o 1 = a e c o t t e s e r t u o y a l e d 2 1 s n w o d - r e w o p r o t a l l i c s o l a n r e t n i c s o n i t n e r r u c e g a k a e l 0 1 . 0 + 0 . 5 a c s o l e s v 0 = c s o n i t n e r r u c p u - l l u p t u p n i 0 1 0 0 1 a c s o l e s v = t u o c s o , g n i t a o l f r o n i v 0 = c s o l e s t n e r r u c p u - l l u p t u p n i 0 1 0 0 1 a c s o l e s v 0 = c s o n i e g n a r y c n e u q e r f 0 0 2 z h k c s o l e s v 0 = c s o n i r o t a l l i c s o l a n r e t x e e g a t l o v d l o h s e r h t v t u o 3 . 0 - v t u o 6 . 0 - 5 6 . 3 0 . 2 v v h i v l i c s o n i h t i w y c n e u q e r f r o t i c a p a c l a n r e t x e 2 z h k c s o l e s c , v 0 = c s o f p 7 4 = v cc = +4.75v to +5.5v for the sp691a/800l , v cc = +4.5v to +5.5v for the sp693a/800m , v batt = +2.8v, and t amb = t min to t max unless otherwise noted. typical values apply at t amb =+25 o c. 1.237 1.263 electrical characteristics
5 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation note 1: either v cc or v batt can go to 0v, if the other is greater than 2.0v. note 2: the supply current drawn by the sp691a/693a/800l/800m from the battery (excluding i out ) typically goes to 5 a when (v batt - 1v) < v cc < v batt . in most applications, this is a brief period as v cc falls through this region. note 3: "+" = battery-discharging current, "-" = battery-charging current. note 4: although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. note 5: reset is an open-drain output and sinks current only. note 6: wdi is internally connected to a voltage divider between v out and gnd. if unconnected, wdi is driven to 1.6v (typ), disabling the watchdog function. note 7: the chip-enable resistance is tested with v cc = +4.75v for the sp691a/800l and v cc = +4.5v for the sp693a/800m . ce in = ce out = v cc /2. note 8: the chip-enable propagation delay is measured from the 50% point at ce in to the 50% point at ce out . figure 1. v cc supply current vs. temperature (normal operating mode) figure 3. chip-enable on-resistance vs. temperature figure 2. battery supply current vs. temperature (battery-backup mode) figure 4. v batt to v out on-resistance vs. temperature v cc = +4.75v to +5.5v for the sp691a/800l , v cc = +4.5v to +5.5v for the sp693a/800m , v batt = +2.8v, and t amb = t min to t max unless otherwise noted. typical values apply at t amb =+25 o c. temperature ( o c) v c c c u r r e n t ( a ) -60 -30 0 30 60 90 120 43 40 37 34 31 28 25 v cc = 5v v batt = 2.8v temperature ( o c) -60 -30 0 30 60 90 120 150 v b a t t c u r r e n t ( a ) 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 v cc = 1.6v v batt = 2.8v temperature ( o c) -80 -60 -40 -20 0 20 40 60 80 100 120 140 c e - i n r e s i s t a n c e ( ? ) 75.0 70.0 65.0 60.0 55.0 50.0 45.0 40.0 v cc = 4.75v v batt = 2.8v ce in = v cc /2 temperature ( o c) -60 -30 0 30 60 90 120 150 r e s i s t a n c e ( ? ) 14 12 10 8 6 4 2 0 v cc = 0v v batt = 2v v batt = 2.8v v batt = 4.5v electrical characteristics (t amb = 25 o c, unless otherwise noted) typical performance characteristics
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 6 1.e-04 1.e-05 1.e-06 1.e-07 1.e-08 1.e-09 1.e-10 1.e-11 1.e-12 1.e-13 1.e-14 figure 7. reset threshold vs. temperature figure 9. reset delay vs. temperature figure 8. reset output resistance vs. temperature figure 10. battery current vs. input supply voltage figure 5. v cc to v out on-resistance vs. temperature figure 6. pfi threshold vs. temperature temperature ( o c) -60 -30 0 30 60 90 120 150 r e s i s t a n c e ( ? ) 0.9 0.7 0.5 0.3 v cc = 4.5v v batt = 2.8v temperature ( o c) -60 -30 0 30 60 90 120 150 p f i t h r e s h o l d ( v ) 1.256 1.252 1.248 1.244 1.240 1.236 v cc = 5v v batt = 0v temperature ( o c) -60 -30 0 30 60 90 120 150 r e s e t t h r e s h o l d ( v ) 4.69 4.68 4.67 4.66 4.65 4.64 4.63 4.62 4.61 4.60 v batt = 0v v cc rising v cc falling temperature ( o c) -60 -30 0 30 60 90 120 150 r e s i s t a n c e ( ? ) 400 350 300 250 200 150 100 50 0 sourcing v cc = 5v sinking v cc = 4.25v temperature ( o c) -60 -30 0 30 60 90 120 150 r e s e t t i m e o u t p e r i o d ( s ) 0.240 0.230 0.220 0.210 0.200 0.190 0.180 v cc = 5v v batt = 2.8v v cc (v) 0 1 2 3 4 5 v b a t t c u r r e n t ( a ) , l o g s c a l e v batt = 2.8v typical performance characteristics
7 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation figure 11. watchdog and reset timeout period vs. osc in timing capacitor (c osc ) figure 12. chip-enable propagation delay vs. ce out load capacitance figure 13. v cc to v out vs. output current (normal operating mode) figure 15. v cc to lowline and ce out delay figure 14. v batt to v out vs. output current (battery- backup mode) v cc reset threshold 0v +5v low hi low hi low hi lowline reset ce out 80 s 1.1 s 16 s oscin capacitor (pf) 10 100 1000 10000 w a t c h d o g a n d r e s e t t i m e o u t p e r i o d ( s ) 1000 100 10 1 0.1 v cc = 5v v batt = 2.8v long watchdog timeout period reset active timeout period short watchdog timeout period cload (pf) 0 50 100 150 200 250 300 350 p r o p a g a t i o n d e l a y ( s ) 30 25 20 15 10 5 0 v cc = 5v v batt = 2.8v 50 ? driver i out (ma) 1 10 100 1000 v o l t a g e d r o p ( m v ) 1000 100 10 1 v cc = 4.5v v batt = 0v slope = 0.6 ? i out (ma) 1 10 100 1000 voltage drop (mv) 1000 100 10 1 v cc = 4.5v v batt = 0v slope = 5 ? typical performance characteristics
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 8 pin 1 ?v batt ?battery-backup input. con- nect to the external battery supply or super- charging capacitor and charging circuit. if a backup battery is not provided, connect this pin to ground. pin 2 ? out ? output supply voltage. v out connects to v cc when v cc is greater than v batt and v cc is above the reset threshold. when v cc falls below v batt and v cc is below the reset threshold, v out connects to v batt . connect a 0.1 f capacitor from v out to gnd. pin 3 ?v cc ?+5v input supply voltage. pin 4 ? gnd ? ground reference for all signals. pin 5 ? batt on ? battery on output. goes high when v out switches to v batt . goes low when v out switches to v cc . connect the base of a pnp through a current-limiting resistor to batt on for v out current requirements greater than 250ma. pin 6 ?lowline ?low line output. this output pin goes low when v cc falls below the reset threshold voltage. this output pin returns to its high output as soon as v cc rises above the reset threshold voltage. pinout pin 7 ? osc in ? external oscillator input. when osc sel is unconnected or driven high, a 10 a pull-up connects from v out to this input pin, the internal oscillator sets the reset and watchdog timeout periods, and this input pin selects between fast and slow watchdog timeout periods. when osc sel is driven low, the reset and watchdog timeout periods may be set either by a capacitor from this input pin to ground or by an external clock at this pin (refer to figure 21 ). pin 8 ? osc sel ? oscillator select. when osc sel is unconnected or driven high, the internal oscillator sets the reset delay and watchdog timeout period. when osc sel is driven low, the external oscillator input pin, osc in , is enabled (refer to table 1 ). this input pin has a 10 a internal pull-up. pin 9 ? pfi ? power-fail input. this is the n o n i nv e r t i n g i n p u t t o t h e p ow e r - f a i l comparator . when pfi is less than 1.25v , pfo goes low . connect pfi to gnd or v out when not used. pin 10 ? pfo ? power-fail output. this is the output of the power-fail comparator . pfo goes low when pfi is less than 1.25v . this is an uncommitted comparator , and has no ef fect on any other internal circuitry . pin 11 ? wdi ? watchdog input. this is a three-level input pin. if wdi remains either high or low for longer than the watchdog timeout period, wdo goes low and reset is asserted for the reset timeout period. wdo remains low until the next transition at this input pin. leaving this input pin unconnected disables the watchdog function. this input pin connects to an internal voltage divider between v out and ground, which sets it to mid-supply when left unconnected. v ba tt v out vcc gnd ba tt on pfo pfi osc in reset wdo ce in ce out wdi lowline 16 dip/so top view 15 14 13 12 1 1 10 9 1 2 3 4 5 6 7 8 corporation reset osc sel pin assignments
9 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation pin 12 ?ce out chip-enable output. this output pin goes low only when ce in is low and v cc is above the reset threshold voltage. if ce in is low when reset is asserted, this output pin will stay low for 16 s or until ce in goes high, whichever occurs first. pin 13 ? ce in ? chip-enable input. this is the input pin to the chip-enable gating circuit. if this input pin is not used, connect it to ground or v out . pin 14 ?wdo ?watchdog output. if wdi remains high or low longer than the watchdog timeout period, this output pin goes low and reset is asserted for the reset timeout period. this output pin returns h i g h o n t h e n e x t t r a n s i t i o n a t w d i . this output pin remains high if wdi is unconnected. pin 15 ? reset ? active low reset output. this output pin goes low whenever v cc falls below the reset threshold. this output pin will remain low typically for 200ms after v cc crosses the reset threshold voltage on power-up. pin 16 ? reset ? active high reset output. this output pin is open drain and the inverse of reset. figure 16. internal block diagram of the sp691a/693a/800l/800m osc in 4 1.25v reset generator ce out control watchdog timer reset / watchdog timebase watchdog transition detector wdi osc sel v cc v batt ba tt on ce in ce out v out lowline reset reset pfo pfi 9 1 1 8 7 3 1 5 13 12 gnd 2 6 16 15 4.65v or 4.40v* wdo 14 10 4.65v for the sp691a/800l 4.40v for the sp693a/800m *
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 10 the sp691a/693a/800l/800m devices are microprocessor ( p) supervisory circuits that monitor the power supplied to digital circuits such as microprocessors, microcontrollers, or memory . the sp691a/693a/800l/800m series i s a n i d e a l s o l u t i o n f o r p o r t a b l e , b a t t e r y - powered equipment that require power supply monitoring. the sp691a/693a/800l/800m watchdog functions will continuously oversee the operational status of a system. implementing t h e s p 6 9 1 a / 6 9 3 a / 8 0 0 l / 8 0 0 m s e r i e s w i l l reduce the number of components and overall complexity in a design that requires power supply monitoring circuitry . the operational features and benefits of this series are described in more detail below . figure 17. typical application circuit of the sp691a/693a/800l/800m reset nmi i/o line v cc reset pfo wdi gnd v ba tt r 2 r 1 unregulated dc regulated +5v v cc pfi p cmos ram 1 to ram n ce out ba tt on v out address decode bus ce in backup supply v cc a0-a15 0.1 f alarm system status indicator wdo lowline t h e s p 6 9 1 a / 6 9 3 a / 8 0 0 l / 8 0 0 m s e r i e s i s a complete p supervisor ic and provides the following main functions: 1) p reset ? reset output is asserted during p o w e r f l u x i a t i o n s s u c h a s p o w e r - u p , power-do wn, and bro wn out conditions, and is guaranteed to be in the correct state for v cc down to 1v , even with no battery in the circuit. 2) p reset ? reset output is pulsed if the o p t i o n a l w a t c h d o g t i m e r h a s n o t b e e n toggled within a specified time. 3) power fail comparator ? pr ovides for p o w e r - f a i l w a r n i n g a n d l o w - b a t t e r y d e t e c t i o n , o r m o n i t o r s a n o t h e r p ow e r supply . fea tures theor y of opera tion
11 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 10k ? and the output saturation v oltage is belo w 0.4v while sinking 40 a. when using a 10k ? external pull-down resistor , the high state for the reset output with vcc = 4.75v is 4.5v typical. for battery voltages less than or equal to 2v connected to v ba tt , reset and reset remains valid for v cc from 0v to 5.5v . reset and reset are asserted when v cc falls below the reset threshold and remain asserted for the reset timeout period (200ms nominal) after v cc rises above the reset threshold voltage on power-up. refer to f igur e 19 . the devices' battery-switchover comparator does not affect reset assertion. however, both reset outputs are asserted in battery-backup mode since v cc must be below the reset threshold to enter this mode. figure 18. external pull-down resistor ensures reset is valid with v cc down to ground. to p reset 10k ? 15 corporation reset figure 19. reset and chip-enable timing 4) w atchdog function ? monitors p activity where the watchdog output goes to a logic low state if the watchdog input is not toggled for greater than the timeout period. 5) internal switch ? switches over from v cc to v ba tt if the v cc falls below the reset threshold. reset and reset outputs t h e s p 6 9 1 a / 6 9 3 a / 8 0 0 l / 8 0 0 m d e v i c e s ' reset and reset outputs ensure that the p p ow e r s u p i n a k n ow n s t a t e , a n d p r eve n t s code-execution errors during power-down or brownout conditions. the reset output is active low , and typically sinks 3.2ma at 0.1v saturation voltage in its active state. when deasserted, reset sources 1.6ma at typically v out ?0.5v . reset output is open drain, active high, and typically sinks 3.2ma with a saturation voltage of 0.1v . when no backup battery is used, reset output is guaranteed to be valid down to v cc = 1v , and an external 10k ? pull-down resistor on reset ensures that reset will be valid with v cc down to gnd as shown on f igur e 18 . as v cc goes below 1v , the gate drive to the reset output switch reduces accordingly , increasing the r ds (on) and the saturation voltage. the 10k ? pull-down resistor ensures the parallel combination of switch plus resistor is around vcc ce in ce out reset 12 100 s 100 s reset threshold reset
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 12 w atchdog function the watchdog monitors p activity via the w atchdog input (wdi). if the p becomes i n a c t ive , r e s e t a n d r e s e t a r e a s s e r t e d . t o use the watchdog function, connect wdi to a bus line or p i/o line. if wdi remains high or low for longer than the watchdog timeout pe- riod (1.6s nominal). wdo, reset , and reset are asserted, indicating a software fault or idle conditions. refer to reset and reset outputs and w atchdog output sections. w atchdog input a c h a n g e o f l o g i c s t a t e ( m i n i m u m 1 0 0 n s duration) at wdi during the watchdog period will reset the watchdog timer . the watchdog default timout is 1.6sec. t o disable the watchdog function, leave wdi floating. an internal resistor network (100k ? equivalent impedance at wdi) biases wdi to a p p r o x i m a t e l y 1 . 6 v . i n t e r n a l c o m p a r a t o r s detect this level and disable the watchdog timer . when vcc is below the reset threshold, the wa t c h d o g f u n c t i o n i s d i s a b l e d a n d w d i i s disconnected from its internal resistor network, thus becoming high impedance. w atchdog output wdo remains high if there is acti vity (transition or pulse) at wdi during the watchdog-timeout period. the watchdog function is disabled and wdo is a logic high when v cc is less than the reset threshold or when wdi is an open circuit. in watchdog mode, if no transition occurs at w d i d u r i n g t h e wa t c h d o g - t i m e o u t p e r i o d , figure 20. watchdog timeout period and reset active time figure 21. selecting timeout periods osc sel no connect x no connect x osc in 7 8 osc sel no connect x osc in 7 8 osc sel osc in 7 8 osc sel osc in 7 8 1.6sec normal watchdog timeout internal oscillator 100ms normal watchdog timeout internal oscillator normal watchdog timeout = [ms] external oscillator normal watchdog timeout = 1024 clock periods external clock 600 x c in 47pf c in t 2 t 1 t 1 t 3 t 1 = reset timeout period t 2 = normal watchdog timeout period t 3 = watchdog timeout period immediately after reset wdi wdo reset
13 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation reset and reset are asserted for the reset timeout period (200ms nominal). wdo goes to logic low and remains low until the next transition at wdi. refer to f igur e 20 . if wdi is held high or low indefinitely , reset and reset will generate 200ms pulses every 1.6s. wdo has a 2 x ttl output characteristic. s e l e c t i n g a n a l t e r n a t i v e wa t c h d o g timeout period t h e o s c sel a n d o s c in i n p u t s c o n t r o l t h e watchdog are reset timeout periods. floating osc sel and osc in or tying them both to v out s e l e c t s t h e n o m i n a l 1 . 6 s wat c h d o g t i m e o u t p e r i o d a n d 2 0 0 m s r e s e t t i m o u t p e r i o d . connecting osc in to ground and floating or connecting osc sel to v out selects a 100ms nor- mal watchdog timeout period and a 1.6s timeout period immediately after reset. the reset timeout period remains 200ms. refer to figure 20 . select alternati v e timeout periods by connecting osc sel to ground and connecting a capacitor between osc in and ground, or by externally driving osc in . a synopsis of this control can be found in f igur e 21 and t able 1 . chip-enable signal gating t h e s p 6 9 1 a / 6 9 3 a / 8 0 0 l / 8 0 0 m d e v i c e s provide internal gating of chip-enable (ce) s i g n a l s , t o p r e v e n t e r r o n e o u s d a t a f r o m corrupting the cmos ram in the event of a power failure. during normal operation, the ce gate is enabled and passes all ce transitions. w h e n r e s e t i s a s s e r t e d , t h i s p a t h b e c o m e s d i s a b l e d , p r ev e n t i n g e r r o n e o u s d a t a f r o m corrupting the cmos ram. the sp691a/ 6 9 3 a / 8 0 0 l / 8 0 0 m d e v i c e s u s e a s e r i e s t r a n s m i s s i o n gate from ce in to ce out . refer to f igur e 16. the 10ns maximum ce propagation from ce in t o c e out e n a b l e s t h e s p 6 9 1 a / 6 9 3 a / 8 0 0 l / 800m devices to be used with most ps. chip-enable input ce in is in high impedance (disabled mode) while reset and/or reset are asserted. during a power-down sequence where v cc falls below the reset threshold, ce in assumes a high impedance state when the voltage at ce in goes h i g h o r 1 2 s a f t e r r e s e t i s a s s e r t e d , whichever occurs first. refer to figure 19 . during a power-up sequence, ce in remains high impedance until reset is deasserted. i n t h e h i g h - i m p e d a n c e m o d e , t h e l e a k a g e currents into ce in are <1 a over temperature. in the low-impedance mode, the impedance of ce in appears as a 65 ? resistor in series with the load at ce out . t h e p r o p a g a t i o n d e l a y t h r o u g h t h e c e transmission gate depends on both the source i m p e d a n c e o f t h e d r i v e t o c e i n a n d t h e c a p a c i t i v e l o a d i n g o n c e o u t ( s e e t h e c h i p - e n a b l e p r o p a g a t i o n d e l a y v s . c e out l o a d c a p a c i t a n c e g r a p h i n t h e ty p i c a l p erformance characteristics section ). the ce propagation delay is defined from the 50% point on ce in to the 50% point on ce out using a 50 ? driver and 50pf of load capacitance as in figure 22 . for minimum propagation delay , minimize the capacitive load at ce out and use a low output-impedance driver . c s o l e s c s o n i d o i r e p t u o e m i t g o d h c t a w d o i r e p t u o e m i t t e s e r l a m r o n t e s e r r e t f a y l e t a i d e m m i w o l t u p n i k c o l c l a n r e t x e s k c o l c 4 2 0 1 s k c o l c 6 9 0 4 s k c o l c 8 4 0 2 w o l r o t i c a p a c l a n r e t x e s m ) c x f p 7 4 / 0 0 6 ( c e s ) c x f p 7 4 / 4 . 2 ( s m ) c x f p 7 4 / 0 0 2 1 ( g n i t a o l f w o l s m 0 0 1 s 6 . 1 s m 0 0 2 g n i t a o l f g n i t a o l f s 6 . 1 s 6 . 1 s m 0 0 2 table 1. reset pulse width and watchdog timeout selections
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 14 chip-enable output in the enabled mode, the impedance of ce out is equivalent to 65 ? in series with the source driving ce in . in the disabled mode, the 65 ? transmission gate is off and ce out is actively pulled to v out . this source turns off when the transmission gate is enabled. lo wline output lowline is the buffered output pin of the reset threshold comparator . refer to f igur e 16 . lowline typically sinks 3.2ma at 0.1v . for normal operation where v cc is above the reset threshold, lowline is pulled to v out . p ower-fail comparator the power-fail comparator is an uncommitted c o m p a r a t o r t h a t h a s n o e ff e c t o n t h e o t h e r functions of the sp691a/693a/800l/800m devices. common uses include low ba ttery detection, as found in figure 23 , and early po wer-fail detection when the unregulated po wer is easily accessible as sho wn in f igur e 17 . p ower-fail input the power-fail input (pfi) has a guaranteed input leakage of +25na max over temperature. the typical comparator delay is 25 s from v il to v ol (power failing), and 60 s from v ih to v o h ( p ow e r b e i n g r e s t o r e d ) . c o n n e c t t h i s input to ground if pfi is not used. p ower-fail output the power-fail output (pfo) goes low when pfi goes below 1.25v . it sinks 3.2ma with a saturation voltage of 0.1v . with pfi above 1.25v , pfo is actively pulled to v out . pfo can be used to generate an nmi for the p , as shown in f igur e 17 . battery-backup mode the sp691a/693a/800l/800m requires two conditions to switch to battery-backup mode: 1) v cc must be below the reset threshold; 2) v cc must be below v ba tt . t able 2 lists the status of the inputs and outputs in battery- backup mode. battery-on output the battery on output (ba tt on) indicates the status of the internal v cc /battery-switchover comparator , which controls the internal v cc and v ba tt switches. for v cc greater that v ba tt (ignoring the small hysteresis effect), b a tt on is a logic low . for v cc less than v ba tt , ba tt on is a logic high. use ba tt on to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-current applications. refer to f igur e 17. ce out ce in 12 v ba tt 2.8v gnd 1 13 4 c load pfo +2.0v to +5.5v r 2 r 1 v cc +5v gnd low batt pfi v ba tt figure 22. chip enable propagation delay test circuit figure 23. low-battery indicator circuit
15 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation input supply v oltage the input supply v oltage (v cc ) should be a regulated +5v source. v cc connects to v out via a parallel diode and a large pmos switch. the switch carries the entire current load for currents less than 250ma. the parallel diode carries any current in excess of 250ma. both t h e s w i t c h a n d t h e d i o d e h ave i m p e d a n c e s less than 1 ? each. refer to f igure 24 . the maximum continuous current is 250ma, but po wer -on transients may reach a maximum of 1a. backup-battery input the backup-battery input (v ba tt ) is similar to v cc , except the pmos switch and parallel diode are much smaller . refer to figure 24 . accordingly , the on-resistances of the diode and the switch are each approximately 10 ? . table 2. input and output status in battery-backup mode; to enter the battery-backup mode, v cc must be less than the reset threshold and less than v batt . figure 24. v cc and v batt to v out switch sw1 d1 d2 sw2 v ba tt v cc v out 0.1 f e m a n s u t a t s r e b m u n n i p v t t a b 1 s i t n e r r u c y l p p u s v n e h w m u m i x a m a c c v ( < t t a b . ) v 2 . 1 - 1 v t u o v t u o v o t d e t c e n n o c t t a b . h c t i w s s o m p l a n r e t n i n a h g u o r h t 2 v c c v s r o t i n o m r o t a r a p m o c r e v o h c t i w s y r e t t a b c c v . r e v o h c t i w s e v i t c a r o f c c s i v m o r f d e t c e n n o c s i d t u o . 3 d n g . s l a n g i s l l a r o f e c n e r e f e r v 0 4 n o t t a b v o t l a u q e s i e g a t l o v t u p t u o t i u c r i c - n e p o e h t . h g i h c i g o l t u o . 5 e n i l w o l . w o l c i g o l 6 c s o n i c s o n i . z - h g i h t a s i d n a d e r o n g i s i 7 c s o l e s c s o l e s . z - h g i h t a s i d n a d e r o n g i s i 8 i f p . d e l b a s i d s i r o t a r a p m o c l i a f - r e w o p e h t 9 o f p . w o l c i g o l o t d e c r o f s i o f p . d e l b a s i d s i r o t a r a p m o c l i a f - r e w o p e h t 0 1 i d w . z - h g i h t a s i d n a d e r o n g i s i i d w 1 1 e c t u o v o t l a u q e s i e g a t l o v t u p t u o t i u c r i c - n e p o e h t . h g i h c i g o l t u o . 2 1 e c n i . z - h g i h 3 1 o d w v o t l a u q e s i e g a t l o v t u p t u o t i u c r i c - n e p o e h t . h g i h c i g o l t u o . 4 1 t e s e r . w o l c i g o l 5 1 t e s e r . z - h g i h 6 1
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 16 continuous current should be limited to 25ma a n d p e a k c u r r e n t s ( o n l y d u r i n g p ow e r- u p ) limited to 250ma. the reverse leakage of this input is less than 1 a over temperature and supply voltage. output supply v oltage the output supply v oltage (v out ) supplies all the current to the external system and internal circuitry . all open-circuit outputs will assume the v out voltage in their high states rather than t h e v cc vo l t a g e . a t t h e m a x i m u m s o u r c e c u r r e n t o f 2 5 0 m a , v o u t w i l l t y p i c a l l y b e 150mv below v cc . v out should be decoupled with 0.1 f capacitor . typical applica tions the sp691a/693a/800l/800m devices are not s h o r t - c i r c u i t p r o t e c t e d . s h o r t i n g v o u t t o ground, other than power-up transients such as charging a decoupling capacitor , may destroy the device. all open-circuit outputs swing between v out and gnd rather than v cc and gnd. if long leads connect to the chip inputs, ensure that these lines are free from ringing and other conditions that would forward bias the chip's protection diodes. there are three distinct modes of operation: 1) normal operating mode with all circuitry powered from v cc . t ypical supply current from v cc is 35 a, while only leakage currents flow from the battery . 2) battery-backup mode where v cc is typically within 0.7v below v ba tt . all circuitry is p o w e r e d f r o m v bat t a n d t h e s u p p l y current from the battery is typically less than 5 a. 3) battery-backup mode where v cc is less than v bat t b y a t l e a s t 0 . 7 v . v bat t s u p p l y current is less than 1 a max. using high capacity capacitor with the sp691a/693a/800l/800m series v ba tt has the same operating voltage range as v cc , a n d t h e b a t t e r y - s w i t c h ove r t h r e s h o l d voltages are typically +30mv centered at v b a tt , a l l ow i n g u s e o f a c a p a c i t o r a n d a s i m p l e charging circuit as a backup source. refer to f igur e 25 . if v cc is above the reset threshold and v ba tt is 0.5v above v cc , current flows to v out and v cc from v ba tt until the voltage at v ba tt is less than 0.5v above v cc . leakage current through the capacitor charging diode and sp691a/693a/800l/800m internal po wer diode e v entually dischar ges the capacitor to v cc . also, if v cc and v ba tt start from 0.5v above the reset threshold and power is lost at v cc , the capacitor on v ba tt discharges through v cc until v ba tt reaches the reset threshold; the sp691a/693a/800l/800m devices then switch to battery-backup mode. using separate p ower supplies for v ba tt and v cc if using separate power supplies for v cc and v ba tt , v ba tt must be less than 0.3v above v cc when v cc is above the reset threshold. as described in the previous section, if v ba tt exceeds this limit and power is lost at v cc , c u r r e n t f l ow s c o n t i n u o u s l y f r o m v ba t t t o v cc via the v ba tt -to-v out diode and the v out -to-v cc switch until the circuit is broken. refer to f igur e 24 . alternative chip-enable gating using memory devices with ce and ce inputs allows the ce loop of the sp691a/693a/800l/ 8 0 0 m s e r i e s t o b e b y p a s s e d . to d o t h i s , connect ce in to ground, pull up ce out to v out , figure 25. high capacity capacitor on v batt ( corporation +5v 1n4148 0.47f 1 3 2 4 vcc v ba tt v out gnd
17 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation and connect ce out to the ce input of each memory device as shown in f igur e 26 . the ce input of each part then connects directly to the chip-select logic, which does not have to gated by the sp691a/693a/800l/800m devices. a dd i n g h y s t e r e s i s t o t h e pow e r- fa i l comparator hysteresis adds noise margin to the power-fail comparator and prevents repeated triggering of pfo when v in is near the po wer -fail comparator trip point. f igur e 27 sho ws ho w to add hysteresis to the power-fail comparator . select the ratio of r1 and r2 such that pfi sees 1.25v when v in falls to the desired trip point (v trip ). resistor r3 adds hysteresis. it will typically be an order o f m a g n i t u d e g r e a t e r t h a n r 1 o r r 2 . t h e current through r1 and r2 should be at least 1 a to ensure that the 25na (max) pfi input current does not shift the trip point. r3 should be larger than 10k ? to prevent it from loading down the pfo pin. capacitor c1 adds additional noise rejection. monitoring a negative v oltage t h e p o w e r - f a i l c o m p a r a t o r c a n b e u s e d t o m o n i t o r a negati ve supply voltage using the circuit sho wn in f igur e 28 . when the negative supply is valid, pfo is low . when the negative supply voltage drops, pfo goes high. this circuit's accuracy is affected by the pfi threshold tolerance, the v cc voltage, and resistors r1 and r2. backup-battery replacement the backup battery may be disconnected while v cc is abo v e the reset threshold. no precautions are necessary to avoid spurious reset pulses. figure 26. alternate chip enable gating gnd v out r p * 2 ce ce ce ce ce ce ce ce active-high ce logic lines for memory devices ce out ce in 13 4 12 * minimum value of r p is 1k ? . maximum value of r p is dependent on the connected number of rams, n. ram 1 ram 2 ram 3 ram n figure 27. adding hysteresis to the power-fail comparator pfi pfo r 3 *c 1 r 2 r 1 v in connect to p v cc +5v gnd pfo v in +5v v l v h v trip 0v 0v *optional v trip = r 2 r 1 + r 2 v h = r 2 || r 3 r 1 + r 2 || r 3 1.25 r 2 = v l - 1.25 r 1 5.0 - 1.25 r 3 + 1.25 1.25
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 18 pfi pfo r 2 r 1 v cc +5v gnd pfo v - +5v *v trip 0v 0v v - *v trip is a negative voltage 5.0 - 1.25 r 1 1.25 - v trip r 2 = figure 28. monitoring a negative voltage negative-going v cc t ransients while asserting resets to the p during po wer -up, power-down, and brownout conditions, these supervisors are relatively imm une to short- duration negative-going v cc transients. it is usually undesirable to reset the p when v cc experiences only small glitches. refer to f igur e 29 for a graph of the maximum transient duration vs. the reset-comparator over- drive for which reset pulses are not generated. the graph was produced using negative-going pulses, starting at 5v and ending below the r e s e t t h r e s h o l d b y t h e m a g n i t u d e i n d i c a t e d (reset comparator overdrive). the graph shows the maximum pulse width a negative-going v cc transient may typically have without causing a reset pulse to be issued. as the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. t ypically , a v cc transient that goes 100mv below the reset threshold and lasts for 40 s or less will not cause a reset pulse to be issued. a 100nf bypass capacitor mounted close to the v cc pin provides additional transient immunity . connecting a timing capacitor to osc in when osc sel is connected to ground, osc in disconnects from its internal 10 a pull-up and is internally connected to a +100na current source. when a capacitor is connected from o s c in t o g r o u n d ( t o s e l e c t a n a l t e r n a t iv e watchdog timeout period), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and watchdog timeout period. t o prevent timing e r r o r s , m i n i m i z e e x t e r n a l c u r r e n t l e a k a g e sources at this pin, and locate the capacitor as close to osc in as possible. the sum of any pc board leakage plus the osc capacitor leakage must be small compared to +100na. figure 29. maximum transient duration without causing a reset pulse vs. reset comparator overdrive reset comparator overdrive (reset threshold voltage - v cc ), (mv) 1 10 1000 10000 m a x i m u m t r a n s i e n t d u r a t i o n ( s ) 160 120 80 40 0 0.1 f capacitor v out to gnd above line reset generated
19 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation figure 30. watchdog flow diagram st art set wdi low subroutine or program loop set wdi high return end w atchdog software considerations a way to help the watchdog timer keep a closer watch on software execution in volves setting and resetting the watchdog input at different points in the program, rather than "pulsing" the watchdog input high-low-high or low-high-low . this technique avoids a "stuck" loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. figure 30 shows an example flow diagram where the i/o driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subrouting or loop, then set high again when the program returns to the beginning. if the program should "hang" in any subroutine, the i/o is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. maximum v cc fall time the v cc fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03v/ s. a standard rule of thumb for filter capacitance on most regulators is on the order of 100 f per amp of current. when the power supply is shut off or the main battery is disconnected, the associated initial v cc fall rate is just the inverse of 1a/100 f = 0.01v/ s. the v cc fall rate decreases with time as v cc falls exponentially , which more than satisfies the maximum fall-time requirement.
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 20 package: 16 pin nsoic top view b gauge plane l1 l ? 1 ? seating plane l2 view c a a1 a2 see view c b b section b-b with pla ting c base met al b symbol min nom max a 1.35 - 1.75 a1 0.1 - 0.25 a2 1.25 - 1.65 b 0.31 - 0.51 c 0.17 - 0.25 d e e1 e l 0.4 - 1.27 l1 l2 ? 0o - 8o ?1 5o - 15o note: dimensions in (mm) 1.27 bsc 1.04 ref 0.25 bsc 16 pin nsoic jedec mo-012 (ac) variation 9.90 bsc 6.00 bsc 3.90 bsc e e/2 e1 index area (d/2 x e1/2) e1/2 d 1 e side view seating plane
21 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation package: 16 pin wsoic a a2 a1 side view seating plane symbol min nom max a 2.35 - 2.65 a1 0.1 - 0.3 a2 2.05 - 2.55 b 0.31 - 0.51 c 0.2 - 0.33 d e e1 e l 0.4 - 1.27 l1 l2 ? 0o - 8o ?1 5o - 15o note: dimensions in (mm) 1.27 bsc 1.04 ref 0.25 bsc 16 pin soic jedec ms-013 (aa) variation 10.30 bsc 10.30 dsc 7.50 bsc l1 l 1 1 seating plane gauge plane l2 view c top view e e e/2 e1 b index area (d/2 x e1/2) e1/2 d 1 2 3 b b see view c c with pla ting base met al b section b-b
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 22 package: 16 pin pdip ea eb e d1 d l a1 b b2 e b3 n 1 2 3 index area n/2 e e1 c b symbol min nom max a - - 0.21 a1 0.15 - - a2 0.115 0.13 0.195 b 0.014 0.018 0.022 b2 0.045 0.06 0.07 b3 0.3 0.039 0.045 c 0.008 0.01 0.014 d 0.735 0.75 0.755 d1 0.005 - - e 0.3 0.31 0.325 e1 0.24 0.25 0.28 e ea eb - - 0.43 l 0.115 0.13 0.15 note: dimensions in (mm) .100 bsc .300 bsc 16 pin pdip jedec ms-001 (bb) variation a a2 c
23 date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation part number temperature range package type sp691acp ............................................... 0 o c to +70 o c ............................................ 16-pin pdip sp691acn ............................................... 0 o c to +70 o c ......................................... 16-pin nsoic sp691acn/tr ......................................... 0 o c to +70 o c ......................................... 16-pin nsoic sp691act ............................................... 0 o c to +70 o c ........................................ 16-pin wsoic sp691act/tr ......................................... 0 o c to +70 o c ........................................ 16-pin wsoic sp691aep ............................................. -40 o c to +85 o c .......................................... 16-pin pdip sp691aen ............................................. -40 o c to +85 o c ....................................... 16-pin nsoic sp691aen/tr ....................................... -40 o c to +85 o c ....................................... 16-pin nsoic sp691aet ............................................. -40 o c to +85 o c ...................................... 16-pin wsoic sp691aet/tr ........................................ -40 o c to +85 o c ...................................... 16-pin wsoic sp693acp ............................................... 0 o c to +70 o c ............................................ 16-pin pdip sp693acn ............................................... 0 o c to +70 o c ......................................... 16-pin nsoic sp693acn/tr ......................................... 0 o c to +70 o c ......................................... 16-pin nsoic sp693act ............................................... 0 o c to +70 o c ........................................ 16-pin wsoic sp693act/tr ......................................... 0 o c to +70 o c ........................................ 16-pin wsoic sp693aep ............................................. -40 o c to +85 o c .......................................... 16-pin pdip sp693aen ............................................. -40 o c to +85 o c ....................................... 16-pin nsoic sp693aen/tr ....................................... -40 o c to +85 o c ....................................... 16-pin nsoic sp693aet ............................................. -40 o c to +85 o c ...................................... 16-pin wsoic sp693aet/tr ........................................ -40 o c to +85 o c ...................................... 16-pin wsoic corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 ordering information available in lead free packaging. to order add ?-l? suffix to part number. example: sp691aen/tr = standard; sp691aen-l/tr = lead free /tr = tape and reel pack quantity is 2500 for nsoic and wsoic. click here to order samples
date: 4/18/05 sp691a/693a/800l/800m low power microprocessor supervisor with battery switch-over ? copyright 2005 sipex corporation 24 part number temperature range package type sp800lcp ............................................... 0 o c to +70 o c ............................................ 16-pin pdip sp800lcn ............................................... 0 o c to +70 o c ......................................... 16-pin nsoic sp800lcn/tr ......................................... 0 o c to +70 o c ......................................... 16-pin nsoic sp800lct ................................................ 0 o c to +70 o c ........................................ 16-pin wsoic sp800lct/tr .......................................... 0 o c to +70 o c ........................................ 16-pin wsoic sp800lep ............................................. -40 o c to +85 o c .......................................... 16-pin pdip sp800len ............................................. -40 o c to +85 o c ....................................... 16-pin nsoic sp800len/tr ....................................... -40 o c to +85 o c ....................................... 16-pin nsoic sp800let .............................................. -40 o c to +85 o c ...................................... 16-pin wsoic sp800let/tr ........................................ -40 o c to +85 o c ...................................... 16-pin wsoic sp800mcp .............................................. 0 o c to +70 o c ............................................ 16-pin pdip sp800mcn .............................................. 0 o c to +70 o c ......................................... 16-pin nsoic sp800mcn/tr ........................................ 0 o c to +70 o c ......................................... 16-pin nsoic SP800MCT ............................................... 0 o c to +70 o c ........................................ 16-pin wsoic SP800MCT/tr ......................................... 0 o c to +70 o c ........................................ 16-pin wsoic sp800mep ............................................. -40 o c to +85 o c .......................................... 16-pin pdip sp800men ............................................ -40 o c to +85 o c ....................................... 16-pin nsoic sp800men/tr ....................................... -40 o c to +85 o c ....................................... 16-pin nsoic sp800met ............................................. -40 o c to +85 o c ...................................... 16-pin wsoic sp800met/tr ....................................... -40 o c to +85 o c ...................................... 16-pin wsoic ordering information corporation analog excellence sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 available in lead free packaging. to order add ?-l? suffix to part number. example: sp800men/tr = standard; sp800men-l/tr = lead free /tr = tape and reel pack quantity is 2500 for nsoic and wsoic.

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