1 ps8460e 08/16/02 1 2 3 4 5 6 7 8 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 32 31 30 29 28 27 26 25 q1 q2 gnd v ddq q3 q4 q5 gnd v ddq q6 q7 v ddq gnd q8 q9 v ddq gnd q10 q11 q12 v ddq gnd q13 q14 d1 d2 gnd v dd d3 d4 d5 d6 d7 clk clk v dd gnd v ref reset d8 d9 d10 d11 d12 v dd gnd d13 d14 product description pericom semiconductor?s PI74SSTV16857 series of logic circuits are produced using the company?s advanced 0.35 micron cmos technology, achieving industry leading speed. the 14-bit PI74SSTV16857 universal bus driver is designed for 2.3v to 2.7v v dd operation and sstl_2 i/o levels except for the reset input which is lvcmos. data flow from d to q is controlled by the differential clock , clk, clk and reset. data is triggered on the positive edge of clk. clk must be used to maintain noise margins. reset must be supported with lvcmos levels as v ref may not be stable during power-up. reset is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the low state, q outputs are low, and all input receivers, data and clock, are switched off. pericom?s PI74SSTV16857 is characterized for operation from 0 to 70c. product features ? pi74 sstv16857 is designed for low-voltage operation, v dd = v ddq = 2.3v to 2.7v ? supports sstl_2 class i and ii specifications ? sstl_2 input and output levels ? designed for ddr memory ? flow-through architecture ? package available: ? 48-pin 240 mil wide plastic tssop (a) ? 48-pin 173 mil wide plastic tvsop (k) logic block diagram product pin configuration pin name description reset reset (active low) clk clock input clk clock input d data input q data output gnd ground v dd core supply voltage v ddq output supply voltage v ref input reference voltage product pin description 48-pin a, k s t u p n is t u p t u o t e s e rk l ck l cdq lxxxl h hh ? ll hh r o lh r o lxo q ) 2 ( truth table (1) notes: 1. h = high signal level l = low signal level = transition low-to-high = transition high-to-low x = irrelevant 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI74SSTV16857 14-bit registered buffer 2. output level before the indicated steady state input conditions were established. to 13 other channels reset clk 38 39 v ref d1 48 35 d r clk q1 1 clk v 34
2 ps8460e 08/16/02 PI74SSTV16857 14-bit registered buffer 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 v d d e g a t l o v y l p p u s3 . 25 . 27 . 2 v v q d d e g a t l o v y l p p u s o / i3 . 25 . 27 . 2 v f e r v e g a t l o v e c n e r e f e r f e r v x 5 . 0 = q d d 5 1 . 15 2 . 15 3 . 1 v t t e g a t l o v n o i t a n i m r e tv f e r 4 0 . 0 ?v f e r v f e r 4 0 . 0 + v h i e g a t l o v h g i h t u p n i c ds t u p n i a t a dv f e r 1 . 0 +5 v q d d 3 . 0 + v l i e g a t l o v w o l t u p n i c d3 . 0 ?v f e r 5 1 . 0 ? v h i e g a t l o v h g i h t u p n i t e s e r 7 . 1v q d d 3 . 0 + v l i e g a t l o v w o l t u p n i3 . 0 ?8 . 0 v n i l e v e l e g a t l o v t u p n i k l c , k l c 3 . 0 ? v d i e g a t l o v l a i t n e r e f f i d t u p n i6 3 . 0v q d d 6 . 0 + v x i r i a p k c o l c l a i t n e r e f f i d f o e g a t l o v t n i o p s s o r cv ( q d d 2 . 0 ? ) 2 /v ( q d d 2 . 0 + ) 2 / i h o t n e r r u c t u p t u o l e v e l - h g i h0 2 ?a m i l o t n e r r u c t u p t u o l e v e l - w o l0 2 t a e r u t a r e p m e t r i a - e e r f g n i t a r e p o00 7c o note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) notes: 1. the input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. this current will flow only when the output is in the high state level v o > v ddq . 3. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions m e t is n o i t i d n o c / l o b m y ss g n i t a rs t i n u e r u t a r e p m e t e g a r o t st g t s 0 5 1 o t 5 6 ?c e g a t l o v y l p p u sv d d v r o q d d 6 . 3 o t 5 . 0 ? v e g a t l o v t u p n i ) 1 ( v i v o t 5 . 0 ? d d 5 . 0 + e g a t l o v t u p t u o ) 2 , 1 ( v o v o t 5 . 0 ? q d d 5 . 0 + t n e r r u c p m a l c t u p n ii k i v , i 0 <0 5 ? a m t n e r r u c p m a l c t u p t u oi k o v , o 0 <0 5 t n e r r u c t u p t u o s u o u n i t n o ci o v , o v o t 0 = q d d 0 5 v d d v , q d d n i p / t n e r r u c d n g r oi d d i , q d d i r o d n g 0 0 1 e c n a d e p m i l a m r e h t e g a k c a p ) 3 ( j a 0 7w / c
PI74SSTV16857 14-bit registered buffer 3 ps8460e 08/16/02 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 s r e t e m a r a ps n o i t i d n o c t s e tv cc . n i m. p y t ) 1 ( . x a ms t i n u v k i i i 8 1 ? =ma v 3 . 22 . 1 ? v v o h i oh =? 0 0 1a v 7 . 2 - v 3 . 2v d d ?v 2 . 0 i oh 6 1 ? =ma v 3 . 25 9 . 1 v o l i ol = 0 0 1a v 7 . 2 - v 3 . 22 . 0 i oh 6 1 =ma v 3 . 25 3 . 0 i i , s t u p n i l l av i v = d d d n g r ov 7 . 25 a i d d ) c i t a t s ( y b d n a t sd n g = t e s e r i o =0 v 7 . 2 0 1 c i t a t s g n i t a r e p o v i v = h i ) c a (r ov i , ) c a ( v = t e s e r d d 6 5a m i d d d c i m a n y d k c o l c - g n i t a r e p o y l n o v = t e s e r d d v i v = h i) c a ( v r o ) c a ( l i , g n i h c t i w s k c d n a k c e l c y c y t u d % 0 5 2 5 / a k c o l c z h m c i m a n y d r e p - g n i t a r e p o t u p n i a t a d h c a e v = t e s e r d d v i v = h i) c a ( v r o ) c a ( l i , g n i h c t i w s k c d n a k c a t a d e n o . e l c y c y t u d % 0 5 k c o l c f l a h t a g n i h c t i w s t u p n i e l c y c y t u d % 0 5 , y c n e u q e r f 9 / a k c o l c z h m a t a d r h o h g i h t u p t u oi h o a m 0 2 ? =v 7 . 2 - v 3 . 27 0 2 m h o r l o w o l t u p t u oi l o a m 0 2 =v 7 . 2 - v 3 . 27 0 2 r o () r h o- r l o i o t , a m 0 2 = a c 5 2 = v 5 . 2 6 c i s t u p n i a t a dv i v = f e r v m 0 5 3 0 . 25 . 3 f p k c d n a k cv r c i v , v 5 2 . 1 = ) p p ( i v m 0 6 3 =v 5 . 20 . 25 . 3 notes: 4. typical values are at v dd = nominal v dd , t a = +25c. dc electrical characteristics (over the operating range, t a = 0c to +70c, v dd = 2.5v 200mv, v ddq = 2.5v 200mv) ?
4 ps8460e 08/16/02 PI74SSTV16857 14-bit registered buffer 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 2 5 2 0 k c o l c fy c n e u q e r f k c o l c 0 0 2z h m t w n o i t a r u d e s l u p5 . 2 s n t t c a e m i t e v i t c a s t u p n i l a i t n e r e f f i d ) 5 ( 2 2 t t c a n i e m i t e v i t c a n i s t u p n i l a i t n e r e f f i d e t a r w e l s t u p t u o ) 6 ( 2 2 t u s e t a r w e l s t s a f , e m i t p u t e s ) 9 , 7 ( k c , k c e r o f e b a t a d 5 7 . 0 e t a r w e l s w o l s , e m i t p u t e s ) 9 , 8 ( 9 . 0 t h e t a r w e l s t s a f , e m i t d l o h ) 9 , 7 ( k c , k c e r o f e b a t a d 5 7 . 0 e t a r w e l s w o l s , e m i t d l o h ) 9 , 8 ( 9 . 0 r e t e m a r a p m o r f ) t u p n i ( o t ) t u p t u o ( v d d v 2 . 0 v 5 . 2 = s t i n u . n i m. p y t. x a m f x a m 0 0 2z h m t d p k l c , k l cq1 . 18 . 2 s n t l h p t e s e rq 0 . 5 timing requirements (over recommended operating free-air temperature range , unless otherwise noted ) switching characteristics (over recommended operating free-air temperature range, unless otherwise noted.) (see test circuits and switching waveforms). notes: 5. data inputs must be held low for a minimum time of t act min , after reset is taken high 6. data and clock inputs must be held at valid levels (not floating) for a minimum time of t inact min, after reset is taken low. 7. data signal input slew rate 1 v/ns 8. data signal input slew rate 0.5v/ns and <1v/ns 9. clk, clk input slew rates are 1 v/ns.
PI74SSTV16857 14-bit registered buffer 5 ps8460e 08/16/02 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 voltage and current waveforms input active and inactive times voltage waveforms - pulse duration voltage waveforms - setup and hold times test circuit and switching waveforms notes: 8. c l includes probe and jig capacitance. 9. i dd tested with clock and data inputs held at v dd or gnd, and i o = 0ma. 10. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ?. input slew rate = 1v/ns 20% (unless otherwise specified). 11. the outputs are measured one at a time with one transition per measurement. 12. v tt = v ref = v ddq /2 13. v ih = v ref + 350mv (ac voltage levels) for sstl inputs. v ih = v dd for lvcmos input. 14. v il = v ref + 350mv (ac voltage levels) for sstl inputs. v il = gnd for lvcmos input. 15. t plh and t phl are the same as t pd . parameter measurement information (v dd = 2.5v 0.2v) load circuit input v il v ref v ref t w v ih input timing input t h t su v il v icr v ref v ref v i(pp) v ih voltage waveforms - propagation delay times timing input output v icr t plh t phl v icr v i(pp) v oh v tt v tt v ol lvcmos reset input output t phl v dd /2 v oh v ih v il v tt v ol voltage waveforms - propagation delay times v tt r l = 50 ? from output under test cl = 30pf (8) test point lvcmos reset input i dd (9) v dd v dd /2 t inact 0v i ddh 10% 90% i ddl t act
6 ps8460e 08/16/02 PI74SSTV16857 14-bit registered buffer 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 .236 .244 .488 .496 .002 .006 seating plane .007 .010 .0197 bsc .004 .008 .319 1 48 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 1.20 max bsc 48-pin tssop package (a) pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com 48-pin tssop package (k) .378 .386 .047 .031 .041 seating plane .0051 .009 .016 bsc 1 48 .169 .177 9.60 9.80 4.30 4.50 0.40 0.13 0.23 0.80 1.05 x.xx x.xx denotes dimensions in millimeters .002 .006 0.05 0.15 .0035 .008 0.09 0.20 .018 .030 0.45 0.75 .252 bsc 6.4 max. 1.20 ordering information e d o c g n i r e d r oe p y t e g a k c a pe g n a r g n i r e d r o a 7 5 8 6 1 v t s s 4 7 i pp o s s t l i m - 0 4 2 n i p - 8 4 c 5 8 o t c 0 4 ? k 7 5 8 6 1 v t s s 4 7 i pp o s v t l i m - 3 7 1 n i p - 8 4
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