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1 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface august 1999 ?1999 fairchild semiconductor corporation nm24c16u/nm24c17u 16k-bit serial eeprom 2-wire bus interface general description the nm24c16u/17u devices are 16k (16,384) bit serial interface cmos eeproms (electrically erasable programmable read- only memory). these devices fully conform to the standard i 2 c 2-wire protocol which uses clock (scl) and data i/o (sda) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the eeprom device). in addi- tion, the serial interface allows a minimal pin count packaging designed to simplify pc board layout requirements and offers the designer a variety of low voltage and low power options. nm24c17u incorporates a hardware "write protect" feature, by which, the upper half of the memory can be disabled against programming by connecting the wp pin to v cc . this section of memory then effectively becomes a rom (read-only memory) and can no longer be programmed as long as wp pin is connected to v cc . fairchild eeproms are designed and tested for applications requir- ing high endurance, high reliability and low power consumption for a continuously reliable non-volatile solution for all markets. block diagram functions i 2 c compatible interface 4,096 bits organized as 512 x 8 extended 2.7v ?5.5v operating voltage 100 khz or 400 khz operation self timed programming cycle (6ms typical) "programming complete" indicated by ack polling nm24c17u: memory "upper block" write protect pin features the i 2 c interface allows the smallest i/o pincount of any eeprom interface 16 byte page write mode to minimize total write time per byte typical 200 a active current (i cca ) typical 1 a standby current (i sb ) for "l" devices and 0.1 a standby current for "lz" devices endurance: up to 1,000,000 data changes data retention greater than 40 years h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic ck d in r/w sda scl v ss wp v cc d out ds800010-1 i 2 c is a registered trademark of philips electronics n.v.
2 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface connection diagrams dual-in-line package (n), 8-pin so package (m8) top view see package number n08e, m08a and mtc08 pin names v ss ground sda serial data i/o scl serial clock input nc no connection v cc power supply dual-in-line package (n), 8-pin so package (m8) top view see package number n08e, m08a and mtc08 pin names v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply nc no connection nc nc nc v ss v cc wp scl sda 8 7 6 5 1 2 3 4 nc nc nc v ss v cc nc scl sda 8 7 6 5 1 2 3 4 nm24c16u nm24c17u ds800010-2 ds800010-4 8-pin tssop package (mt8) rotated die (24c16ut) nc v cc nc nc scl sda v ss nc 8 7 6 5 1 2 3 4 ds800010-3 nm24c16ut 8-pin tssop package (mt8) rotated die (24c17ut) ds800010-5 wp v cc nc nc scl sda v ss nc 8 7 6 5 1 2 3 4 nm24c17ut
3 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface ordering information nm 24 c xx u f t lz e xx letter description package n 8-pin dip m8 8-pin soic mt8 8-pin tssop temp. range none 0 to 70 c v -40 to +125 c e -40 to +85 c voltage operating range blank 4.5v to 5.5v l 2.7v to 5.5v lz 2.7v to 5.5v and <1 a standby current blank normal pin out t rotated die pin out scl clock frequency blank 100khz f 400khz ultralite cs100ul process density 16 16k 17 16k with write protect c cmos technology w total array write protect interface 24 iic nm fairchild non-volatile memory
4 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface product specifications absolute maximum ratings ambient storage temperature 65 c to +150 c all input or output voltages with respect to ground 6.5v to 0.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature nm24c16u/17u 0 c to +70 c nm24c16ue/17ue -40 c to +85 c nm24c16uv/17uv -40 c to +125 c positive power supply nm24c16u/17u 4.5v to 5.5v nm24c16ul/17ul 2.7v to 5.5v nm24c16ulz/17ulz 2.7v to 5.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd or v cc 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v low v cc (2.7v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.2 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.7v - 4.5v 1 10 a or v cc v cc = 2.7v - 4.5v 0.1 1 a v cc = 4.5v - 5.5v 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage 0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested.
5 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface ac conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.5 output load 1 ttl gate and c l = 100 pf read and write cycle limits (standard and low v cc range 2.7v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 s t su:dat data in setup time 250 100 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 300 50 ns t wr write cycle time - nm24c16u/17u 10 10 ms (note 3) - nm24c16u/17ul, nm24c16u/17ulz 15 15 note 3 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the nm24c16u/17u bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the dev ice does not respond to its slave address.
6 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc bus timing system layout typical system configuration note: due to open drain configuration of sda, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) example of 16k of memory on 2-wire bus device address pins memory size # of page a0 a1 a2 blocks nm24c16u/17u no connect no connect no connect 16,384 bits 8 ds800010-8 ds800010-20 scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto
7 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface device operation background information (iic bus) as mentioned, the iic bus allows synchronous bidirectional com- munication between transmitter/receiver using the scl (clock) and sda (data i/o) lines. all communication must be started with a valid start condition, concluded with a stop condition and acknowledged by the receiver with an acknowledge condi- tion. as shown below, the eeproms on the iic bus may be configured in any manner required, the total memory addressed can not exceed 16k (16,384 bits). eeprom memory address program- ming is controlled by 2 methods: all unused pins must be grounded (tied to v ss ). software addressing the required page block within the device memory array (as sent in the slave address string). for devices with densities greater than 16k, a different protocol, the extended iic protocol, is used. refer to nm24c32u datasheet (for example) for additional details. addressing an eeprom memory location involves sending a command string with the following information: [device type] [device address] [page block ad- dress] [byte address] definitions word 8 bits (byte) of data page 16 sequential addresses (one byte each) that may be programmed during a 'page write' programming cycle page block 2048 (2k) bits organized into 16 pages of addressable memory. (8 bits) x (16 pages) = 2048 bits master any iic device controlling the transfer of data (such as a microprocessor) slave device being controlled (eeproms are always considered slaves) transmitter device currently sending data on the bus (may be either a master or slave). receiver device currently receiving data on the bus (master or slave) pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. wp write protection (nm24c17u only) if tied to v cc , program operations onto the upper half of the memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/write over the entire memory is possible. this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. device operation the nm24c16u/17u supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the nm24c16u/17u will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 2 and figure 3 on next page. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the nm24c16u/17u continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the nm24c16u/17u to place the device in the standby power mode. write cycle timing acknowledge acknowledge is a hardware convention used to indicate success- ful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line to low to acknowledge that it received the eight bits of data. refer to figure 4.
8 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface ds800010-10 sda scl stop condition start condition word n 8th bit ack t wr write cycle timing (figure 1) note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. data validity (figure 2) start and stop definition (figure 3) acknowledge response from receiver (figure 4) scl from master data output from transmitter data output from receiver 189 start acknowledge sda scl start condition stop condition scl data stable data change sda ds800010-11 ds800010-12 ds800010-13
9 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface device type identifier 1 0 1 0 a2 a1 a0 r/w (lsb) nm24c16u/17u page block address ds800010-14 write cycle timing (continued) the nm24c16u/17u device will always respond with an acknowl- edge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the nm24c16u/17u will respond with an acknowledge after the receipt of each subsequent eight bit byte. in the read mode the nm24c16u/17u slave will transmit eight bits of data, release the sda line and monitor the line for an acknowl- edge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are those of the device type identifier ( see figure 5) . this is fixed as 1010 for all eeprom devices. slave addresses (figure 5) refer to the following table for slave addresses string details: device a0 a1 a2 page page block blocks addresses nm24c16u/17u p p p 8 000 001 010 011 ... 111 p: refers to an internal page block memory segment. all iic eeproms use an internal protocol that defines a page block size of 2k bits (for word addressess 0000 through 1111). therefore, address bits a0, a1, or a2 (if designated 'p') are used to access a page block in conjunction with the word address used to access any individual data byte (word). the last bit of the slave address defines whether a write or read condition is requested by the master. a '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. a simple review: after the nm24c16u/17u recognizes the start condition, the devices interfaced to the iic bus wait for a slave address to be transmitted over the sda line. if the transmitted slave address matches an address of one of the devices, the designated slave pulls the line low with an acknowledge signal and awaits further transmissions.
10 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface write operations byte write for a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. upon receipt of the byte address the nm24c16u/17u responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the nm24c16u/17u begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the nm24c16u/17u inputs are disabled, and the device will not respond to any requests from the master. refer to figure 6 for the address, acknowledge and data transfer sequence. page write the nm24c16u/17u is capable of a sixteen byte page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. after the receipt of each byte, the nm24c16u/17u will respond with an acknowledge. after the receipt of each byte, the internal address counter increments to the next address and the next sda data is accepted. if the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 7 for the address, acknowl- edge, and data transfer sequence. s t o p bus activity: master sda line bus activity: nm24c16u/17u data n + 15 data n + 1 data n word address (n) a c k s t a r t slave address a c k a c k a c k a c k s t o p a c k data a c k a c k s t a r t word address slave address bus activity: master sda line bus activity: nm24c16u/17u ds800010-15 ds800010-16 acknowledge polling once the stop condition is issued to indicate the end of the host s write operation the nm24c16u/17u initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the nm24c16u/17u is still busy with the write operation no ack will be returned. if the nm24c16u/17u has completed the write operation an ack will be returned and the host can then proceed with the next read or write operation. write protection (nm24c17u only) programming of the upper half of the memory will not take place if the wp pin of the nm24c17u is connected to v cc . the nm24c17u will accept slave and byte addresses; but if the memory accessed is write protected by the wp pin, the nm24c17u will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. byte write (figure 6) page write (figure 7)
11 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface s t o p a c k no a c k slave address a c k a c k s t a r t s t a r t word address slave address bus activity: master sda line bus activity: nm24c16u/17u data n s t o p a c k bus activity: master sda line bus activity: nm24c16u/17u a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address ds800010-18 ds800010-19 read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the nm24c16u/17u contains an address counter that maintains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to one, the nm24c16u/17u issues an acknowledge and transmits the eight bit byte. the master will not acknowledge the transfer but does generate a stop condition, and therefore the nm24c16u/ 17u discontinues transmission. refer to figure 8 for the se- quence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to one, the master must first perform a dummy write operation. the master issues the start condition, slave address and then the byte address it is to read. after the byte address acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the nm24c16u/17u and then by the eight bit data. the master will not acknowledge the transfer but does generate the stop condition, and therefore the nm24c16u/17u discontinues transmission. refer to figure 9 for the address, acknowledge and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the nm24c16u/17u continues to output data for each acknowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential, with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" and the nm24c16u/17u continues to output data for each acknowledge received. refer to figure 10 for the address, acknowledge, and data transfer sequence. current address read (figure 8) s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: nm24c16u/17u ds800010-17 random read (figure 9) sequential read (figure 10)
12 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface 8-pin molded small outline package (m8) package number m08a physical dimensions inches (millimeters) unless otherwise noted 8-pin molded thin shrink small outline package package number mtc08 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0098 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
13 www.fairchildsemi.com nm24c16u/17u rev. b.1 nm24c16u/nm24c17u C 16k-bit serial eeprom 2-wire bus interface physical dimensions inches (millimeters) unless otherwise noted molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841

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