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_______________general description the MAX536/max537 combine four 12-bit, voltage-output digital-to-analog converters (dacs) and four precision output amplifiers in a space-saving 16-pin package. offset, gain, and linearity are factory calibrated to provide the MAX536? ? lsb total unadjusted error. the max537 operates with ?v supplies, while the MAX536 uses -5v and +10.8v to +13.2v supplies. each dac has a double-buffered input, organized as an input register followed by a dac register. a 16-bit serial word is used to load data into each input/dac register. the serial interface is compatible with either spi/qspi or microwire, and allows the input and dac registers to be updated independently or simulta- neously with a single software command. the dac reg- isters can be simultaneously updated with a hardware ldac pin. all logic inputs are ttl/cmos compatible. ________________________applications industrial process controls automatic test equipment digital offset and gain adjustment motion control devices remote industrial controls microprocessor-controlled systems ____________________________features ? four 12-bit dacs with output buffers ? simultaneous or independent control of four dacs via a 3-wire serial interface ? power-on reset ? spi/qspi and microwire compatible ? ? lsb total unadjusted error (MAX536) ? full 12-bit performance without adjustments ? ?v supply operation (max537) ? double-buffered digital inputs ? buffered voltage output ? 16-pin dip/so packages ______________ ordering information MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 outc outd v dd tp agnd v ss outa outb top view MAX536 max537 refcd sdo sck cs sdi ldac dgnd refab dip/so + __________________ pin configuration MAX536/max537 dac a dac reg a input reg a dac b dac reg b input reg b dac c dac reg c input reg c dac d dac reg d input reg d decode control outa outb outc outd 16-bit shift register sr control cs sdi sck sdo ldac agnd dgnd v ss tp v dd refab refcd ________________functional diagram spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. 19-0230; rev 3; 3/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package inl (lsb) MAX536 acpe+ 0? to +70? 16 pdip ?.5 MAX536bcpe+ 0? to +70? 16 pdip ? MAX536acwe+ 0? to +70? 16 wide so ?.5 MAX536bcwe+ 0? to +70? 16 wide so ? MAX536aepe+ -40? to +85? 16 pdip ?.5 MAX536bepe+ -40? to +85? 16 pdip ? MAX536aewe+ -40? to +85? 16 wide so ?.5 MAX536bewe+ -40? to +85? 16 wide so ? + denotes a lead(pb)-free/rohs-compliant package. ordering information continued at end of data sheet.
parameter symbol conditions min typ max units static performance?nalog section resolution n12 bits MAX536a ?.0 t a = +25? MAX536b ?.0 MAX536ac ?.0 MAX536bc ?.0 MAX536ae ?.5 total unadjusted error (note 1) tue t a = t min to t max MAX536be ?.5 lsb MAX536a ?.15 ?.50 integral nonlinearity inl MAX536b ? lsb differential nonlinearity dnl guaranteed monotonic ? lsb MAX536a ?.5 t a = +25? MAX536b ?.0 MAX536ac ?.0 MAX536bc ?.5 MAX536ae ?.1 offset error t a = t min to t max MAX536be ?.5 mv r l = -0.1 ?.0 MAX536_c/e -0.6 ?.5 gain error r l = 5k ? MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface 2 ____________________________________________________________________________________________________ v dd to agnd or dgnd MAX536 ............................................................-0.3v to +13.2v max537 .................................................................-0.3v to +7v v ss to agnd or dgnd ............................................-7v to +0.3v sdi, sck , cs , ldac , tp, sdo to agnd or dgnd..................................-0.3v to (v dd + 0.3v) refab, refcd to agnd or dgnd ..........-0.3v to (v dd + 0.3v) out_ to agnd or dgnd ..........................................v dd to v ss maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) plastic dip (derate 10.53mw/? above +70?) ................. 842mw wide so (derate 9.52mw/? above +70?).................762mw operating temperature ranges max53_ac_e/bc_e.............................................0? to +70? max53_ae_e/be_e ..........................................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? electrical characteristics?ax536 (v dd = +12v, v ss = -5v, refab/refcd = 8v, agnd = dgnd = 0v, r l = 5k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings
parameter symbol conditions min typ max units matching performance (t a = +25?) MAX536a ?.0 total unadjusted error tue MAX536b ?.0 lsb gain error ?.1 ?.0 lsb MAX536a ?.2 ?.5 offset error MAX536b ?.2 ?.0 mv integral nonlinearity inl ?.2 ?.0 lsb reference input reference input range ref 0 v d d - 4 v reference input resistance r ref code dependent, minimum at code 555 5k ? multiplying-mode performance reference 3db bandwidth v ref = 2v p-p 700 khz v ref = 10v p-p at 400hz -100 reference feedthrough input code = all 0s v ref = 10v p-p at 4khz -82 db total harmonic distortion plus noise thd+n v ref = 2.0v p-p at 50khz 0.024 % digital inputs (sdi, sck, cs , ldac ) input high voltage v ih 2.4 v input low voltage v il 0.8 v input leakage current v in = 0v or v dd 1.0 ? input capacitance (note 2) 10 pf digital output (sdo) output low voltage v ol sdo sinking 5ma 0.13 0.40 v output leakage current sdo = 0v to v dd ?0 ? dynamic performance (r l = 5k ? , c l = 100pf) voltage output slew rate 5 v/? output settling time to ?.5 lsb of full scale 3 s digital feedthrough 5 nv-s digital crosstalk (note 3) v ref = 5v 8 nv-s power supplies positive supply range v dd 10.8 13.2 v negative supply range v ss -4.5 -5.5 v t a = +25? 8 18 positive supply current (note 4) i dd t a = t min to t max 25 ma t a = +25? -6 -16 negative supply current (note 4) i ss t a = t min to t max -23 ma MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface _______________________________________________________________________________________ 3 electrical characteristics?ax536 (continued) (v dd = +12v, v ss = -5v, refab/refcd = 8v, agnd = dgnd = 0v, r l = 5k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.)
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface 4 _______________________________________________________________________________________ electrical characteristics?ax536 (continued) (v dd = +12v, v ss = -5v, refab/refcd = 8v, agnd = dgnd = 0v, r l = 5k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units t por 20 s sck clock period t cp 100 ns sck pulse width high t ch 30 ns sck pulse width low t cl 30 ns t css 20 ns t csh 10 ns sdi setup time t ds 40 26 ns sdi hold time t dh 0 ns t do1 1k ? pullup on sdo to v dd, c load = 50pf sdo high 78 105 ns sdo low 50 80 sck fall to sdo valid propagation delay (note 7) t do2 1k ? pullup on sdo to v dd, c l oad = 50pf sdo high 81 110 ns sdo low 53 85 t dv 27 45 ns t tr 40 60 ns sck rise to cs fall delay t cs0 continuous sck, sck edge ignored 20 ns t cs1 sck edge ignored 20 ns ldac pulse width low t ldac 30 ns cs pulse width high t csw 40 ns internal power-on reset pulse width (note 2) cs fall to sck rise setup time sck rise to cs rise hold time sck rise to sdo valid propagation delay (note 6) cs fall to sdo enable (note 8) cs rise to sdo disable (note 9) cs rise to sck rise hold time note 1: tue is specified with no resistive load. note 2: guaranteed by design. note 3: crosstalk is defined as the glitch energy at any dac output in response to a full-scale step change on any other dac . note 4: digital inputs at 2.4v; with digital inputs at cmos levels, i dd decreases slightly. note 5: all input signals are specified with t r = t f 5ns. logic input swing is 0 to 5v. note 6: serial data clocked out of sdo on sck? falling edge. (sdo is an open-drain output for the MAX536. the max537? sdo pin has an internal active pullup.) note 7: serial data clocked out of sdo on sck? rising edge. note 8: sdo changes from high-z state to 90% of final value. note 9: sdo rises 10% toward high-z state. timing characteristics (note 5)
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface _______________________________________________________________________________________ 5 electrical characteristics?ax537 (v dd = +5v, v ss = -5v, refab/refcd = 2.5v, agnd = dgnd = 0v, r l = 5k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units static performance?nalog section resolution n12 bits max537a ?.15 ?.50 integral nonlinearity inl max537b ? lsb differential nonlinearity dnl guaranteed monotonic ? lsb max537a ?.0 t a = +25? max537b ?.0 max537ac ?.0 max537bc ?.0 max537ae ?.0 offset error t a = t min to t max max537be ?1.0 mv r l = -0.3 ?.5 gain error r l = 5k ? -0.8 ?.0 lsb v d d p ow er - s up p l y rej ecti on rati o psrr t a = +25?, 4.5v v dd 5.5v ?.01 ?.5 lsb/v v s s p ow er - s up p l y rej ecti on rati o psrr t a = +25?, -5.5v v ss -4.5v ?.02 ?.7 lsb/v matching performance (t a = +25?) gain error ?.1 ?.25 lsb max537a ?.3 ?.0 offset error max537b ?.3 ?.0 mv integral nonlinearity inl ?.35 ?.0 lsb reference input reference input range ref 0 v d d - 2.2 v reference input resistance rref code dependent, minimum at code 555 hex 5 k ? multiplying-mode performance reference 3db bandwidth v ref = 2v p-p 700 khz v ref = 10v p-p at 400hz -100 reference feedthrough input code = all 0s v ref = 10v p-p at 4khz -82 db total harmonic distortion plus noise thd+n v ref = 850mv p-p at 100khz 0.024 % digital inputs (sdi, sck, cs, ldac) input high voltage v ih 2.4 v input low voltage v il 0.8 v input leakage current v in = 0v or v dd 1.0 ? input capacitance (note 2) 10 pf
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface 6 _______________________________________________________________________________________ electrical characteristics?ax537 (continued) (v dd = +5v, v ss = -5v, refab/refcd = 2.5v, agnd = dgnd = 0v, r l = 5k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units digital output (sdo) output high voltage v oh sdo sourcing 2ma v dd - 0.5 v dd - 0.25 v output low voltage v ol sdo sinking 2ma 0.13 0.40 v dynamic performance (r l = 5k ? , c l = 100pf) voltage output slew rate 5 v/? output settling time to ?.5 lsb of full scale 5 ? digital feedthrough 5 nv-s digital crosstalk (note 3) 5 nv-s power supplies positive supply range v dd 4.5 5.5 v negative supply range v ss -4.5 -5.5 v t a = +25? 5.5 12 positive supply current (note 4) i dd t a = t min to t max 16 ma t a = +25? -4.7 -10 negative supply current (note 4) i ss t a = t min to t max -14 ma timing characteristics (note 5) internal power-on reset pulse width (note 2) t por 50 ? sck clock period t cp 100 ns sck pulse width high t ch max537_c/e 35 ns sck pulse width low t cl max537_c/e 35 ns cs fall to sck rise setup time t css max537_c/e 40 ns sck rise to cs rise hold time t csh 0 ns sdi setup time t ds max537_c/e 40 24 ns sdi hold time t dh 0ns sck rise to sdo valid propagation delay (note 6) t do1 c load = 50pf, max537_c/e 116 200 ns sck fall to sdo valid propagation delay (note 7) t do2 c load = 50pf, max537_c/e 123 210 ns
note 2: guaranteed by design. note 3: crosstalk is defined as the glitch energy at any dac output in response to a full-scale step change on any other dac . note 4: digital inputs at 2.4v; with digital inputs at cmos levels, i dd decreases slightly. note 5: all input signals are specified with t r = t f 5ns. logic input swing is 0 to 5v. note 6: serial data clocked out of sdo on sck? falling edge. (sdo is an open-drain output for the MAX536. the max537? sdo pin has an internal active pullup.) note 7: serial data clocked out of sdo on sck? rising edge. note 10: when disabled, sdo is internally pulled high. MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface _______________________________________________________________________________________ 7 electrical characteristics?ax537 (continued) (v dd = +5v, v ss = -5v, refab/refcd = 2.5v, agnd = dgnd = 0v, r l = 5k ? , c l = 100pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units cs fall to sdo enable t dv c load = 50pf, max537_c/e 75 140 ns cs rise to dso disable (note 10) t tr c load = 50pf, max537_c/e 70 130 ns sck rise to cs fall delay t cso continuous sck, sck edge ignored 35 ns cs rise to sck rise hold time t cs1 sck edge ignored, max537_c/e 35 ns ldac pulse width high t ldac max537_c/e 50 ns cs pulse width high t csw max537_c/e 100 ns
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface 8 _______________________________________________________________________________________ __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.) inl error (lsb) -1.0 0 reference voltage (v) MAX536/7-01 4 8 12 16 --0.6 -0.2 0.2 0.6 1.0 v dd = +15v v dd = +12v v ss = -5v MAX536 integral nonlinearity error vs. reference voltage 1k 10k 100k MAX536 reference voltage input frequency response MAX536/7-02 frequency (hz) relative output (db) 1m 10m -50 -40 -30 -20 -10 10 20 0 refab swept 2v p-p v outa monitored 10 100 200 MAX536 total harmonic distortion plus noise vs. reference frequency max1536/7-03 frequency (khz) thd + noise (%) 0.200 0.175 0.150 0.125 0.100 0.075 0.050 0.025 0 dac code = all 1s refab = 10v p-p r l = 10k ? , c l = 100pf r l = no load, c l = 0pf 1 -5 0.1 10 1000 MAX536 full-scale error vs. load -4 MAX536/7-04 load (k ? ) full-scale error (lsb) -3 -2 -1 1100 0 MAX536 supply current vs. temperature supply current (ma) -10 -60 temperature (?) MAX536/7-05 -6 -2 2 6 10 -20 20 60 100 140 v dd = +15v v ss = -5v i ss i dd input code = all 0s 500 s/div refab, 5v/div 0v outa, 100 v/div MAX536 reference feedthrough at 400hz input code = all 0s MAX536 reference feedthrough at 4khz 50 s/div refab, 5v/div 0v outa, 200 v/div 10 100 200 MAX536 total harmonic distortion plus noise vs. reference frequency max1536/7-03b frequency (khz) thd + noise (%) 0.200 0.175 0.150 0.125 0.100 0.075 0.050 0.025 0 dac code = all 1s refab = 5v p-p r l = no load, c l = 0pf r l = 10k ? , c l = 100pf MAX536
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface _______________________________________________________________________________________ 9 ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) v dd = +15v, v ss = -5v, refab = 5v, c l = 100pf, r l = 10k ? MAX536 dynamic response (all bits on, off, on) 5 s/div cs, 5v/div outa, 2v/div v dd = +15v, v ss = -5v, refab = 10v, c l = 100pf, r l = 10k ? MAX536 negative full-scale settling time (all bits on to all bits off) 1 s/div cs, 5v/div outa, 5v/div outa, 5mv/div v dd = +15v, v ss = -5v, refab = 10v, c l = 100pf, r l = 10k ? MAX536 positive full-scale settling time (all bits off to all bits on) 1 s/div cs, 5v/div outa, 5v/div outa, -10v offset 5mv/div v dd = +15v, v ss = -5v, refab = 10v, cs = high, din toggling at 1 2 the clock rate, outa = 5v MAX536 digital feedthrough sck, 5v/div outa, ac-coupled, 10mv/div MAX536
input code = all 0s max537 reference feedthrough at 400hz 500 s/div refab, 1v/div 0v outa, ac-coupled, 100 v/div input code = all 0s max537 reference feedthrough at 4khz 50 s/div refab, 1v/div 0v outa, ac-coupled, 100 v/div MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface 10 ______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) inl error (lsb) -2.0 0 v ref (v) MAX536/7-06 12 45 -0.5 0.5 1.0 2.0 max537 integral nonlinearity error vs. reference voltage -1.5 -1.0 0 1.5 3 v dd = +5v v ss = -5v 1k 10k 100k max537 reference voltage input frequency response MAX536/7-07 frequency (hz) relative output (db) 1m 10m -50 -40 -30 -20 -10 10 20 0 refab swept 2v p-p v outa monitored 10 100 200 max537 total harmonic distortion plus noise vs. frequency max1536/7-14 frequency (khz) thd + noise (%) 0.200 0.175 0.150 0.125 0.100 0.075 0.050 0.025 0 refab = 2.5v p-p r l = 10k ? , c l = 100pf r l = no load, c l = 0pf max537 10 100 200 max537 total harmonic distortion plus noise vs. frequency max1536/7-09 frequency (khz) thd + noise (%) 0.200 0.175 0.150 0.125 0.100 0.075 0.050 0.025 0 refab = 1v p-p r l = 10k ? , c l = 100pf r l = no load, c l = 0pf -4 -3 0.1 10 1000 max537 full-scale error vs. load -2 MAX536/7-10 load (k ? ) full-scale error (lsb) -1 0 1 1 100 2 max537 supply current vs. temperature supply current (ma) -5 -60 temperature (?) MAX536/7-11 -3 -1 1 3 5 -20 20 60 100 140 v dd = +5v v ss = -5v i ss i dd
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface ______________________________________________________________________________________ 11 v dd = +5v, v ss = -5v, refab = 2.5v, c l = 100pf, r l = 10k ? max537 dynamic response (all bits on, off, on) 5 s/div cs, 5v/div outa, 1v/div v dd = +5v, v ss = -5v, refab = 2.5v, c l = 100pf, r l = 10k ? max537 negative full-scale settling time (all bits on to all bits off) 1 s/div cs, 5v/div outa, 5mv/div v dd = +5v, v ss = -5v, refab = 2.5v, c l = 100pf, r l = 10k ? max537 positive full-scale settling time (all bits off to all bits on) 1 s/div cs, 5v/div outa, 5mv/div v dd = +5v, v ss = -5v, refab = 2.5v, cs = high, din toggling at 1 2 the clock rate, outa = 1.25v max537 digital feedthrough 100ns/div sck, 5v/div outa, ac-coupled, 20mv/div ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) max537
MAX536/max537 _______________detailed description the MAX536/max537 contain four 12-bit voltage-output dacs that are easily addressed using a simple 3-wire serial interface. they include a 16-bit data-in/data-out shift register, and each dac has a double-buffered input composed of an input register and a dac register (see the functional diagram on the front page). the dacs are ?nverted?r-2r ladder networks that convert 12-bit digital inputs into equivalent analog out- put voltages in proportion to the applied reference-volt- age inputs. dac a and dac b share the refab refer- ence input, while dac c and dac d share the refcd reference input. the two reference inputs allow different full-scale output voltage ranges for each pair of dacs. figure 1 shows a simplified circuit diagram of one of the four dacs. reference inputs the two reference inputs accept positive dc and ac signals. the voltage at each reference input sets the full-scale output voltage for its two correspond- ing dacs. the refab/refcd voltage range is 0v to (v dd - 4v) for the MAX536 and 0v to (v dd - 2.2v) for the max537. the output voltages v out _ are represented by a digitally programmable voltage source as: v out_ = n b (v ref) /4096 where n b is the numeric value of the dac? binary input code (0 to 4095) and v ref is the reference voltage. calibrated, quad, 12-bit voltage-output dacs with serial interface 12 ______________________________________________________________________________________ ______________________________________________________________pin description pin name function outb dac b output voltage 2 outa dac a output voltage 3 v ss negative power supply agnd analog ground 5 refab reference voltage input for dac a and dac b 6 dgnd digital ground 7 ldac 8 sdi serial data input. data is shifted into an internal 16-bit shift register on sck's rising edge. 9 cs 10 sck 11 sdo 12 refcd reference voltage input for dac c and dac d 13 tp test pin. connect to v dd for proper operation. 14 v dd positive power supply 15 outd dac d output voltage 1 4 16 dac c output voltage load dac input (active low). driving this asynchronous input low transfers the contents of all input registers to their respective dac registers. chip-select input (active low). a low level on cs enables the input shift register and sdo. on cs ? rising edge, data is latched into the appropriate register(s). shift register clock input serial data output. sdo is the output of the internal shift register. sdo is enabled when cs is low. for the MAX536, sdo is an open-drain output. for the max537, sdo has an active pullup to v dd . outc v out shown for all 1s on dac d0 d9 d10 d11 2r 2r 2r 2r 2r rrr ref agnd figure 1. simplified dac circuit diagram
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface the input impedance at each reference input is code dependent, ranging from a low value of typically 6k ? (with an input code of 0101 0101 0101) to a high value of 60k ? (with an input code of 0000 0000 0000). since the input impedance at the reference pins is code dependent, load regulation of the reference source is important. the refab and refcd reference inputs have a 5k ? guaranteed minimum input impedance. when the two reference inputs are driven from the same source, the effective minimum impedance becomes 2.5k ? . the reference input capacitance is also code depen- dent and typically ranges from 125pf to 300pf. output buffer amplifiers all MAX536/max537 voltage outputs are internally buffered by precision unity-gain followers with a typical slew rate of 5v/ s for the MAX536 and 3v/ s for the max537. with a full-scale transition at the MAX536 output (0 to 8v or 8v to 0), the typical settling time to ?.5 lsb is 3 s when loaded with 5k ? in parallel with 100pf (loads less than 5k ? degrade performance). with a full-scale transition at the max537 output (0 to 2.5v or 2.5v to 0), the typical settling time to ?.5 lsb is 5 s when loaded with 5k ? in parallel with 100pf (loads less than 5k ? degrade performance). output dynamic responses and settling performances of the MAX536/max537 output amplifier are shown in the typical operating characteristics . serial-interface configurations the MAX536/max537? 3-wire or 4-wire serial interface is compatible with both microwire (figure 2) and spi/qspi (figure 3). in figures 2 and 3, ldac can be tied either high or low for a 3-wire interface, or used as the fourth input with a 4-wire interface. the connection between sdo and the serial-interface port is not neces- sary, but may be used for data echo. (data held in the shift register of the MAX536/max537 can be shifted out of sdo and returned to the microprocessor for data veri- fication; data in the MAX536/max537 input/dac regis- ters cannot be read.) with a 3-wire interface ( cs , sck, sdi) and ldac tied high, the dacs are double-buffered. in this mode, depending on the command issued through the serial interface, the input register(s) may be loaded without affecting the dac register(s), the dac register(s) can be loaded directly, or all four dac registers may be simultaneously updated from the input registers. with a 3- wire interface ( cs , sck, sdi) and ldac tied low (figure sck sdi sdo* cs ldac** sk so si* i/o i/o MAX536 max537 microwire port 5v *the sdo-si connection is not required for writing to the MAX536, but may be used for readback purposes. **the ldac connection is not required when using the 3-wire interface. ? the max537 has an internal active pullup to v dd, so r p is not necessary. ? r p 1k ? figure 2. connections for microwire figure 3. connections for spi/qspi sdo* sdi sck cs ldac** miso* mosi sck i/o i/o spi/qspi port ss 5v cpol = 0, cpha = 0 *the sdo-miso connection is not required for writing to the MAX536, but may be used for readback purposes. **the ldac connection is not required when using the 3-wire interface. MAX536 max537 ? r p 1k ? ? the max537 has an internal active pullup to v dd, so r p is not necessary. _______________________________________________________________________________________ 13
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface 14 ______________________________________________________________________________________ cs sck sdi sdo ldac* t cso t css t cl t ch t cp t do1 t tr t csw t csi t ldac t do2 t csh t ds t dh t dv *use of ldac is optional figure 6. detailed serial-interface timing diagram figure 4. 3-wire serial-interface timing diagram (ldac = gnd or v dd ) figure 5. 4-wire serial-interface timing diagram for asynchronous dac updating using ldac cs sck sdi sdo msb msb from previous write lsb lsb from previous write d15 d14 d13 d2 d1 d0 .......... q15 q0 command executed .......... .......... ........... 9 8 16 1 cs sck sdi sdo msb msb from previous write lsb lsb from previous write d15 d14 d13 d2 d1 d0 .......... q15 q0 input register(s) updated .......... .......... .......... 9 816 1 dacs updated ldac
4), the dac registers remain transparent. any time an input register is updated, the change appears at the dac output with the rising edge of cs . the 4-wire interface ( cs , sck, sdi, ldac ) is similar to the 3-wire interface with ldac tied high, except ldac is a hardware input that simultaneously and asynchronously loads all dac registers from their respective input regis- ters when driven low (figure 5). serial-interface description the MAX536/max537 require 16 bits of serial data. data is sent msb first and can be sent in two 8-bit packets or one 16-bit word ( cs must remain low until 16 bits are trans- ferred). the serial data is composed of two dac address bits (a1, a0), two control bits (c1, c0), and the 12 data bits d11?0 (figure 7). the 4-bit address/control code deter- mines the following: 1) the register(s) to be updated and/or the status of the input and dac registers (i.e., whether they are in transparent or latch mode), and 2) the edge on which data is clocked out of sdo. figure 6 shows the serial-interface timing requirements. the chip-select pin ( cs ) must be low to enable the dac? serial interface. when cs is high, the interface control circuitry is disabled and the serial data output pin (sdo) is driven high (max537) or is a high-impedance open drain (MAX536). cs must go low at least t css before the rising serial clock (sck) edge to properly clock in the first bit. when cs is low, data is clocked into the internal shift register via the serial data input pin (sdi) on sck? rising edge. the maximum guaranteed clock frequency is 10mhz. data is latched into the appropri- ate MAX536/max537 input/dac registers on cs s rising edge. interface timing is optimized when serial data is clocked out of the microcontroller/microprocessor on one clock edge and clocked into the MAX536/max537 on the other edge. table 1 lists the serial-interface programming commands. for certain commands, the 12 data bits are ?on? cares? the programming command load-all-dacs-from-shift- register allows all input and dac registers to be simultane- ously loaded with the same digital code from the input shift register. the nop (no operation) command allows the regis- ter contents to be unaffected and is useful when the MAX536/max537 are configured in a daisy-chain (see the daisy-chaining devices section). the command to change the clock edge on which serial data is shifted out of the MAX536/max537 sdo pin also loads data from all input reg- isters to their respective dac registers. serial-data output the serial-data output, sdo, is the internal shift register? output. the MAX536/max537 can be programmed so that data is clocked out of sdo on sck? rising (mode 1) or falling (mode 0) edge . in mode 0, output data at sdo lags input data at sdi by 16.5 clock cycles, maintaining compati- bility with microwire, spi/qspi, and other serial interfaces. in mode 1, output data lags input data by 16 clock cycles. on power-up, sdo defaults to mode 1 timing. for the MAX536, sdo is an open-drain output that should be pulled up to +5v. the data sheet timing specifications for sdo use a 1k ? pullup resistor. for the max537, sdo is a complementary output and does not require an external pullup. test pin the test pin (tp) is used for pre-production analysis of the ic. connect tp to v dd for proper MAX536/max537 operation. failure to do so affects dac operation . daisy-chaining devices any number of MAX536/max537s can be daisy-chained by connecting the sdo pin of one device (with a pullup resistor, if appropriate) to the sdi pin of the following device in the chain (figure 8). since the max537? sdo pin has an internal active pullup, the sdo sink/source capability determines the time required to discharge/charge a capacitive load. refer to the serial data out v oh and v ol specifications in the electrical characteristics. MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface ______________________________________________________________________________________ 15 msb ..................................................................................lsb 16 bits of serial data control bits data bits msb.............................................lsb a1 a0 c1 c0 d11................................................d0 12 data bits 4 address/ control bits address bits figure 7. serial-data format (msb sent first)
MAX536/max537 when daisy-chaining MAX536s, the delay from cs low to sck high (t css ) must be the greater of: t dv + t ds or t tr + t rc + t ds - t csw where t rc is the time constant of the external pullup resistor (r p ) and the load capacitance (c) at sdo. for t rc < 20ns, t css is simply t dv + t ds . calculate t rc from the following equation: t rc = r p (c) ln where v pullup is the voltage to which the pullup resistor is connected. additionally, when daisy-chaining devices, the maximum clock frequency is limited to: 1 f sck (max) = 2 (t do + t rc - 38ns + t ds ) for example, with t rc = 23ns (5v ?0% supply with r p = 1k ? and c = 30pf), the maximum clock frequency is 8.7mhz. figure 9 shows an alternate method of connecting sev eral MAX536/max537s. in this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. more i/o lines are required in this configu- ration because a dedicated chip-select input ( cs ) is required for each ic. calibrated, quad, 12-bit voltage-output dacs with serial interface 16 ______________________________________________________________________________________ v pullup v pullup - 2.4v table 1. serial-interface programming commands ??= don? care. ldac provides true latch control: when ldac is low, the dac registers are transparent; when ldac is high, the dac registers are latched. mode 0, dout clocked out on sck? falling edge. all dacs updated from their respective input registers. mode 1 (default condition at power-up), dout clocked out on sck? rising edge. all dacs updated from their respective input registers. load dac d input register; dac d is immediately updated. 0 12-bit dac data 1 x 1 1 load dac c input register; dac c is immediately updated. 0 12-bit dac data 1 x 0 1 load dac b input register; dac b is immediately updated. 0 12-bit dac data 1 x 1 0 load dac a input register; dac a is immediately updated. 0 12-bit dac data 1 0 x 0 x xxxxxxxxxxxx 0 1 0 1 x xxxxxxxxxxxx 0 1 1 1 update all dacs from their respective input registers. 1 xxxxxxxxxxxx 0 1 x 0 no operation (nop) x xxxxxxxxxxxx 0 0 1 x load all dacs from shift register. x 12-bit dac data 0 0 0 x load input register d; all dac registers updated. 1 12-bit dac data 1 1 1 1 load input register c; all dac registers updated. 1 12-bit dac data 1 1 0 1 load input register b; all dac registers updated. 1 12-bit dac data 1 1 1 0 load input register a; all dac registers updated. 1 12-bit dac data 1 1 0 0 load dac d input register; dac output unchanged. 1 12-bit dac data 1 0 1 1 load dac c input register; dac output unchanged. 1 12-bit dac data 1 0 0 1 load dac b input register; dac output unchanged. 1 12-bit dac data 1 0 1 0 load dac a input register; dac output unchanged. 1 12-bit dac data 1 0 0 0 d11?0 c0 c1 a0 a1 function ldac 16-bit serial word () [ ]
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface ______________________________________________________________________________________ 17 din cs to other serial devices MAX536 max537 sck sdi cs sdo +5v +5v +5v r p * 1k ? MAX536 max537 sck sdi cs sdo MAX536 max537 sck sdi cs sdo r p * 1k ? r p * 1k ? * the max537 has an active internal pullup, so r p is not necessary. sck figure 8. daisy-chaining MAX536/max537s with a 3-wire serial interface to other serial devices MAX536 max537 sdi sck ldac cs MAX536 max537 sdi sck ldac cs MAX536 max537 sdi sck ldac cs din sck ldac cs1 cs2 cs3 figure 9. multiple devices sharing a common din line may be simultaneously updated by bringing ldac low. cs1, cs2, cs3?are driven separately, thus controlling which data are written to devices 1, 2, 3
__________applications information interfacing to the m68hc11* port d of the 68hc11 supports spi. the four registers used for spi operation are the serial peripheral control register, the serial peripheral status register, the serial peripheral data i/o register, and port d? data direction register. these registers have a default starting location of $1000. on reset, the port d register (memory location $1008) is cleared and bits 5-0 are configured as general-purpose inputs. setting bit 6 (spe) of the serial peripheral control register (spcr) configures port d for spi as follows: bit 76543210 name ss sck mosi miso txd rxd bits 6 and 7 are not used. writes to these bits are ignored. the port d data direction register (ddrd) deter- mines whether the port bits are inputs or outputs. its configuration is shown below: setting ddd_ = 0 configures the port bit as an input, while setting ddd_ = 1 configures the port bit as an output. writes to bits 6 and 7 have no effect. in spi mode with mstr = 1, when a port d bit is expected to be an input ( ss , miso, rxd), the corresponding ddrd bit (ddd_) is ignored. if the bit is expected to be an output (sck, mosi, txd), the corresponding ddrd bit must be set for the bit to be an output. table 3. serial peripheral status-register definitions MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface 18 ______________________________________________________________________________________ name spie spe mstr cpol cpha spr1/0 spr1 spr0 0 0 ? clock divided by 2 0 1 ? clock divided by 4 1 0 ? clock divided by 16 1 1 ? clock divided by 32 definition when dwom is set, the six port d outputs are open drain. when dwom is cleared, the outputs are complementary. master/slave select option determines the clock phase. setting spe (serial peripheral system enable) configures port d for spi. clearing spe configures the port as a general- purpose i/o port. serial peripheral interrupt enable. clearing spie disables the spi hardware-interrupt request; the spsr is polled to determine when an spi data transfer is complete. setting spie requests a hardware interrupt when the serial peripheral status register? spif bit or modf bit is set. determines clock polarity. when set, the serial clock idles high while data is not being transferred; when cleared, the clock idles low. table 2. serial peripheral control-register definitions dwom spi clock-rate select name definition spif spif is set when an spi data transfer is complete. it is cleared by reading the spsr and then accessing the spdr. wcol modf the write collision flag is set when a write to the spdr occurs while a data transfer is in progress. it is cleared by read- ing the spsr and then accessing the spdr. the mode fault flag detects master/slave conflicts in a multimaster environment. it is set when the ?aster?controller has its ss line (port d) pulled low, and cleared by reading the spsr followed by a write to the spcr. *m68hc11 is a motorola microcontroller. general information about the device was obtained from m68hc11 technical manuals. bit 76543 210 name ddd5 ddd4 ddd3 ddd2 ddd1 ddd0
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface ______________________________________________________________________________________ 19 table 4. m68hc11 programming code
MAX536/max537 ss is an input intended for use in a multimaster environ- ment. however, ss or unused port d bit rxd, txd, or possibly miso (if dac readback is not used) should be configured as a general-purpose output and used as cs by setting the appropriate data direction register bit. the spcr configuration (memory location $1028) is shown below: when mstr = 1 in the spcr, a write to the serial peripheral data i/o register (spdr), located at memory location $102a, initiates the transmission/reception of data. the data transfer is monitored and the appropri- ate flags are set in the serial peripheral status register (spsr). the spsr configuration is shown below: an example of 68hc11 programming code for a two-byte spi transfer to the MAX536/max537 is given in table 4. ss is used for cs , the high byte of MAX536/ max537 digital data is stored in memory location $0100, and the low byte is stored in memory location $0101. interfacing to other controllers when using microwire, refer to the section on inter- facing to the m68hc11 for guidance, since microwire can be considered similar to spi when cpol = 0 and cpha = 0. when interfacing to intel? 80c51/80c31 microcontroller family, use bit-pushing to configure a desired port as the MAX536/max537 interface port. bit- pushing involves arbitrarily assigning i/o port bits as interface control lines, and then writing to the port each time a signal transition is required. unipolar output for a unipolar output, the output voltages and the reference inputs are the same polarity. figure 10 shows the MAX536/max537 unipolar output circuit, which is also the typ- ical operating circuit. table 5 lists the unipolar output codes. bipolar output the MAX536/max537 outputs can be configured for bipolar operation using figure 11? circuit. one op amp and two resistors are required per dac. with r1 = r2: v out = v ref [(2n b /4096) - 1] where n b is the numeric value of the dac? binary input code. table 6 shows digital codes and corresponding output voltages for figure 11? circuit. calibrated, quad, 12-bit voltage-output dacs with serial interface 20 ______________________________________________________________________________________ dac contents analog output msb lsb 4095 1111 1111 1111 +v ref ( ?) 4096 2049 1000 0000 0001 +v ref ( ?) 4096 2048 +v ref 1000 0000 0000 +v ref ( ?) = 4096 2 2047 0111 1111 1111 +v ref ( ?) 4096 1 0000 0000 0001 +v ref ( ?) 4096 0000 0000 0000 0v dac contents analog output msb lsb 2047 1111 1111 1111 +v ref ( ?) 2048 1 1000 0000 0001 +v ref ( ?) 2048 1000 0000 0000 0v 1 0111 1111 1111 -v ref ( ?) 2048 2047 0000 0000 0001 -v ref ( ?) 2048 2048 0000 0000 0000 -v ref ( ?) = -v ref 2048 table 5. unipolar code table table 6. bipolar code table note: 1 lsb = (v ref ) ( 4096 ) 1 bit 76543210 name spie spe dwom mstr cpol cpha spr1 spr0 setting after reset 00 0 0 0 1 u * u * setting for typical spi communication 0101000 ** 1 ** *u = unknown **depends on ? clock frequency. always configure the 68hc11 as the ?aster?controller and the MAX536/max537 as the ?lave?device. bit 7654 321 0 name spif wcol modf reset conditions 0000 000 0
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface ______________________________________________________________________________________ 21 MAX536 max537 dac a dac b dac c dac d outa 2 1 16 15 outb outc outd dgnd agnd v ss 3 4 6 -5v refab refcd 13 14 12 5 reference inputs +12v (+5v) note: ( ) are for max537. v dd tp figure 10. unipolar output circuit figure 11. bipolar output circuit v ref dac output r1 r2 +12v (+5v) v out ?v notes: ( ) are for max537. v ref is the selected reference input for the MAX536/max537. r1 = r2 = 10k ? 0.1% MAX536 max537 dac b outb MAX536/max537 10k ? 15k ? refab tp v dd v ss agnd dgnd 6 4 3 -5v 1 14 13 5 +12v (+5v) ac reference input +4v (+750mv) -4v (-750mv) notes: ( ) are for max537. digital inputs not shown. dac a outa MAX536/max537 refab tp v dd v ss dgnd 6 3 -5v 2 14 13 5 notes: ( ) are for max537. digital inputs not shown. + v in - + v bias - agnd 4 +12v (+5v) figure 12. ac reference input circuit figure 13. agnd bias circuit
MAX536/max537 using an ac reference in applications where the reference has ac signal compo- nents, the MAX536/max537 have multiplying capability within the reference input range specifications. figure 12 shows a technique for applying a sine-wave signal to the reference input where the ac signal is offset before being applied to refab/refcd. the reference voltage must never be more negative than dgnd. the MAX536? total harmonic distortion plus noise (thd+n) is typically less than 0.012%, given a 5v p-p signal swing and input frequencies up to 35khz, or given a 2v p-p swing and input frequencies up to 50khz. the typical -3db frequency is 700khz as shown in the typical operating characteristics graphs. for the max537, with an input signal amplitude of 0.85mv p-p , thd+n is typically less than 0.024% with a 5k ? load in parallel with 100pf and input frequencies up to 100khz, or with a 2k ? load in parallel with 100pf and input frequencies up to 95khz. offsetting agnd agnd can be biased from dgnd to the reference voltage to provide an arbitrary nonzero output voltage for a zero input code (figure 13). the output voltage v outa is: v outa = v bias + n b (v in ) where v bias is the positive offset voltage (with respect to dgnd) applied to agnd, and n b is the numeric value of the dac? binary input code. since agnd is common to all four dacs, all outputs will be offset by v bias in the same manner. as the voltage at agnd increases, the dac? resolution decreases because its full-scale voltage swing is effectively reduced. agnd should not be biased more negative than dgnd. power-supply considerations on power-up, v ss should come up first, v dd next, then refab or refcd. if supply sequencing is not possible, tie an external schottky diode between v ss and agnd as shown in figure 14. on power-up, all input and dac registers are cleared (set to zero code) and sdo is in mode 0 (serial data is shifted out of sdo on the clock? rising edge). for rated MAX536 performance, v dd should be 4v higher than refab/refcd and should be between 10.8v and 13.2v. when using the max537, v dd should be at least 2.2v higher than refab/refcd and should be between 4.75v and 5.5v. bypass both v dd and v ss with a 4.7 f capacitor in parallel with a 0.1 f capacitor to agnd. use short lead lengths and place the bypass capacitors as close to the supply pins as possible. grounding and layout considerations digital or ac transient signals between agnd and dgnd can create noise at the analog outputs. tie agnd and dgnd together at the dac, then tie this point to the highest quality ground available. good pcb ground layout minimizes crosstalk between dac outputs, reference inputs, and digital inputs. reduce crosstalk by keeping analog lines away from digital lines. wire-wrapped boards are not recommend- ed. calibrated, quad, 12-bit voltage-output dacs with serial interface 22 ______________________________________________________________________________________ MAX536 max537 1n5817 3 4 v ss agnd figure 14. when v ss and v dd cannot be sequenced, tie a schottky diode between v ss and agnd.
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface ______________________________________________________________________________________ 23 ordering information (continued) + denotes a lead(pb)-free/rohs-compliant package. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 pdip p16+9 21-0043 16 so w16+7 21-0042 90-0107 part temp range pin- package inl (lsb) max537 acpe+ 0? to +70? 16 pdip ?.5 max537bcpe+ 0? to +70? 16 pdip ? max537acwe+ 0? to +70? 16 wide so ?.5 max537bcwe+ 0? to +70? 16 wide so ? max537aepe+ -40? to +85? 16 pdip ?.5 max537bepe+ -40? to +85? 16 pdip ? max537aewe+ -40? to +85? 16 wide so ?.5 max537bewe+ -40? to +85? 16 wide so ?
MAX536/max537 calibrated, quad, 12-bit voltage-output dacs with serial interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/94 initial release 3 3/11 removed dice and ceramic sb packages and changed voltage supply specifications 1?, 13, 21, 22, 23

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