pc/104-plus series 4 6 w , t r i p l e o u t p u t d c / d c c o n v e r t e r 2 table 1. MAPC-104 input power header ????????????? ??????????? ????? ??????? ????? ??????? ? ? ? ? ? ? ? ?? ? ? ?? ?? ? ? ???? ??????? ???? ??????? ????? ?????? ?????????? ?????? ????????????????? ??????? ???????????????? ???????????? ??????? ???????????????? ????? ??????? ????? ?????? ????? ??????? ????? ??????? ???? ?????? ???? ?????? ???? ?????? ?????????? ?????? ?? ???? ??????? ????????????? ? ?????????????????? ?????????? ??? ? ? ??? ? ? m e c h a n i c a l s p e c i f i c a t i o n s case c46 dimensions are in inches (mm) iph mating connector: molex 5557 (39-01-4040) pin assignment functional description pin assignment functional description pin assignment functional description 1 ot_warn out overtemperature warning 1 ot_warn out overtemperature warning 1 ot_warn out overtemperature warning 1 ot_warn out overtemperature warning 2 pwr_led_drive out external power good led driver 2 pwr_led_drive out external power good led driver 2 pwr_led_drive out external power good led driver 2 pwr_led_drive out external power good led driver 3 v 3 v 3 v in C input ground C input ground 4 v 4 v 4 v in + positive input + positive input 0.718 (18.24) pin 2 +5vdc po wer out pin 1 gr ound 0.025 (0.64) squ are posts , 2 positions 0.295 (7.49) 0.10 (2.54) 0.10 (2.54) 0.10 (2.54) 5 volt auxiliary power connector, p2 (optional) top view
4 6 w , t r i p l e o u t p u t d c / d c c o n v e r t e r pc/104-plus series 3 j3/p3 pin a b c d 1 gnd 1 gnd ? reserved +5.1v ad00 reserved +5.1v ad00 reserved +5.1v ad00 2 vi/o ad02 ad01 +5.1v 2 vi/o ad02 ad01 +5.1v 3 ad05 gnd ad04 ad03 3 ad05 gnd ad04 ad03 4 c/be0* ad07 gnd ad06 4 c/be0* ad07 gnd ad06 5 gnd ad09 ad08 gnd 5 gnd ad09 ad08 gnd 5 gnd ad09 ad08 gnd 6 ad11 vi/o ad10 m66en 7 ad14 ad13 gnd ad12 7 ad14 ad13 gnd ad12 8 +3.3v c/be1* ad15 +3.3v 8 +3.3v c/be1* ad15 +3.3v 8 +3.3v c/be1* ad15 +3.3v 9 serr* gnd sb0* par 9 serr* gnd sb0* par 10 gnd perr* +3.3v sdone 10 gnd perr* +3.3v sdone 10 gnd perr* +3.3v sdone 11 stop* +3.3v lock* gnd 11 stop* +3.3v lock* gnd 11 stop* +3.3v lock* gnd 12 +3.3v trdy* gnd devsel* 12 +3.3v trdy* gnd devsel* 12 +3.3v trdy* gnd devsel* 13 frame* gnd irdy* +3.3v 13 frame* gnd irdy* +3.3v 13 frame* gnd irdy* +3.3v 14 gnd ad16 +3.3v c/be2* 14 gnd ad16 +3.3v c/be2* 14 gnd ad16 +3.3v c/be2* 15 ad18 +3.3v ad17 gnd 15 ad18 +3.3v ad17 gnd 15 ad18 +3.3v ad17 gnd 16 ad21 ad20 gnd ad19 16 ad21 ad20 gnd ad19 17 +3.3v ad23 ad22 +3.3v 17 +3.3v ad23 ad22 +3.3v 17 +3.3v ad23 ad22 +3.3v 18 idsel0 gnd idsel1 idsel2 18 idsel0 gnd idsel1 idsel2 19 ad24 c/be3* vi/o idsel3 20 gnd ad26 ad25 gnd 20 gnd ad26 ad25 gnd 20 gnd ad26 ad25 gnd 21 ad29 +5.1v ad28 ad27 21 ad29 +5.1v ad28 ad27 22 +5.1v ad30 gnd ad31 22 +5.1v ad30 gnd ad31 22 +5.1v ad30 gnd ad31 23 req0* gnd req1* vi/o 23 req0* gnd req1* vi/o 24 gnd req2* +5.1v gnt0* 24 gnd req2* +5.1v gnt0* 24 gnd req2* +5.1v gnt0* 25 gnt1* vi/o gnt2* gnd 25 gnt1* vi/o gnt2* gnd 26 +5.1v clk0 gnd clk1 26 +5.1v clk0 gnd clk1 26 +5.1v clk0 gnd clk1 27 clk2 +5.1v clk3 gnd 27 clk2 +5.1v clk3 gnd 27 clk2 +5.1v clk3 gnd 28 gnd intd* +5.1v rst* 28 gnd intd* +5.1v rst* 28 gnd intd* +5.1v rst* 29 +12v inta* intb* intc* 29 +12v inta* intb* intc* 30 na (C12v) ? reserved reserved 3.3v key ? j1/p1 pin a b 1 iochck* gnd 1 iochck* gnd 2 d7 rstdrv 3 d6 +5.1v 3 d6 +5.1v 4 d5 irq9 5 d4 na (C5v) ? 6 d3 drq2 j2/p2 7 d2 na (C12v) ? pin d c 8 d1 endxfr* 0 gnd gnd 9 d0 +12v 0 gnd gnd 9 d0 +12v 0 gnd gnd 9 d0 +12v 0 gnd gnd 9 d0 +12v 1 memcs16* sbhe* 10 iochrdy key 1 memcs16* sbhe* 10 iochrdy key ? 2 iocs16* la23 11 aen smemw* 3 irq10 la22 12 a19 smemr* 4 irq11 ls21 13 a18 iow* 5 irq12 ls20 14 a17 ior* 6 irq15 ls19 15 a16 dack3* 7 irq14 la18 16 a15 drq3 8 dack0* la17 17 a14 dack1* 9 drq0 memr* 18 a13 drq1 10 dack5* memw* 19 a12 refresh* 11 drq5 sd8 20 a11 sysclk 12 dack6* sd9 21 a10 irq7 13 drq6 sd10 22 a9 irq6 14 dack7* sd11 23 a8 irq5 15 drq7 sd12 24 a7 irq4 16 +5.1v sd13 25 a6 irq3 16 +5.1v sd13 25 a6 irq3 16 +5.1v sd13 25 a6 irq3 17 master* sd14 26 a5 dack2* 18 gnd sd15 27 a4 tc 18 gnd sd15 27 a4 tc 18 gnd sd15 27 a4 tc 19 gnd key 19 gnd key ? 28 a3 bale 28 a3 bale 29 a2 +5.1v 29 a2 +5.1v 30 a1 osc 31 a0 gnd 31 a0 gnd 32 gnd gnd 32 gnd gnd 32 gnd gnd 32 gnd gnd pin a b c d 1 gnd 2 vi/o ad02 ad01 +5.1v 3 ad05 gnd ad04 ad03 4 c/be0* ad07 gnd ad06 5 gnd ad09 ad08 gnd 6 ad11 vi/o ad10 m66en 7 ad14 ad13 gnd ad12 8 +3.3v c/be1* ad15 +3.3v 9 serr* gnd sb0* par 10 gnd perr* +3.3v sdone 11 stop* +3.3v lock* gnd 12 +3.3v trdy* gnd devsel* 12 +3.3v trdy* gnd devsel* 13 frame* gnd irdy* +3.3v 14 gnd ad16 +3.3v c/be2* 14 gnd ad16 +3.3v c/be2* 15 ad18 +3.3v ad17 gnd 16 ad21 ad20 gnd ad19 17 +3.3v ad23 ad22 +3.3v 17 +3.3v ad23 ad22 +3.3v 18 idsel0 gnd idsel1 idsel2 19 ad24 c/be3* vi/o idsel3 20 gnd ad26 ad25 gnd 20 gnd ad26 ad25 gnd 21 ad29 +5.1v ad28 ad27 22 +5.1v ad30 gnd ad31 22 +5.1v ad30 gnd ad31 23 req0* gnd req1* vi/o 24 gnd req2* +5.1v gnt0* 24 gnd req2* +5.1v gnt0* 25 gnt1* vi/o gnt2* gnd 26 +5.1v clk0 gnd clk1 26 +5.1v clk0 gnd clk1 27 clk2 +5.1v clk3 gnd 28 gnd intd* +5.1v rst* 28 gnd intd* +5.1v rst* 29 +12v inta* intb* intc* 29 +12v inta* intb* intc* 30 na (C12v) pin a b c d reserved +5.1v ad00 reserved +5.1v ad00 2 vi/o ad02 ad01 +5.1v 3 ad05 gnd ad04 ad03 3 ad05 gnd ad04 ad03 4 c/be0* ad07 gnd ad06 5 gnd ad09 ad08 gnd 5 gnd ad09 ad08 gnd 6 ad11 vi/o ad10 m66en 7 ad14 ad13 gnd ad12 8 +3.3v c/be1* ad15 +3.3v 8 +3.3v c/be1* ad15 +3.3v 9 serr* gnd sb0* par 9 serr* gnd sb0* par 10 gnd perr* +3.3v sdone 10 gnd perr* +3.3v sdone 11 stop* +3.3v lock* gnd 11 stop* +3.3v lock* gnd 12 +3.3v trdy* gnd devsel* 12 +3.3v trdy* gnd devsel* 13 frame* gnd irdy* +3.3v 13 frame* gnd irdy* +3.3v 14 gnd ad16 +3.3v c/be2* 14 gnd ad16 +3.3v c/be2* 15 ad18 +3.3v ad17 gnd 15 ad18 +3.3v ad17 gnd 16 ad21 ad20 gnd ad19 17 +3.3v ad23 ad22 +3.3v 17 +3.3v ad23 ad22 +3.3v 18 idsel0 gnd idsel1 idsel2 18 idsel0 gnd idsel1 idsel2 19 ad24 c/be3* vi/o idsel3 20 gnd ad26 ad25 gnd 20 gnd ad26 ad25 gnd 21 ad29 +5.1v ad28 ad27 21 ad29 +5.1v ad28 ad27 22 +5.1v ad30 gnd ad31 22 +5.1v ad30 gnd ad31 23 req0* gnd req1* vi/o 23 req0* gnd req1* vi/o 24 gnd req2* +5.1v gnt0* 24 gnd req2* +5.1v gnt0* 25 gnt1* vi/o gnt2* gnd 26 +5.1v clk0 gnd clk1 26 +5.1v clk0 gnd clk1 27 clk2 +5.1v clk3 gnd 27 clk2 +5.1v clk3 gnd 28 gnd intd* +5.1v rst* 28 gnd intd* +5.1v rst* 29 +12v inta* intb* intc* 29 +12v inta* intb* intc* reserved reserved 3.3v key pin a b c d reserved +5.1v ad00 2 vi/o ad02 ad01 +5.1v 3 ad05 gnd ad04 ad03 3 ad05 gnd ad04 ad03 4 c/be0* ad07 gnd ad06 4 c/be0* ad07 gnd ad06 5 gnd ad09 ad08 gnd 6 ad11 vi/o ad10 m66en 7 ad14 ad13 gnd ad12 7 ad14 ad13 gnd ad12 8 +3.3v c/be1* ad15 +3.3v 9 serr* gnd sb0* par 10 gnd perr* +3.3v sdone 10 gnd perr* +3.3v sdone 11 stop* +3.3v lock* gnd 12 +3.3v trdy* gnd devsel* 12 +3.3v trdy* gnd devsel* 13 frame* gnd irdy* +3.3v 14 gnd ad16 +3.3v c/be2* 14 gnd ad16 +3.3v c/be2* 15 ad18 +3.3v ad17 gnd 16 ad21 ad20 gnd ad19 16 ad21 ad20 gnd ad19 17 +3.3v ad23 ad22 +3.3v 18 idsel0 gnd idsel1 idsel2 19 ad24 c/be3* vi/o idsel3 20 gnd ad26 ad25 gnd 21 ad29 +5.1v ad28 ad27 22 +5.1v ad30 gnd ad31 22 +5.1v ad30 gnd ad31 23 req0* gnd req1* vi/o 24 gnd req2* +5.1v gnt0* 24 gnd req2* +5.1v gnt0* 25 gnt1* vi/o gnt2* gnd 26 +5.1v clk0 gnd clk1 26 +5.1v clk0 gnd clk1 27 clk2 +5.1v clk3 gnd 28 gnd intd* +5.1v rst* 29 +12v inta* intb* intc* reserved reserved 3.3v key pin a b c d reserved +5.1v ad00 reserved +5.1v ad00 2 vi/o ad02 ad01 +5.1v 2 vi/o ad02 ad01 +5.1v 3 ad05 gnd ad04 ad03 4 c/be0* ad07 gnd ad06 5 gnd ad09 ad08 gnd 5 gnd ad09 ad08 gnd 6 ad11 vi/o ad10 m66en 7 ad14 ad13 gnd ad12 7 ad14 ad13 gnd ad12 8 +3.3v c/be1* ad15 +3.3v 8 +3.3v c/be1* ad15 +3.3v 9 serr* gnd sb0* par 10 gnd perr* +3.3v sdone 10 gnd perr* +3.3v sdone 11 stop* +3.3v lock* gnd 11 stop* +3.3v lock* gnd 12 +3.3v trdy* gnd devsel* 12 +3.3v trdy* gnd devsel* 13 frame* gnd irdy* +3.3v 13 frame* gnd irdy* +3.3v 14 gnd ad16 +3.3v c/be2* 14 gnd ad16 +3.3v c/be2* 15 ad18 +3.3v ad17 gnd 15 ad18 +3.3v ad17 gnd 16 ad21 ad20 gnd ad19 17 +3.3v ad23 ad22 +3.3v 17 +3.3v ad23 ad22 +3.3v 18 idsel0 gnd idsel1 idsel2 19 ad24 c/be3* vi/o idsel3 20 gnd ad26 ad25 gnd 20 gnd ad26 ad25 gnd 21 ad29 +5.1v ad28 ad27 22 +5.1v ad30 gnd ad31 23 req0* gnd req1* vi/o 24 gnd req2* +5.1v gnt0* 25 gnt1* vi/o gnt2* gnd 26 +5.1v clk0 gnd clk1 27 clk2 +5.1v clk3 gnd 28 gnd intd* +5.1v rst* 28 gnd intd* +5.1v rst* 29 +12v inta* intb* intc* reserved reserved 3.3v key pin a b c d 1 gnd 2 vi/o ad02 ad01 +5.1v 3 ad05 gnd ad04 ad03 4 c/be0* ad07 gnd ad06 5 gnd ad09 ad08 gnd 6 ad11 vi/o ad10 m66en 7 ad14 ad13 gnd ad12 8 +3.3v c/be1* ad15 +3.3v 9 serr* gnd sb0* par 10 gnd perr* +3.3v sdone 11 stop* +3.3v lock* gnd 12 +3.3v trdy* gnd devsel* 13 frame* gnd irdy* +3.3v 14 gnd ad16 +3.3v c/be2* 15 ad18 +3.3v ad17 gnd 16 ad21 ad20 gnd ad19 17 +3.3v ad23 ad22 +3.3v 18 idsel0 gnd idsel1 idsel2 19 ad24 c/be3* vi/o idsel3 20 gnd ad26 ad25 gnd 21 ad29 +5.1v ad28 ad27 22 +5.1v ad30 gnd ad31 23 req0* gnd req1* vi/o 24 gnd req2* +5.1v gnt0* 25 gnt1* vi/o gnt2* gnd 26 +5.1v clk0 gnd clk1 27 clk2 +5.1v clk3 gnd 28 gnd intd* +5.1v rst* 29 +12v inta* intb* intc* 30 na (C12v) pin d c 0 gnd gnd 9 d0 +12v 1 memcs16* sbhe* 10 iochrdy key 2 iocs16* la23 11 aen smemw* 3 irq10 la22 12 a19 smemr* 4 irq11 ls21 13 a18 iow* 5 irq12 ls20 14 a17 ior* 6 irq15 ls19 15 a16 dack3* 7 irq14 la18 16 a15 drq3 8 dack0* la17 17 a14 dack1* 9 drq0 memr* 18 a13 drq1 10 dack5* memw* 19 a12 refresh* 11 drq5 sd8 20 a11 sysclk 12 dack6* sd9 21 a10 irq7 13 drq6 sd10 22 a9 irq6 14 dack7* sd11 23 a8 irq5 15 drq7 sd12 24 a7 irq4 16 +5.1v sd13 25 a6 irq3 17 master* sd14 26 a5 dack2* 18 gnd sd15 27 a4 tc 19 gnd key pin d c 0 gnd gnd 9 d0 +12v 0 gnd gnd 9 d0 +12v 1 memcs16* sbhe* 10 iochrdy key 2 iocs16* la23 11 aen smemw* 3 irq10 la22 12 a19 smemr* 4 irq11 ls21 13 a18 iow* 5 irq12 ls20 14 a17 ior* 6 irq15 ls19 15 a16 dack3* 7 irq14 la18 16 a15 drq3 8 dack0* la17 17 a14 dack1* 9 drq0 memr* 18 a13 drq1 10 dack5* memw* 19 a12 refresh* 11 drq5 sd8 20 a11 sysclk 12 dack6* sd9 21 a10 irq7 13 drq6 sd10 22 a9 irq6 14 dack7* sd11 23 a8 irq5 15 drq7 sd12 24 a7 irq4 16 +5.1v sd13 25 a6 irq3 16 +5.1v sd13 25 a6 irq3 17 master* sd14 26 a5 dack2* 18 gnd sd15 27 a4 tc 18 gnd sd15 27 a4 tc 19 gnd key 19 gnd key pin d c 0 gnd gnd 9 d0 +12v 1 memcs16* sbhe* 10 iochrdy key 2 iocs16* la23 11 aen smemw* 3 irq10 la22 12 a19 smemr* 4 irq11 ls21 13 a18 iow* 5 irq12 ls20 14 a17 ior* 6 irq15 ls19 15 a16 dack3* 7 irq14 la18 16 a15 drq3 8 dack0* la17 17 a14 dack1* 9 drq0 memr* 18 a13 drq1 10 dack5* memw* 19 a12 refresh* 11 drq5 sd8 20 a11 sysclk 12 dack6* sd9 21 a10 irq7 13 drq6 sd10 22 a9 irq6 14 dack7* sd11 23 a8 irq5 15 drq7 sd12 24 a7 irq4 16 +5.1v sd13 25 a6 irq3 16 +5.1v sd13 25 a6 irq3 17 master* sd14 26 a5 dack2* 18 gnd sd15 27 a4 tc 18 gnd sd15 27 a4 tc 19 gnd key 1 iochck* gnd 2 d7 rstdrv 3 d6 +5.1v 4 d5 irq9 5 d4 na (C5v) 6 d3 drq2 7 d2 na (C12v) 8 d1 endxfr* 0 gnd gnd 9 d0 +12v 0 gnd gnd 9 d0 +12v 1 memcs16* sbhe* 10 iochrdy key 2 iocs16* la23 11 aen smemw* 3 irq10 la22 12 a19 smemr* 4 irq11 ls21 13 a18 iow* 5 irq12 ls20 14 a17 ior* 6 irq15 ls19 15 a16 dack3* 7 irq14 la18 16 a15 drq3 8 dack0* la17 17 a14 dack1* 9 drq0 memr* 18 a13 drq1 10 dack5* memw* 19 a12 refresh* 11 drq5 sd8 20 a11 sysclk 12 dack6* sd9 21 a10 irq7 13 drq6 sd10 22 a9 irq6 14 dack7* sd11 23 a8 irq5 15 drq7 sd12 24 a7 irq4 16 +5.1v sd13 25 a6 irq3 17 master* sd14 26 a5 dack2* 18 gnd sd15 27 a4 tc 28 a3 bale 28 a3 bale 29 a2 +5.1v 30 a1 osc 31 a0 gnd 32 gnd gnd pin a b 1 iochck* gnd 2 d7 rstdrv 3 d6 +5.1v 4 d5 irq9 5 d4 na (C5v) 6 d3 drq2 7 d2 na (C12v) 8 d1 endxfr* 0 gnd gnd 9 d0 +12v 1 memcs16* sbhe* 10 iochrdy key 2 iocs16* la23 11 aen smemw* 3 irq10 la22 12 a19 smemr* 4 irq11 ls21 13 a18 iow* 5 irq12 ls20 14 a17 ior* 6 irq15 ls19 15 a16 dack3* 7 irq14 la18 16 a15 drq3 8 dack0* la17 17 a14 dack1* 9 drq0 memr* 18 a13 drq1 10 dack5* memw* 19 a12 refresh* 11 drq5 sd8 20 a11 sysclk 12 dack6* sd9 21 a10 irq7 13 drq6 sd10 22 a9 irq6 14 dack7* sd11 23 a8 irq5 15 drq7 sd12 24 a7 irq4 16 +5.1v sd13 25 a6 irq3 17 master* sd14 26 a5 dack2* 18 gnd sd15 27 a4 tc 28 a3 bale 29 a2 +5.1v 30 a1 osc 31 a0 gnd 32 gnd gnd pin a b 1 iochck* gnd 1 iochck* gnd 2 d7 rstdrv 3 d6 +5.1v 3 d6 +5.1v 4 d5 irq9 5 d4 na (C5v) 6 d3 drq2 7 d2 na (C12v) 8 d1 endxfr* 0 gnd gnd 9 d0 +12v 0 gnd gnd 9 d0 +12v 1 memcs16* sbhe* 10 iochrdy key 1 memcs16* sbhe* 10 iochrdy key 2 iocs16* la23 11 aen smemw* 3 irq10 la22 12 a19 smemr* 4 irq11 ls21 13 a18 iow* 5 irq12 ls20 14 a17 ior* 6 irq15 ls19 15 a16 dack3* 7 irq14 la18 16 a15 drq3 8 dack0* la17 17 a14 dack1* 9 drq0 memr* 18 a13 drq1 10 dack5* memw* 19 a12 refresh* 11 drq5 sd8 20 a11 sysclk 12 dack6* sd9 21 a10 irq7 13 drq6 sd10 22 a9 irq6 14 dack7* sd11 23 a8 irq5 15 drq7 sd12 24 a7 irq4 16 +5.1v sd13 25 a6 irq3 17 master* sd14 26 a5 dack2* 18 gnd sd15 27 a4 tc 28 a3 bale 29 a2 +5.1v 29 a2 +5.1v 30 a1 osc 31 a0 gnd 31 a0 gnd 32 gnd gnd ? the shaded area denotes power or ground signals. ? the key pins are to guarantee proper module installation: j3/p3, pin a1 is electrically connected to gnd for shielding j3/p3, pin d30 is removed and the female side is plugged for 3.3v i/o j2/p2, pin c19 is keyed, pin is removed and the female side is plugged j1/p1, pin b10 is keyed, pin is removed and the female side is plugged ? j3/p3, pin a30 and j1/p1, pins b5 and b7 are not used. pin assignments for C5v and C12v are for reference only. table 2. MAPC-104 (pc/104- plus ) bus signal assignments plus ) bus signal assignments plus table 3. MAPC-104 (pc/104-reference) bus signal assignments for the MAPC-104-5v model version, spare +5 vdc power may be taken from the p2 connector which is adjacent to the pin 1 end of the j1 connector (see drawings). be aware that this power is generated on the MAPC-104 and therefore is in addition to whatever 5v current is used by the host pc- 104 system. all power characteristics (regulation, tempco, ripple, etc.) are derived from the MAPC-104. speci? cations (typical unless noted) power output ? +5 vdc at 1 amp maximum power characteristics see MAPC-104 speci? cations p2 header type amp/tyco electronics 640455-2 contact dimensions two 0.025 square posts, 0.3" long, 0.10" spacing on centers. see drawings. contact material tin plating over copper alloy contact assembly force 3 lbs. (13n) mating connector ? single-row, 2-position idc on 0.10" spacing environmental compatible with host MAPC-104 system ? the contacts are rated at 5 amps 250vac. however, whatever current is drawn must be summed with current powering the pc-104 system. summed with current po w er ing the pc-104 system. summed ? a suggested mating connector is amp / tyco electronics mta-100 series, part number 647000-2. see also the cst-100 series.. auxiliary 5v power connector, p2
pc/104-plus series 4 6 w , t r i p l e o u t p u t d c / d c c o n v e r t e r 4 performance/functional speci? cations typical @ t a = +25c under nominal line voltage and nominal-load conditions unless noted. ? input voltage: continuous 36v up to 5 minutes maximum 48v transient (100ms) 125v (30kva) input reverse polarity protection external fuse mandatory output current current limited. devices can withstand an inde? nite output short circuit. these are stress ratings. exposure of devices to any of these conditions may adversely affect long-term reliability. proper operation under conditions other than those listed in the performance/functional speci? cations table is not implied, nor recommended. absolute maximum ratings input input voltage range 9-32 volts (12v or 24v battery) transient voltage protection 125v/100ms (30kva) overvoltage shutdown 32-36 volts (34v typical) overvoltage protection 48v/5 minutes start-up threshold ? 9-10 volts (9.4v typical) undervoltage shutdown ? 7-9 volts (8.2v typical) input current see performance speci? cations input re? ected ripple current ? 45mvp-p internal filter type pi reverse polarity protection yes (external fuse mandatory) output minimum loading per output no load maximum capacitive loading 2000 f (+3.3v) 1000 f (+5.1v) 500 f (+12v) v out accuracy (50% load) 3% maximum temperature coef? cient 0.02%/c ripple/noise (20mhz bw) see performance speci? cations line/load regulation see performance speci? cations ef? ciency see performance speci? cations current limit inception ? 7-9 amps (+3.3v) (97% v out , each other 8.5-11 amps (+5.1v) output @ 0 amps) 0.2-0.5 amps (+12v) short circuit current 2.65 amps (+3.3v) (zener) 3.24 amps (+5.1v) 0.12 amps (+12v) overvoltage protection ? 3.9v (+3.3v) 6v (+5.1v) 13v (+12v) power good see tech notes within 7-10% of v out (led and external signal) dynamic characteristics dynamic load response ? 200 sec max. (+3.3v & +5.1v) (50-100% step to within 1% of v out ) 100 sec max. (+12v) power-up sequencing ? 2-6msec (5.1v power-up before 3.3v) power-down sequencing 1-4msec (5.1v power-down before 3.3v) switching frequency 320khz (+3.3v & +5.1v) 1120khz (+12v) environmental calculated mtbf ? tbc million hours operating ambient temperature ? with 100 lfm air flow, no derating C40 to +85c board temperature C40 to +105c thermal shutdown +112 to +118c thermal shutdown warning 27 to 33 seconds 2nd level thermal shutdown +122 to +128c storage temperature C40 to +105c physical dimensions see mechanical dimensions connector and pin material according to pc/104- plus spec plus spec plus weight 3.6 ounces (102 grams) insulation level non-isolated ? all models are tested and speci? ed with a single, external, 0.1f, multi-layer ceramic output capacitor on each output and no external input capacitors, unless otherwise noted. all models will effectively regulate under no-load conditions (with perhaps a slight increase in output ripple/noise). ? see technical notes/performance curves for additional explanations and details. ? input ripple current is tested/speci? ed over a 5-20mhz bandwidth with an external 33f input capacitor and a simulated source impedance of 220f and 12h. see i/o filtering, input ripple current and output noise for details. ? the current-limit-inception point is the output current level at which the converter's power- limiting circuitry drops the output voltage 3% from its initial value. see output current limiting and short-circuit protection for more details. ? see dynamic load response for detailed results including switching frequencies. ? for start-up-time speci? cations, output settling time is de? ned as the output voltage having reached 1% of its ? nal value and the load current having reached at least 80% of its ? nal value. ? mtbf is calculated using telcordia sr-332 method 1 case 3, ground ? xed, +25c ambient air and full-load conditions. contact datel for demonstrated life test data. ? all models are fully operational and meet all published speci? cations, including "cold start," at C40c. ? the highly unlikely, simultaneous failure of several speci? c on-board components could result in the MAPC-104's input voltage appearing at its output, despite the unit's output overvoltage protection mechanisms. in this rare situation, the power good signal (iph pin 2, pwr_led_drive) will be deactivated and systems monitoring power good will eventually shut down. if you are using an MAPC-104 to power a load that must be protected against any and all possible overvoltages, no matter how rare, you will have to provide the protection external to the MAPC-104. please contact datel for recommendations. ordering guide model number auxiliary power connector (p2) MAPC-104 not installed MAPC-104-5v installed MAPC-104-y rohs-5 hazardous substance compliance, no p2 connector designations the of? cial pc/104 bus speci? cation identi? es the standard interboard bus connections as paired j1/p1 and j2/p2 on one side and j3/p3 on the other side. however, j1/p1/j2/p2 is physically all one big 4-row connector with j1/ j2 bus receptacle sockets (female) on the top side and p1/p2 pins (male) on the bottom. this arrangement provides interboard pass-through connections between pc/104 boards. datel refers to this single connector as j1. datels auxiliary connectors (the iph and the 5v auxilliary power connec- tor) are internally designated p1 and p2 respectively and this nomenclature may appear on the board silkscreening. this is purely an artifact of auto- mated sequential part numbering in our cad system and has no relation to the standard pc/104 interboard bus connectors. dont get the connectors confused since they are all very different types and locations!
4 6 w , t r i p l e o u t p u t d c / d c c o n v e r t e r pc/104-plus series typical performance curves for MAPC-104 series 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 e f f i c i e n c y v s . l i n e @ 4 6 w 9 1 2 1 8 2 4 2 8 3 2 i n p u t v o l t a g e ( v ) e f f i c i e n c y ( % ) 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 3 . 3 v o u t e f f i c i e n c y v s . l i n e v o l t a g e a n d l o a d c u r r e n t ( 5 . 1 v @ 5 . 4 6 a a n d 1 2 v @ 0 . 0 7 a ) 0 1 . 2 5 2 . 5 3 . 7 5 5 6 . 3 l o a d c u r r e n t ( a m p s ) e f f i c i e n c y ( % ) v i n = 1 2 v v i n = 2 4 v v i n = 3 2 v v i n = 9 v 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 5 . 1 v o u t e f f i c i e n c y v s . l i n e v o l t a g e a n d l o a d c u r r e n t ( 3 . 3 v @ 5 a a n d 1 2 v @ 0 . 0 7 a ) 0 1 . 2 5 2 . 5 3 . 7 5 5 6 . 3 l o a d c u r r e n t ( a m p s ) e f f i c i e n c y ( % ) v i n = 1 2 v v i n = 2 4 v v i n = 3 2 v v i n = 9 v 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 1 2 v o u t e f f i c i e n c y v s . l i n e v o l t a g e a n d l o a d c u r r e n t ( 5 . 1 v @ 5 . 4 6 a a n d 3 . 3 v @ 5 a ) 0 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 l o a d c u r r e n t ( a m p s ) e f f i c i e n c y ( % ) v i n = 1 2 v v i n = 2 4 v v i n = 3 2 v v i n = 9 v
pc/104-plus series 4 6 w , t r i p l e o u t p u t d c / d c c o n v e r t e r 6 self-protection features the MAPC-104 contains two systems for protection of out-of-limit voltages, currents and temperature. these systems control two output lines located on the input power header connector. both systems operate independently and concurrently. the MAPC-104 will respond to both temperature and voltage/ current simultaneously. the output circuits for both these controls are shown below. both of them will drive either an external led lamp and/or a logic circuit. the overtemperature warning circuit assumes that an external pullup resistor is supplied by the user. the power good circuit (pwr_led_drive out) includes an on-board pullup resistor to drive an external led with about 15ma. the transistors in these outputs are either on (typically less than 0.4 volts out) or off (high impedance state). depending on how the user wires the external circuit, these indicators have the following sense: ot_warn out (pin 1): hi (transistor off) = temperature is normal lo (transistor on) = over temperature condition pwr_led_drive out (pin 2, pullup to internal +5v): hi (transistor off) = power is normal. led lamp is illuminated. lo (transistor on) = power fault, led lamp is dark overtemperature operation the overtemperature system includes a on-board temperature sensor, a local microcontroller with a/d inputs, a timer and hysteresis so that the user may take steps to prevent inadvertant shut down. operation proceeds as follows: if the on-board temperature exceeds +115c, the ot_warn output is asserted (lo) by the microcontroller and an internal 30 second software timer is started. the outputs remain powered on. if the 30-second timer has not expired and the on-board temperature cools below +110c, the ot_warn output will be deasserted (hi) and operation will continue unchanged. if the 30-second timer has expired and the temperature still exceeds +115c, the outputs will shut down. as soon as the on-board temperature cools to less than +110c, the MAPC-104 will automatically restart and power will be restored to the outputs. the 5 degree hysteresis between 110 and 115c prevents rapid cycling of the ot_warn output. if the on-board temperature reaches +125c, the outputs will shut down, regardless of the state of the 30-second timer. the temperature must cool to less than +110c for autorestart. ????? ???????????? ??????????????????????? ????????????????????? ? ? ??????????? ???? ? ?? ?? ??? ? ????? ???????????? ? ?? ?? ? ??????????? ? ? ???? ???????????????????? ?????????? ?????? ???????? ?????? ??????? ?????????? ? ? ?? ?? ??????????? ? ??????????????????????????????? figure 1. overtemperature warning circuit typical external logic wiring typical ot warning external led lamp wiring figure 2. power good circuit typical power good external led lamp wiring ? ? ? ?????? ?????? ??????????????????????????????? ????? ?? ?? ????????????????? ?????????? ??? ?
4 6 w , t r i p l e o u t p u t d c / d c c o n v e r t e r pc/104-plus series 7 power good operation local power is measured by several circuits shared with the overtemperature system. the pwr_led_drive output is indirectly controlled by the on-board microcontroller. the on-board pwm switching controller measures +3.3v and +5v output voltages and all output currents. the microcontroller measures input voltage and the +12v output voltage. the system requires that the input voltage is within normal tolerances at all times. if the input voltage is too high very brie? y at startup (but not exceeding the absolute input voltage), the system will start normally if the input voltage reaches acceptable limits quickly (under half a second). this typically occurs as a load is applied. when the system ? rst starts, the power good led (if installed) remains dark brie? y until all on-board startup conditions are met (less than half a second) at which point the led is illuminated. operation proceeds as follows: if the outputs on any lines deviate from approximately 7% of nominal and/or the output current is excessive, the outputs are all shut down and the pwr_led_drive output is desasserted (lo, lamp dark). the system will attempt to restart in about half a second by brie? y turning on all outputs. if successful and the fault is eliminated, the pwr_led_drive output will be asserted (hi, lamp lit) and operation continues. if the fault condition remains, the system will attempt to restart two more times, spaced about half a second apart. if the fault remains for the third time, the system will shut down and will not retest the fault. the system must now be restored by fully cycling the input power. the 3-fault countdown only occurs if the fault does not recover continuously throughout the attempted restart interval. an occasional random shutdown and successful restart will not trigger the 3-fault counter. however, external logic should record the frequency and quantity of such shutdowns. rohs-5 compliance refers to the exclusion of the six hazardous substances in the rohs speci? cation with the excepion of lead. c&d technologies' rohs-5 products use all the conforming rohs materials, however our solders are sn63/pb37. ds-0528 12/05 c&d technologies (datel), inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subject to change without notice. the datel logo is a registered trademark of c&d technologies, inc.. c&d technologies (ncl), ltd. milton keynes, united kingdom, tel: 44 (0) 1908 615232 internet: www.cd4power.com e-mail: ped.ltd@cdtechno.com c&d technologies (datel) s.a.r.l . montigny le bretonneux, france tel: 01-34-60-01-01 internet: www.cd4power.com e-mail: ped.sarl@cdtechno.com c&d technologies (datel) gmbh mnchen, germany tel: 89-544334-0 internet: www.cd4power.com e-mail: ped.gmbh@cdtechno.com c&d technologies kk tokyo, japan tel: 3-3779-1031, osaka tel: 6-6354-2025 c&d technologies kk t okyo, ja pan t el: 3-3779-1031, osaka t el: 6-6354-2025 c&d technologies kk int.: www.cd4power.jp email: sales_tokyo@cdtechno.com, sales_osaka@cdtechno.com china shanghai, people's republic of china tel: 86-50273678 internet: www.cd4power.com e-mail: shanghai@cdtechno.com c&d technologies (datel), inc. 11 cabot boulevard, mans? eld, ma 02048-1151 u.s.a. tel: (508) 339-3000 (800) 233-2765 fax: (508) 339-6356 www.cd4power.com email: sales@cdtechno.com iso 9001 registered
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