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hitachi single-chip microcomputer h8/538, h8/539 hardware manual omc942723072 2nd edition

preface the h8/538 and h8/539 are original hitachi high-performance single-chip microcontrollers with a high-speed 16-bit h8/500 cpu core and extensive on-chip peripheral functions. they are suitable for controlling a wide range of medium-scale office and industrial equipment and consumer products. the general-register architecture and highly orthogonal, optimized instruction set of the h8/500 cpu enable even programs coded in the high-level c language to be compiled into efficient object code. many of the peripheral functions needed in microcontroller application systems are provided on- chip, including large ram and rom, a powerful set of timers, a serial interface, a high-precision a/d converter, and i/o ports. compact, high-performance systems can be implemented easily. the h8/538 and h8/539 are available with mask-programmable rom for full-scale volume production, and in ztat (zero turn-around time) versions with on-chip prom for products with frequent design changes, or for the early stages of volume production. this document describes the h8/538 and h8/539 hardware. for further details about the h8/500 cpu instruction set, refer to the h8/500 series programming manual . note: ztat is a registered trademark of hitachi, ltd.

contents section 1 overview ....................................................................................................... 1 1.1 features ................................................................................................................... ....... 1 1.2 block diagram .............................................................................................................. .5 1.3 pin descriptions ........................................................................................................... .. 7 1.3.1 pin arrangement .............................................................................................. 7 1.3.2 pin functions .................................................................................................... 9 section 2 operating modes ........................................................................................ 21 2.1 overview ................................................................................................................... ..... 21 2.1.1 selection of operating mode ........................................................................... 21 2.1.2 register configuration ..................................................................................... 22 2.2 mode control register .................................................................................................. 23 2.3 operating mode descriptions ........................................................................................ 24 2.3.1 mode 1 (expanded minimum mode) .............................................................. 24 2.3.2 mode 2 (expanded minimum mode) .............................................................. 24 2.3.3 mode 3 (expanded maximum mode) .............................................................. 24 2.3.4 mode 4 (expanded maximum mode) .............................................................. 24 2.3.5 modes 5 and 6 .................................................................................................. 24 2.3.6 mode 7 (single-chip mode) ............................................................................ 24 2.4 pin functions in each operating mode ......................................................................... 25 2.5 memory map in each mode .......................................................................................... 26 2.5.1 h8/538 memory maps ...................................................................................... 26 2.5.2 h8/539 memory maps ...................................................................................... 28 section 3 cpu ................................................................................................................ 31 3.1 overview ................................................................................................................... ..... 31 3.1.1 features ............................................................................................................ 31 3.1.2 address space .................................................................................................. 32 3.1.3 programming model ........................................................................................ 34 3.2 general registers .......................................................................................................... .35 3.2.1 overview .......................................................................................................... 35 3.2.2 register configuration ..................................................................................... 35 3.2.3 stack pointer .................................................................................................... 35 3.2.4 frame pointer ................................................................................................... 35 3.3 control registers .......................................................................................................... .36 3.3.1 overview .......................................................................................................... 36 3.3.2 register configuration ..................................................................................... 36 3.3.3 program counter .............................................................................................. 36 3.3.4 status register .................................................................................................. 37
3.4 page registers ............................................................................................................. ... 40 3.4.1 overview .......................................................................................................... 40 3.4.2 register configuration ..................................................................................... 41 3.4.3 code page register .......................................................................................... 41 3.4.4 data page register ........................................................................................... 42 3.4.5 extended page register..................................................................................... 42 3.4.6 stack page register .......................................................................................... 42 3.5 base register .............................................................................................................. ... 43 3.5.1 overview .......................................................................................................... 43 3.5.2 register configuration ..................................................................................... 43 3.6 data formats ............................................................................................................... ... 44 3.6.1 data formats in general registers ................................................................... 44 3.6.2 data formats in memory ................................................................................. 45 3.6.3 stack data formats .......................................................................................... 45 3.7 addressing modes and effective address calculation ................................................. 46 3.7.1 addressing modes ............................................................................................ 46 3.7.2 effective address calculation .......................................................................... 50 3.8 operating modes ........................................................................................................... 5 2 3.8.1 minimum mode ............................................................................................... 52 3.8.2 maximum mode ............................................................................................... 52 3.9 basic operational timing .............................................................................................. 52 3.9.1 overview .......................................................................................................... 53 3.9.2 access to on-chip memory ............................................................................. 53 3.9.3 access to two-state-access address space .................................................... 54 3.9.4 access to on-chip supporting modules ......................................................... 55 3.9.5 access to three-state-access address space ................................................. 56 3.10 cpu states ................................................................................................................ ..... 58 3.10.1 overview .......................................................................................................... 58 3.10.2 program execution state .................................................................................. 59 3.10.3 exception-handling state ................................................................................ 59 3.10.4 bus-released state ........................................................................................... 60 3.10.5 reset state ........................................................................................................ 68 3.10.6 power-down state ............................................................................................ 68 section 4 exception handling ................................................................................... 69 4.1 overview ................................................................................................................... ..... 69 4.1.1 exception handling types and priority ........................................................... 69 4.1.2 exception handling operation ......................................................................... 70 4.1.3 exception sources and vector table ................................................................ 71 4.2 reset ...................................................................................................................... ..... 73 4.2.1 overview .......................................................................................................... 73
4.2.2 reset sequence ................................................................................................ 73 4.2.3 interrupts after reset ........................................................................................ 76 4.3 address error .............................................................................................................. ... 76 4.3.1 address error in instruction prefetch .............................................................. 77 4.3.2 address error in word data access ................................................................ 77 4.3.3 address error in single-chip mode ................................................................ 78 4.4 trace ...................................................................................................................... ..... 81 4.5 interrupts ................................................................................................................. ....... 81 4.6 invalid instructions ....................................................................................................... .82 4.7 trap instructions and zero divide ................................................................................. 83 4.8 cases in which exception handling is deferred ........................................................... 84 4.8.1 instructions that disable exception handling ................................................. 84 4.8.2 disabling of exceptions immediately after a reset ......................................... 85 4.8.3 disabling of interrupts after a data transfer cycle ......................................... 85 4.9 stack status after completion of exception handling .................................................. 86 4.9.1 pc value pushed on stack for trace, interrupts, trap instructions, and zero divide exceptions ............................................................................. 87 4.9.2 pc value pushed on stack for address error and invalid instruction ............. 87 4.10 notes on use of the stack .............................................................................................. 87 section 5 h8 multiplier (h8/539 only) ................................................................... 89 5.1 overview.................................................................................................................... ..... 89 5.1.1 features ............................................................................................................. 89 5.1.2 block diagram .................................................................................................. 90 5.1.3 register configuration ...................................................................................... 91 5.2 register descriptions...................................................................................................... 9 2 5.2.1 mult control register .................................................................................... 92 5.2.2 mult base address register........................................................................... 94 5.2.3 mult multiplier address register .................................................................. 94 5.2.4 mult multiplicand address register.............................................................. 94 5.2.5 mult multiplier register a ............................................................................ 95 5.2.6 mult multiplier register b............................................................................. 95 5.2.7 mult multiplier register c............................................................................. 95 5.2.8 mult immediate multiplier register .............................................................. 96 5.2.9 mult immediate multiplicand register.......................................................... 96 5.2.10 mult result register, extended high word................................................... 97 5.2.11 mult result register, high word................................................................... 97 5.2.12 mult result register, low word ................................................................... 97 5.3 operation ................................................................................................................... ..... 98 5.3.1 initialization of mult result registers ........................................................... 98 5.3.2 writing to mult multiplier registers ............................................................. 99
5.3.3 bus-stealing function....................................................................................... 99 5.3.4 multiply and multiply-accumulate functions ................................................. 102 section 6 interrupt controller .................................................................................... 111 6.1 overview ................................................................................................................... ..... 111 6.1.1 features ............................................................................................................ 111 6.1.2 block diagram ................................................................................................. 112 6.1.3 register configuration ..................................................................................... 113 6.2 interrupt sources .......................................................................................................... .. 114 6.2.1 nmi .................................................................................................................. 117 6.2.2 irq0 ................................................................................................................. 118 6.2.3 irq1 to irq3 ................................................................................................... 118 6.2.4 internal interrupts ............................................................................................. 121 6.3 register descriptions ..................................................................................................... 1 22 6.3.1 interrupt priority registers a to f ................................................................... 122 6.3.2 timing of priority changes .............................................................................. 124 6.4 interrupt operations ....................................................................................................... 124 6.4.1 operations up to interrupt acceptance ............................................................ 124 6.4.2 interrupt exception handling ........................................................................... 126 6.4.3 interrupt exception handling sequence .......................................................... 128 6.4.4 stack after interrupt exception handling ........................................................ 130 6.5 interrupts during dtc operation .................................................................................. 131 6.6 interrupt response time ................................................................................................ 132 section 7 data transfer controller .......................................................................... 135 7.1 overview ................................................................................................................... ..... 135 7.1.1 features ............................................................................................................ 135 7.1.2 block diagram ................................................................................................. 136 7.1.3 register configuration ..................................................................................... 137 7.2 register descriptions ..................................................................................................... 1 38 7.2.1 data transfer mode register ........................................................................... 138 7.2.2 data transfer source address register ........................................................... 139 7.2.3 data transfer destination address register .................................................... 139 7.2.4 data transfer count register ........................................................................... 140 7.2.5 data transfer enable registers a to f ............................................................. 140 7.2.6 note on timing of dte modifications ............................................................ 142 7.3 operation .................................................................................................................. ..... 143 7.3.1 dtc operations ............................................................................................... 143 7.3.2 dtc vector table ............................................................................................ 145 7.3.3 location of register information in memory .................................................. 149 7.3.4 number of states per data transfer ................................................................. 150
7.4 procedure for using dtc .............................................................................................. 152 7.5 example .................................................................................................................... ..... 153 section 8 wait-state controller ................................................................................. 157 8.1 overview ................................................................................................................... ..... 157 8.1.1 features ............................................................................................................ 157 8.1.2 block diagram ................................................................................................. 158 8.1.3 register configuration ..................................................................................... 158 8.2 wait control register .................................................................................................... 15 9 8.3 operation .................................................................................................................. ..... 160 8.3.1 programmable wait mode ............................................................................... 161 8.3.2 pin wait mode .................................................................................................. 162 8.3.3 pin auto-wait mode ........................................................................................ 163 section 9 clock pulse generator .............................................................................. 165 9.1 overview ................................................................................................................... ..... 165 9.1.1 block diagram ................................................................................................. 165 9.2 oscillator circuit ......................................................................................................... .. 166 9.2.1 connecting a crystal resonator ....................................................................... 166 9.2.2 external clock input ........................................................................................ 168 9.3 system clock divider .................................................................................................... 170 9.4 duty adjustment circuit................................................................................................. 170 section 10 i/o ports ........................................................................................................ 171 10.1 overview .................................................................................................................. ...... 171 10.2 port 1 .................................................................................................................... ....... 176 10.2.1 overview .......................................................................................................... 176 10.2.2 register descriptions ....................................................................................... 177 10.2.3 pin functions in each mode ............................................................................ 178 10.2.4 port 1 read/write operations .......................................................................... 180 10.3 port 2 .................................................................................................................... ....... 182 10.3.1 overview .......................................................................................................... 182 10.3.2 register descriptions ....................................................................................... 183 10.3.3 pin functions in each mode ............................................................................ 184 10.3.4 port 2 read/write operations ........................................................................... 185 10.4 port 3 .................................................................................................................... ....... 187 10.4.1 overview .......................................................................................................... 187 10.4.2 register descriptions ....................................................................................... 188 10.4.3 pin functions in each mode ............................................................................ 189 10.4.4 port 3 read/write operations ........................................................................... 190 10.5 port 4 .................................................................................................................... ....... 192
10.5.1 overview .......................................................................................................... 192 10.5.2 register descriptions ....................................................................................... 193 10.5.3 pin functions in each mode ............................................................................ 194 10.5.4 port 4 read/write operations .......................................................................... 194 10.6 port 5 .................................................................................................................... ....... 197 10.6.1 overview .......................................................................................................... 197 10.6.2 register descriptions ....................................................................................... 198 10.6.3 pin functions in each mode ............................................................................ 199 10.6.4 port 5 read/write operations .......................................................................... 200 10.7 port 6 .................................................................................................................... ....... 203 10.7.1 overview .......................................................................................................... 203 10.7.2 register descriptions ....................................................................................... 204 10.7.3 pin functions in each mode ............................................................................ 206 10.7.4 port 6 read/write operations .......................................................................... 206 10.8 port 7 .................................................................................................................... ....... 211 10.8.1 overview .......................................................................................................... 211 10.8.2 register descriptions ....................................................................................... 212 10.8.3 pin functions in each mode ............................................................................ 214 10.8.4 port 7 read/write operations .......................................................................... 214 10.9 port 8 .................................................................................................................... ....... 220 10.9.1 overview .......................................................................................................... 220 10.9.2 register descriptions ...................................................................................... 220 10.9.3 port 8 read operation....................................................................................... 221 10.10 port 9 ................................................................................................................... ........ 222 10.10.1 overview .......................................................................................................... 222 10.10.2 register descriptions ....................................................................................... 222 10.10.3 port 9 read operation ...................................................................................... 223 10.11 port a ................................................................................................................... ........ 224 10.11.1 overview .......................................................................................................... 224 10.11.2 register descriptions ....................................................................................... 225 10.11.3 pin functions in each mode ............................................................................ 227 10.11.4 port a read/write operations ......................................................................... 231 10.12 port b ................................................................................................................... ........ 238 10.12.1 overview .......................................................................................................... 238 10.12.2 register descriptions ....................................................................................... 239 10.12.3 pin functions in each mode ............................................................................ 240 10.12.4 built-in pull-up transistors ............................................................................. 242 10.12.5 port b read/write operations ......................................................................... 243 10.13 port c ................................................................................................................... ........ 246 10.13.1 overview .......................................................................................................... 246 10.13.2 register descriptions ....................................................................................... 247
10.13.3 pin functions in each mode ............................................................................ 248 10.13.4 built-in mos pull-up transistors ................................................................... 250 10.13.5 port c read/write operations ......................................................................... 251 10.14 ?pin ..................................................................................................................... ...... 254 10.14.1 overview ........................................................................................................... 254 10.14.2 register description.......................................................................................... 254 section 11 16-bit integrated-timer pulse unit ...................................................... 255 11.1 overview .................................................................................................................. ...... 255 11.1.1 features ............................................................................................................ 255 11.1.2 block diagram ................................................................................................. 256 11.1.3 input/output pins ............................................................................................. 257 11.2 timer counters and compare/capture registers .......................................................... 258 11.3 channel 1 registers ....................................................................................................... 259 11.3.1 register configuration ..................................................................................... 260 11.3.2 timer control register (high) ......................................................................... 262 11.3.3 timer control register (low) .......................................................................... 264 11.3.4 timer status register (high) ........................................................................... 268 11.3.5 timer status register (low) ............................................................................ 272 11.3.6 timer output enable register .......................................................................... 276 11.4 channel 2 to 5 registers ................................................................................................ 28 1 11.4.1 register configuration ..................................................................................... 282 11.4.2 timer control register (low) .......................................................................... 286 11.4.3 timer status register (high) ........................................................................... 288 11.4.4 timer status register (low) ............................................................................ 290 11.4.5 timer output enable register .......................................................................... 292 11.5 channel 6 and 7 registers ............................................................................................. 295 11.5.1 register configuration ..................................................................................... 296 11.5.2 timer status register (high) ........................................................................... 298 11.5.3 timer status register (low) ............................................................................ 300 11.5.4 timer output enable register .......................................................................... 302 11.6 ipu register descriptions ............................................................................................. 304 11.6.1 timer mode register a .................................................................................... 304 11.6.2 timer mode register b .................................................................................... 307 11.6.3 timer start register ......................................................................................... 310 11.7 h8/500 cpu interface ................................................................................................... 312 11.7.1 16-bit accessible registers ............................................................................. 312 11.7.2 eight-bit accessible registers ......................................................................... 315 11.8 examples of timer operation ....................................................................................... 318 11.8.1 examples of counting ...................................................................................... 318 11.8.2 selection of output level ................................................................................ 321
11.8.3 input capture function .................................................................................... 324 11.8.4 counter clearing function ............................................................................... 328 11.8.5 pwm output mode .......................................................................................... 330 11.8.6 synchronizing mode ....................................................................................... 334 11.8.7 external event counting .................................................................................. 337 11.8.8 programmed periodic counting mode ............................................................ 340 11.8.9 phase counting mode ...................................................................................... 343 11.9 interrupts ................................................................................................................ ........ 349 11.9.1 interrupt timing ............................................................................................... 349 11.9.2 interrupt sources and dtc interrupts .............................................................. 351 11.10 notes and precautions .................................................................................................... 353 section 12 pwm timers (h8/539 only) .................................................................... 365 12.1 overview................................................................................................................... ...... 365 12.1.1 features ............................................................................................................. 365 12.1.2 block diagram .................................................................................................. 366 12.1.3 pin configuration .............................................................................................. 367 12.1.4 register configuration ...................................................................................... 367 12.2 register descriptions...................................................................................................... 368 12.2.1 timer counter ................................................................................................... 368 12.2.2 duty register .................................................................................................... 368 12.2.3 timer control register...................................................................................... 369 12.3 pwm timer operation ................................................................................................... 371 12.4 usage notes ................................................................................................................ .... 373 section 13 watchdog timer .......................................................................................... 375 13.1 overview .................................................................................................................. ...... 375 13.1.1 features ............................................................................................................ 375 13.1.2 block diagram ................................................................................................. 376 13.1.3 register configuration ..................................................................................... 376 13.2 register descriptions ..................................................................................................... 377 13.2.1 timer counter .................................................................................................. 377 13.2.2 timer control/status register .......................................................................... 378 13.2.3 reset control/status register .......................................................................... 380 13.2.4 notes on register access ................................................................................. 381 13.3 operation ................................................................................................................. ...... 383 13.3.1 watchdog timer operation .............................................................................. 383 13.3.2 interval timer operation .................................................................................. 384 13.3.3 operation in software standby mode .............................................................. 385 13.3.4 timing of setting of overflow flag (ovf) ..................................................... 385 13.3.5 timing of setting of watchdog timer reset bit (wrst) ............................... 386
13.4 usage notes ............................................................................................................... .... 387 section 14 serial communication interface ............................................................ 389 14.1 overview .................................................................................................................. ...... 389 14.1.1 features ............................................................................................................ 389 14.1.2 block diagram ................................................................................................. 390 14.1.3 input/output pins ............................................................................................. 391 14.1.4 register configuration ..................................................................................... 391 14.2 register descriptions ..................................................................................................... 393 14.2.1 receive shift register ...................................................................................... 393 14.2.2 receive data register ...................................................................................... 393 14.2.3 transmit shift register .................................................................................... 394 14.2.4 transmit data register ..................................................................................... 394 14.2.5 serial mode register ........................................................................................ 395 14.2.6 serial control register ..................................................................................... 399 14.2.7 serial status register ....................................................................................... 403 14.2.8 bit rate register .............................................................................................. 408 14.3 operation ................................................................................................................. ...... 415 14.3.1 overview .......................................................................................................... 415 14.3.2 operation in asynchronous mode ................................................................... 417 14.3.3 clocked synchronous operation ...................................................................... 427 14.3.4 multiprocessor communication ....................................................................... 437 14.4 interrupts and dtc ........................................................................................................ 445 14.5 usage notes ............................................................................................................... .... 445 section 15 a/d converter ............................................................................................. 449 15.1 overview .................................................................................................................. ...... 449 15.1.1 features ............................................................................................................ 449 15.1.2 block diagram ................................................................................................. 450 15.1.3 input/output pins ............................................................................................. 451 15.1.4 register configuration ..................................................................................... 452 15.2 register descriptions ..................................................................................................... 453 15.2.1 a/d data registers 0 to b ................................................................................ 453 15.2.2 a/d control status register ............................................................................. 454 15.2.3 a/d control register ....................................................................................... 458 15.3 h8/500 cpu interface ................................................................................................... 460 15.4 operation ................................................................................................................. ...... 462 15.4.1 single mode ..................................................................................................... 462 15.4.2 scan mode ........................................................................................................ 465 15.4.3 analog input sampling and a/d conversion time ......................................... 468 15.4.4 external triggering of a/d conversion ........................................................... 470
15.4.5 starting a/d conversion by ipu ..................................................................... 470 15.5 interrupts and dtc ........................................................................................................ 471 15.6 usage notes ............................................................................................................... .... 471 section 16 bus controller ............................................................................................. 475 16.1 overview .................................................................................................................. ...... 475 16.1.1 features ............................................................................................................ 475 16.1.2 block diagram ................................................................................................. 476 16.1.3 register configuration ..................................................................................... 477 16.2 register descriptions ..................................................................................................... 477 16.2.1 byte area top register .................................................................................... 477 16.2.2 three-state area top register ......................................................................... 478 16.2.3 bus control register ........................................................................................ 479 16.3 operation ................................................................................................................. ...... 483 16.3.1 operation after reset in each mode ................................................................ 483 16.3.2 timing of changes in bus areas and bus size ............................................... 490 16.3.3 i/o port expansion function ............................................................................ 492 16.4 usage notes ............................................................................................................... .... 493 section 17 ram ............................................................................................................... 501 17.1 overview .................................................................................................................. ...... 501 17.1.1 block diagram ................................................................................................. 501 17.1.2 register configuration ..................................................................................... 502 17.2 ram control register ................................................................................................... 503 17.3 operation ................................................................................................................. ...... 504 17.3.1 expanded modes (modes 1 to 6) ..................................................................... 504 17.3.2 single-chip mode (mode 7) ............................................................................ 504 section 18 rom ............................................................................................................... 505 18.1 overview .................................................................................................................. ...... 505 18.1.1 block diagram ................................................................................................. 506 18.2 prom mode ................................................................................................................. . 508 18.2.1 prom mode setting ........................................................................................ 508 18.2.2 socket adapter and memory map ................................................................... 508 18.3 programming ............................................................................................................... .. 511 18.3.1 programming and verification ......................................................................... 512 18.3.2 programming precautions ................................................................................ 514 18.4 reliability of programmed data .................................................................................... 515 section 19 power-down state ...................................................................................... 517 19.1 overview .................................................................................................................. ...... 517
19.2 sleep mode ................................................................................................................ .... 518 19.2.1 transition to sleep mode ................................................................................. 518 19.2.2 exit from sleep mode ...................................................................................... 518 19.3 software standby mode ................................................................................................ 519 19.3.1 transition to software standby mode ............................................................. 519 19.3.2 software standby control register................................................................... 519 19.3.3 exit from software standby mode .................................................................. 520 19.3.4 sample application of software standby mode .............................................. 521 19.3.5 note .................................................................................................................. 52 1 19.4 hardware standby mode ............................................................................................... 522 19.4.1 transition to hardware standby mode ............................................................ 522 19.4.2 recovery from hardware standby mode ......................................................... 522 19.4.3 timing for hardware standby mode ............................................................... 522 section 20 electrical characteristics ......................................................................... 523 20.1 absolute maximum ratings (h8/538) ........................................................................... 523 20.2 electrical characteristics (h8/538)................................................................................. 524 20.2.1 dc characteristics ........................................................................................... 524 20.2.2 ac characteristics ............................................................................................ 528 20.2.3 a/d conversion characteristics ....................................................................... 532 20.3 absolute maximum ratings (h8/539) ........................................................................... 533 20.4 electrical characteristics (h8/539)................................................................................. 534 20.4.1 dc characteristics ............................................................................................ 534 20.4.2 ac characteristics............................................................................................. 544 20.4.3 a/d conversion characteristics........................................................................ 550 20.5 operational timing ........................................................................................................ 551 20.5.1 bus timing ....................................................................................................... 551 20.5.2 control signal timing ...................................................................................... 555 20.5.3 clock timing .................................................................................................... 557 20.5.4 i/o port timing ................................................................................................ 558 20.5.5 pwm timing..................................................................................................... 558 20.5.6 ipu timing ....................................................................................................... 559 20.5.7 sci input/output timing ................................................................................. 560 appendix a instruction set .......................................................................................... 561 a.1 instruction list ........................................................................................................... .... 561 a.2 machine-language instruction codes ........................................................................... 568 a.3 operation code map....................................................................................................... 580 a.4 number of states required for execution ..................................................................... 585 a.5 instruction set ............................................................................................................ .... 595 a.5.1 features ............................................................................................................ 595
a.5.2 instruction types .............................................................................................. 595 a.5.3 basic instruction formats ................................................................................ 596 a.5.4 data transfer instructions ................................................................................ 597 a.5.5 arithmetic instructions .................................................................................... 601 a.5.6 logic instructions ............................................................................................ 608 a.5.7 shift instructions .............................................................................................. 610 a.5.8 bit manipulation instructions .......................................................................... 612 a.5.9 branch instructions .......................................................................................... 615 a.5.10 system control instructions ............................................................................. 623 a.5.11 short-format instructions ................................................................................ 630 appendix b initial values of cpu registers .......................................................... 631 appendix c on-chip registers .................................................................................. 632 appendix d pin function selection .......................................................................... 652 d.1 port 3 function selection ............................................................................................... 652 d.2 port 4 function selection ............................................................................................... 653 d.3 port 5 function selection ............................................................................................... 655 d.4 port 6 function selection ............................................................................................... 657 d.5 port 7 function selection ............................................................................................... 658 d.6 port a function selection .............................................................................................. 660 appendix e i/o port block diagrams ....................................................................... 665 appendix f memory maps .......................................................................................... 691 f.1 h8/538 ..................................................................................................................... ...... 691 f.2 h8/539 ..................................................................................................................... ...... 692 appendix g pin states ................................................................................................... 693 g.1 states of i/o ports ........................................................................................................ .. 693 g.2 pin states at reset ........................................................................................................ .. 694 appendix h package dimensions ............................................................................... 699
section 1 overview 1.1 features the h8/538 and h8/539 are cmos microcontroller units (mcus) with an original hitachi architecture. each consists of an h8/500 cpu core plus supporting functions required in system configurations. the h8/500 cpu features a highly orthogonal instruction set that permits addressing modes and data sizes to be specified independently in each instruction. an internal 16-bit architecture and 16-bit, two-state access to both on-chip memory and external memory enhance the cpus data- processing capability and provide the speed needed for realtime control applications. the on-chip supporting functions include ram, rom, timers, a serial communication interface (sci), a/d converter, and i/o ports. an on-chip data transfer controller (dtc) provides an efficient way to transfer data in either direction between memory and i/o without using the cpu. for on-chip rom, a choice is offered between mask-programmable rom and electrically programmable rom (prom). the prom version can be programmed by the user with a general-purpose prom programmer. table 1-1 lists the main features of the h8/538 and h8/539. table 1-1 features feature description h8/500 cpu general-register machine eight 16-bit general registers five 8-bit and two 16-bit control registers high-speed operation maximum clock rate (h8/538): 10 mhz (oscillator frequency: 20 mhz) maximum clock rate (h8/539): 16 mhz (oscillator frequency: 16 mhz) two operating modes minimum mode: maximum 64-kbyte address space maximum mode: maximum 1-mbyte address space highly orthogonal instruction set addressing modes and data size can be specified independently for each instruction register and memory addressing modes register-register operations register-memory (or memory-register) operations instruction set optimized for c language special short formats for frequently-used instructions and addressing modes 1
table 1-1 features (cont) feature description memory h8/538 2-kbyte high-speed on-chip ram 60-kbyte on-chip electrically programmable rom or masked rom h8/539 4-kbyte high-speed on-chip ram 128-kbyte on-chip electrically programmable rom or masked rom 16-bit integrated- pulse unit with seven 16-bit timer channels timer pulse unit compare/capture (ipu) channel compare registers registers channel 1 4 4 channels 2 to 5 2 2 channels 6 & 7 2 clock source can be selected independently for each channel thirteen internal clock sources three external clock sources two counting modes free-running timer interval timer three types of pulse output one-shot output toggle output pwm output automatic measurement functions programmable period counting phase counting synchronization function counters on different channels can be synchronized serial communication asynchronous or clocked synchronous mode (selectable) interface (sci) full duplex: can send and receive simultaneously on-chip baud rate generator multiprocessor communication function (asynchronous mode) a/d converter ten-bit resolution twelve channels, single mode or scan mode selectable can be triggered externally, or by ipu compare match selectable voltage conversion range 2
3 table 1-1 features (cont) feature description i/o ports 74 input/output pins 12 input-only pins interrupt controller five external interrupt pins (nmi, irq 0 to irq 3 ) (intc) thirty-nine internal interrupt sources eight programmable priority levels data transfer can transfer data in both directions between memory and i/o controller (dtc) without using the cpu wait-state can insert wait states (t w ) in access to external i/o or memory controller (wsc) bus controller (bsc) address space can be partitioned into 16-bit-bus and 8-bit-bus areas address space can be partitioned into two-state-access and three- state-access areas i/o ports can be expanded and reconfigured operating modes seven operating modes 1. high-speed 16-bit bus modes, starting in 2-state 16-bit mode at reset expanded minimum mode (mode 1) expanded maximum modes (modes 3 and 4) 2. low-speed 16-bit bus modes, starting in 3-state 8-bit mode at reset expanded minimum mode (mode 6) expanded maximum mode (mode 5) 3. low-speed 8-bit bus mode expanded minimum mode (mode 2) 4. single-chip mode h8/539 maximum mode (mode 7) h8/538 minimum mode (mode 7) power-down state three power-down modes sleep mode software standby mode hardware standby mode watchdog timer timer overflow can generate reset output (wdt) also usable as an interval timer pwm timer * duty cycle: 0% to 100% resolution: 1/250 multiplier * 16 bit 16 bit signed or unsigned multiplication (h8mult) multiply-accumulate: 32 bits (saturating); 42 bits (non-saturating) other features on-chip clock oscillator note: * h8/539 only.
table 1-1 features (cont) feature description product lineup model package rom hd6475388f 112-pin plastic qfp (fp-112) prom hd6435388f 112-pin plastic qfp (fp-112) masked rom hd6475398f 112-pin plastic qfp (fp-112) prom HD6435398F 112-pin plastic qfp (fp-112) masked rom 4
1.2 block diagram figures 1-1 and 1-2 show block diagrams of the h8/538 and h8/539. figure 1-1 h8/538 block diagram pa 6 /back/t3oc 2 pa 5 /breq/t3oc 1 pa 4 /wait pa 3 /a 19 /t5oc 2 pa 2 /a 18 /t5oc 1 pa 1 /a 17 /t4oc 2 pa 0 /a 16 /t4oc 1 p9 7 /an 7 p9 6 /an 6 p9 5 /an 5 p9 4 /an 4 p9 3 /an 3 p9 2 /an 2 p9 1 /an 1 p9 0 /an 0 p8 3 /an 11 p8 2 /an 10 p8 1 /an 9 p8 0 /an 8 p7 7 /sck 2 p7 6 /sck 1 p7 5 /rxd 2 p7 4 /txd 2 p7 3 /rxd 1 p7 2 /txd 1 p7 1 /irq 1 /adtrg p7 0 /irq 0 p3 5 /t2oc 2 p3 4 /t2oc 1 p3 3 /t1oc 4 p3 2 /t1oc 3 p3 1 /t1oc 2 p3 0 /t1oc 1 p4 7 /t7ioc 2 p4 6 /t7ioc 1 p4 5 /t6ioc 2 p4 4 /t6ioc 1 p4 3 /t5ioc 2 p4 2 /t5ioc 1 p4 1 /t4ioc 2 p4 0 /t4ioc 1 p5 7 /t3ioc 2 p5 6 /t3ioc 1 p5 5 /t2ioc 2 p5 4 /t2ioc 1 p5 3 /t1ioc 4 p5 2 /t1ioc 3 p5 1 /t1ioc 2 p5 0 /t1ioc 1 p6 4 /tclk 3 p6 3 /tclk 2 p6 2 /tclk 1 p6 1 /irq 3 p6 0 /irq 2 p2 7 /d 7 p2 6 /d 6 p2 5 /d 5 p2 4 /d 4 p2 3 /d 3 p2 2 /d 2 p2 1 /d 1 p2 0 /d 0 p1 7 /d 15 p1 6 /d 14 p1 5 /d 13 p1 4 /d 12 p1 3 /d 11 p1 2 /d 10 p1 1 /d 9 p1 0 /d 8 pc 7 /a 7 pc 6 /a 6 pc 5 /a 5 pc 4 /a 4 pc 3 /a 3 pc 2 /a 2 pc 1 /a 1 pc 0 /a 0 pb 7 /a 15 pb 6 /a 14 pb 5 /a 13 pb 4 /a 12 pb 3 /a 11 pb 2 /a 10 pb 1 /a 9 pb 0 /a 8 port 2 port 1 port c port b port a port 9 port 8 port 7 port 3 port 4 port 5 port 6 clock oscil- lator wait- state controller ram 2 kbytes prom or masked rom 60 kbytes interrupt controller data transfer controller h8/500 cpu watchdog timer 10-bit a/d converter (12 channels) 16-bit integrated- timer pulse unit (ipu) bus controller serial communication interface (2 channels) address bus data bus (upper) data bus (lower) data bus (lower) data bus (upper) address bus extal xtal reso nmi res stby md 0 md 1 md 2 hwr lwr rd as v cc v cc v cc v ss v ss v ss v ss v ss v ss av cc av ss v ref 5
figure 1-2 h8/539 block diagram pa 6 /back/t3oc 2 /txd 3 pa 5 /breq/t3oc 1 /rxd 3 pa 4 /wait pa 3 /a 19 /t5oc 2 /sck 3 pa 2 /a 18 /t5oc 1 /pw 3 pa 1 /a 17 /t4oc 2 /pw 2 pa 0 /a 16 /t4oc 1 /pw 1 p9 7 /an 7 p9 6 /an 6 p9 5 /an 5 p9 4 /an 4 p9 3 /an 3 p9 2 /an 2 p9 1 /an 1 p9 0 /an 0 p8 3 /an 11 p8 2 /an 10 p8 1 /an 9 p8 0 /an 8 p7 7 /sck 2 /pw 2 p7 6 /sck 1 /pw 1 p7 5 /rxd 2 p7 4 /txd 2 p7 3 /rxd 1 p7 2 /txd 1 p7 1 /irq 1 /adtrg p7 0 /irq 0 p3 5 /t2oc 2 p3 4 /t2oc 1 p3 3 /t1oc 4 p3 2 /t1oc 3 p3 1 /t1oc 2 p3 0 /t1oc 1 p4 7 /t7ioc 2 p4 6 /t7ioc 1 p4 5 /t6ioc 2 p4 4 /t6ioc 1 p4 3 /t5ioc 2 p4 2 /t5ioc 1 p4 1 /t4ioc 2 p4 0 /t4ioc 1 p5 7 /t3ioc 2 p5 6 /t3ioc 1 p5 5 /t2ioc 2 p5 4 /t2ioc 1 p5 3 /t1ioc 4 p5 2 /t1ioc 3 p5 1 /t1ioc 2 p5 0 /t1ioc 1 p6 4 /tclk 3 p6 3 /tclk 2 p6 2 /tclk 1 p6 1 /irq 3 p6 0 /irq 2 /pw 3 p2 7 /d 7 p2 6 /d 6 p2 5 /d 5 p2 4 /d 4 p2 3 /d 3 p2 2 /d 2 p2 1 /d 1 p2 0 /d 0 p1 7 /d 15 p1 6 /d 14 p1 5 /d 13 p1 4 /d 12 p1 3 /d 11 p1 2 /d 10 p1 1 /d 9 p1 0 /d 8 pc 7 /a 7 pc 6 /a 6 pc 5 /a 5 pc 4 /a 4 pc 3 /a 3 pc 2 /a 2 pc 1 /a 1 pc 0 /a 0 pb 7 /a 15 pb 6 /a 14 pb 5 /a 13 pb 4 /a 12 pb 3 /a 11 pb 2 /a 10 pb 1 /a 9 pb 0 /a 8 port 2 port 1 port c port b port a port 9 port 8 port 7 port 3 port 4 port 5 port 6 clock oscil- lator wait- state controller ram 4 kbytes prom or masked rom 128 kbytes interrupt controller data transfer controller h8/500 cpu watchdog timer 10-bit a/d converter (12 channels) 16-bit integrated- timer pulse unit (ipu) bus controller serial communication interface (3 channels) address bus data bus (upper) data bus (lower) data bus (lower) data bus (upper) address bus extal xtal reso nmi res stby md 0 md 1 md 2 hwr lwr rd as v cc v cc v cc v ss v ss v ss v ss v ss v ss av cc av ss v ref multiplier pwm timer (3 channels) 6
1.3 pin descriptions 1.3.1 pin arrangement figure 1-3 shows the pin arrangement of the h8/538 (fp-112 package). figure 1-4 shows the pin arrangement of the h8/539 (fp-112 package). figure 1-3 h8/538 pin arrangement (fp-112, top view) pin 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 av cc md 2 md 1 md 0 lwr hwr rd as v cc xtal extal v ss nmi res stby pa 6 /back/t3oc 2 pa 5 /breq/t3oc 1 pa 4 /wait pa 3 /a 19 /t5oc 2 pa 2 /a 18 /t5oc 1 pa 1 /a 17 /t4oc 2 pa 0 /a 16 /t4oc 1 pb 7 /a 15 pb 6 /a 14 pb 5 /a 13 pb 4 /a 12 pb 3 /a 11 p5 0 /t1ioc 1 p5 1 /t1ioc 2 p5 2 /t1ioc 3 p5 3 /t1ioc 4 p5 4 /t2ioc 1 p5 5 /t2ioc 2 p5 6 /t3ioc 1 p5 7 /t3ioc 2 v ss p4 0 /t4ioc 1 p4 1 /t4ioc 2 p4 2 /t5ioc 1 p4 3 /t5ioc 2 p4 4 /t6ioc 1 p4 5 /t6ioc 2 p4 6 /t7ioc 1 p4 7 /t7ioc 2 p3 0 /t1oc 1 p3 1 /t1oc 2 p3 2 /t1oc 3 p3 3 /t1oc 4 p3 4 /t2oc 1 p3 5 /t2oc 2 v ss p2 0 /d 0 p2 1 /d 1 h8/538 hd6475388f japan v cc reso top view (fp-112) 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 pb 2 /a 10 pb 1 /a 9 pb 0 /a 8 v ss pc 7 /a 7 pc 6 /a 6 pc 5 /a 5 pc 4 /a 4 pc 3 /a 3 pc 2 /a 2 pc 1 /a 1 pc 0 /a 0 v cc p1 7 /d 15 p1 6 /d 14 p1 5 /d 13 p1 4 /d 12 p1 3 /d 11 p1 2 /d 10 p1 1 /d 9 p1 0 /d 8 v ss p2 7 /d 7 p2 6 /d 6 p2 5 /d 5 p2 4 /d 4 p2 3 /d 3 p2 2 /d 2 v ref p9 0 /an 0 p9 1 /an 1 p9 2 /an 2 p9 3 /an 3 p9 4 /an 4 p9 5 /an 5 p9 6 /an 6 p9 7 /an 7 p8 0 /an 8 p8 1 /an 9 p8 2 /an 10 p8 3 /an 11 av ss v ss p7 0 /irq 0 p7 1 /irq 1 / adtrg p7 2 /txd 1 p7 3 /rxd 1 p7 4 /txd 2 p7 5 /rxd 2 p7 6 /sck 1 p7 7 /sck 2 p6 0 /irq 2 p6 1 /irq 3 p6 2 /tclk 1 p6 3 /tclk 2 p6 4 /tclk 3 7
figure 1-4 h8/539 pin arrangement (fp-112, top view) pin 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 av cc md 2 md 1 md 0 lwr hwr rd as v cc xtal extal v ss nmi res stby pa 6 /back/t3oc 2 /txd 3 pa 5 /breq/t3oc 1 /rxd 3 pa 4 /wait pa 3 /a 19 /t5oc 2 /sck 3 pa 2 /a 18 /t5oc 1 /pw 3 pa 1 /a 17 /t4oc 2 /pw 2 pa 0 /a 16 /t4oc 1 /pw 1 pb 7 /a 15 pb 6 /a 14 pb 5 /a 13 pb 4 /a 12 pb 3 /a 11 p5 0 /t1ioc 1 p5 1 /t1ioc 2 p5 2 /t1ioc 3 p5 3 /t1ioc 4 p5 4 /t2ioc 1 p5 5 /t2ioc 2 p5 6 /t3ioc 1 p5 7 /t3ioc 2 v ss p4 0 /t4ioc 1 p4 1 /t4ioc 2 p4 2 /t5ioc 1 p4 3 /t5ioc 2 p4 4 /t6ioc 1 p4 5 /t6ioc 2 p4 6 /t7ioc 1 p4 7 /t7ioc 2 p3 0 /t1oc 1 p3 1 /t1oc 2 p3 2 /t1oc 3 p3 3 /t1oc 4 p3 4 /t2oc 1 p3 5 /t2oc 2 v ss p2 0 /d 0 p2 1 /d 1 h8/539 hd6475398f japan v cc reso top view (fp-112) 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 pb 2 /a 10 pb 1 /a 9 pb 0 /a 8 v ss pc 7 /a 7 pc 6 /a 6 pc 5 /a 5 pc 4 /a 4 pc 3 /a 3 pc 2 /a 2 pc 1 /a 1 pc 0 /a 0 v cc p1 7 /d 15 p1 6 /d 14 p1 5 /d 13 p1 4 /d 12 p1 3 /d 11 p1 2 /d 10 p1 1 /d 9 p1 0 /d 8 v ss p2 7 /d 7 p2 6 /d 6 p2 5 /d 5 p2 4 /d 4 p2 3 /d 3 p2 2 /d 2 v ref p9 0 /an 0 p9 1 /an 1 p9 2 /an 2 p9 3 /an 3 p9 4 /an 4 p9 5 /an 5 p9 6 /an 6 p9 7 /an 7 p8 0 /an 8 p8 1 /an 9 p8 2 /an 10 p8 3 /an 11 av ss v ss p7 0 /irq 0 p7 1 /irq 1 /adtrg p7 2 /txd 1 p7 3 /rxd 1 p7 4 /txd 2 p7 5 /rxd 2 p7 6 /sck 1 /pw 1 p7 7 /sck 2 /pw 2 p6 0 /irq 2 /pw 3 p6 1 /irq 3 p6 2 /tclk 1 p6 3 /tclk 2 p6 4 /tclk 3 8
1.3.2 pin functions (1) pin assignments in each operating mode: table 1-2 lists the assignments of the pins of the fp-112 package in each operating mode. h8/538 and h8/539 pin functions are the same unless otherwise noted. table 1-2 pin assignments in each operating mode (fp-112) expanded minimum expanded maximum single-chip modes modes mode modes modes prom no. 1 and 6 mode 2 3 and 5 mode 4 mode 7 mode 1v cc v cc v cc v cc v cc v cc 2p5 0 /t1ioc 1 p5 0 /t1ioc 1 p5 0 /t1ioc 1 p5 0 /t1ioc 1 p5 0 /t1ioc 1 nc 3p5 1 /t1ioc 2 p5 1 /t1ioc 2 p5 1 /t1ioc 2 p5 1 /t1ioc 2 p5 1 /t1ioc 2 nc 4p5 2 /t1ioc 3 p5 2 /t1ioc 3 p5 2 /t1ioc 3 p5 2 /t1ioc 3 p5 2 /t1ioc 3 nc 5p5 3 /t1ioc 4 p5 3 /t1ioc 4 p5 3 /t1ioc 4 p5 3 /t1ioc 4 p5 3 /t1ioc 4 nc 6p5 4 /t2ioc 1 p5 4 /t2ioc 1 p5 4 /t2ioc 1 p5 4 /t2ioc 1 p5 4 /t2ioc 1 nc 7p5 5 /t2ioc 2 p5 5 /t2ioc 2 p5 5 /t2ioc 2 p5 5 /t2ioc 2 p5 5 /t2ioc 2 nc 8p5 6 /t3ioc 1 p5 6 /t3ioc 1 p5 6 /t3ioc 1 p5 6 /t3ioc 1 p5 6 /t3ioc 1 nc 9p5 7 /t3ioc 2 p5 7 /t3ioc 2 p5 7 /t3ioc 2 p5 7 /t3ioc 2 p5 7 /t3ioc 2 nc 10 v ss v ss v ss v ss v ss v ss 11 p4 0 /t4ioc 1 p4 0 /t4ioc 1 p4 0 /t4ioc 1 p4 0 /t4ioc 1 p4 0 /t4ioc 1 nc 12 p4 1 /t4ioc 2 p4 1 /t4ioc 2 p4 1 /t4ioc 2 p4 1 /t4ioc 2 p4 1 /t4ioc 2 nc 13 p4 2 /t5ioc 1 p4 2 /t5ioc 1 p4 2 /t5ioc 1 p4 2 /t5ioc 1 p4 2 /t5ioc 1 nc 14 p4 3 /t5ioc 2 p4 3 /t5ioc 2 p4 3 /t5ioc 2 p4 3 /t5ioc 2 p4 3 /t5ioc 2 nc 15 p4 4 /t6ioc 1 p4 4 /t6ioc 1 p4 4 /t6ioc 1 p4 4 /t6ioc 1 p4 4 /t6ioc 1 nc 16 p4 5 /t6ioc 2 p4 5 /t6ioc 2 p4 5 /t6ioc 2 p4 5 /t6ioc 2 p4 5 /t6ioc 2 nc 17 p4 6 /t7ioc 1 p4 6 /t7ioc 1 p4 6 /t7ioc 1 p4 6 /t7ioc 1 p4 6 /t7ioc 1 nc 18 p4 7 /t7ioc 2 p4 7 /t7ioc 2 p4 7 /t7ioc 2 p4 7 /t7ioc 2 p4 7 /t7ioc 2 nc 19 reso reso reso reso reso v pp 20 p3 0 /t1oc 1 p3 0 /t1oc 1 p3 0 /t1oc 1 p3 0 /t1oc 1 p3 0 /t1oc 1 nc 21 p3 1 /t1oc 2 p3 1 /t1oc 2 p3 1 /t1oc 2 p3 1 /t1oc 2 p3 1 /t1oc 2 nc 22 p3 2 /t1oc 3 p3 2 /t1oc 3 p3 2 /t1oc 3 p3 2 /t1oc 3 p3 2 /t1oc 3 nc 23 p3 3 /t1oc 4 p3 3 /t1oc 4 p3 3 /t1oc 4 p3 3 /t1oc 4 p3 3 /t1oc 4 nc notes: 1. for the prom mode, see section 18, rom. 2. pins marked nc should be left unconnected. 9
10 table 1-2 pin assignments in each operating mode (fp-112) (cont) expanded minimum expanded maximum single-chip modes modes mode modes modes prom no. 1 and 6 mode 2 3 and 5 mode 4 mode 7 mode 24 p3 4 /t2oc 1 p3 4 /t2oc 1 p3 4 /t2oc 1 p3 4 /t2oc 1 p3 4 /t2oc 1 nc 25 p3 5 /t2oc 2 p3 5 /t2oc 2 p3 5 /t2oc 2 p3 5 /t2oc 2 p3 5 /t2oc 2 nc 26 v ss v ss v ss v ss v ss v ss 27 d 0 p2 0 d 0 d 0 p2 0 nc 28 d 1 p2 1 d 1 d 1 p2 1 nc 29 d 2 p2 2 d 2 d 2 p2 2 nc 30 d 3 p2 3 d 3 d 3 p2 3 nc 31 d 4 p2 4 d 4 d 4 p2 4 nc 32 d 5 p2 5 d 5 d 5 p2 5 nc 33 d 6 p2 6 d 6 d 6 p2 6 nc 34 d 7 p2 7 d 7 d 7 p2 7 nc 35 v ss v ss v ss v ss v ss v ss 36 d 8 d 8 d 8 d 8 p1 0 o 0 37 d 9 d 9 d 9 d 9 p1 1 o 1 38 d 10 d 10 d 10 d 10 p1 2 o 2 39 d 11 d 11 d 11 d 11 p1 3 o 3 40 d 12 d 12 d 12 d 12 p1 4 o 4 41 d 13 d 13 d 13 d 13 p1 5 o 5 42 d 14 d 14 d 14 d 14 p1 6 o 6 43 d 15 d 15 d 15 d 15 p1 7 o 7 44 v cc v cc v cc v cc v cc v cc 45 a 0 pc 0 /a 0 a 0 pc 0 /a 0 pc 0 a 0 46 a 1 pc 1 /a 1 a 1 pc 1 /a 1 pc 1 a 1 47 a 2 pc 2 /a 2 a 2 pc 2 /a 2 pc 2 a 2 48 a 3 pc 3 /a 3 a 3 pc 3 /a 3 pc 3 a 3 49 a 4 pc 4 /a 4 a 4 pc 4 /a 4 pc 4 a 4 50 a 5 pc 5 /a 5 a 5 pc 5 /a 5 pc 5 a 5 notes: 1. for the prom mode, see section 18, ?om. 2. pins marked nc should be left unconnected.
11 table 1-2 pin assignments in each operating mode (fp-112) (cont) expanded minimum expanded maximum single-chip modes modes mode modes modes prom no. 1 and 6 mode 2 3 and 5 mode 4 mode 7 mode 51 a 6 pc 6 /a 6 a 6 pc 6 /a 6 pc 6 a 6 52 a 7 pc 7 /a 7 a 7 pc 7 /a 7 pc 7 a 7 53 v ss v ss v ss v ss v ss v ss 54 a 8 pb 0 /a 8 a 8 pb 0 /a 8 pb 0 a 8 55 a 9 pb 1 /a 9 a 9 pb 1 /a 9 pb 1 oe 56 a 10 pb 2 /a 10 a 10 pb 2 /a 10 pb 2 a 10 57 a 11 pb 3 /a 11 a 11 pb 3 /a 11 pb 3 a 11 58 a 12 pb 4 /a 12 a 12 pb 4 /a 12 pb 4 a 12 59 a 13 pb 5 /a 13 a 13 pb 5 /a 13 pb 5 a 13 60 a 14 pb 6 /a 14 a 14 pb 6 /a 14 pb 6 a 14 61 a 15 pb 7 /a 15 a 15 pb 7 /a 15 pb 7 ce 62 pa 0 /t4oc 1 /pa 0 /t4oc 1 /a 16 pa 0 /a 16 /pa 0 /t4oc 1 /v cc pw 1 * 3 pw 1 * 3 pw 1 * 3 pw 1 * 3 63 pa 1 /t4oc 2 /pa 1 /t4oc 2 /a 17 pa 1 /a 17 /pa 1 /t4oc 2 /v cc pw 2 * 3 pw 2 * 3 pw 2 * 3 pw 2 * 3 64 pa 2 /t5oc 1 /pa 2 /t5oc 1 /a 18 pa 2 /a 18 /pa 2 /t5oc 1 /nc pw 3 * 3 pw 3 * 3 pw 3 * 3 pw 3 * 3 65 pa 3 /t5oc 2 /pa 3 /t5oc 2 /a 19 pa 3 /a 19 /pa 3 /t5oc 2 /nc sck 3 * 3 sck 3 * 3 sck 3 * 3 sck 3 * 3 66 pa 4 / wait pa 4 / wait pa 4 / wait pa 4 / wait pa 4 a 16 67 pa 5 / breq /pa 5 / breq /pa 5 / breq /pa 5 / breq /pa 5 /t3oc 1 /nc t3oc 1 /rxd 3 * 3 t3oc 1 /rxd 3 * 3 t3oc 1 /rxd 3 * 3 t3oc 1 /rxd 3 * 3 rxd 3 * 3 68 pa 6 / back /pa 6 / back /pa 6 / back /pa 6 / back /pa 6 /t3oc 2 /nc t3oc 2 /txd 3 * 3 t3oc 2 /txd 3 * 3 t3oc 2 /txd 3 * 3 t3oc 2 /txd 3 * 3 txd 3 * 3 69 nc 70 stby stby stby stby stby v ss 71 res res res res res v ss 72 nmi nmi nmi nmi nmi a 9 notes: 1. for the prom mode, see section 18, rom. 2. pins marked nc should be left unconnected. 3. in the h8/538, port a does not have the pw 1 to pw 3 , sck 3 , rxd 3 , and txd 3 functions.
12 table 1-2 pin assignments in each operating mode (fp-112) (cont) expanded minimum expanded maximum single-chip modes modes mode modes modes prom no. 1 and 6 mode 2 3 and 5 mode 4 mode 7 mode 73 v ss v ss v ss v ss v ss v ss 74 extal extal extal extal extal nc 75 xtal xtal xtal xtal xtal nc 76 v cc v cc v cc v cc v cc v cc 77 as as as as as nc 78 rd rd rd rd rd nc 79 hwr hwr hwr hwr hwr nc 80 lwr lwr lwr lwr lwr nc 81 md 0 md 0 md 0 md 0 md 0 v ss 82 md 1 md 1 md 1 md 1 md 1 v ss 83 md 2 md 2 md 2 md 2 md 2 v ss 84 av cc av cc av cc av cc av cc v cc 85 v ref v ref v ref v ref v ref v cc 86 p9 0 /an 0 p9 0 /an 0 p9 0 /an 0 p9 0 /an 0 p9 0 /an 0 nc 87 p9 1 /an 1 p9 1 /an 1 p9 1 /an 1 p9 1 /an 1 p9 1 /an 1 nc 88 p9 2 /an 2 p9 2 /an 2 p9 2 /an 2 p9 2 /an 2 p9 2 /an 2 nc 89 p9 3 /an 3 p9 3 /an 3 p9 3 /an 3 p9 3 /an 3 p9 3 /an 3 nc 90 p9 4 /an 4 p9 4 /an 4 p9 4 /an 4 p9 4 /an 4 p9 4 /an 4 nc 91 p9 5 /an 5 p9 5 /an 5 p9 5 /an 5 p9 5 /an 5 p9 5 /an 5 nc 92 p9 6 /an 6 p9 6 /an 6 p9 6 /an 6 p9 6 /an 6 p9 6 /an 6 nc 93 p9 7 /an 7 p9 7 /an 7 p9 7 /an 7 p9 7 /an 7 p9 7 /an 7 nc 94 p8 0 /an 8 p8 0 /an 8 p8 0 /an 8 p8 0 /an 8 p8 0 /an 8 nc 95 p8 1 /an 9 p8 1 /an 9 p8 1 /an 9 p8 1 /an 9 p8 1 /an 9 nc 96 p8 2 /an 10 p8 2 /an 10 p8 2 /an 10 p8 2 /an 10 p8 2 /an 10 nc 97 p8 3 /an 11 p8 3 /an 11 p8 3 /an 11 p8 3 /an 11 p8 3 /an 11 nc 98 av ss av ss av ss av ss av ss v ss 99 v ss v ss v ss v ss v ss v ss notes: 1. for the prom mode, see section 18, rom. 2. pins marked nc should be left unconnected.
13 table 1-2 pin assignments in each operating mode (fp-112) (cont) expanded minimum expanded maximum single-chip modes modes mode modes modes prom no. 1 and 6 mode 2 3 and 5 mode 4 mode 7 mode 100 p7 0 /irq 0 p7 0 /irq 0 p7 0 /irq 0 p7 0 /irq 0 p7 0 /irq 0 a 15 101 p7 1 /irq 1 /p7 1 /irq 1 /p7 1 /irq 1 /p7 1 /irq 1 /p7 1 /irq 1 / pgm adtrg adtrg adtrg adtrg adtrg 102 p7 2 /txd 1 p7 2 /txd 1 p7 2 /txd 1 p7 2 /txd 1 p7 2 /txd 1 nc 103 p7 3 /rxd 1 p7 3 /rxd 1 p7 3 /rxd 1 p7 3 /rxd 1 p7 3 /rxd 1 nc 104 p7 4 /txd 2 p7 4 /txd 2 p7 4 /txd 2 p7 4 /txd 2 p7 4 /txd 2 nc 105 p7 5 /rxd 2 p7 5 /rxd 2 p7 5 /rxd 2 p7 5 /rxd 2 p7 5 /rxd 2 nc 106 p7 6 /sck 1 /p7 6 /sck 1 /p7 6 /sck 1 /p7 6 /sck 1 /p7 6 /sck 1 /nc pw 1 * 3 pw 1 * 3 pw 1 * 3 pw 1 * 3 pw 1 * 3 107 p7 7 /sck 2 /p7 7 /sck 2 /p7 7 /sck 2 /p7 7 /sck 2 /p7 7 /sck 2 /nc pw 2 * 3 pw 2 * 3 pw 2 * 3 pw 2 * 3 pw 2 * 3 108 p6 0 /irq 2 /p6 0 /irq 2 /p6 0 /irq 2 /p6 0 /irq 2 /p6 0 /irq 2 /nc pw 3 * 3 pw 3 * 3 pw 3 * 3 pw 3 * 3 pw 3 * 3 109 p6 1 /irq 3 p6 1 /irq 3 p6 1 /irq 3 p6 1 /irq 3 p6 1 /irq 3 nc 110 p6 2 /tclk 1 p6 2 /tclk 1 p6 2 /tclk 1 p6 2 /tclk 1 p6 2 /tclk 1 nc 111 p6 3 /tclk 2 p6 3 /tclk 2 p6 3 /tclk 2 p6 3 /tclk 2 p6 3 /tclk 2 nc 112 p6 4 /tclk 3 p6 4 /tclk 3 p6 4 /tclk 3 p6 4 /tclk 3 p6 4 /tclk 3 nc notes: 1. for the prom mode, see section 18, ?om. 2. pins marked nc should be left unconnected. 3. in the h8/538, port 7 does not have the pw 1 and pw 2 functions, and port 6 does not have the pw 3 function.
14 (2) pin functions: table 1-3 indicates the function of each pin. h8/538 and h8/539 pin functions are the same unless otherwise noted. table 1-3 pin functions type symbol pin no. i/o name and function power v cc 1, 44, 76 input power: connected to the power supply (+5 v). connect all v cc pins to the +5-v system power supply. the chip will not operate if any v cc pin is left unconnected. v ss 10, 26, input ground: connected to ground (0 v). connect 35, 53, all v ss pins to the 0-v system power supply. 73, 99 the chip will not operate if any v ss pin is left unconnected. clock xtal 75 input crystal: connected to a crystal resonator. for the h8/539, the frequency should be equal to the desired system clock frequency ( ). for the h8/538, the frequency should be double the frequency. if an external clock is input at the extal pin, input a complementary clock at xtal. extal 74 input crystal/external clock: connected to a crystal resonator or external clock. for the h8/539, the frequency should be equal to the desired system clock frequency ( ). for the h8/538, the frequency should be double the frequency. see section 9.2, ?scillator circuit?for examples of connections at xtal and extal. 69 output system clock: supplies the system clock (? to peripheral devices. system back 68 output bus request acknowledge: indicates that the control bus right has been granted to an external device. a device requesting the bus sends a breq signal to the microcontroller. the microcontroller replies with a back signal. breq 67 input bus request: sent by an external device to the microcomputer chip to request the bus right. granting of the bus is indicated by the back signal. stby 70 input standby: input pin for transition to the hardware standby mode (a power-down state). res 71 input reset: input pin for transition to the reset state.
table 1-3 pin functions (cont) type symbol pin no. i/o name and function address a 19 ? 0 65?4, output address bus: address output pins. bus 52?5 data bus d 15 ? 0 43?6, input/ data bus: sixteen-bit bidirectional data bus. 34?7 output bus wait 66 input wait: requests insertion of wait states (t w ) in control external-device access cycles by the cpu; signals used for interfacing to low-speed external devices. as 77 output address strobe: indicates valid address output on the address bus during external-device access. rd 78 output read: indicates reading of data from the data bus during external-device access. the cpu latches read data at the rising edge of rd . hwr 79 output high write: indicates output of data on the upper data bus (d 15 to d 8 ) during external- device access. lwr 80 output low write: indicates output of data on the lower data bus (d 7 to d 0 ) during external-device access. interrupt nmi 72 input nonmaskable interrupt: nonmaskable signals interrupt request signal. the input edge can be selected in the nmi control register (nmicr). irq 0 100 input interrupt request 0 to 3: maskable interrupt irq 1 101 request signals. the type of input can be irq 2 108 selected in the irq control register (irqcr). irq 3 109 15
table 1-3 pin functions (cont) type symbol pin no. i/o name and function operating md 2 83 input mode 2 to mode 0: input pins for setting the mode md 1 82 operating mode. the following table lists the control md 0 81 operating modes and bus widths. h8/539 h8/500 cpu exter- mode inputs operating operating on-chip nal md 2 md 1 md 0 mode mode rom bus 0 0 0 do not use 0 0 1 mode 1 expanded disabled 16 bits minimum 0 1 0 mode 2 expanded enabled 8 bits minimum 0 1 1 mode 3 expanded disabled 16 bits maximum 1 0 0 mode 4 expanded enabled 16 bits maximum 1 0 1 mode 5 expanded disabled 16 bits maximum 1 1 0 mode 6 expanded disabled 16 bits minimum 1 1 1 mode 7 single chip enabled maximum * 1 serial txd 1 102 output transmit data 1, 2, and 3 * 2 : serial data output commu- txd 2 104 pins for sci1, sci2, and sci3. nication txd 3 68 interface rxd 1 103 input receive data 1, 2, and 3 * 2 : serial data input (sci) rxd 2 105 pins for sci1, sci2, and sci3. rxd 3 67 sck 1 106 input/ serial clock 1, 2, and 3 * 2 : serial clock sck 2 107 output input/output pins for sci1, sci2, and sci3. sck 3 65 used for input and output of the serial clock in clocked synchronous mode, and of the sci operating clock in asynchronous mode. pwm pw 1 62 output pwm1, pwm2, and pwm3 output: output timer * 3 106 pins for pwm1, pwm2, and pwm3. pw 2 63 output 107 pw 3 64 output 108 notes: 1. minimum mode in the h8/538. 2. the h8/538 does not have txd 3 , rxd 3 , and sck 3 . 3. the h8/538 does not have pw 1 to pw 3 . 16
table 1-3 pin functions (cont) type symbol pin no. i/o name and function 16-bit t1ioc 1 2 input/ input capture/output compare 1 to 4 integrated- t1ioc 2 3 output (channel 1): input capture or output compare timer pulse t1ioc 3 4 pins for ipu channel 1. unit (ipu) t1ioc 4 5 t1oc 1 20 output output compare 1 to 4 (channel 1): output t1oc 2 21 compare pins for ipu channel 1. t1oc 3 22 t1oc 4 23 t2ioc 1 6 input/ input capture/output compare 1 and 2 t2ioc 2 7 output (channel 2): input capture or output compare pins for ipu channel 2. t2oc 1 24 output output compare 1 and 2 (channel 2): output t2oc 2 25 compare pins for ipu channel 2. t3ioc 1 8 input/ input capture/output compare 1 and 2 t3ioc 2 9 output (channel 3): input capture or output compare pins for ipu channel 3. t3oc 1 67 output output compare 1 and 2 (channel 3): t3oc 2 68 output compare pins for ipu channel 3. t4ioc 1 11 input/ input capture/output compare 1 and 2 t4ioc 2 12 output (channel 4): input capture or output compare pins for ipu channel 4. t4oc 1 62 output output compare 1 and 2 (channel 4): output t4oc 2 63 compare pins for ipu channel 4. t5ioc 1 13 input/ input capture/output compare 1 and 2 t5ioc 2 14 output (channel 5): input capture or output compare pins for ipu channel 5. t5oc 1 64 output output compare 1 and 2 (channel 5): output t5oc 2 65 compare pins for ipu channel 5. t6ioc 1 15 input/ input capture/output compare 1 and 2 t6ioc 2 16 output (channel 6): input capture or output compare pins for ipu channel 6. t7ioc 1 17 input/ input capture/output compare 1 and 2 t7ioc 2 18 output (channel 7): input capture or output compare pins for ipu channel 7. tclk 1 110 input timer clock 1 to 3 (all channels): ipu tclk 2 111 external clock input pins. all channels can tclk 3 112 select these clock inputs. 17
table 1-3 pin functions (cont) type symbol pin no. i/o name and function a/d an 11 ?n 0 97?6 input analog input 11 to 0: analog input pins for the converter a/d converter. v ref 85 input reference power supply: input pin for the a/d converters full-scale reference voltage. av cc 84 input analog power supply: power supply pin for analog circuits in the a/d converter. connect to a regulated +5-v analog power supply separate from the other power supply pins. av ss 98 input analog ground: ground pin for analog circuits in the a/d converter. connect to a regulated 0-v analog power supply separate from the other power supply pins. adtrg 101 input a/d trigger: trigger input for starting a/d conversion. conversion is triggered by the falling edge of adtrg. watchdog reso 19 output reset output: if reset output is selected, a low timer pulse is output for 132 cycles when the watchdog timer overflows. reso is an open- drain output pin and should be pulled up to v cc (+5 v) externally, regardless of whether reset output is selected or not. i/o ports p1 7 ?p1 0 43 ?6 input/ port 1: 8-bit input/output port. the direction of output each bit can be selected in the port 1 data direction register (p1ddr). p2 7 ?p2 0 34?7 input/ port 2: 8-bit input/output port. the direction of output each bit can be selected in the port 2 data direction register (p2ddr). p3 5 ?p3 0 25?0 input/ port 3: 6-bit input/output port. the direction of output each bit can be selected in the port 3 data direction register (p3ddr). leds can be driven directly (10-ma sink). p4 7 ?p4 0 18 ?1 input/ port 4: 8-bit input/output port with schmitt- output trigger inputs. the direction of each bit can be selected in the port 4 data direction register (p4ddr). p5 7 ?p5 0 9 ?2 input/ port 5: 8-bit input/output port with schmitt- output trigger inputs. the direction of each bit can be selected in the port 5 data direction register (p5ddr). leds can be driven directly (10-ma sink). 18
19 table 1-3 pin functions (cont) type symbol pin no. i/o name and function i/o ports p6 4 ?p6 0 112?08 input/ port 6: 5-bit input/output port. the direction of output each bit can be selected in the port 6 data direction register (p6ddr). p7 7 ?p7 0 107?00 input/ port 7: 8-bit input/output port. the direction of output each bit can be selected in the port 7 data direction register (p7ddr). p8 3 ?p8 0 97 ?94 input port 8: 4-bit input port. p9 7 ?p9 0 93 ?86 input port 9: 8-bit input port. pa 6 ?pa 0 68 ?62 input/ port a: 7-bit input/output port. the direction output of each bit can be selected in the port a data direction register (paddr). pb 7 ?pb 0 61 ?54 input/ port b: 8-bit input/output port with mos input output pull-up transistors. the direction of each bit can be selected in the port b data direction register (pbddr). pc 7 ?pc 0 52 ?45 input/ port c: 8-bit input/output port with mos input output pull-up transistors. the direction of each bit can be selected in the port c data direction register (pcddr).
20
section 2 operating modes 2.1 overview 2.1.1 selection of operating mode the h8/538 and h8/539 have seven operating modes (modes 1 to 7). modes 1 to 6 are externally expanded modes in which external memory and peripheral devices can be accessed. modes 1, 2, and 6 are expanded minimum modes, supporting a 64-kbyte address space. modes 3, 4, and 5 are expanded maximum modes, supporting a maximum 1-mbyte address space. mode 7 is a single-chip mode: all ports are available for general-purpose input and output, but external addresses cannot be used. mode 7 is a minimum mode in the h8/538, and a maximum mode in the h8/539. mode 0 is reserved for future use and must not be selected in the h8/538 or h8/539. both the pin functions and address space vary depending on the mode. table 2-1 summarizes the selection of operating modes. table 2-1 operating mode selection mcu cpu operating operating on-chip on-chip data bus mode md 2 md 1 md 0 description mode ram rom width mode 0 0 0 0 mode 1 0 0 1 expanded minimum enabled * 1 disabled 16 bits minimum mode mode mode 2 0 1 0 expanded minimum enabled * 1 enabled 8 bits minimum mode mode mode 3 0 1 1 expanded maximum enabled * 1 disabled 16 bits maximum mode mode mode 4 1 0 0 expanded maximum enabled * 1 enabled 16 bits maximum mode mode mode 5 1 0 1 expanded maximum enabled * 1 disabled 16 bits * 2 maximum mode mode 21
table 2-1 operating mode selection (cont) mcu cpu operating operating on-chip on-chip data bus mode md 2 md 1 md 0 description mode ram rom width mode 6 1 1 0 expanded minimum enabled * 1 disabled 16 bits * 2 minimum mode mode mode 7 1 1 1 single-chip minimum enabled enabled mode mode (h8/538) maximum mode (h8/539) legend 0: low 1: high ? not available notes: 1. h8/539: if ram enable bits 1 and 2 (rame1 and rame2) in the ram control register (ramcr) are cleared to 0, these addresses become external addresses. h8/538: if the ram enable bit (rame) in the ram control register (ramcr) is cleared to 0, these addresses become external addresses. 2. eight-bit three-state-access address space after a reset. 2.1.2 register configuration the mcu operating mode can be monitored in the mode control register (mdcr). table 2-2 summarizes this register. table 2-2 register configuration address name abbreviation r/w initial value h'ff19 mode control register mdcr r undetermined 22
2.2 mode control register the mode control register (mdcr) is an eight-bit register that indicates the current operating mode of the h8/538 or h8/539. the mdcr bit structure is shown next. (1) bits 7 and 6?eserved: read-only bits, always read as 1. (2) bits 5 to 3?eserved: read-only bits, always read as 0. (3) bits 2 to 0?ode select 2 to 0 (mds2 to mds0): these bits indicate the values of pins md 2 to md 0 latched at the rise of the res signal (the current operating mode). mds2 to mds0 correspond to md 2 to md 0 . mds2 to mds0 are read-only bits. bit initial value r/w 7 1 6543210 1000 * * * r r r mode select 2 to 0 mds2 mds1 mds0 bits indicating the current operating mode determined by pins md 2 to md 0 . mdcr latches the inputs at the mode pins (md 2 to md 0 ) at the rise of the res signal. note: * reserved bits 23
2.3 operating mode descriptions 2.3.1 mode 1 (expanded minimum mode) in mode 1 the data bus is 16 bits wide. the bus controllers byte area register (arbt) is enabled in mode 1, so part of the address space can be accessed with an eight-bit bus width. the maximum address space supported in mode 1 is 64 kbytes. the on-chip rom is disabled in mode 1. 2.3.2 mode 2 (expanded minimum mode) in mode 2 the data bus is eight bits wide. the on-chip rom is enabled. the maximum address space supported in mode 2 is 64 kbytes. the bus controllers byte-area register (arbt) is disabled in mode 2. 2.3.3 mode 3 (expanded maximum mode) in mode 3 the data bus is 16 bits wide. the bus controllers byte area register (arbt) is enabled in mode 3, so part of the address space can be accessed with an eight-bit bus width. the maximum address space supported in mode 3 is 1 mbyte. the on-chip rom is disabled in mode 3. 2.3.4 mode 4 (expanded maximum mode) in mode 4 the data bus is 16 bits wide. the bus controllers byte area register (arbt) is enabled in mode 4, so part of the address space can be accessed with an eight-bit bus width. the maximum address space supported in mode 4 is 1 mbyte. the on-chip rom is enabled. 2.3.5 modes 5 and 6 mode 5 is functionally identical to mode 3, and mode 6 is functionally identical to mode 1. when the chip comes out of reset, however, the bus controllers byte area register (arbt) is disabled in modes 5 and 6 and eight-bit, three-state access is performed throughout the address space. the byte area register can be enabled by setting the bcre bit to 1 in the bus control register (bcr). 2.3.6 mode 7 (single-chip mode) the external address space cannot be accessed. 24
2.4 pin functions in each operating mode the pin functions of the i/o ports vary depending on the operating mode. table 2-3 summarizes the functions in each mode in the h8/538 and h8/539. selection of pin functions is described in section 10, ?/o ports. table 2-3 pin functions in each mode expanded minimum modes expanded maximum modes single-chip mode port modes 1 and 6 mode 2 modes 3 and 5 mode 4 mode 7 port 1 data bus data bus data bus data bus input/output (d 15 to d 8 )(d 15 to d 8 )(d 15 to d 8 )(d 15 to d 8 ) port port 2 data bus input/output data bus data bus input/output (d 7 to d 0 ) port (d 7 to d 0 )(d 7 to d 0 ) port port 3 input/output input/output input/output input/output input/output port * 1 port * 1 port * 1 port * 1 port * 1 port 4 input/output input/output input/output input/output input/output port * 1 port * 1 port * 1 port * 1 port * 1 port 5 input/output input/output input/output input/output input/output port * 1 port * 1 port * 1 port * 1 port * 1 port 6 input/output input/output input/output input/output input/output port * 4, * 6 port * 4, * 6 port * 4, * 6 port * 4, * 6 port * 4, * 6 irq 2 , irq 3 irq 2 , irq 3 irq 2 , irq 3 irq 2 , irq 3 irq 2 , irq 3 port 7 input/output input/output input/output input/output input/output port * 5, * 6 port * 5, * 6 port * 5, * 6 port * 5, * 6 port * 5, * 6 irq 0 , irq 1 , irq 0 , irq 1 , irq 0 , irq 1 , irq 0 , irq 1 , irq 0 , irq 1 , adtrg adtrg adtrg adtrg adtrg port 8 input port * 3 input port * 3 input port * 3 input port * 3 input port * 3 port 9 input port * 3 input port * 3 input port * 3 input port * 3 input port * 3 port a input/output input/output input/output input/output input/output port * 2, * 4, * 6 port * 2, * 4, * 6 port * 1, * 2, * 6 port * 2, * 4, * 6 port * 2, * 4, * 6 breq , back , breq , back , breq , back , breq , back , wait wait wait , address wait , address bus (a 19 to a 16 ) bus (a 19 to a 16 ) port b address bus input port/ address bus input port/ input/output (a 15 to a 8 ) address bus (a 15 to a 8 ) address bus port (a 15 to a 8 )(a 15 to a 8 ) port c address bus input port/ address bus input port/ input/output (a 7 to a 0 ) address bus (a 7 to a 0 ) address bus port (a 7 to a 0 )(a 7 to a 0 ) notes on next page. 25
notes: 1. also used for timer input/output. 2. also used for serial communication. 3. also used for a/d conversion. 4. also used for timer input/output and pwm timer output. 5. also used for serial communication and pwm timer output. 6. the h8/538 does not have the following pin functions: port a: pwm timer output, serial communication port 7: pwm timer output port 6: pwm timer output 2.5 memory map in each mode 2.5.1 h8/538 memory maps figure 2-1 shows an h8/538 memory map for the expanded minimum modes (modes 1, 6, and 2). figure 2-2 shows a memory map for the expanded maximum modes (modes 3, 5, and 4). figure 2- 3 shows a memory map for single-chip mode (mode 7). figure 2-1 memory map in expanded minimum modes (h8/538) h'0000 h'00ff h'0100 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'0000 h'00ff h'0100 h'f67f h'f680 h'fe7f h'fe80 h'ffff modes 1 and 6 mode 2 h'ee7f h'ee80 vector table external address space on-chip ram (2 kbytes) on-chip registers (384 bytes) vector table on-chip rom (60 kbytes) external address space on-chip ram (2 kbytes) on-chip registers (384 bytes) 26
figure 2-2 memory map in expanded maximum modes (h8/538) figure 2-3 memory map in single-chip mode (h8/538) h'00000 h'001ff h'00200 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'10000 h'1ffff h'20000 h'fffff h'00000 h'001ff h'00200 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ee7f h'0ee80 h'0ffff h'10000 h'1ffff h'20000 h'fffff vector table external address space on-chip ram (2 kbytes) on-chip registers (384 bytes) external address space modes 3 and 5 vector table on-chip rom (60 kbytes) external address space on-chip ram (2 kbytes) on-chip registers (384 bytes) external address space mode 4 page 0 page 1 pages 2 to 15 page 0 page 1 pages 2 to 15 h'0000 h'00ff h'0100 h'fe7f h'fe80 h'ffff h'ee7f h'ee80 h'f67f h'f680 vector table on-chip rom (60 kbytes) on-chip ram (2 kbytes) on-chip registers (384 bytes) mode 7 27
2.5.2 h8/539 memory maps figure 2-4 shows an h8/539 memory map for the expanded minimum modes (modes 1, 2, and 6). figure 2-5 shows a memory map for the expanded maximum modes (modes 3, 4, and 5). figure 2- 6 shows a memory map for single-chip mode (mode 7). figure 2-4 memory map in expanded minimum modes (h8/539) h'0000 h'00ff h'0100 h'ee7f h'ee80 h'fe7f h'fe80 h'ffff h'0000 h'00ff h'0100 h'ee7f h'ee80 h'fe7f h'fe80 h'ffff modes 1 and 6 mode 2 h'3fff h'4000 vector table external address space on-chip ram (4 kbytes) on-chip registers (384 bytes) vector table on-chip rom (16 kbytes) external address space on-chip ram (4 kbytes) on-chip registers (384 bytes) 28
figure 2-5 memory map in expanded maximum modes (h8/539) h'00000 h'001ff h'00200 h'0ee7f h'0ee80 h'0fe7f h'0fe80 h'0ffff h'10000 h'1ffff h'20000 h'fffff h'00000 h'001ff h'00200 h'0ee7f h'0ee80 h'0fe7f h'0fe80 h'03fff h'04000 h'0ffff h'10000 h'1ffff h'20000 h'fffff vector table external address space on-chip ram (4 kbytes) on-chip registers (384 bytes) external address space modes 3 and 5 vector table on-chip rom (16 kbytes) external address space on-chip ram (4 kbytes) on-chip registers (384 bytes) on-chip rom (64 kbytes) mode 4 page 0 page 1 pages 2 to 15 page 0 page 1 pages 2 to 15 h'2ffff h'3ffff on-chip rom (64 kbytes) external address space 29
figure 2-6 memory map in single-chip mode (h8/539) h'00000 h'0fe7f h'0fe80 h'03fff h'04000 h'0ee7f h'0ee80 vector table on-chip rom (16 kbytes) on-chip ram (4 kbytes) on-chip registers (384 bytes) mode 7 on-chip rom (64 kbytes) on-chip rom (64 kbytes) h'0ffff h'10000 h'1ffff h'20000 h'2ffff h'001ff h'00200 30
section 3 cpu 3.1 overview the h8/538 and h8/539 have the h8/500 cpu, which is common to all chips in the h8/500 family. the h8/500 cpu is a high-speed central processing unit that is designed for realtime control and supports a large address space. its architecture features eight general registers, 16-bit internal data paths, and an optimized instruction set. the h8/500 cpu is suitable for control of a wide range of medium-scale office and industrial equipment. section 3 summarizes the cpu architecture, instruction set, and operation. 3.1.1 features the main features of the h8/500 cpu are listed below. general-register machine eight 16-bit general registers seven control registers (two 16-bit registers, five 8-bit registers) high-speed operation: 16 mhz maximum clock rate* at 16 mhz a register-register add operation takes only 125 ns. note: * 10 mhz for the h8/538. maximum address space: 1 mbyte* managed in 64-kbyte pages four pages available simultaneously: code page, stack page, data page, and extended page. note: * the cpu architecture supports up to 16 mbytes, but the chip has only enough pins to address 1 mbyte. two cpu operating modes minimum mode: 64-kbyte address space maximum mode: 1-mbyte address space highly orthogonal instruction set addressing modes and data sizes can be specified independently within each instruction. 31
register and memory addressing modes register-register and register-memory (or memory-register) operations are supported. instruction set optimized for c language in addition to the general registers and orthogonal instruction set, the cpu has special short formats for frequently-used instructions and addressing modes. 3.1.2 address space the h8/500 cpu has different address spaces in its two operating modes, the minimum mode and maximum mode. the cpu operating mode is selected by the input at the mode pins (md 2 to md 0 ) at a reset. table 3-1 summarizes the cpu operating modes. figure 3-1 shows a memory map for the minimum mode. figure 3-2 shows a memory map for the maximum mode. table 3-1 cpu operating modes figure 3-1 memory map in minimum mode operating mode features minimum mode maximum combined size of program area and data area: 64 kbytes maximum mode maximum combined size of program area and data area: 1 mbyte h'0000 h'ffff page 0 (64 kbytes) 64 kbytes 32
figure 3-2 memory map in maximum mode h'00000 h'0ffff h'10000 h'1ffff h'20000 h'f0000 h'fffff 1 mbyte page 0 (64 kbytes) page 1 (64 kbytes) page 15 (64 kbytes) 33
3.1.3 programming model figure 3-3 shows a programming model of the h8/500 cpu. figure 3-3 programming model 0 15 r0 r1 r2 r3 r4 r5 r6 (fp) r7 (sp) 0 15 pc 0 15 t i 2 i 1 i 0 n z v c 87 sr ccr cp dp ep tp br pc: program counter sr: status register ccr: condition code register cp: code page register dp: data page register ep: extended page register tp: stack page register br: base register fp: frame pointer sp: stack pointer 34
3.2 general registers the h8/500 cpu has eight 16-bit general registers. the general registers are described next. 3.2.1 overview all eight of the general registers are functionally alike; there is no distinction between data registers and address registers. when these registers are accessed as data registers, either byte or word size can be selected. when these registers are accessed as address registers, word size is implicitly assumed. 3.2.2 register configuration figure 3-4 shows the general register configuration. figure 3-4 general register configuration 3.2.3 stack pointer r7 functions as the stack pointer (sp), and is used implicitly in exception handling and subroutine calls. it is also used implicitly in pre-decrement or post-increment mode by the ldm and stm instructions, which load and store multiple registers on the stack. 3.2.4 frame pointer r6 functions as a frame pointer (fp). the link and unlk instructions use r6 implicitly to reserve or release a stack frame. 0 15 r0 r1 r2 r3 r4 r5 r6 (fp) r7 (sp) fp: sp: frame pointer stack pointer 35
3.3 control registers the h8/500 cpu has two control registers. the control registers are described next. 3.3.1 overview the control registers include a 16-bit program counter and a 16-bit status register. the program counter and status register are described next. 3.3.2 register configuration figure 3-5 illustrates the program counter and status register. figure 3-5 program counter and status register 3.3.3 program counter the 16-bit program counter (pc) indicates the address of the next instruction the cpu will execute. 0 15 pc 0 15 t i 2 i 1 i 0 n z v c 87 sr ccr pc: program counter sr: status register ccr: condition code register pc bit 1514131211109876543210 36
3.3.4 status register the 16-bit status register (sr) contains status flags that indicate the internal state of the cpu. the lower eight bits of the status register are referred to as the condition code register (ccr). byte access to the ccr is possible. (1) bit 15?race (t): selects trace mode. for information about trace exception handling, see section 4.4, ?race. (2) bits 14 to 11?eserved: read-only bits, always read as 0. (3) bits 10 to 8?nterrupt mask (i 2 , i 1 , i 0 ): these bits indicate the interrupt request mask level (0 to 7) of the program that is currently executing. table 3-2 explains the interrupt request mask levels. sr bit 1514131211109876543210 t i 2 i 1 i 0 n z v c trace bit reserved bits interrupt mask bits reserved bits negative flag zero flag overflow flag carry flag ccr bit 15 t description 0 instructions are executed in succession (initial mode after reset) 1 trace exception handling starts after each instruction (trace mode) 37
table 3-2 interrupt mask levels the cpu accepts only interrupts higher than the interrupt mask level. nmi (level 8) is accepted at any interrupt mask level. after accepting an interrupt, the h8/500 cpu updates i 2 , i 1 , and i 0 to the level of the interrupt. table 3-3 indicates the values of the interrupt mask bits after an interrupt is accepted. a reset sets all three interrupt mask bits to 1. table 3-3 interrupt mask bits (i 2 , i 1 , i 0 ) after an interrupt is accepted interrupt mask i 2 i 1 i 0 level priority acceptable interrupts 1 1 1 7 high nmi 1 1 0 6 level 7 and nmi 1 0 1 5 levels 6 to 7 and nmi 1 0 0 4 levels 5 to 7 and nmi 0 1 1 3 levels 4 to 7 and nmi 0 1 0 2 levels 3 to 7 and nmi 0 0 1 1 levels 2 to 7 and nmi 0 0 0 0 low levels 1 to 7 and nmi interrupt mask level of interrupt accepted i 2 i 1 i 0 nmi (8) 1 1 1 7 111 6 110 5 101 4 100 3 011 2 010 1 001 38
(4) bits 7 to 4?eserved: read-only bits, always read as 0. (5) bit 3?egative (n): the most significant data bit, regarded as a sign bit. (6) bit 2?ero (z): set to 1 to indicate zero data and cleared to 0 at other times. (7) bit 1?verflow (v): set to 1 when an arithmetic overflow occurs and cleared to 0 at other times. (8) bit 0?arry (c): set to 1 when a carry or borrow occurs at the most significant data bit and cleared to 0 at other times. the specific changes that occur in the condition code bits when each instruction is executed are listed in appendix a.1 ?nstruction tables.? see the h8/500 series programming manual for further details. 39
3.4 page registers the h8/500 cpu has four page registers. the page registers are described next. 3.4.1 overview all page registers are eight-bit registers. the four page registers are the code page register (cp), data page register (dp), extended page register (ep), and stack page register (tp). the page registers are not used to calculate effective addresses in minimum mode. in maximum mode, the page registers combine with the program counter and general registers to generate 24- bit effective addresses as shown in figure 3-6, thereby expanding the program area, data area, and stack area. figure 3-6 combinations of page registers with pc and general registers cp dp ep tp pc r0 r1 r2 r3 @aa:16 r4 r5 r6 r7 page register general register 8 bits 16 bits 24 bits (effective address) 40
3.4.2 register configuration figure 3-7 shows the page registers. figure 3-7 page registers 3.4.3 code page register the code page register (cp) combines with the program counter to generate a 24-bit program code address. cp contains the upper eight bits of the address. in maximum mode, cp is initialized at a reset to a value loaded from the vector table, and cp and pc are both saved and restored in exception handling. the ldc instruction can be used to modify the cp contents. cp dp ep tp cp: code page register dp: data page register ep: extended page register tp: stack page register 0 7 bit cp 7 6543210 41
3.4.4 data page register the data page register (dp) combines with general registers r0 to r3 to generate a 24-bit effective address. dp contains the upper eight bits of the address. dp is used to calculate effective addresses in register indirect addressing mode using r0 to r3, and in absolute addressing mode (but not short absolute addressing mode). the ldc instruction can be used to modify the dp contents. 3.4.5 extended page register the extended page register (ep) combines with general register r4 or r5 to generate a 24-bit operand address. ep contains the upper eight bits of the address. ep is used to calculate effective addresses in register indirect addressing mode using r4 or r5. the ldc instruction can be used to modify the ep contents. 3.4.6 stack page register the stack page register (tp) combines with r6 (sp) or r7 (fp) to generate a 24-bit stack address. tp contains the upper eight bits of the address. tp is used to calculate effective addresses in the register indirect addressing mode using r6 or r7, in exception handling, and in subroutine calls. the ldc instruction can be used to modify the tp contents. bit dp 7 6543210 bit ep 7 6543210 bit tp 7 6543210 42
3.5 base register the h8/500 cpu has one 8-bit base register. the base register is described next. 3.5.1 overview the eight-bit base register (br) stores the base address used in short absolute addressing mode (representing the upper eight bits of an address in page 0). figure 3-8 illustrates the base register and short absolute addressing mode. in this addressing mode a 16-bit effective address is generated by using the br contents as the upper eight bits and an address given in the instruction code as the lower eight bits. the short absolute addressing mode always addresses page 0. the ldc instruction can be used to modify the br contents. figure 3-8 short absolute addressing mode and base register 3.5.2 register configuration figure 3-9 shows the base register. figure 3-9 base register br @aa:8 8 bits 8 bits 16 bits (effective address) br 0 7 43
3.6 data formats the h8/500 cpu can process five types of data: one-bit data, four-bit bcd data, eight-bit (byte) data, 16-bit (word) data, and 32-bit (longword) data. bit manipulation instructions operate on one-bit data. decimal arithmetic instructions operate on four-bit bcd data. all instructions except certain arithmetic and data transfer instructions can operate on byte and word data. multiply and divide instructions operate on longword data. the data formats are described next. 3.6.1 data formats in general registers table 3-4 indicates the data formats in general registers. all sizes of data can be stored: one-bit data, four-bit bcd data, eight-bit (byte) data, 16-bit (word) data, and 32-bit (longword) data. in addressing of one-bit data, bit 15 is the most significant bit and bit 0 is the least significant bit. bcd and byte data are stored in the lower eight bits of a general register. all 16 bits of a general register are used to store word data. two general registers are used for longword data: the upper 16 bits are stored in rn (n must be an even number); the lower 16 bits are stored in rn+1. operations performed on bcd data or byte data do not alter the upper eight bits of the register. table 3-4 general register data formats rn rn rn rn+1 15 0 70 don? care upper digit lower digit 70 msb lsb 15 0 0 15 31 16 msb lsb lsb msb rn 15 rn don? care 14131211109876543210 43 data type register no. data structure upper 16 bits lower 16 bits one bit bcd byte word longword * note: * for longword data n must be even (0, 2, 4, or 6). 44
3.6.2 data formats in memory table 3-5 indicates the data formats in memory. instructions that access bit data in memory have byte or word operands. the instruction specifies a bit number to indicate a specific bit in the operand. access to word data in memory must always begin at an even address. access to word data starting at an odd address causes an address error. the upper eight bits of word data are stored in address n (where n is an even number); the lower eight bits are stored in address n + 1. table 3-5 data formats in memory 3.6.3 stack data formats table 3-6 shows the data formats on the stack. when the stack is accessed in exception processing (to save or restore the program counter, code page register, or status register), word access is always performed, regardless of the actual data size. similarly, when the stack is accessed by an instruction using the pre-decrement or post- increment register indirect addressing mode specifying r7 (@?7 or @r7+), which is the stack pointer, word access is performed regardless of the operand size specified in the instruction. programs should be coded so that the stack pointer always indicates an even address. an address error will occur if the stack pointer indicates an odd address. msb lsb msb lsb 76543210 15 14 13 12 11 10 9 8 76543210 data type data format one bit (in byte operand data) one bit (in word operand data) byte word address n even address odd address address n even address odd address upper 8 bits lower 8 bits 45
table 3-6 data formats on the stack 3.7 addressing modes and effective address calculation the h8/500 cpu supports seven addressing modes. these modes and the corresponding effective address calculations are described next. 3.7.1 addressing modes the seven addressing modes supported by the h8/500 cpu are: 1. register direct 2. register indirect 3. register indirect with displacement 4. register indirect with pre-decrement or post-increment 5. immediate 6. absolute 7. pc-relative due to the highly orthogonal nature of the instruction set, most instructions having operands can use any applicable addressing mode from 1 through 6. the pc-relative mode 7 is used by branching instructions. in most instructions, the addressing mode is specified in the effective address (ea) field and effective address extension (if present). table 3-7 indicates how the addressing mode is specified in the effective address field. data type data format byte data on stack word data on stack even address odd address even address odd address undetermined data upper 8 bits lower 8 bits msb msb lsb lsb 46
(1) register direct addressing mode: the contents of a general register rn are used directly as operand data. this addressing mode is specified by giving the general register name. register direct addressing mode (2) register indirect addressing mode: the contents of a general register rn are used as a memory address, and data access is performed at that memory address. this addressing mode is specified by giving the general register name with an address qualifier (@). register indirect addressing mode (3) register indirect addressing mode with displacement: a displacement value is added to the contents of a general register rn, the sum is used as a memory address, and data access is performed at that memory address. this addressing mode is specified by giving the general register name with the address qualifier (@) and an 8-bit or 16-bit displacement value. register indirect addressing mode with displacement (4) register indirect addressing mode with pre-decrement or post-increment: in register indirect addressing mode with pre-decrement, a general register value is first decremented by ? or ?, then the result is used as a memory address and data access is performed at that memory address. in register indirect addressing mode with post-increment, a general register value is used as a memory address and data access is performed at that memory address, then the register value is incremented by 1 or 2. this addressing mode is specified by giving the general register name with the address qualifier (@) and a plus or minus sign (+ or ?. general register name rn general register name @rn address qualifier general register name @(disp:8, rn) 8-bit displacement (with :8) address qualifier @(disp:16, rn) 16-bit displacement (with :16) or 47
register indirect addressing mode with pre-decrement or post-increment (5) immediate addressing mode: eight-bit or 16-bit immediate data given in the instruction are used directly as the operand data. this addressing mode is specified by giving the immediate data with a data qualifier (#). immediate addressing mode (6) absolute addressing mode: data access is performed at a memory address given as a 16-bit absolute address in the instruction, or given as an eight-bit absolute address in the instruction and combined with the base register (br) value. this addressing mode is specified by giving the absolute address with an address qualifier. absolute addressing mode (7) pc-relative addressing mode: an eight-bit or 16-bit displacement value given in the instruction is added to the program counter value, the sum is used as a memory address, and this memory address is moved into the program counter. this addressing mode is specified by giving the displacement value. pc-relative addressing mode @?n minus sign (pre-decrement) address qualifier or general register name @rn+ general register name address qualifier plus sign (post-increment) #xx:8 data qualifier or 8-bit immediate data #xx:16 data qualifier 16-bit immediate data @aa:16 address qualifier or 16-bit absolute address @aa:8 address qualifier 8-bit absolute address (lower 8 bits of address * ) * upper 8 bits are specified by br displacement disp 48
table 3-7 addressing modes r r r sz 0 1 0 1 1 4 5 6 7 3 * 2 * 1 r r r sz 1 0 1 1 r r r sz 0 1 1 1 r r r sz 1 1 1 1 addressing mode no. mnemonic ea field ea extension register direct register indirect 2 rn register indirect with displacement register indirect with pre-decrement register indirect with post-increment immediate absolute (@aa:8 is short absolute) pc-relative @rn @(d:8,rn) @(d:16,rn) @?n @rn+ #xx:8 #xx:16 @aa:8 @aa:16 disp no ea field. addressing mode is specified in op-code. none none displacement (1 byte) displacement (2 bytes) none immediate data (1 byte) immediate data (2 bytes) 1-byte absolute address (offset from br) 2-byte absolute address 1- or 2-byte displacement r r r sz 1 1 0 1 r r r sz 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 sz 0 0 0 0 1 0 1 sz 1 0 0 0 notes: 1. sz specifies the operand size. sz 0 1 operand size byte word 2. rrr specifies a general register. general register r0 r1 r2 r3 r4 r5 r6 r7 rrr 000 001 010 011 100 101 110 111 49
3.7.2 effective address calculation table 3-8 explains how an effective address is calculated in each addressing mode. table 3-8 effective address calculation r r r sz 0 1 0 1 1 2 3 4 + 23 15 0 dp rn 0 15 rn * 2 no. addressing mode mnemonic ea field effective address calculation effective address rn operand is contents of rn. r r r sz 1 0 1 1 @rn or tp or ep r r r sz 0 1 1 1 @(d:8,rn) 0 15 23 15 0 dp result * 2 or tp or ep displacement 16 bits (8 bits with sign-bit extension) + 0 15 rn r r r sz 1 1 1 1 @(d:16,rn) 0 15 23 15 0 dp result * 2 or tp or ep displacement 0 15 rn 23 15 0 dp result * 2 or tp or ep 1 or 2 * 1 23 15 0 dp rn * 2 or tp or ep rn is decremented by ? or ? before instruction execution. r r r sz 1 1 0 1 @?n @rn+ r r r sz 0 0 1 1 rn is incremented by +1 or +2 after instruction execution. register direct register indirect register indirect with displacement register indirect with pre- decrement register indirect with post- increment notes: 1. 2. 1 for a byte operand, 2 for a word operand, and always 2 for r7 in register indirect mode with pre-decrement or post-increment, even if byte size is specified. register indirect r7, r6 r5, r4 r3?0 page register tp ep dp 50
table 3-8 effective address calculation (cont) 1 0 1 sz 0 0 0 0 5 6 7 no. @aa:8 1 0 1 sz 1 0 0 0 @aa:16 + 0 15 pc d:8 0 15 23 15 0 cp result displacement + 0 15 pc 23 15 0 cp result d:16 23 15 0 h'00 ea extension data br 23 15 0 dp ea extension data 0 0 1 0 0 0 0 0 #xx:8 0 0 1 1 0 0 0 0 #xx:16 operand is 1-byte ea extension data. operand is 2-byte ea extension data. no ea field. specified in op-code. no ea field. specified in op-code. 16 bits (8 bits with sign extension) 0 15 displacement addressing mode mnemonic ea field effective address calculation effective address absolute immediate pc-relative 51
3.8 operating modes the h8/500 cpu has two operating modes: minimum mode and maximum mode. the mode is selected by the mode pins (md 2 to md 0 ). the operating modes are described next. 3.8.1 minimum mode minimum mode supports an address space of up to 64 kbytes. the page registers are ignored. instructions that branch across page boundaries (pjmp, pjsr, prts, prtd) are invalid. 3.8.2 maximum mode in maximum mode the page registers are valid, expanding the maximum address space to 1 mbyte. it is possible to move from one page to another with branching instructions (pjmp, pjsr, prts, prtd) and when branching to interrupt-handling routines. when data access crosses a page boundary, the program must rewrite the page register before it can access the data in the next page. for further information on the operating modes, see section 2, ?perating modes. 3.9 basic operational timing in the h8/538, when an external clock signal is fed to the extal pin or a crystal resonator is connected across the xtal and extal pins, the on-chip clock oscillator circuit divides the applied frequency by two to create the system clock (?. in the h8/539, the system clock (? is generated with the same frequency as the frequency at the xtal and extal pins. figure 3-10 shows a block diagram of the clock oscillator. the basic operational timing of the h8/500 cpu is described next. figure 3-10 block diagram of clock oscillator xtal extal cpg ?2 ?4096 prescaler oscillator divider (1/2) * note: * the h8/539 does not have this divider. 52
3.9.1 overview the system clock (? supplied from the clock oscillator is the h8/500 cpus time base. one cycle of the system clock is referred to as a ?tate. the h8/500 cpus bus cycle consists of two or three states. the cpu uses different methods to access on-chip memory, the on-chip register field, and external devices. these access methods are described next. 3.9.2 access to on-chip memory on-chip memory is accessed in two states using a 16-bit bus. figure 3-11 shows the on-chip memory access cycle. figure 3-12 shows the pin states during on-chip memory access. figure 3-11 on-chip memory access cycle bus cycle t 1 state t 2 state address read data write data internal address bus internal read signal internal data bus (read access) internal write signal internal data bus (write access) 53
figure 3-12 pin states during access to on-chip memory 3.9.3 access to two-state-access address space two-state access permits high-speed processing. no wait states can be inserted in access to the two-state-access address space. the external two-state-access address space is accessed via a 16-bit bus. figure 3-13 shows the access cycle for the external two-state-access address space. figure 3-13 access cycle for external two-state-access address space bus cycle t 1 state t 2 state address read data write data a 19 ? 0 as, rd d 15 ? 0 hwr, lwr d 15 ? 0 t 1 state t 2 state address a 19 to a 0 as, rd, hwr, lwr d 15 to d 0 high high impedance 54
3.9.4 access to on-chip supporting modules the on-chip supporting modules are always accessed in three states. the data bus is eight bits wide, except that some of the registers in the 16-bit integrated-timer pulse unit (ipu) are accessed via a 16-bit data bus. figure 3-14 shows the on-chip supporting module access cycle. figure 3-15 indicates the pin states during access to an on-chip supporting module. figure 3-14 access cycle for on-chip supporting modules figure 3-15 pin states during access to on-chip supporting modules bus cycle t 1 state t 2 state t 3 state internal address bus internal read signal internal data bus (read access) internal write signal internal data bus (write access) read data write data address address t 1 state t 2 state t 3 state a 19 ? 0 as, rd, hwr, lwr d 15 ? 0 high high impedance 55
3.9.5 access to three-state-access address space three-state access is used for interfacing to low-speed devices. the wait-state controller (wsc) can insert wait states (t w ) in access to the three-state-access address space. figure 3-16 shows the three-state read access cycle. figure 3-17 shows the three-state write access cycle. figure 3-16 read access cycle for three-state-access address space read cycle t 1 state t 2 state t 3 state address read data high a 19 ? 0 as rd hwr, lwr d 15 ? 0 (read access) 56
figure 3-17 write access cycle for three-state-access address space read cycle t 1 state t 2 state t 3 state address write data high a 19 ? 0 as rd hwr, lwr d 15 ? 0 (write access) 57
3.10 cpu states the h8/500 cpu has five processing states. these states are described next. 3.10.1 overview the five processing states of the h8/500 cpu are the program execution state, exception-handling state, bus-released state, reset state, and power-down state. the power-down state is further divided into a sleep mode, software standby mode, and hardware standby mode. table 3-9 summarizes these states. figure 3-18 shows a map of the state transitions. table 3-9 processing states state description program execution state the h8/500 cpu executes program instructions in sequence. exception-handling state a transient state in which the h8/500 cpu executes a hardware sequence (saving the program counter and status register, fetching a vector, etc.) triggered by a reset, interrupt, or other exception. bus-released state the h8/500 cpu has released the external bus in response to an external bus request signal. reset state the h8/500 cpu and all on-chip supporting modules have been initialized and are stopped. powe sleep mode some or all clock signals are stopped to conserve power. software standby mode hardware standby mode power- down state 58
figure 3-18 state transitions 3.10.2 program execution state in this state the h8/500 cpu executes program instructions in normal sequence. 3.10.3 exception-handling state the exception-handling state is a transient state that occurs when the h8/500 cpu alters the normal program flow due to an interrupt, trap instruction, address error, or other exception. see section 4, ?xception handling?for further information on the exception-handling state. bus-released state exception-handling state reset state * 1 program execution state sleep mode software standby mode hardware standby mode * 2 end of exception handling request for exception handling interrupt request stby = 1 res = 0 breq = 1 breq = 1 breq = 0 breq = 0 from any state except hardware standby mode, a transition to the reset state occurs whenever res goes low. from any state, a transition to hardware standby mode occurs when stby goes low. notes: 1. 2. res = 1 sleep instruc- tion with standby flag set sleep instruc- tion nmi 59
3.10.4 bus-released state when so requested, the h8/500 cpu can grant control of the external bus to an external device. while an external device has the bus right, the h8/500 cpu is said to be in the bus-released state. granting of the bus is controlled by the breq and back signals. bus requests are input at the breq pin. when the bus has been released, an acknowledging signal is output at the back pin. figure 3-19 illustrates the procedure for releasing the bus. figure 3-19 bus release procedure breq input acknowledge place a 19 to a 0 , d 15 to d 0 , as, rd, lwr, and hwr in high- impedance state external device request bus check back get bus bus-released state when the h8/500 cpu receives a low breq signal it drives the back pin low to notify the external device that the bus has been released. after receiving the back signal, the external device that requested the bus becomes the bus master. it can use the address bus (a 19 to a 0 ), data bus (d 15 to d 0 ), and bus control signals (as, rd, lwr, hwr). when the h8/500 cpu releases the bus it places the address bus, data bus, and bus control signals in the high-impedance state. the device that became bus master controls the bus. 1. 2. 3. h8/500 breq = low back = low 60
bus release control register (address h'ff1b): this register (brcr) enables and disables breq input and back output. brcr is initialized to h'fe by a reset and in hardware standby mode. it is not initialized in software standby mode. the brcr bit structure is shown next. bits 7 to 1?eserved: read-only bits, always read as 1. bit 0?us release enable bit (brle): selects the functions of pins pa 6 and pa 5 . bit 0 brle description 0pa 6 and pa 5 are used for general-purpose input and output (initial value) 1pa 6 is used for back output; pa 5 is used for breq input bit initial value r/w 7 1 ? ? 6543210 1111110 ? ? ? ? ? ? ? r/w ??? ? ? brle reserved bits bus release enable bit selects port a functions 61
(1) case in which breq is acknowledged at end of bus cycle figure 3-20 shows the timing when the h8/500 cpu acknowledges the breq signal at the end of a bus cycle. the breq signal is sampled during every instruction fetch cycle and data read or write cycle. if breq is low, the h8/500 cpu releases the bus at the end of the cycle. in word data access by means of two successive byte accesses, first to the upper byte, then to the lower byte (access to the eight-bit-bus-access address space or an on-chip supporting module), the h8/500 cpu does not release the bus right until it has accessed the lower byte. figure 3-20 case of breq acknowledged at end of bus cycle (e.g., read cycle) hi-z high hi-z hi-z hi-z address data read cycle * bus-released state t 1 t 2 t 3 tx tx bus-release acknowledge signal output note: * instruction fetch or data read cycle. in access to word data in the byte-access address space, the cycle shown is the lower byte read cycle. breq (input) back (output) a 19 ? 0 d 15 ? 0 as, rd lwr, hwr breq acknowledged at end of bus cycle 62
(2) case in which breq is acknowledged at end of machine cycle figure 3-21 shows the timing when the h8/500 cpu acknowledges the breq signal at the end of a machine cycle. the h8/500 cpu acknowledges the breq signal at the end of machine cycles during execution of the mulxu or divxu instruction. figure 3-21 case of breq acknowledged at end of machine cycle (during execution of mulxu or divxu instruction) hi-z high hi-z hi-z hi-z n + 1 breq (input) back (output) mulxu or divxu calculation cycles bus-released state tx tx bus-release acknowledge signal output a 19 ? 0 d 15 ? 0 as, rd lwr, hwr breq acknowledged at end of machine cycle n + 2 n hi-z high 63
(3) case in which breq is acknowledged in sleep mode figure 3-22 shows the timing when the h8/500 cpu acknowledges the breq signal in sleep mode. the h8/500 cpu acknowledges the breq signal at any time during sleep mode. figure 3-22 case of breq acknowledged in sleep mode hi-z high hi-z hi-z hi-z breq (input) back (output) sleep mode bus-released state tx tx bus-release acknowledge signal output a 19 ? 0 d 15 ? 0 as, rd lwr, hwr breq acknowledged at any time hi-z high hi-z 64
(4) bus-release operation during two-state access figure 3-23 shows the timing when the bus is requested during a two-state access cycle. when an external device requests the bus during two-state access, the h8/500 cpu enters the bus- released state as follows: ? the breq pin is sampled at the start of the t 1 state. if breq is low, at the end of the bus cycle the h8/500 cpu halts and enters the bus-released state. - in the case of two-state access, at the end of the t 2 state the back signal goes low to indicate that the bus-released state has been entered. the address bus (a 19 to a 0 ), data bus (d 15 to d 0 ), and bus control signals ( as , rd , lwr , hwr ) are placed in the high-impedance state. ? while the bus is released, the h8/500 cpu constantly samples the breq pin (at each tx state) and remains in the bus-released state while breq is low. when breq goes high during a tx state, at the end of the next state the h8/500 cpu drives the back signal high to indicate that it has regained possession of the bus (and that cpu cycles will resume). cpu cycles resume at the end of the next state after back goes high. figure 3-23 bus release during two-state access (e.g., read cycle) 1245 t 2 t 1 t 2 tx tx tx tx t 1 two-state access cpu cycles bus-released cycles cpu cycles address address data high breq (input) back (output) a 19 ? 0 d 15 ? 0 as, rd lwr, hwr 3 65
(5) bus-release operation during three-state access figure 3-24 shows the timing when the bus is requested during a three-state access cycle. when an external device requests the bus during three-state access, the h8/500 cpu enters the bus-released state as follows: ? the breq pin is sampled at the start of the t 1 , t 2 , and t w states. if breq is low, at the end of the bus cycle the h8/500 cpu halts and enters the bus-released state. - in the case of three-state access, at the end of the t 3 state the back signal goes low to indicate that the bus-released state has been entered. the address bus (a 19 to a 0 ), data bus (d 15 to d 0 ), and bus control signals ( as , rd , lwr , hwr ) are placed in the high-impedance state. ? when breq goes high during a tx state, at the end of the next state the h8/500 cpu drives the back signal high to indicate that it has regained possession of the bus (and that cpu cycles will resume). cpu cycles resume at the end of the next state after back goes high. figure 3-24 bus release during three-state access (e.g., read cycle) 123 4 t 1 t 2 t w t 3 tx tx tx t 1 cpu cycles bus-released cycles cpu cycles breq (input) back (output) a 19 ? 0 d 15 ? 0 as, rd lwr, hwr high address data three-state access 66
(6) bus-release operation during internal cpu operations figure 3-25 shows the timing when the bus is requested during internal cpu operations. when an external device requests the bus during internal cpu operations, the h8/500 cpu enters the bus-released state as follows: ? the breq pin is sampled at the start of the t 1 state. if breq is low, at the end of the internal cycle the h8/500 cpu halts and enters the bus-released state. - in the case of internal cpu operations, at the end of a t 1 state the back signal goes low to indicate that the bus-released state has been entered. the address bus (a 19 to a 0 ), data bus (d 15 to d 0 ), and bus control signals ( as , rd , lwr , hwr ) are placed in the high-impedance state. ? when breq goes high during a tx state, at the end of the next state the h8/500 cpu drives the back signal high to indicate that it has regained possession of the bus (and that cpu cycles will resume). cpu cycles resume at the end of the next state after back goes high. figure 3-25 bus release during internal cpu operation 123 4 t 1 t 1 t 1 tx tx tx t 1 cpu cycles bus-released cycles cpu cycles breq (input) back (output) a 19 ? 0 d 15 ? 0 as, rd lwr, hwr address internal cpu operation high high hi-z hi-z t 1 67
(7) notes the h8/500 cpu does not accept interrupts while in the bus-released state. the breq signal must be held low until back goes low. if breq returns to the high level before back goes low, the bus release operation may be executed incorrectly. 3.10.5 reset state in the reset state, the h8/500 cpu and all on-chip supporting modules are initialized and placed in the stopped state. the h8/500 cpu enters the reset state whenever the res pin goes low, unless the h8/500 cpu is currently in the hardware standby mode. see section 4.2, ?eset?for further information on the reset state. 3.10.6 power-down state the power-down state comprises three power-down modes: sleep mode, software standby mode, and hardware standby mode. see section 19, ?ower-down state?for further information. 68
section 4 exception handling 4.1 overview there are five types of exceptions: reset, address error, trace, interrupt, and instruction exceptions. there are three types of instruction exceptions: invalid instruction, trap instruction, and divxu instruction with zero divisor. handling of these exceptions is described next. 4.1.1 exception handling types and priority table 4-1 lists the types of exception handling for exceptions other than instruction exceptions, and indicates their priority. the system assigns a reserved priority to each of these exception types. if two or more exceptions occur simultaneously, they are accepted and handled in priority order. table 4-2 lists the types of instruction exception handling. instruction exceptions cannot occur simultaneously, so there is no priority order. table 4-1 exception types and priority table 4-2 instruction exceptions priority exception type source start of exception handling high reset res input rising edge of res signal address error invalid access (address error) end of instruction execution trace trace bit (t) = 1 in sr end of instruction execution interrupt external or internal interrupt end of instruction execution or end low request of exception handling exception type source start of exception handling invalid instruction fetching of invalid instruction start of execution of instruction with undefined code trap instruction trap instruction start of execution of trap instruction zero divide divxu instruction start of execution of divxu instruction with zero divisor 69
4.1.2 exception handling operation exception handling can originate from a variety of sources. exception handling other than reset exception handling is described next. for reset exception handling, see section 4.2, ?eset. figure 4-1 is a flowchart of the handling of exceptions other than a reset. in minimum mode, the program counter (pc) and status register (sr) are saved on the stack. in maximum mode the code page register (cp), pc, and sr are saved on the stack. next the t bit in the status register is cleared to 0, the start address corresponding to the exception source is read from the exception vector table, and program execution begins from the indicated address. figure 4-1 exception handling flowchart exception exception handling pc ? @ e sp cp ? @ e sp sr ? @ e sp 0 ? t bit (sr) start address ? cp start address ? pc state saving: pc, cp, and sr are pushed in that order on the stack. cp is pushed only in maximum mode. preparations for program execution: after the trace bit is cleared to 0, an address is loaded from the vector table into cp and pc. cp is loaded only in maximum mode. start of program execution 70
4.1.3 exception sources and vector table figure 4-2 classifies the exception sources. table 4-3 shows the exception vector table. the vector addresses differ between minimum and maximum modes. in maximum mode the vector table is located in page 0. for internal interrupt vectors, see table 6-3 and table 6-4, ?nterrupt priorities and vector addresses. figure 4-2 classification of exception sources ? reset ? address error ? trace ? instructions invalid instruction trapa instruction trap/vs instruction zero divide ? interrupts external interrupts internal interrupts nmi irq0 irq1? 39 interrupt sources in on-chip supporting modules exception sources 71
table 4-3 exception vector table vector address exception source minimum mode maximum mode reset (initial pc value) h'0000?'0001 h'0000?'0003 (reserved for system) h'0002?'0003 h'0004?'0007 invalid instruction h'0004?'0005 h'0008?'000b divxu instruction (zero divisor) h'0006?'0007 h'000c?'000f trap/vs instruction h'0008?'0009 h'0010?'0013 (reserved for system) h'000a?'000b h'0014?'0017 h'000e?'000f h'001c?'001f address error h'0010?'0011 h'0020?'0023 trace h'0012?'0013 h'0024?'0027 (reserved for system) h'0014?'0015 h'0028?'002b external interrupt: nmi h'0016?'0017 h'002c?'002f (reserved for system) h'0018?'0019 h'0030?'0033 h'001e?'001f h'003c?'003f trapa instruction (16 sources) h'0020?'0021 h'0040?'0043 h'003e?'003f h'007c?'007f external interrupt: irq0 h'0040?'0041 h'0080?'0083 wdt interval interrupt h'0042?'0043 h'0084?'0087 external interrupts: irq1 h'0048?'0049 h'0090?'0093 irq2 h'004a?'004b h'0094?'0097 irq3 h'004c?'004d h'0098?'009b internal interrupts h'0044?'0045 h'0088?'008b h'0050?'0051 h'00a0?'00a3 h'009e?'009f h'013c?'013f 72
4.2 reset 4.2.1 overview a reset has the highest exception priority. reset exception handling is described below. when the res pin goes low, all processing halts and the chip enters the reset state. a reset initializes the internal state of the h8/500 cpu and the registers of on-chip supporting modules. when the res pin rises from low to high, the h8/500 cpu begins reset exception handling. 4.2.2 reset sequence the chip enters the reset state when the res pin goes low. to ensure that the chip is reset, the res pin should be held low for at least 20 ms at power-up. to reset the chip during operation, the res pin should be held low for at least six system clock cycles (6?. see appendix e, ?in states?for the states of the pins in the reset state. when the res pin rises to the high level after being held low for the necessary time, the h8/500 cpu begins reset exception handling. figure 4-3 shows the sequence of operations at the end of the reset state. figure 4-3 reset exception handling flowchart a start address is loaded from vector table. h8/500 cpu starts program execution from that address. res pin end of reset (low-to-high transition) values of mode pins (md 2 to md 0 ) are latched in bits mds2 to mds0 in mdcr. program execution begins t bit in sr is cleared to 0 to disable trace mode. interrupt mask bits i 2 to i 0 are all set to 1 (level 7). reset exception handling 0 ? t bit (sr) 1 ? i 2 to i 0 bits (sr) start address ? cp start address ? pc ? mds2e0 md 2e0 73
the vector table contents differs between minimum and maximum mode. the vector table contents in each mode are described next. (1) minimum mode: figure 4-4 shows the reset vector in minimum mode. in minimum mode the reset vector is located at addresses h'0000 and h'0001. when exception handling begins, the h8/500 cpu copies the reset vector into the program counter (pc). program execution then starts from the pc address. figure 4-4 reset vector in minimum mode figure 4-5 shows the reset sequence in minimum mode. figure 4-5 shows the case in which the program area and stack area are both located in the eight- bit-bus three-state-access address space. figure 4-5 reset sequence in minimum mode pc h pc l h'0000 h'0001 (1) instruction prefetch address (2) instruction code res a 19 ? 0 d 15 ? 0 rd vector address vector (3) (4) (1) (2) reset interval (at least 6 states) internal pro- cessing cycles fetching reset vector prefetching first instruc- tion of program instruction execution starts (3) program start address (4) first instruction of program 74
(2) maximum mode: figure 4-6 shows the reset vector in maximum mode. in maximum mode the reset vector is located at addresses h'0000 to h'0003. when exception handling begins, the h8/500 cpu copies the reset vector into the code page register (cp) and program counter (pc), ignoring the vector data at h'0000. program execution then starts from the cp and pc address. figure 4-6 reset vector in maximum mode figure 4-7 shows the reset sequence in maximum mode. figure 4-7 shows the case in which the program area and stack area are both located in the 16-bit- bus two-state-access address space. figure 4-7 reset sequence in maximum mode pc h pc l h'0000 h'0001 cp don? care h'0002 h'0003 (1) instruction prefetch address (2) instruction code res internal address bus internal data bus internal read signal (1) (2) v v + 2 (3) (4) pc v: vector address reset vector reset interval (at least 6 states) internal processing cycles fetching reset vector prefetching first instruction of program instruction execution starts (3) program start address (4) first instruction of program cp 75
4.2.3 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the program counter and status register will not be saved correctly, leading to a program crash. this danger can be avoided as explained next. when the chip comes out of the reset state all interrupts, including nmi, are disabled, so the first instruction is always executed. crashes can be avoided by using this first instruction to initialize sp. in minimum mode, the first instruction after a reset should initialize sp. in maximum mode, the first instruction after a reset should initialize the stack page register (tp), and the next instruction should initialize sp. examples: 1. minimum mode .org h'0000 mov.w #h'fe80, sp 2. maximum mode .org h'0000 ldc.b #h'00, tp mov.w #h'fe80, sp 4.3 address error an address error occurs when invalid access is attempted. there are three types of address errors: 1. address error in instruction prefetch 2. address error in word data access 3. address error in single-chip mode when an address error occurs, the h8/500 cpu begins address error exception handling and clears the t bit of the status register to 0. the interrupt mask level in bits i 2 to i 0 is not changed. each type of address error is described next. 76
4.3.1 address error in instruction prefetch an attempt to prefetch an instruction from the on-chip registers at addresses h'fe80 to h'ffff causes an address error. the address error exception handling sequence for this case is: instruction prefetch from on-chip register area (h'fe80 to h'ffff) wait for execution of current instruction to end address error exception handling the pc value pushed on the stack is the address of the instruction immediately following the last instruction executed. program code should not be located in addresses h'fe7d to h'fe7e. if program code is located in these addresses, instruction prefetch will be attempted in the on-chip register area, causing an address error. figure 4-8 shows the areas in which instruction prefetch leads to an address error. figure 4-8 areas in which instruction prefetch leads to address error 4.3.2 address error in word data access an address error occurs if an attempt is made to access word data starting at an odd address. the pc value pushed on the stack is the address of the next instruction after the instruction that attempted to access word data at an odd address. h'0000 h'fe7d h'fe80 h'ffff areas in which instruction prefetch leads to address error (3 bytes) on-chip register area 77
figure 4-9 shows an example of illegal location of word data. figure 4-9 example of illegal location of word data 4.3.3 address error in single-chip mode in single-chip mode there is no external memory, so in addition to the word access address errors described in section 4.3.2, address errors can occur due to access to missing areas in the address space. (1) h8/538 access to addresses h'ee80 to h'f67f: in single-chip mode these addresses form a missing address area; they are assigned neither to on-chip memory nor to on-chip registers. instruction prefetch, byte data access, or word data access in the missing address area causes an address error. an address error also occurs if an instruction is located in the last three bytes of on- chip rom, because the h8/500 cpu will attempt to prefetch the next instruction from addresses h'ee80 to h'ee82 in the missing address area. figure 4-10 areas in which instruction prefetch leads to address error (single-chip mode) h'0000 h'fe80 on-chip register area h'fe7d h'f67f (3 bytes) areas in which instruction prefetch leads to address error missing address area (data access also causes an address error) h'ee7d h'ee80 rom area (3 bytes) on-chip ram area h'ffff 2m 2m+1 2m+2 upper data lower data (example) word data located at odd address (error) mov.w @2m+1, r0 causes an address error. 78
access to disabled ram area: when the on-chip ram area is disabled in single-chip mode, the missing address area extends from h'ee80 to h'fe7f. instruction prefetch, byte data access, or word data access in this missing address area causes an address error. an address error also occurs if an instruction is located in the last three bytes of on-chip rom, because the h8/500 cpu will attempt to prefetch the next instruction from addresses h'ee80 to h'ee82 in the missing address area. figure 4-11 areas in which instruction prefetch leads to address error (single-chip mode with on-chip ram disabled) (2) h8/539 access to addresses h'04000 to h'0ee7f and h'30000 to h'fffff: in single-chip mode these addresses form a missing address area; they are assigned neither to on-chip memory nor to on-chip registers. instruction prefetch, byte data access, or word data access in the missing address area causes an address error. an address error also occurs if an instruction is located in the last three bytes of on- chip rom in page 0, because the h8/500 cpu will attempt to prefetch the next instruction from addresses h'04000 to h'04002 in the missing address area. the same type of error will occur if an instruction is located in the last three bytes of on-chip rom in page 1 or page 2. h'0000 h'fe80 on-chip register area areas in which instruction prefetch leads to address error missing address area (data access also causes an address error) h'ee7d h'ee80 rom area (3 bytes) h'f680 h'ffff on-chip ram area (on-chip ram disabled) h'fe7d 79
figure 4-12 areas in which instruction prefetch leads to address error (single-chip mode) access to disabled ram area: when the on-chip ram area is disabled in single-chip mode, addresses h'04000 to h'0fe7f are also a missing area. instruction prefetch, byte data access, or word data access in this missing address area causes an address error. an address error also occurs if an instruction is located in the last three bytes of on-chip rom in page 0, because the h8/500 cpu will attempt to prefetch the next instruction from addresses h'04000 to h'04002 in the missing address area. the same type of error will occur if an instruction is located in the last three bytes of on-chip rom in page 1 or page 2. figure 4-13 areas in which instruction prefetch leads to address error (single-chip mode with on-chip ram disabled) h'00000 h'0fe80 on-chip register area areas in which instruction prefetch leads to address error missing address area (data access also causes an address error) h'03ffd h'04000 rom area (3 bytes) h'0ee80 h'0ffff on-chip ram area (on-chip ram disabled) page 0 h'00000 h'0fe80 on-chip register area h'0fe7d h'0ee7f h'0ee80 (3 bytes) areas in which instruction prefetch leads to address error missing address area (data access also causes an address error) h'03ffd h'04000 rom area (3 bytes) on-chip ram area h'0ffff page 0 80
4.4 trace trace mode can be used by a debug program, for example, to monitor the execution of a program under test. (1) trace mode: when the trace bit (t bit) in the status register (sr) is set to 1, the h8/500 cpu operates in trace mode. a trace exception occurs at the completion of each instruction. in trace exception handling the t bit in sr is cleared to 0 to disable trace mode. the interrupt mask level in bits i 2 to i 0 is not changed, however; interrupts are accepted during trace exception handling. the trace exception-handling routine should end with an rte instruction. when the trace routine returns with the rte instruction, the status register is popped from the stack and trace mode resumes. (2) contention with address error exception handling: address error exception handling occurs at the end of a bus cycle, so it does not normally conflict with trace exception handling. one instruction is always executed after exception handling, however, so contention may occur at this point, requiring special consideration. if address error and trace exceptions both occur at the end of an instruction, because of the priority relationship between these exceptions, address error exception handling is carried out. trace mode is disabled during execution of the instruction that caused the address error and during the address error exception handling routine. after return from address error exception handling, one instruction is executed, then trace mode resumes. 4.5 interrupts there are five external sources of interrupt exception handling (nmi, irq 0 , irq 1 , irq 2 , irq 3 ) and 39 sources in the on-chip supporting modules. table 4-4 classifies the interrupt sources. the on-chip supporting modules that can request interrupts are the 16-bit integrated timer pulse unit (ipu), serial communication interfaces 1 and 2 (sci1 and sci2), a/d converter, and watchdog timer (wdt). nmi is the highest-priority interrupt and is always accepted. the other 43 interrupt sources are controlled by the interrupt controller. the interrupt controller arbitrates between simultaneous interrupts by means of internal registers in which interrupt priorities are assigned to each module. the interrupt priorities are set in interrupt priority registers a to f (ipra to iprf) in the interrupt controller. an interrupt priority level from 7 to 0 can be assigned to irq 0 . a single priority level from 7 to 0 can be assigned collectively to irq 1 , irq 2 , and irq 3 . independent priority levels from 7 to 0 can also be assigned to each of the on-chip supporting modules. 81
the interrupt controller also controls the starting of the data transfer controller (dtc) in response to an interrupt. the dtc can transfer data in either direction between memory and i/o without using the cpu. whether to start the dtc can be selected on an individual interrupt basis in data transfer enable registers a to f (dtea to dtef) in the interrupt controller. the dtc is started if the corresponding bit in dtea to dtef is set to 1. if this bit is cleared to 0, interrupt exception handling is carried out. a few interrupts, including nmi, cannot start the dtc. the cpu halts during dtc operation. for details of dtc interrupts, see section 7, ?ata transfer controller. interrupt controller functions are detailed in section 6, ?nterrupt controller. table 4-4 interrupt sources interrupt category number of sources external interrupts nmi 1 irq0 1 irq1?rq3 3 internal interrupts ipu 29 sci1 4 sci2/sci3 * 1 4 a/d converter 1 wdt 1 note: 1. h8/539 only 4.6 invalid instructions an invalid instruction is an instruction with an undefined operation code or illegal addressing mode. if an attempt is made to execute an invalid instruction, the h8/500 cpu starts invalid instruction exception handling. the pc value pushed on the stack is the value of the program counter when the invalid instruction code was detected. in the invalid instruction exception-handling sequence the t bit of the status register is cleared to 0, but the interrupt mask level (i 2 to i 0 ) is not changed. 82
4.7 trap instructions and zero divide when the trapa or trap/vs instruction is executed, the h8/500 cpu starts trap exception handling. if an attempt is made to execute a divxu instruction with a zero divisor, the h8/500 cpu starts zero divide exception handling. in the exception-handling sequences for these exceptions the t bit of the status register is cleared to 0, but the interrupt mask level (i 2 to i 0 ) is not changed. if a normal interrupt is requested during execution of a trap or zero-divide instruction, interrupt handling begins after the exception-handling sequence for the trap or zero-divide instruction has been executed. (1) trapa instruction: when the trapa instruction is executed, the h8/500 cpu starts exception handling according to the cpu operating mode. the trapa instruction includes a vector number from 0 to 15. the start address is read from the corresponding location in the vector table. (2) trap/vs instruction: when the trap/vs instruction is executed, the h8/500 cpu starts exception handling if the overflow (v) flag in the condition code register (ccr) is set to 1. if the v flag is cleared to 0, no exception occurs and the next instruction is executed. (3) divxu instruction with zero divisor: the h8/500 cpu starts exception handling if an attempt is made to divide by zero in a divxu instruction. 83
4.8 cases in which exception handling is deferred exception handling of address errors, trace exceptions, external interrupt requests (nmi, irq 0 , irq 1 , irq 2 , irq 3 ), and internal interrupt requests (39 sources) is not carried out immediately after execution of an interrupt-disabling instruction, reset exception, or data transfer cycle, but is deferred until after the next instruction has been executed. 4.8.1 instructions that disable exception handling interrupts are disabled immediately after the execution of five instructions: xorc, orc, andc, ldc, and rte. after executing one of these instructions, the h8/500 cpu always executes the next instruction. if the next instruction is also one of these five, the next instruction after that is executed too. exception handling starts after the next instruction that is not one of these five has been executed. see the following example. example: ldc.b mov.w mov.b program flow interrupt controller notifies h8/500 cpu of interrupt request h8/500 cpu executes next instruction before starting exception handling to exception-handling sequence #h'00,tp #h'fe80,sp #h'00,@wcr 84
4.8.2 disabling of exceptions immediately after a reset after carrying out reset exception handling, the h8/500 cpu always executes the initial instruction. if an interrupt is accepted after a reset but before sp is initialized, the program counter and status register will not be saved correctly, leading to a program crash. to prevent this, in minimum mode the first instruction after a reset should initialize sp. in maximum mode, the first instruction after a reset should be an ldc instruction initializing tp, and the next instruction should initialize sp. 4.8.3 disabling of interrupts after a data transfer cycle if an interrupt starts the data transfer controller and a second interrupt is requested during the data transfer cycle, when the data transfer cycle ends, the h8/500 cpu always executes the next instruction before handling the second interrupt. even if a nonmaskable interrupt (nmi) occurs during a data transfer cycle, it is not accepted until the next instruction has been executed. an example is shown next. example: add.w mov.w mov.w program flow dtc interrupt request to nmi exception handling data transfer cycle nmi request after data transfer cycle, h8/cpu executes next instruction before starting exception handling r2,r0 r0,@h'ef00 @h'ef02,r0 85
4.9 stack status after completion of exception handling the status of the stack after exception handling is described next. table 4-5 shows the stack after completion of exception handling for various types of exceptions in minimum and maximum modes. table 4-5 stack after exception handling sp tp:sp note: the cp and pc values pushed on the stack are the address of the next instruction after exception source trace, interrupt, trap instruction, divxu (zero divide) invalid instruction address error next instruction address (lower 8 bits) sr (upper 8 bits) sr (lower 8 bits) next instruction address (upper 8 bits) next instruction address (lower 8 bits) sr (upper 8 bits) sr (lower 8 bits) next instruction page address (8 bits) next instruction address (upper 8 bits) don? care note: the rte instruction returns to the next instruction after the instruction being executed when the exception occurred. sr (upper 8 bits) sr (lower 8 bits) pc (lower 8 bits) when error occurred sr (upper 8 bits) sr (lower 8 bits) cp (8 bits) when error occurred pc (upper 8 bits) when error occurred don? care note: the cp and pc values pushed on the stack are not necessarily the address of the first byte pc (lower 8 bits) when error occurred sr (upper 8 bits) sr (lower 8 bits) pc (upper 8 bits) when error occurred pc (lower 8 bits) when error occurred sr (upper 8 bits) sr (lower 8 bits) don? care cp (8 bits) when error occurred pc (upper 8 bits) when error occurred minimum mode maximum mode of the invalid instruction. the last instruction successfully executed. sp tp:sp sp tp:sp pc (lower 8 bits) when error occurred pc (upper 8 bits) when error occurred 86
4.9.1 pc value pushed on stack for trace, interrupts, trap instructions, and zero divide exceptions the pc value pushed on the stack for a trace, interrupt, trap, or zero divide exception is the address of the next instruction at the time when the interrupt was accepted. 4.9.2 pc value pushed on stack for address error and invalid instruction the pc value pushed on the stack for an address error or invalid instruction exception differs depending on the conditions when the exception occurs. 4.10 notes on use of the stack when using the stack, pay attention to the following points. mistakes may lead to address errors when the stack is accessed, or may cause system crashes. 1. always set sp on an even address. if sp indicates an odd address, an address error will occur when the h8/500 cpu accesses the stack during interrupt handling or for a subroutine call. to keep sp pointing to an even address, always use word data size when saving or restoring register data or other data to or from the stack. 2. @?p and @sp+ addressing modes to keep sp pointing to an even address, in the @?p and @sp+ addressing modes the h8/500 cpu performs word access even if the instruction specifies byte size. this is not true in the @?n (pre-decrement) and @rn+ (post-increment) addressing modes when rn is a register from r0 to r6. 87
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section 5 h8 multiplier (h8/539 only) 5.1 overview the on-chip multiplier module (h8mult) can perform 16-bit 16-bit signed or unsigned multiply and multiply-accumulate operations. these operations can be speeded up by a bus- stealing function. the h8/538 does not have an on-chip multiplier module. 5.1.1 features features of the h8mult module are listed below. 16-bit 16-bit multiplication executed in two clock cycles signed or unsigned multiplication can be selected. up to three multiplier values can be designated in advance. multiply-and-accumulate operations can be executed in three clock cycles saturating or non-saturating operation can be selected. the results of non-saturating multiply- accumulate operations are stored in 42-bit form. the results of saturating multiply-accumulate operation are stored in 32-bit form. up to three multiplier values can be designated in the h8 mult registers in advance, an arrangement ideally suited for second-order digital filtering. built-in bus-stealing function for higher-speed operation, the bus-stealing function enables multipliers and multiplicands to be loaded into h8mult while the cpu is reading memory. 89
5.1.2 block diagram figure 5-1 shows a block diagram of the h8mult module. figure 5-1 h8mult block diagram internal address bus (a 15 to a 0 ) internal data bus (d 15 to d 0 ) mltbr module data bus mltar mltmar mltcr s-on mac, mul, clr mca mcb mcc mr mmr multiplier matrix macxh mach macl legend mltcr: mltar: mltmar: mltbr: mca: mcb: mcc: macxh: mach: macl: mr: mmr: mult control register mult multiplier address register mult multiplicand address register mult base address register mult multiplier register a mult multiplier register b mult multiplier register c mult result register, extended high word mult result register, high word mult result register, low word mult immediate multiplier register mult immediate multiplicand register 90
5.1.3 register configuration table 5-1 summarizes the internal registers of the h8mult module. the type of operation (multiply or multiply-accumulate, signed or unsigned) and the bus-stealing function can be selected by register settings. table 5-1 h8mult registers type address name abbreviation r/w initial value control h'ffa0 mult control register mltcr r/w h'38 registers h'ffa1 mult base address register mltbr r/w h'00 h'ffa2 mult multiplier address mltar r/w h'00 register h'ffa3 mult multiplicand address mltmar r/w h'00 register arithmetic h'ffb0 mult multiplier register a mca r/w h'0000 registers * 1 h'ffb2 mult multiplier register b mcb r/w h'0000 h'ffb4 mult multiplier register c mcc r/w h'0000 h'ffb6 mult result register, extended macxh r/w undetermined high word h'ffb8 mult result register, high word mach r/w * 2 undetermined h'ffba mult result register, low word macl r/w * 2 undetermined h'ffbc mult immediate multiplier mr w undetermined register h'ffbe mult immediate multiplicand mmr w undetermined register notes: 1. the arithmetic registers require word-size access. byte-size access is not supported. if byte-size access is attempted, subsequent results may be incorrect. 2. mult result registers mach and macl cannot be modified independently. write access to mach must be immediately followed by write access to macl, so that the modification takes place 32 bits at a time. example: mdv.w #aa:16, @mach } these instructions must be executed mdv.w #aa:16, @macl consecutively. 91
5.2 register descriptions this section describes the h8mult registers. 5.2.1 mult control register the mult control register (mltcr) is an eight-bit readable/writable register that clears the mult result registers, selects the type of multiplication operation, and selects the bus-stealing function. the bit structure of mltcr is shown next. bit initial value r/w 7 0 clr s_on 543210 0111000 r/w r/w r/w r/w r/w 6 sign mul mac clear bit multiply-accumulate bit multiply bit sign bit reserved bits bus-steal on bit enables or disables the bus-stealing function simplifies the procedure for initializing mult result registers macxh, mach, and macl selects signed arithmetic enables or disables the multiply function enables or disables the multiply-accumulate function rrr 92
(1) bit 7?lear (clr): the purpose of this bit is to simplify the procedure for initializing mult result registers macxh, mach, and macl. if the clr bit is set to 1, when a write access is made to one of these three registers (macxh, mach, or macl), regardless of the value of the write data, the other two registers are initialized to h'0000. (2) bit 6?us-steal on (s_on): enables or disables the bus-stealing function. if the s_on bit is set to 1, data can be set in the mult registers at the same time as the cpu accesses memory. if the s_on bit is cleared to 0, this bus-stealing function is disabled. for further information, see section 5.3 ?peration. (3) bits 5 to 3?eserved: read-only bits, always read as 1. (4) bit 2?ign (sign): specifies signed arithmetic. the multiplication is performed in signed mode if the sign bit is set to 1, and in unsigned mode if the sign bit is cleared to 0. when a multiply-accumulate operation is executed, the operation is performed in non-saturating mode or saturating mode. the results of saturating multiply-accumulate operations are stored in 32-bit form of mach and macl registers. in this case, macxh register is not used. when an overflow occurs, set bit 0 in the macxh register to 1. the results of non-saturating multiply-accumulate operations are stored in 42-bit form of macxh, mach, and macl registers. in this case, an overflow is not detected. for further details, see section 5.3.4 ?ultiply and multiply-accumulate function. (5) bit 1?ultiply (mul): enables or disables the multiply function. the multiply function is enabled when the mul bit is set to 1. do not set both the mul bit and mac bit (bit 0) to 1 at the same time. if both bits are set to 1, neither function is enabled. (6) bit 0?ultiply-accumulate (mac): enables or disables the multiply-accumulate function. the multiply-accumulate function is enabled when the mac bit is set to 1. do not set both the mac bit and mul bit (bit 1) to 1 at the same time. if both bits are set to 1, neither function is enabled. 93
5.2.2 mult base address register the mult base address register (mltbr) is a readable/writable register that specifies the upper eight bits of the memory address of the multiplier or multiplicand in multiply or multiply- accumulate operations when the bus-stealing function is enabled. 5.2.3 mult multiplier address register the mult multiplier address register (mltar) is a readable/writable register that specifies the lower eight bits of the memory address of the multiplier in multiply or multiply-accumulate operations when the bus-stealing function is enabled. 5.2.4 mult multiplicand address register the mult multiplicand address register (mltmar) is a readable/writable register that specifies the lower eight bits of the memory address of the multiplicand in multiply or multiply-accumulate operations when the bus-stealing function is enabled. bit initial value r/w 7 0 543210 0000000 r/w r/w r/w r/w r/w 6 r/w r/w r/w bit initial value r/w 7 0 543210 0000000 r/w r/w r/w r/w r/w 6 r/w r/w r/w bit initial value r/w 7 0 543210 0000000 r/w r/w r/w r/w r/w 6 r/w r/w r/w 94
5.2.5 mult multiplier register a mult multiplier register a (mca) is a readable/writable register that stores a multiplier for use in multiply or multiply-accumulate operations. note: mca requires word-size access. 5.2.6 mult multiplier register b mult multiplier register b (mcb) is a readable/writable register that stores a multiplier for use in multiply or multiply-accumulate operations. note: mcb requires word-size access. 5.2.7 mult multiplier register c mult multiplier register c (mcc) is a readable/writable register that stores a multiplier for use in multiply or multiply-accumulate operations. note: mcc requires word-size access. bit initial value r/w 15 10 8 4 2 0 0 r/w 11 14 13 12 9 7 6 5 3 1 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w bit initial value r/w 15 10 8 4 2 0 0 r/w 11 14 13 12 9 7 6 5 3 1 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w bit initial value r/w 15 10 8 4 2 0 0 r/w 11 14 13 12 9 7 6 5 3 1 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 95
5.2.8 mult immediate multiplier register the mult immediate multiplier register (mr) is a 16-bit write-only register into which a multiplier value can be loaded for use in multiply or multiply-accumulate operations. mr is a write-only register. when read, it always returns h'ffff. note: mr requires word-size access. 5.2.9 mult immediate multiplicand register the mult immediate multiplicand register (mmr) is a 16-bit write-only register into which a multiplicand value can be loaded for use in multiply or multiply-accumulate operations. mmr is a write-only register. when read, it always returns h'ffff. note: mmr requires word-size access. bit initial value r/w 15 10 8 4 2 0 w 11 14 13 12 9 7 6 5 3 1 w w w w w w w w w w w w w w w bit initial value r/w 15 10 8 4 2 0 w 11 14 13 12 9 7 6 5 3 1 w w w w w w w w w w w w w w w 96
5.2.10 mult result register, extended high word the mult result register, extended high word (macxh) is a 16-bit readable/writable register that stores the upper 10 bits of the 42-bit result of a non-saturating multiply-accumulate operation. the sign extended value of bit 9 is set to bits 15 to 10. macxh is not used in a multiply operation. bits 15 to 1 are not used in a saturating multiply-accumulate operations. bit 0 of the macxh register is an overflow flag (ovf) that is set to 1 when the result of a saturating multiply-accumulate operation overflows. note: macxh requires word-size access. 5.2.11 mult result register, high word the mult result register, high word (mach) is a 16-bit readable/writable register that stores bits 31 to 16 of the 32-bit result of a multiply or saturating multiply-accumulate operation, and 31 to 16 of the 42-bit result of a non saturating multiply-accumulate operation. note: mach requires word-size access. 5.2.12 mult result register, low word the mult result register, low word (macl) is a 16-bit readable/writable register that stores bits 15 to 0 of the 32-bit result of a multiply or saturating multiply-accumulate operation, and 15 to 0 of the 42-bit result of a non saturating multiply-accumulate operation. note: macl requires word-size access. bit initial value r/w 15 10 8 4 2 0 r/w 11 14 13 12 9 7 6 5 3 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit initial value r/w 15 10 8 4 2 0 r/w 11 14 13 12 9 7 6 5 3 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit initial value r/w 15 10 8 4 2 0 r/w 11 14 13 12 9 7 6 5 3 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 97
5.3 operation the operation of the h8/539s on-chip multiplier module will be described in the following order: initialization of mult result registers; register read/write; bus-stealing function; then multiply and multiply-accumulate operations. 5.3.1 initialization of mult result registers mult result registers macxh, mach, and macl are not initialized by a reset. in a multiply- accumulate operation, in which the multiplication result is added to the value in the mult result registers, the mult result registers must be initialized before use, either by clearing them or by writing the necessary values in them ahead of time. initialization is not necessary when these registers are only used for multiplication. initialization should be performed by one of the following methods. (1) individual register initialization: the registers can be initialized by writing to them individually. the mach and macl registers must be written to consecutively. example: mov.w #h'0000, @macxh mov.w #h'0000, @mach ; do not change the order mov.w #h'0000, @macl ; of these two instructions or clr.w @macxh clr.w @mach ; do not change the order clr.w @macl ; of these two instructions (2) one-step initialization: all three registers can be initialized at once. macxh, mach, and macl are all initialized to h'0000, regardless of the write data. example: bset.b #7, @mltcr ; set clr bit in mltcr mov.w #aa:16, @macxh ; destination can be @mach or @macl instead (bclr.b #7, @mltcr) the one-step initialization function operates at a write access to macxh, mach, or macl. it does not operate at a read access, or a write access to any other register, so the clr bit does not necessarily have to be cleared to 0 after one-step initialization. 98
5.3.2 writing to mult multiplier registers the mult multiplier registers (mca, mcb, mcc) can be loaded by writing to them directly, or by bus stealing. the bus-stealing function and direct writing are performed independently for mca, mcb, and mcc, so both types of loading can be used together. (1) direct writing: this method writes to mca, mcb, or mcc by direct addressing. specify the address of mca, mcb, or mcc as the destination operand in a write instruction. be sure to use a word-size instruction. example: mov.w #aa:16, @mca ; write 16-bit data in mca (2) loading data by bus stealing: when the cpu accesses its memory address space, the data on the data bus can loaded automatically into a mult multiplier register (bus stealing). bus stealing is performed only for particular addresses, which are specified in the mult multiplier address register (mltar) and mult base address register (mltbr). for further information, see section 5.3.3 ?us-stealing function. example: bset.b #6, @mltcr ; mov.b #h'fe, @mltbr ; set up bus-stealing function mov.b #h'80, @mltar ; mov.w #aa:16, @fe80 ; write data #aa:16 to @fe80 and load same data into mca mov.w @fe80, r0 ; read data from @fe80 and load same data into mca ; tst.w @fe80 instruction would do the same 5.3.3 bus-stealing function the bus-stealing function loads the value on the data bus into the h8mult module when the cpu accesses its memory address space. the bus-stealing function can be used to multiply or multiply- and-accumulate two values stored in memory. the bus-stealing function can be enabled or disabled by bit 6 (s_on) in the mult control register (mltcr). 99
(1) loading of multiplier by bus stealing: figure 5-2 shows the loading of data into register mca by bus stealing. if the s_on bit is set to 1, the h8mult module monitors the address bus when the cpu accesses its memory address space, and compares the address (@aa:16) on the bus with the mult base address register (mltbr) and mult multiplier address register (mltar). if mltbr (upper 8 bits) and mltar (lower 8 bits) = @aa:16, the data on the data bus is loaded into mult multiplier register a (mca). if mltbr (upper 8 bits) and mltar (lower 8 bits) + 2 = @aa:16, the data on the data bus is loaded into mult multiplier register b (mcb). if mltbr (upper 8 bits) and mltar (lower 8 bits) + 4 = @aa:16, the data on the data bus is loaded into mult multiplier register c (mcc). figure 5-2 loading of data into register mca by bus stealing direct write control section bus-stealing control section address bus (@aa:16) data bus (#aa:16) address decoder upper 8 address bits lower 8 address bits mltbr mltar write match address comparator s_on (mltcr bit 6) read/write bus interface controls writing to registers data on bus loaded into mca mca (#aa: 16) mcb mcc (@aa: 16) 100
(2) loading of multiplicand and activation of multiplier by bus stealing: figure 5-3 shows the loading of the multiplicand and automatic selection of the multiplier register by bus stealing. if the s_on bit is set to 1, the h8mult module monitors the address bus when the cpu accesses its memory address space, and compares the address (@aa:16) on the bus with the mult base address register (mltbr) and mult multiplicand address register (mltmar). if mltbr (upper 8 bits) and mltmar (lower 8 bits) = @aa:16, the data on the data bus is loaded as the multiplicand, the multiplier is fetched from mult multiplier register a (mca), and these values are multiplied, or multiplied and accumulated. if mltbr (upper 8 bits) and mltmar (lower 8 bits) + 2 = @aa:16, the multiplier is fetched from mult multiplier register b (mcb). if mltbr (upper 8 bits) and mltmar (lower 8 bits) + 4 = @aa:16, the multiplier is fetched from mult multiplier register c (mcc). figure 5-3 loading of multiplicand and activation of multiplier by bus stealing address bus (@aa:16) data bus (#aa:16) activate multiplier matrix upper 8 address bits lower 8 address bits multiplicand multiplier matrix match address comparator s_on (mltcr bit 6) multiplier read/write bus-stealing control section bus interface multiplier selected automatically mltbr mltmar mca (#aa: 16) mcb mcc (@aa: 16) 101
5.3.4 multiply and multiply-accumulate functions the h8mult module can execute 16 16-bit multiplication, and accumulate products up to a data length of 42 bits. the multiplier and multiplicand on which arithmetic is carried out can be specified in two ways. they can be loaded directly into the h8mult module, or data on memory can be loaded into the h8mult module by the bus-stealing function. (1) multiply: direct loading of multiplier and multiplicand: the procedure is given next. (a) select the multiply function. unsigned multiplication: set bits 2 to 0 (sign, mul, mac) in the mult control register (mltcr) to 010. the results are stored in 32-bit form of mach and macl registers. when an overflow occurs, set bit 0 in the macxh register to 1. signed multiplication: set mltcr bits 2 to 0 (sign, mul, mac) to 110. thre results are stored in 42-bit form of macxh, mach and macl registers. in this case, an overflow is not detected. (b) set the multiplier and multiplicand. load the multiplier into the mult immediate multiplier register (mr), then load the multiplicand into the mult immediate multiplicand register (mmr). the multiplier matrix is activated automatically when the multiplicand is loaded. be sure to use word-size data transfer instructions to load the multiplier and multiplicand. the instruction that loads mmr must be executed immediately after the instruction that loads mr. a coding example is given next. example: signed multiplication, #aaaa #bbbb mov.b #06, @mltcr ; sign = 1, mul = 1 mov.w #aaaa, @mr ; load multiplier mov.w #bbbb, @mmr ; load multiplicand and start multiplying 102
(2) multiply: multiplier loaded by bus stealing, multiplicand loaded directly: the procedure is given next. (a) select the multiply function. see under (1). (b) select the bus-stealing function. set bit 6 (s_on) to 1 in the mult control register (mltcr), and specify the address at which the multiplier will be located in the mult base address register (mltbr) and mult multiplier address register (mltar). the multiplier can be located in any of three words starting at the specified address. place the upper eight bits of the address in mltbr and the lower eight bits in mltar. see the example in figure 5-4. figure 5-4 mltbr and mltar settings h'ee80 h'ee82 h'ee84 h8mult #ee #80 mltbr mltar memory #(multiplier 0) #(multiplier 1) #(multiplier 2) set this address 103
(c) set the multiplier and multiplicand the multiplicand must be set immediately after the multiplier. first access the multiplier on memory, then load the multiplicand into mmr. the multiplier matrix is activated automatically when the multiplicand is loaded. be sure to use word-size instructions to access the multiplier on memory and load the multiplicand. these instructions must be executed consecutively. a coding example is given next. figure 5-5 shows the data flow. example: unsigned multiplication, multiplier #bbbb, multiplier loaded from @ee80 on memory by bus stealing mov.b #42, @mltcr ; s_on = 1, mul = 1 mov.b #ee, @mltbr mov.b #80, @mltar ; multiplier address = #ee80 mov.w @ee80, r0 ; access multiplier address ; bus-stealing function loads multiplier into mca mov.w #bbbb, @mmr ; load multiplicand to start multiplying multiplier #bbbb figure 5-5 multiplication data flow h'ee80 h'ee82 h'ee84 memory #(multiplier 0) #(multiplier 1) #(multiplier 2) #ee #80 mltbr mltar h8mult mca mcb mcc r0 #bbbb multiplier matrix #(multiplier 0) is loaded by bus stealing into mca, then into multiplier matrix 104
(3) multiply: multiplier and multiplicand loaded by bus stealing (a) select the multiply function. see under (1). (b) select the bus-stealing function. see under (2) (b). to load the multiplicand by bus stealing, in addition to the steps in (2) (b), set the lower eight bits of the address where the multiplicand will be located in the mult multiplicand address register (mltmar). see the example in figure 5-6. figure 5-6 mltbr, mltar, and mltmar settings h'ee80 h'ee82 h'ee84 h'eea0 h'eea2 h'eea4 h8mult #ee #80 #a0 mltbr mltar mltmar memory #(multiplier 0) #(multiplier 1) #(multiplier 2) #(multiplicand 0) #(multiplicand 1) #(multiplicand 2) 105
(c) set the multiplier and multiplicand access the multiplier, then the multiplicand. the two accesses do not have to be consecutive. when the multiplier is accessed on memory, it is temporarily stored in one of the mult multiplier registers (mca, mcb, or mcc) by the bus-stealing function. after that, when the multiplicand is accessed, the multiplier is fetched from mca, mcb, or mcc, the multiplier and multiplicand are both loaded into the h8mult module, and multiplication begins. the register from which the multiplier is fetched is determined by the multiplicand address. for details see section 5.3.3 ?us-stealing function.?a coding example is given next. figure 5-7 shows the data flow. example: unsigned multiplication, multiplier (@ee80) multiplicand (@eea0), loaded from memory by bus stealing mov.b #42, @mltcr ; s_on = 1, mul = 1 mov.b #ee, @mltbr mov.b #80, @mltar ; multiplier address = #ee80 mov.b #a0, @mltmar ; multiplicand address = #eea0 mov.w @ee80, r0 ; access multiplier address ; bus-stealing function loads multiplier into mca mov.w @eea0, r0 ; access multiplicand address; h8mult loads multiplicand ; by bus-stealing function, gets multiplier from mca, ; loads multiplier into multiplier matrix, and starts ; multiplying 106
(4) multiply and accumulate: direct loading of multiplier and multiplicand: the procedure is given next. (a) select the multiply-accumulate function. saturating accumulation: set bits 2 to 0 (sign, mul, mac) in the mult control register (mltcr) to 001. the results are stored in 32-bit form of mach and macl registers. when an overflow occurs, set bit 0 in the macxh register to 1. non-saturating accumulation: set bits 2 to 0 (sign, mul, mac) in the mult control register (mltcr) to 101. the results are stored in 42-bit form of macxh, mach, and macl registers. in this case, an overflow is not detected. (b) set a constant and specify the multiplier and multiplicand. first set a constant in the mult result registers (macxh, mach, macl), or clear these registers. next load the multiplier into the mult immediate multiplier register (mr), then load the multiplicand into the mult immediate multiplicand register (mmr). the multiplier matrix is activated automatically when the multiplicand is loaded. the operation performed is (multiplier) (multiplicand) + (constant). be sure to use word-size data transfer instructions to load the multiplier and multiplicand. the instruction that loads mmr must be executed immediately after the instruction that loads mr. a coding example is given next. example: non-saturating multiply-accumulate, #aaaa #bbbb + #cccc bset.b #7, @mltcr ; clr = 1 clr.w @macxh ; initialize macxh, mach, and macl bclr.b #7, @mltcr ; clr = 0 mov.w #0000, @mach mov.w #cccc, @macl ; set 32-bit constant mov.b #05, @mltcr ; sign = 1, mac = 1 mov.w #aaaa, @mr ; load multiplier mov.w #bbbb, @mmr ; load multiplicand and start multiplying 107
(5) multiply and accumulate: multiplier loaded by bus stealing, multiplicand loaded directly: the procedure is given next. (a) select the multiply-accumulate function. see under (4). (b) select the bus-stealing function. set bit 6 (s_on) to 1 in the mult control register (mltcr), and specify the address at which the multiplier will be located in the mult base address register (mltbr) and mult multiplier address register (mltar). the multiplier can be located in any of three words starting at the specified address. place the upper eight bits of the address in mltbr and the lower eight bits in mltar. (c) set the multiplier and multiplicand the multiplicand must be set immediately after the multiplier. first access the multiplier on memory, then load the multiplicand into mmr. the multiplier matrix is activated automatically when the multiplicand is loaded. be sure to use word-size instructions to access the multiplier on memory and load the multiplicand. these instructions must be executed consecutively. a coding example is given next. example: saturating accumulation, multiplier #bbbb + #cccc, multiplier loaded from @ee80 on memory by bus stealing bset.b #7, @mltcr ; clr = 1 clr.w @macxh bclr.b #7, @mltcr ; clr = 0 mov.w #0000, @mach mov.w #cccc, @macl mov.b #41, @mltcr ; s_on = 1, mac = 1, sign = 0 mov.b #ee, @mltbr mov.b #80, @mltar ; multiplier address = #ee80 mov.w @ee80, r0 ; access multiplier address ; bus-stealing function loads multiplier into mca mov.w #bbbb, @mmr ; load multiplicand to start multiply-accumulate operation ; multiplier #bbbb + #cccc. 108
(6) multiply and accumulate: multiplier and multiplicand loaded by bus stealing (a) select the multiply-accumulate function. see under (4). (b) select the bus-stealing function. see under (5) (b). to load the multiplicand by bus stealing, in addition to the steps in (5) (b), set the lower eight bits of the address where the multiplicand will be located in the mult multiplicand address register (mltmar). (c) set the multiplier and multiplicand access the multiplier, then the multiplicand. the two accesses do not have to be consecutive. when the multiplier is accessed on memory, it is temporarily stored in one of the mult multiplier registers (mca, mcb, or mcc) by the bus-stealing function. after that, when the multiplicand is accessed, the multiplier is fetched from mca, mcb, or mcc, the multiplier and multiplicand are both loaded into the h8mult module, and multiplication begins. the register from which the multiplier is fetched is determined by the multiplicand address. for details see section 5.3.3 ?us-stealing function.?a coding example is given next. example: saturating multiplication and accumulation, bus stealing, multiplier (@ee80) multiplicand (@eea0) + #cccc bset.b #7, @mltcr ; clr = 1 clr.w @macxh bclr.b #7, @mltcr ; clr = 0 mov.w #0000, @mach mov.w #cccc, @macl mov.b #41, @mltcr ; s_on = 1, mac = 1 mov.b #ee, @mltbr mov.b #80, @mltar ; multiplier address = #ee80 mov.b #a0, @mltmar ; multiplicand address = #eea0 mov.w @ee80, r0 ; access multiplier address ; bus-stealing function loads multiplier into mca mov.w @eea0, r0 ; access multiplicand address; h8mult loads multiplicand ; by bus-stealing function, fetches multiplier from mca, ; loads multiplier into multiplier matrix, and starts multiplying 109
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section 6 interrupt controller 6.1 overview the interrupt controller decides when to start interrupt exception handling and when to start the data transfer controller (dtc), and arbitrates between competing interrupts. this section describes the interrupts and the functions, features, internal structure, and registers of the interrupt controller. for details of data transfers performed by the dtc, see section 7, ?ata transfer controller. 6.1.1 features the features of the interrupt controller are: six interrupt priority registers (ipr) priority levels from 7 to 0 can be assigned to irq0, irq1 to irq3, and each of the on-chip supporting modules, covering all interrupts except nmi. default priority order for simultaneous interrupts on the same level lower-priority interrupts remain pending until higher-priority interrupts have been handled. nmi has the highest priority level (8) and cannot be masked. six data transfer enable (dte) registers software can select which interrupts (other than nmi) to have served by the dtc. 111
6.1.2 block diagram figure 6-1 shows a block diagram of the interrupt controller. figure 6-1 block diagram nmi ipu wdt sci1 sci2/sci3 * irq 1? i 2 i 1 i 0 sr (cpu) ipra ???iprf dtea ???dtef irq 0 a/d converter interrupt request signals from modules interrupt controller priority decision logic comparator nmi request interrupt request dtc request integrated-timer pulse unit watchdog timer serial communication interface status register interrupt priority register data transfer enable register legend ipu: wdt: sci: sr: ipr: dte: * h8/539 only 112
6.1.3 register configuration the interrupt controller has six interrupt priority registers (ipra to iprf) and six data transfer enable registers (dtea to dtef). see section 7.2.5, ?ata transfer enable registers a to f?for details of dtea to dtef. table 6-1 summarizes these registers. table 6-1 interrupt controller registers table 6-2 summarizes the nmi control register (nmicr), irq control register (irqcr), and irq flag register (irqfr). table 6-2 interrupt controller registers address name abbreviation r/w initial value h'ff00 interrupt priority register a ipra r/w h'00 h'ff01 interrupt priority register b iprb r/w h'00 h'ff02 interrupt priority register c iprc r/w h'00 h'ff03 interrupt priority register d iprd r/w h'00 h'ff04 interrupt priority register e ipre r/w h'00 h'ff05 interrupt priority register f iprf r/w h'00 h'ff08 data transfer enable register a dtea r/w h'00 h'ff09 data transfer enable register b dteb r/w h'00 h'ff0a data transfer enable register c dtec r/w h'00 h'ff0b data transfer enable register d dted r/w h'00 h'ff0c data transfer enable register e dtee r/w h'00 h'ff0d data transfer enable register f dtef r/w h'00 address name abbreviation r/w initial value h'ff1c nmi control register nmicr r/w h'fe h'ff1d irq control register irqcr r/w h'f0 h'fede irq flag register irqfr r/w h'f1 113
6.2 interrupt sources there are two types of interrupts: external interrupts (nmi, irq0, irq1 etc.), and internal interrupts (39 sources). tables 6-3 and 6-4 indicates the default priority order and vector addresses of these interrupts. when multiple interrupts occur simultaneously, the interrupt with the highest priority is served first. using ipra to iprf, software can assign priorities to interrupts on a module basis. relative priorities within the same module are fixed. if the same priority is assigned to two or more modules, simultaneous interrupt requests from those modules are served in the priority order in tables 6-3 and 6-4. after a reset, all interrupts except nmi are assigned priority 0 and are disabled. 114
table 6-3 interrupt priorities and vector addresses (h8/538) assignable priority priority priority among levels within minimum maximum interrupts on interrupt source (initial value) ipr bits module mode mode same level nmi 8 (8) h'0016?017 h'002c?02f high irq0 7? (0) ipra 2 h'0040?041 h'0080?083 interval timer upper 1 h'0042?043 h'0084?087 a/d 4 bits 0 h'0044?045 h'0088?08b converter irq1 7? (0) ipra 2 h'0048?049 h'0090?093 irq2 lower 1 h'004a?04b h'0094?097 irq3 4 bits 0 h'004c?04d h'0098?09b ipu imi1 7? (0) iprb 3 h'0050?051 h'00a0?0a3 channel imi2 upper 2 h'0052?053 h'00a4?0a7 1 cmi1/cmi2 4 bits 1 h'0054?055 h'00a8?0ab ovi 0 h'0056?057 h'00ac?0af imi3 7? (0) iprb 2 h'0058?059 h'00b0?0b3 imi4 lower 1 h'005a?05b h'00b4?0b7 cmi3/cmi4 4 bits 0 h'005c?05d h'00b8?0bb ipu imi1 7? (0) iprc 3 h'0060?061 h'00c0?0c3 channel imi2 upper 2 h'0062?063 h'00c4?0c7 2 cmi1/cmi2 4 bits 1 h'0064?065 h'00c8?0cb ovi 0 h'0066?067 h'00cc?0cf ipu imi1 7? (0) iprc 3 h'0068?069 h'00d0?0d3 channel imi2 lower 2 h'006a?06b h'00d4?0d7 3 cmi1/cmi2 4 bits 1 h'006c?06d h'00d8?0db ovi 0 h'006e?06f h'00dc?0df ipu imi1 7? (0) iprd 3 h'0070?071 h'00e0?0e3 channel imi2 upper 2 h'0072?073 h'00e4?0e7 4 cmi1/cmi2 4 bits 1 h'0074?075 h'00e8?0eb ovi 0 h'0076?077 h'00ec?0ef ipu imi1 7? (0) iprd 3 h'0078?079 h'00f0?0f3 channel imi2 lower 2 h'007a?07b h'00f4?0f7 5 cmi1/cmi2 4 bits 1 h'007c?07d h'00f8?0fb ovi 0 h'007e?07f h'00fc?0ff ipu imi1 7? (0) ipre 2 h'0080?081 h'0100?103 channel imi2 upper 1 h'0082?083 h'0104?107 6 ovi 4 bits 0 h'0086?087 h'010c?10f ipu imi1 7? (0) ipre 2 h'0088?089 h'0110?113 channel imi2 lower 1 h'008a?08b h'0114?117 7 ovi 4 bits 0 h'008e?08f h'011c-011f sci1 eri1 7? (0) iprf 3 h'0090?091 h'0120?123 ri1 upper 2 h'0092?093 h'0124?127 ti1 4 bits 1 h'0094?095 h'0128?12b tei1 0 h'0096?097 h'012c?12f sci2 eri2 7? (0) iprf 3 h'0098?099 h'0130?133 ri2 lower 2 h'009a?09b h'0134?137 ti2 4 bits 1 h'009c?09d h'0138?13b tei2 0 h'009e?09f h'013c?13f low vector table entry address adi 115
table 6-4 interrupt priorities and vector addresses (h8/539) 116 assignable priority priority priority among levels within minimum maximum interrupts on interrupt source (initial value) ipr bits module mode mode same level nmi 8 (8) h'0016?017 h'002c?02f high irq0 7? (0) ipra 2 h'0040?041 h'0080?083 interval timer upper 1 h'0042?043 h'0084?087 a/d 4 bits 0 h'0044?045 h'0088?08b converter irq1 7? (0) ipra 2 h'0048?049 h'0090?093 irq2 lower 1 h'004a?04b h'0094?097 irq3 4 bits 0 h'004c?04d h'0098?09b ipu imi1 7? (0) iprb 3 h'0050?051 h'00a0?0a3 channel imi2 upper 2 h'0052?053 h'00a4?0a7 1 cmi1/cmi2 4 bits 1 h'0054?055 h'00a8?0ab ovi 0 h'0056?057 h'00ac?0af imi3 7? (0) iprb 2 h'0058?059 h'00b0?0b3 imi4 lower 1 h'005a?05b h'00b4?0b7 cmi3/cmi4 4 bits 0 h'005c?05d h'00b8?0bb ipu imi1 7? (0) iprc 3 h'0060?061 h'00c0?0c3 channel imi2 upper 2 h'0062?063 h'00c4?0c7 2 cmi1/cmi2 4 bits 1 h'0064?065 h'00c8?0cb ovi 0 h'0066?067 h'00cc?0cf ipu imi1 7? (0) iprc 3 h'0068?069 h'00d0?0d3 channel imi2 lower 2 h'006a?06b h'00d4?0d7 3 cmi1/cmi2 4 bits 1 h'006c?06d h'00d8?0db ovi 0 h'006e?06f h'00dc?0df ipu imi1 7? (0) iprd 3 h'0070?071 h'00e0?0e3 channel imi2 upper 2 h'0072?073 h'00e4?0e7 4 cmi1/cmi2 4 bits 1 h'0074?075 h'00e8?0eb ovi 0 h'0076?077 h'00ec?0ef ipu imi1 7? (0) iprd 3 h'0078?079 h'00f0?0f3 channel imi2 lower 2 h'007a?07b h'00f4?0f7 5 cmi1/cmi2 4 bits 1 h'007c?07d h'00f8?0fb ovi 0 h'007e?07f h'00fc?0ff ipu imi1 7? (0) ipre 2 h'0080?081 h'0100?103 channel imi2 upper 1 h'0082?083 h'0104?107 6 ovi 4 bits 0 h'0086?087 h'010c?10f ipu imi1 7? (0) ipre 2 h'0088?089 h'0110?113 channel imi2 lower 1 h'008a?08b h'0114?117 7 ovi 4 bits 0 h'008e?08f h'011c-011f sci1 eri1 7? (0) iprf 3 h'0090?091 h'0120?123 ri1 upper 2 h'0092?093 h'0124?127 ti1 4 bits 1 h'0094?095 h'0128?12b tei1 0 h'0096?097 h'012c?12f sci2/ eri2/eri3 7? (0) iprf 3 h'0098?099 h'0130?133 sci3 ri2/ri3 lower 2 h'009a?09b h'0134?137 ti2/ti3 4 bits 1 h'009c?09d h'0138?13b tei2/tei3 0 h'009e?09f h'013c?13f low vector table entry address adi
the five external interrupts are nmi and irq0 to irq3. each external interrupt is described below. 6.2.1 nmi nmi has the highest interrupt priority level (8) and cannot be masked. input at the nmi pin is edge-sensed. either the rising edge or falling edge can be selected by setting or clearing the nonmaskable interrupt edge bit (nmieg) in the nmi control register (nmicr). in nmi exception handling the t bit in the status register (sr) is cleared to 0 and i 2 to i 0 are all set to 1, thereby setting the interrupt mask level to 7. nmi control register (address h'ff1c): the nmi control register (nmicr) selects the sensitive edge of the nmi input. nmicr is initialized to h'fe by a reset and in hardware standby mode. it is not initialized in software standby mode. the nmicr bit structure is shown next. (1) bits 7 to 1?eserved: read-only bits, always read as 1. (2) bit 0?onmaskable interrupt edge (nmieg): selects the sensitive edge of the nmi input. bit initial value r/w 7 1 6543210 1111110 r/w nonmaskable interrupt edge nmieg reserved bits selects sensitive edge of nmi input bit 0 nmieg description 0 nmi is requested on falling edge of nmi input (initial value) 1 nmi is requested on rising edge of nmi input 117
6.2.2 irq0 an irq0 interrupt can be requested by an interrupt signal from the irq 0 pin or an interrupt signal from the watchdog timer (wdt). these two interrupt sources have different vectors. the interrupt from the irq 0 pin is level-sensed. a low irq 0 input requests an irq0 interrupt if the interrupt request enable 0 bit (irq0e) in the irq control register (irqcr) is set to 1. a wdt overflow requests an irq0 interrupt when the wdt is set to interval timer mode. the wdt then requests an irq0 interrupt each time the timer counter (tcnt) overflows. a priority level from 7 to 0 can be assigned to irq0 in the upper four bits of ipra. if bit 4 in dtea is set to 1, irq0 is served by the dtc. in irq0 exception handling the t bit in sr is cleared to 0 and the interrupt mask level is set to the value selected in the four upper bits of ipra. 6.2.3 irq1 to irq3 interrupts irq1 to irq3 are requested by interrupt signals from the irq 1 to irq 3 pins. the irq 1 to irq 3 inputs are sensed on the falling edge. the falling edge generates an irq1, irq2, or irq3 interrupt request if the interrupt request enable 1, 2, or 3 bit (irq1e, irq2e, or irq3e) in the irq control register (irqcr) is set to 1. a priority level from 7 to 0 can be assigned to irq1, irq2, and irq3 collectively in the lower four bits of ipra. if bits 2 to 0 in dtea are set, these interrupts are served by the dtc. in irq1, irq2, and irq3 exception handling the t bit in sr is cleared to 0 and the interrupt mask level is set to the value selected in the lower four bits of ipra. irq control register (address h'ff1d): the irq control register (irqcr) enables and disables inputs at irq 3 , irq 2 , irq 1 , and irq 0 . irqcr is initialized to h'f0 by a reset and in hardware standby mode. it is not initialized in software standby mode. the bit structure of irqcr is shown next. bit initial value r/w 7 1 irq3e 6543210 1110000 r/w r/w r/w r/w interrupt request enable bits irq2e irq1e irq0e reserved bits these bits select functions of pins in ports 6 and 7 118
(1) bits 7 to 4?eserved: read-only bits, always read as 1. (2) bit 3?nterrupt request 3 enable (irq3e): selects the function of pin p6 1 . (3) bit 2?nterrupt request 2 enable (irq2e): selects the function of pin p6 0 . (4) bit 1?nterrupt request 1 enable (irq1e): selects the function of pin p7 1 . (5) bit 0?nterrupt request 0 enable (irq0e): selects the function of pin p7 0 . bit 3 irq3e description 0p6 1 is used for general-purpose input and output (initial value) 1p6 1 is used for irq 3 input bit 2 irq2e description 0p6 0 is used for general-purpose input and output (initial value) 1p6 0 is used for irq 2 input bit 1 irq1e description 0p7 1 is used for general-purpose input and output (initial value) 1p7 1 is used for irq 1 input bit 0 irq0e description 0p7 0 is used for general-purpose input and output (initial value) 1p7 0 is used for irq 0 input 119
irq flag register (address h'fede): the irq flag register (irqfr) indicates the presence of irq3, irq2, and irq1 interrupt requests. when irq3, irq2, or irq1 is requested by external input, the h8/500 cpu sets the interrupt request 1, 2, or 3 flag (irq3f, irq2f, or irq1f) to 1. the interrupt request can be cleared by reading this flag after it has been set to 1, then writing 0. the h8/500 cpu clears irq3f, irq2f, or irq1f to 0 when it outputs the interrupt vector. irqfr is initialized to h'f1 by a reset and in hardware standby mode. it is not initialized in software standby mode. the bit structure of irqfr is shown next. (1) bits 7 to 4?eserved: read-only bits, always read as 1. (2) bit 3?nterrupt request 3 flag (irq3f): indicates that interrupt request 3 (irq3) has been input. bit initial value r/w 7 1 irq3f 6543210 1110001 r/w * r/w * r/w * irq2f irq1f reserved bits interrupt request flags reserved bit these bits indicate interrupt request input note: * software can write 0 to clear the flag. bit 3 irq3f description 0 interrupt request 3 (irq3) has not been input (initial value) 1 interrupt request 3 (irq3) has been input and is waiting for interrupt service (clearing conditions) 1. cleared automatically when the h8/500 cpu accepts irq3 and the interrupt vector is output 2. can also be cleared by reading 1, then writing 0, in which case the pending irq3 interrupt request is deleted 120
(3) bit 2?nterrupt request 2 flag (irq2f): indicates that interrupt request 2 (irq2) has been input. (4) bit 1?nterrupt request 1 flag (irq1f): indicates that interrupt request 1 (irq1) has been input. (5) bit 0?eserved: read-only bit, always read as 1. 6.2.4 internal interrupts there are 39 internal interrupt sources in the on-chip supporting modules. a different interrupt vector address is assigned to each source, so the interrupt handling routine does not have to determine which interrupt has occurred. priority levels from 7 to 0 are assigned to each module in ipra to iprf. dtea to dtef indicate which interrupts in each module are served by the dtc. when an internal interrupt request is accepted, the t bit in sr is cleared to 0 and the interrupt mask level in i 2 to i 0 is set to the value selected in ipra to iprf. bit 2 irq2f description 0 interrupt request 2 (irq2) has not been input (initial value) 1 interrupt request 2 (irq2) has been input and is waiting for interrupt service (clearing conditions) 1. cleared automatically when the h8/500 cpu accepts irq2 and the interrupt vector is output 2. can also be cleared by reading 1, then writing 0, in which case the pending irq2 interrupt request is deleted bit 1 irq1f description 0 interrupt request 1 (irq1) has not been input (initial value) 1 interrupt request 1 (irq1) has been input and is waiting for interrupt service (clearing conditions) 1. cleared automatically when the h8/500 cpu accepts irq1 and the interrupt vector is output 2. can also be cleared by reading 1, then writing 0, in which case the pending irq1 interrupt request is deleted 121
6.3 register descriptions 6.3.1 interrupt priority registers a to f the six interrupt priority registers (ipra to iprf) assign priority levels from 7 to 0 to interrupt sources other than nmi. a reset initializes ipra to iprf to h'00. the bit structure of ipra to iprf is shown next. (1) bits 7 to 4?nterrupt priority, upper four bits: these bits select an interrupt priority level. bit 7 must always be cleared to 0. (2) bits 3 to 0?nterrupt priority, lower four bits: these bits select an interrupt priority level. bit 3 must always be cleared to 0. the on-chip supporting modules are mapped onto the interrupt priority registers as shown in tables 6-5 and 6-6. each interrupt priority register is assigned two on-chip supporting modules. the upper four bits of the interrupt priority register specify the priority level of one module; the lower four bits specify the priority of the other module. table 6-7 indicates how priority levels are set in the interrupt priority registers. for example, to assign level 7 to sci1, set bits 6 to 4 in iprf to 111. bit initial value r/w 7 0 0 0 6543210 0000000 r r/w r/w r/w r r/w r/w r/w upper four bits lower four bits 122
table 6-5 on-chip supporting modules and interrupt priority registers (h8/538) bits 6 to 4 bits 2 to 0 register on-chip supporting module on-chip supporting module ipra irq 0 , wdt, a/d converter irq 1 to irq 3 iprb ipu channel 1 ipu channel 1 iprc ipu channel 2 ipu channel 3 iprd ipu channel 4 ipu channel 5 ipre ipu channel 6 ipu channel 7 iprf sci1 sci2 table 6-6 on-chip supporting modules and interrupt priority registers (h8/539) bits 6 to 4 bits 2 to 0 register on-chip supporting module on-chip supporting module ipra irq 0 , wdt, a/d converter irq 1 to irq 3 iprb ipu channel 1 ipu channel 1 iprc ipu channel 2 ipu channel 3 iprd ipu channel 4 ipu channel 5 ipre ipu channel 6 ipu channel 7 iprf sci1 sci2/sci3 table 6-7 interrupt priority settings in iprh and iprl setting of bits 6 to 4 or bits 2 to 0 interrupt priority level 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 123
6.3.2 timing of priority changes the interrupt controller requires two system clock cycles (2? to determine the priority level of an interrupt. when an instruction modifies an instruction priority register, the new priority takes effect starting from the third state after that instruction has been executed. 6.4 interrupt operations interrupt operations are described next. 6.4.1 operations up to interrupt acceptance figure 6-2 is a flowchart of the interrupt sequence up to the point at which an interrupt is accepted. 1. the interrupt controller receives interrupt request signals from one or more on-chip supporting modules or external interrupt sources. 2. the interrupt controller checks the interrupt priorities assigned in ipra to iprf and selects the interrupt with the highest priority level. interrupts with lower priorities remain pending. among interrupts with the same assigned level, the interrupt controller determines priority as explained in table 6-3, 6-4. 3. the interrupt controller compares the priority level of the selected interrupt request with the mask level in sr bits i 2 to i 0 . if the priority level is equal to or less than the mask level, the interrupt request remains pending. if the priority level is higher than the mask level, the interrupt controller accepts the interrupt request. 4. after accepting an interrupt, the interrupt controller checks the corresponding bit in dtea to dtef. if this bit is set to 1, the data transfer controller is started. if it is cleared to 0, interrupt exception handling is started. 124
figure 6-2 flowchart up to interrupt acceptance interrupt requested? address error? trace? level-7 interrupt? nmi? level-6 interrupt? level-1 interrupt? sr mask level 6? sr mask level 5? sr mask level = 0? data transfer enabled? program execution state interrupt exception handling held pending start dtc no yes no yes no yes no yes no yes no yes no yes no yes no yes yes no yes no 125
6.4.2 interrupt exception handling interrupt exception handling is described below. figure 6-3 shows a flowchart. for dtc operations, see section 7, ?ata transfer controller. 1. when the interrupt controller accepts an interrupt, after the h8/500 cpu finishes executing the current instruction, pc and sr (in minimum mode) or pc, cp, and sr (in maximum mode) are pushed on the stack, leaving the stack in the condition shown in section 6.4.4, ?tack after interrupt exception handling. 2. the interrupt controller clears the t bit in sr to 0, and sets the interrupt mask level (i 2 to i 0 ) to the priority level of the interrupt. 3. in minimum mode, the interrupt controller reads a one-word vector address corresponding to the accepted interrupt from the vector table and copies this word into pc. execution of the interrupt handling routine then starts from the pc address. in maximum mode, the interrupt controller reads a two-word vector address corresponding to the accepted interrupt from the vector table, copies the lower byte of the first word into cp, and copies the second word into pc. execution of the interrupt handling routine then starts from the address indicated by cp and pc. 126
figure 6-3 interrupt exception handling flowchart yes no yes no no yes to interrupt handling routine maximum mode? save sr clear t bit address error? vectoring change mask level save cp trace? save pc 127
6.4.3 interrupt exception handling sequence figure 6-4 is a timing diagram of the interrupt sequence in minimum mode, for the case in which the interrupt handling routine starts at an even address and the program area and stack area are in the external 16-bit-bus two-state-access address space. figure 6-4 interrupt sequence in minimum mode address bus data bus (16 bits) rd wr vector address vector priority level decision and wait for end of current instruction nmi, irq 0 , irqn (n = 1?) internal proces- sing cycles stack access interrupt vector prefetch first instruction of interrupt- handling routine start instruction execution interrupt is accepted (1) instruction prefetch address (2) instruction code (3) starting address of interrupt-handling routine (4) first instruction of interrupt-handling routine (1) (1) (1) sp-2 sp-4 (3) (2) (2) (2) pc sr (4) 128
figure 6-5 is a timing diagram of the interrupt sequence in maximum mode, for the case in which the interrupt handling routine starts at an even address and the program area and stack area are in the external 16-bit-bus two-state-access address space. figure 6-5 interrupt sequence in maximum mode (1) (3) (1) (1) sp-2 sp-4 (2) (4) (2) (2) pc sr sp-6 cp address bus data bus (16 bits) rd wr nmi, irq 0 , irqn (n = 1?) vector address vector address vector cp vector pc priority level decision and wait for end of current instruction inter- nal cy- cles stack access interrupt vector prefetch first instruction of interrupt- handling routine start instruc- tion execu- tion interrupt is accepted (1) instruction prefetch address (2) instruction code (3) starting address of interrupt-handling routine (4) first instruction of interrupt-handling routine 129
6.4.4 stack after interrupt exception handling figure 6-6 shows the stack before and after interrupt exception handling in minimum mode. figure 6-7 shows the stack before and after interrupt exception handling in maximum mode. the pc value saved on the stack is the address of the next instruction to be executed. sp must always point to an even address. if an odd address is set in sp, an address error will occur when the stack is accessed. figure 6-6 stack before and after interrupt exception handling in minimum mode figure 6-7 stack before and after interrupt exception handling in maximum mode 2m-4 2m-3 2m-2 2m-1 2m 2m-4 2m-3 2m-2 2m-1 2m address address sp sp before exception handling sr (upper 8 bits) sr (lower 8 bits) pc (upper 8 bits) pc (lower 8 bits) after exception handling save to stack stack area 2m-6 2m-5 2m-4 2m-3 2m-2 2m-1 2m address address sp before exception handling sr (upper 8 bits) sr (lower 8 bits) don? care cp pc (upper 8 bits) pc (lower 8 bits) after exception handling save to stack stack area 2m-6 2m-5 2m-4 2m-3 2m-2 2m-1 2m sp 130
6.5 interrupts during dtc operation if an interrupt is requested during a dtc data transfer cycle, the interrupt controller holds the interrupt pending until the data transfer cycle has been completed and the next instruction has been executed. an example is shown below. example: add.w mov.w mov.w program flow dtc interrupt request to nmi exception handling sequence data transfer cycle nmi interrupt request after data transfer cycle, h8/500 cpu executes next instruction before starting exception handling r2,r0 r0,@h'fe00 @h'fe02,r0 131
6.6 interrupt response time the h8/538 and h8/539 can access a memory area in two states via a 16-bit bus. fastest interrupt service is obtained by placing the program and stack in this area. table 6-8 indicates the interrupt response time in minimum mode. the maximum number of states occurs when the ldm instruction is executed with all registers specified. table 6-8 number of states before interrupt service in minimum mode number of states stack area: 16 * 1 stack area: 8 * 2 instruction: instruction: instruction: instruction: reason for wait 16 * 3 8 * 4 16 * 3 8 * 4 interrupt priority decision and 2222 comparison with sr mask level 38 38 74 + 16 m 74 + 16 m saving of pc and sr 16 16 28 + 6 m 28 + 6 m total number of states 56 92 + 16 m 68 + 6 m 104 + 22 m notes: 1. stack area in 16-bit-bus two-state-access address space 2. stack area in 8-bit-bus three-state-access address space 3. instruction in 16-bit-bus two-state-access address space 4. instruction in 8-bit-bus three-state-access address space m: number of wait states inserted in memory access maximum number of states to completion of current instruction 132
table 6-9 indicates the interrupt response time in maximum mode. the maximum number of states occurs when the ldm instruction is executed with all registers specified. table 6-9 number of states before interrupt service in maximum mode number of states stack area: 16 * 1 stack area: 8 * 2 instruction: instruction: instruction: instruction: reason for wait 16 * 3 8 * 4 16 * 3 8 * 4 interrupt priority decision and 2222 comparison with sr mask level maximum number of states to 38 74 + 16 m 38 74 + 16 m completion of current instruction saving of pc, cp, and sr 21 21 41 + 10 m 41 + 10 m total number of states 61 97 + 16 m 81 + 10 m 117 + 26 m notes: 1. stack area in 16-bit-bus two-state-access address space 2. stack area in 8-bit-bus three-state-access address space 3. instruction in 16-bit-bus two-state-access address space 4. instruction in 8-bit-bus three-state-access address space m: number of wait states inserted in memory access 133
134
section 7 data transfer controller 7.1 overview an interrupt-triggered data transfer controller (dtc) is included on-chip. the dtc can transfer data between memory and i/o, memory and memory, or i/o and i/o without using the cpu. for example, the dtc can set data in the registers of an on-chip supporting module or send data to an i/o port or serial communication interface (sci) independently of program execution. the h8/500 cpu halts while the dtc is operating. 7.1.1 features the features of the dtc are: the source address and destination address can be set anywhere in the 64-kbyte address space of page 0. the dtc can be programmed to increment the source address and/or destination address after each byte or word is transferred. the dtc can be programmed to transfer one byte or one word of data per interrupt. a data transfer count of up to 65,536 bytes or words can be set in the data transfer counter register (dtcr). after a data transfer, if the data transfer count is zero, the interrupt request that started the dtc is transferred to the h8/500 cpu. the h8/500 cpu then starts normal interrupt exception handling. 135
7.1.2 block diagram figure 7-1 shows a block diagram of the data transfer controller. when dtc service is requested, the dtc loads its control registers from memory with information corresponding to the interrupt source, transfers a byte or word of data, and writes any altered register information back to memory. figure 7-1 block diagram of data transfer controller internal data bus dtc service request memory register information 0 register information 1 dtc interrupt controller dtea dteb dtef dtmr irq 0 dtsr dtdr dtcr irq 1 dtmr: dtsr: dtdr: dtcr: dtea to dtef: data transfer enable registers a to f legend data transfer mode register data transfer source address register data transfer destination address register data transfer count register 136
7.1.3 register configuration table 7-1 summarizes the dtc control registers. table 7-1 dtc registers these registers cannot be accessed directly. to set information in the dtc control registers, software should alter the information on memory. starting of the dtc is controlled by the interrupt controllers data transfer enable registers. table 7-2 summarizes these registers. table 7-2 data transfer enable registers address name abbreviation r/w initial value h'ff08 data transfer enable register a dtea r/w h'00 h'ff09 data transfer enable register b dteb r/w h'00 h'ff0a data transfer enable register c dtec r/w h'00 h'ff0b data transfer enable register d dted r/w h'00 h'ff0c data transfer enable register e dtee r/w h'00 h'ff0d data transfer enable register f dtef r/w h'00 name abbreviation r/w data transfer mode register dtmr data transfer source address register dtsr data transfer destination address register dtdr data transfer count register dtcr 137
7.2 register descriptions 7.2.1 data transfer mode register the data transfer mode register (dtmr) is a 16-bit register that selects the data size and specifies whether to increment the source and destination addresses. the dtmr bit structure is shown next. (1) bit 15?ize (sz): selects byte-size or word-size data transfer. (2) bit 14?ource increment mode (si): specifies whether to increment the source address. bit r/w 15 sz 14 si 13 di 12 11 10 9 8 7 6 5 4 3 2 1 0 size bit selects byte-size or word-size data transfer source increment mode bit selects source address increment mode destination increment mode bit selects destination address increment mode reserved bits bit 15 sz description 0 byte transfer 1 word (two-byte) transfer * note: * for word transfer, dtsr and dtdr must indicate even addresses. bit 14 si description 0 not incremented 1 1. if sz = 0: incremented by +1 after each data transfer 2. if sz = 1: incremented by +2 after each data transfer 138
(3) bit 13?estination increment mode (di): specifies whether to increment the destination address. (4) bits 12 to 0?eserved: reserved bits. 7.2.2 data transfer source address register the data transfer source address register (dtsr) is a 16-bit register that designates the data transfer source address. the dtsr bit structure is shown next. for word transfer the source address must be even. in maximum mode, the source address is implicitly located in page 0. 7.2.3 data transfer destination address register the data transfer destination address register (dtdr) is a 16-bit register that designates the data transfer destination address. the dtsr bit structure is shown next. for word transfer the destination address must be even. in maximum mode, the destination address is implicitly located in page 0. bit 13 di description 0 not incremented 1 1. if sz = 0: incremented by +1 after each data transfer 2. if sz = 1: incremented by +2 after each data transfer bit r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 139
7.2.4 data transfer count register the data transfer count register (dtcr) is a 16-bit register that designates the number of bytes or words to be transferred. the initial count can be set from 1 to 65,536. a register value of 0 designates an initial count of 65,536. the dtcr bit structure is shown next. the data transfer count register is decremented automatically after each byte or word is transferred. when the count reaches 0, indicating that the designated number of bytes or words have been transferred, the dtc sends the h8/500 cpu an interrupt request with the same interrupt source that started the data transfer. 7.2.5 data transfer enable registers a to f the six data transfer enable registers (dtea to dtef) specify whether an interrupt starts the dtc. (certain interrupts, such as nmi, cannot start the dtc.) the bit structure of dtea to dtef is shown next. the bits in these registers are assigned to interrupts as indicated in table 7-3. if the bit for a certain interrupt is set to 1, that interrupt is regarded as a request for dtc service. if the bit is cleared to 0, the interrupt is regarded as an h8/500 cpu interrupt request. only the interrupts indicated in tables 7-3 and 7-4 can request dtc service in the h8/538 and h8/539. dte bits not assigned to any interrupt (indicated by ?in tables 7-3 and 7-4) should be left cleared to 0. bit initial value r/w 7 0 0 0 6543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w bit r/w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 140
table 7-3 bit assignments of data transfer enable registers (h8/538) adi (irq0) irq0 7654 cmi1, 2 imi2 imi1 cmi1, 2 imi2 imi1 cmi1, 2 imi2 imi1 imi2 imi1 ?iri register on-chip supporting module on-chip supporting module irq3 irq2 irq1 3210 cmi3,4 imi4 imi3 cmi1, 2 imi2 imi1 cmi1, 2 imi2 imi1 imi2 imi1 ?iri dtea dteb dtec dted dtee dtef irq 0 , adi ipu (ch1) ipu (ch2) ipu (ch4) ipu (ch6) sci1 irq 1? ipu (ch1) ipu (ch3) ipu (ch5) ipu (ch7) sci2 bits 7 to 4 bits 3 to 0 141
table 7-4 bit assignments of data transfer enable registers (h8/539) 7.2.6 note on timing of dte modifications the interrupt controller requires two system clock cycles (2? to determine the priority level of an interrupt. when an instruction modifies one of dtea to dtef, the new setting takes effect starting from the third state after the instruction has been executed. 142 adi (irq0) irq0 7654 cmi1, 2 imi2 imi1 cmi1, 2 imi2 imi1 cmi1, 2 imi2 imi1 imi2 imi1 ?iri register on-chip supporting module on-chip supporting module irq3 irq2 irq1 3210 cmi3,4 imi4 imi3 cmi1, 2 imi2 imi1 cmi1, 2 imi2 imi1 imi2 imi1 ?iri dtea dteb dtec dted dtee dtef irq 0 , adi ipu (ch1) ipu (ch2) ipu (ch4) ipu (ch6) sci1 irq 1? ipu (ch1) ipu (ch3) ipu (ch5) ipu (ch7) sci2/sci3 bits 7 to 4 bits 3 to 0
7.3 operation dtc operations are described next. 7.3.1 dtc operations figure 7-2 is a flowchart of the data transfer operations performed by the dtc. for operations from the occurrence of an interrupt until the dtc is activated, see section 6.4.1, ?equence of interrupt operations. 1. from the dtc vector table, the dtc reads the address at which the register information for the interrupt is stored in memory and loads the stored information into its control registers. when the dtc is activated, the interrupt source that activated the dtc is cleared, except for interrupts from the serial communication interface. 2. the dtc transfers the data and increments the source and destination addresses as required, then decrements dtcr. if the dtc was activated by an interrupt from the serial communication interface, the interrupt source is cleared when the dtc accesses the transmit data register (tdr) or receive data register (rdr). 3. the dtc writes updated register information back to memory. 4. if the dtcr value is 0, the h8/500 cpu starts interrupt exception handling for the interrupt that activated the dtc. 143
figure 7-2 flowchart of dtc operations interrupt dtc no yes yes no yes no yes no dtc interrupt? read dtc vector read data transfer mode read source address read data increment source address (+1 or +2) write source address write data destination address increment mode? increment destination address (+1 or +2) read dtcr dtcr ? ? dtcr write dtcr h8/500 cpu interrupt handling starts. see section 6.4.2, ?nterrupt exception handling. dtcr = 0? source address increment mode? read destination address write destination address int program execution state 144
7.3.2 dtc vector table figure 7-3 shows how the dtc vector table works. for each interrupt that can request dtc service, the dtc vector table provides a pointer to an address in memory where the dtc control register information for that interrupt is stored. register information tables can be placed in any available locations in page 0. figure 7-3 shows an example in which the register information is located on ram. register information can also be stored on rom if there is no need to update the information after each transfer (if the source and destination addresses are not incremented and the desired data transfer count is one). figure 7-3 dtc vector table the dtc vector table structure differs between minimum and maximum modes. in maximum mode there is no page specification: page 0 is assumed implicitly. figure 7-4 shows a dtc vector table entry in minimum and maximum mode. vector table ram exception vector table register information 0 register information 1 dtc vector table ta1 ta0 * * ta0 ta1 dtmr0 dtsr0 dtdr0 dtcr0 dtmr1 dtsr1 dtdr1 dtcr1 note: * ta0, ta1, ...: addresses of dtc register information tables in memory. 145
figure 7-4 dtc vector table entry tables 7-5 and 7-6 list the address of the entry in the dtc vector table for each interrupt. table 7-5 addresses of dtc vectors (h8/538) 2 m 2 m + 1 2 m + 2 2 m + 3 address address vector table address (high) address (low) register information vector table memory don? care * don? care * address (high) address (low) (1) minimum mode (2) maximum mode note: * addresses 2m and 2 m + 1 are not accessed when the vector is read. m m + 1 address of vector table entry interrupt source minimum mode maximum mode irq0 h'00c0?0c1 h'0180?183 interval timer h'00c2?0c3 h'0184?187 ad converter adi h'00c4?0c5 h'0188?18b irq1 h'00c8?0c9 h'0190?193 irq2 h'00ca?0cb h'0194?197 irq3 h'00cc?0cd h'0198?19b ipu channel 1 imi1 h'00d0?0d1 h'01a0?1a3 imi2 h'00d2?0d3 h'01a4?1a7 cmi1/cmi2 h'00d4?0d5 h'01a8?1ab imi3 h'00d8?0d9 h'01b0?1b3 imi4 h'00da?0db h'01b4?1b7 cmi3/cmi4 h'00dc?0dd h'01b8?1bb 146
147 table 7-5 addresses of dtc vectors (h8/538) (cont) address of vector table entry interrupt source minimum mode maximum mode ipu channel 2 imi1 h'00e0?0e1 h'01c0?1c3 imi2 h'00e2?0e3 h'01c4?1c7 cmi1/cmi2 h'00e4?0e5 h'01c8?1cb ipu channel 3 imi1 h'00e8?0e9 h'01d0?1d3 imi2 h'00ea?0eb h'01d4?1d7 cmi1/cmi2 h'00ec?0ed h'01d8?1db ipu channel 4 imi1 h'00f0?0f1 h'01e0?1e3 imi2 h'00f2?0f3 h'01e4?1e7 cmi1/cmi2 h'00f4?0f5 h'01e8?1eb ipu channel 5 imi1 h'00f8?0f9 h'01f0-01f3 imi2 h'00fa?0fb h'01f4?1f7 cmi1/cmi2 h'00fc?0fd h'01f8?1fb ipu channel 6 imi1 h'00a0?0a1 h'0140?143 imi2 h'00a2?0a3 h'0144?147 ipu channel 7 imi1 h'00a8?0a9 h'0150?153 imi2 h'00aa?0ab h'0154?157 sci1 ri1 h'00b2?0b3 h'0164?167 ti1 h'00b4?0b5 h'0168?16b sci2 ri2 h'00ba?0bb h'0174?177 ti2 h'00bc?0bd h'0178?17b
table 7-6 addresses of dtc vectors (h8/539) address of vector table entry interrupt source minimum mode maximum mode irq0 h'00c0?0c1 h'0180?183 interval timer h'00c2?0c3 h'0184?187 ad converter adi h'00c4?0c5 h'0188?18b irq1 h'00c8?0c9 h'0190?193 irq2 h'00ca?0cb h'0194?197 irq3 h'00cc?0cd h'0198?19b ipu channel 1 imi1 h'00d0?0d1 h'01a0?1a3 imi2 h'00d2-00d3 h'01a4?1a7 cmi1/cmi2 h'00d4?0d5 h'01a8?1ab imi3 h'00d8?0d9 h'01b0?1b3 imi4 h'00da?0db h'01b4?1b7 cmi3/cmi4 h'00dc?0dd h'01b8?1bb ipu channel 2 imi1 h'00e0?0e1 h'01c0?1c3 imi2 h'00e2?0e3 h'01c4?1c7 cmi1/cmi2 h'00e4?0e5 h'01c8?1cb ipu channel 3 imi1 h'00e8?0e9 h'01d0?1d3 imi2 h'00ea?0eb h'01d4?1d7 cmi1/cmi2 h'00ec?0ed h'01d8?1db ipu channel 4 imi1 h'00f0?0f1 h'01e0?1e3 imi2 h'00f2?0f3 h'01e4?1e7 cmi1/cmi2 h'00f4?0f5 h'01e8?1eb ipu channel 5 imi1 h'00f8?0f9 h'01f0-01f3 imi2 h'00fa?0fb h'01f4?1f7 cmi1/cmi2 h'00fc?0fd h'01f8?1fb ipu channel 6 imi1 h'00a0?0a1 h'0140?143 imi2 h'00a2?0a3 h'0144?147 ipu channel 7 imi1 h'00a8?0a9 h'0150?153 imi2 h'00aa?0ab h'0154?157 148
table 7-6 addresses of dtc vectors (h8/539) (cont) address of vector table entry interrupt source minimum mode maximum mode sci1 ri1 h'00b2?0b3 h'0164?167 ti1 h'00b4?0b5 h'0168?16b sci2/sci3 ri2/ri3 h'00ba?0bb h'0174?177 ti2/ti3 h'00bc?0bd h'0178?17b 7.3.3 location of register information in memory for each interrupt, the dtc control register information is stored in four consecutive words in memory in the order shown in figure 7-5. figure 7-5 order of register information 149 vector table ta ta + 2 ta + 4 ta + 6 memory dtmr dtsr dtdr dtcr 8 bits 8 bits
7.3.4 number of states per data transfer table 7-7 lists the number of states required per data transfer, assuming that the dtc control register information is stored in the 16-bit-bus two-state-access address space. table 7-7 number of states per data transfer 16-bit-bus on-chip 8-bit-bus on-chip 2-state-access ? supporting 3-state-access ? supporting increment mode address space module address space module source destination (si) (di) byte transfer word transfer byte transfer word transfer 0 0 31 34 32 38 0 1 33 36 34 40 1 0 33 36 34 40 1 1 35 38 36 42 note: numbers in the table are the number of states. the values in table 7-7 are calculated from the formula: n = 26 + 2 si + 2 di + m s + m d where m s and m d have the following meanings: m s : number of states for reading source data m d : number of states for writing destination data the values of m s and m d depend on the data location as follows: 1. byte or word data in 16-bit-bus two-state-access address space: 2 states 2. byte data in eight-bit-bus three-state-access address space or on-chip supporting module: 3 states 3. word data in eight-bit-bus three-state-access address space or on-chip supporting module: 6 states if the dtc control register information is stored in the eight-bit-bus three-state-access address space, 20 + 4 si + 4 di must be added to the values in table 7-7. table 7-8 indicates the number of additional states between the occurrence of an interrupt request and the starting of the dtc (states during which the interrupt controller checks priority and waits for execution of the current instruction to end). at maximum, this number of states is the sum of 150
the values indicated for items no. 1 and 2 in table 7-8. if the data transfer count is 0 at the end of a data transfer cycle, the number of states from the end of the data transfer cycle until the first instruction of the interrupt-handling routine is executed is the value given for item no. 3 in table 7-8. the maximum number of states in table 7-8 occurs when the ldm instruction is executed with all registers specified. table 7-8 number of states before interrupt service number of states no. reason for wait minimum mode maximum mode 1 interrupt priority decision and comparison 2 with mask level in sr 2 number of states instruction is in 16-bit-bus (ldm instruction specifying all to completion of two-state-access address registers) current instruction space 38 instruction is in 8-bit-bus (ldm instruction specifying all three-state-access address registers) space 74 + 16 m 3 instruction is in 16-bit-bus 16 21 two-state-access address space instruction is in 8-bit-bus 28 + 6 m 41 + 10 m three-state-access address space notation m: number of wait states inserted in external memory access number of states from saving of pc and sr or pc, cp, and sr until prefetching of first instruction of interrupt-handling routine 151
7.4 procedure for using dtc the procedure for using the dtc is explained next. figure 7-6 is a flowchart. procedure for using the dtc 1. dtc register setup: set the appropriate dtmr, dtsr, dtdr, and dtcr register information in the memory location indicated in the dtc vector table. 2. dten, iprn (n = a to f), and sr setup: set the data transfer enable bit of the pertinent interrupt to 1, and set the priority of the interrupt source (in the interrupt priority register) and the interrupt mask level (in the cpu status register) so that the interrupt can be accepted. 3. interrupt enabling: set the interrupt enable bit for the interrupt source in the control register of the on-chip supporting module (or irq control register). following these preparations, the dtc will be started each time the interrupt occurs. figure 7-6 procedure for using dtc #dtmr ? @dt_reg #dtsr ? @dt_reg + 2 #dtdr ? @dt_reg + 4 #dtcr ? @dt_reg + 6 <1> ? dte bit (dten) ? iprn ? sr enable interrupt request dtc is enabled set dtc register information set dten, iprn, and sr (n = a to f) enable interrupt request dtc 152
7.5 example (1) purpose: to receive 128 bytes of serial data via serial communication interface channel 1. (2) conditions: operating mode: minimum mode. received data are to be stored in consecutive addresses starting at h'fc00. the dtc vector table contains h'f6 at address h'00b2 and h'80 at address h'00b3. the desired interrupt mask level in the cpu status register is 4, and the desired sci1 interrupt priority level is 5. table 7-9 shows the dtc control register information to set on ram. table 7-9 dtc control register information set on ram (3) operation ? software sets dtmr, dtsr, dtdr, and dtcr information in ram addresses h'f680 to h'f687 as shown in table 7-9. - software sets the ri (sci1 receive interrupt) bit in data transfer enable register f (dtef) to 1. ? software sets the interrupt mask level in sr bits i 2 to i 0 to 4, and the sci1 interrupt priority level in the upper four bits of interrupt priority register f (iprf) to 0101 (5). software sets sci1 to the appropriate receive mode, and sets the receive interrupt enable bit (rie) in the serial control register (scr) to 1 to enable receive interrupts. thereafter, each time sci1 receives one byte of data, the dtc is activated and transfers the byte of receive data into ram. the dtc automatically clears the sci1 receive interrupt request. register setting value dtmr byte transfer h'2000 source address fixed destination address incremented dtsr address of sci1 receive data register h'fecd dtdr address h'fc00 h'fc00 dtcr transfer count (128) h'0080 153
when 128 bytes have been transferred (dtcr = 0), sci1 receive interrupt exception handling begins. 2 the interrupt-handling routine executes a receive wrap-up routine. figure 7-7 is a flowchart for this example. figure 7-7 flowchart for dtc example dtcr = 0? no yes 5 6 7 1 2 3 4 5 6 7 #dtmr ? @f680 #dtsr ? @f682 #dtdr ? @f684 #dtcr ? @f686 <1> ? ri bit (dtef) <100> ? i 2 to i 0 (sr) <101> ? iprf (bits 6 to 4) set up sci1 and enable interrupt @ dtsr ? @dtdr+ clear interrupt request dtcr ?1 ? dtcr sci1 receive wrap-up routine write dtc control register information on ram set ri bit in dtef to 1 set interrupt mask level (sr) and interrupt priority level (iprf) set sci1 to receive mode and enable interrupt requests transfer received data to ram test for end of data: start interrupt handling if dtcr = 0 interrupt handling: receive-data wrap-up routine dtc setup end of setup start dtc 154
figure 7-8 shows the dtc vector table and data in ram for this example. receive data are stored in consecutive addresses. figure 7-8 example of use of dtc to receive continuous serial data ram h'f680 h'f681 h'f687 h'20 h'00b2 h'00b3 h'f6 h'80 h'00 h'fe h'cd h'fc h'00 h'00 h'80 h'fc00 h'fc7f rdr sci dtc vector table data transfer mode address address receive data 1 receive data 2 receive data 128 source address destination address transfer count transferred by dtc 155
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section 8 wait-state controller 8.1 overview for interfacing to low-speed external devices, an on-chip wait-state controller (wsc) can insert wait states (t w ) into bus cycles. the wait function can be used in cpu and dtc access cycles to the external three-state-access address space. it is not used in access to the two-state-access address space or the on-chip register area (h'fe80 to h'ffff). wait states are inserted between the t 2 state and t 3 state in the bus cycle. the number of wait states can be selected by a value set in the wait control register (wcr), or by holding the wait pin low for the required interval. 8.1.1 features the features of the wait-state controller are: selection of three operating modes programmable wait mode, pin wait mode, or pin auto-wait mode selection of number of wait states 0, 1, 2, or 3 wait states can be inserted, and 4 or more wait states can be inserted in pin wait mode by holding the wait pin low. 157
8.1.2 block diagram figure 8-1 shows a block diagram of the wait-state controller. figure 8-1 block diagram of wait state controller 8.1.3 register configuration table 8-1 summarizes the wait control register. table 8-1 wait control register internal data bus wait counter wait request control logic wait input legend wcr: wms1/0: wc1/0: wcr wms1 wc1 wc0 wms0 wait control register wait mode select bits 1 and 0 wait count bits 1 and 0 address name abbreviation r/w initial value h'ff14 wait control register wcr r/w h'f3 158
8.2 wait control register the wait control register (wcr) is an eight-bit register that specifies the wait mode and the number of wait states to be inserted. the wcr bit structure is shown next. wcr is initialized to h'a3 by a reset and in hardware standby mode. wcr is not initialized in software standby mode. (1) bits 7 to 4?eserved: read-only bits, always read as 1. (2) bits 3 and 2?ait mode select 1 and 0 (wms1 and wms0): these bits select the wait mode. bit initial value r/w 7 1 wms1 6543210 1110011 r/w r/w r/w r/w wms0 wc1 wc0 reserved bits wait mode select 1 and 0 these bits select the wait mode wait count 1 and 0 these bits indicate the number of wait states to be inserted bit 3 bit 2 wms1 wms0 description 0 0 programmable wait mode (initial value) 0 1 no wait states inserted, regardless of wait count 1 0 pin wait mode 1 1 pin auto-wait mode 159
(3) bits 1 and 0?ait count 1 and 0 (wc1 and wc0): these bits specify the number of wait states to be inserted. wait states (t w ) are inserted only in bus cycles in which the cpu or dtc accesses the external three-state-access address space. 8.3 operation table 8-2 summarizes the operation of the three wait modes. table 8-2 wait modes bit 1 bit 0 wc1 wc0 description 0 0 no wait states inserted, except in pin wait mode 0 1 1 wait state inserted 1 0 2 wait states inserted 1 1 3 wait states inserted (initial value) description number of wait mode wait pin function insertion conditions states inserted programmable disabled inserted in access to 0 to 3 states are wait mode external three-state-access inserted as specified wms1 = 0 address space by bits wc0 and wc1 wms0 = 0 pin wait mode enabled inserted in access to 0 to 3 states are wms1 = 1 external three-state-access inserted as wms0 = 0 address space specified by bits wc0 and wc1 additional states can be inserted by driving the wait signal low pin auto-wait enabled inserted in access to 0 to 3 states are mode external three-state-access inserted as specified wms1 = 1 address space if by bits wc0 and wc1 wms0 = 1 wait is low 160
8.3.1 programmable wait mode programmable wait mode is selected when wms1 = 0 and wms0 = 0. whenever the cpu or dtc accesses the external three-state-access address space, the number of wait states selected by bits wc1 and wc0 are inserted. the pa 4 / wait pin is not used for wait control; it is available for general-purpose input or output. figure 8-2 shows the timing of operation in this mode when the wait count is 1 (wc1 = 0, wc0 = 1). figure 8-2 programmable wait mode (example of external 16-bit-bus, three-state-access address space) rd (read access) d 15 ? 0 (read access) hwr, lwr (write access) d 15 ? 0 (write access) as a 19 ? 0 one wait state inserted by wait count read data write data 3-state access + 1 wait state read data external three-state-access address space t 1 t 2 t 1 t 2 t w t 3 t 1 161
8.3.2 pin wait mode pin wait mode is selected when wms1 = 1 and wms0 = 0. in this mode the wait function of the pa 4 / wait pin is used automatically. the number of wait states indicated by wait count bits wc1 and wc0 are inserted into any bus cycle in which the cpu or dtc accesses the external three-state-access address space. in addition, wait states are inserted if the wait signal is driven low, even if the wait count is 0. wait states continue to be inserted until the wait signal goes high. this mode is useful for inserting four or more wait states, or when different external devices require different numbers of wait states. figure 8-3 shows the timing of operation in this mode when the wait count is 1 (wc1 = 0, wc0 = 1) and the wait signal is held low to insert one additional wait state. figure 8-3 pin wait mode (example of external 16-bit-bus, three-state-access address space) hwr, lwr (write access) rd (read access) d 15 ? 0 (read access) d 15 ? 0 (write access) as a 19 ? 0 wait one wait state inserted by wait count pin-requested wait (one state) external three-state-access address space write data 3-state access + 1 wait state + pin-requested wait (1 state) read data read data t 1 t 2 t 1 t 2 t w t w t 3 ** note: * arrows indicate times at which the wait pin is sampled. 162
8.3.3 pin auto-wait mode pin auto-wait mode is selected when wms1 = 1 and wms0 = 1. in this mode the wait function of the pa 4 / wait pin is used automatically. when the cpu or dtc accesses the external three- state-access address space, if the wait pin is low the number of wait states indicated by bits wc1 and wc0 are inserted. this mode offers a simple way to interface a low-speed device: wait states can be inserted by routing the address strobe signal ( as ) and a decoded address signal to the wait pin. figure 8-4 shows the timing of operation in this mode when the wait count is 1 (wc1 = 0, wc0 = 1). in pin auto-wait mode the wait pin is sampled only once, on the falling edge of the system clock (? in the t 2 state. if the wait signal is low at this time, the wait-state controller inserts the number of wait states indicated by bits wc1 and wc0. the wait pin is not sampled during the t w and t 3 states, so no additional wait states are inserted even if the wait signal continues to be held low. figure 8-4 pin auto-wait mode (example of external 16-bit-bus, three-state-access address space) t 1 t 2 t 3 t 1 t 2 t w t 3 read data read data hwr, lwr (write access) rd (read access) d 15 ? 0 (read access) d 15 ? 0 (write access) as a 19 ? 0 wait pin auto-wait (one wait state) inserted by wait count external three-state-access address space write data 3-state access + pin auto-wait (1 state) note: * arrows indicate times at which the wait pin is sampled. ** 163
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section 9 clock pulse generator 9.1 overview the on-chip clock pulse generator (cpg) consists of an oscillator circuit, a system clock divider, and prescalers for the clock signals of the on-chip supporting modules. the ztat version of the h8/538 has a clock-halving clock pulse generator. the masked-rom versions of the h8/538 include a version with a clock-halving clock pulse generator and a version with a 1:1 clock pulse generator. the h8/539 has a 1:1 clock pulse generator. the 1:1 clock pulse generator has a duty adjustment circuit instead of a system clock divider. 9.1.1 block diagram figure 9-1 shows the configuration of the clock-halving version of the clock pulse generator. figure 9-2 shows the configuration of the 1:1 version. figure 9-1 block diagram of clock-halving clock pulse generator (h8/538 ztat and masked-rom versions) ?2/4096 xtal extal oscillator frequency divider (1/2) prescalers cpg 165
figure 9-2 block diagram of 1:1 clock pulse generator (h8/538 masked-rom version and h8/539) 9.2 oscillator circuit clock pulses can be generated by connecting a crystal resonator to the clock oscillator circuit, or by supplying an external clock signal. these two methods are described next. 9.2.1 connecting a crystal resonator (1) circuit configuration: a crystal resonator can be connected as in the example in figure 9-3. an at-cut parallel resonating crystal should be used. for versions with a 1:1 clock pulse generator, insert a damping resistor as listed in table 9-1. figure 9-3 connection of crystal resonator (example) extal xtal c l c l c l = 10?2 pf rd * note: * insert a damping resistor for versions with a 1:1 clock pulse generator (h8/539, h8/538 masked-rom version). do not insert a damping resistor for versions with a clock-halving version (h8/538 ztat). ?2/4096 xtal extal oscillator duty adjustment circuit prescalers cpg 166
table 9-1 damping resistance (examples) frequency (mhz) 2 4 8 12 16 20 rd max ( w ) 1 k 500 200 0 0 0 (2) crystal resonator: figure 9-4 shows an equivalent circuit of the crystal resonator. the crystal resonator should have the characteristics listed in table 9-2. the crystal frequency depends on the desired system clock frequency, as follows: clock-halving versions use a crystal resonator with a frequency equal to twice the system clock frequency (?. 1:1 versions use a crystal resonator with a frequency equal to the system clock frequency (?. figure 9-4 crystal resonator equivalent circuit table 9-2 crystal resonator parameters frequency (mhz) 2 4 8 12 16 20 rs max ( w ) 500 120 60 40 30 20 c 0 (pf) 7 pf max (3) notes on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. see figure 9-5. when the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the xtal and extal pins. c l c 0 rs extal xtal l at-cut parallel resonator 167
figure 9-5 example of incorrect board design 9.2.2 external clock input (1) circuit configuration: an external clock signal can be input at the extal pin as shown in the example in figure 9-6. a reverse-phase clock should be input at the xtal pin. when the circuit configuration in figure 9-6 is used, the external clock should be held high in standby mode. figure 9-6 external clock input (example) note: the ztat version of the h8/538 can be driven with the xtal pin left open if the clock frequency is 16 mhz or less. the h8/539 and the masked rom version of the h8/538 can be driven with the xtal pin left open if the stray capacitance at the xtal pin does not exceed 10 pf and the clock input can be held high in standby mode. extal xtal external clock input 74hc04 or equivalent 168 xtal extal h8/53x signal a signal b not allowed c l c l
(2) external clock clock-halving version table 9-3 lists the required characteristics of the external clock signal. table 9-3 external clock frequency double the system clock frequency ( ) duty cycle 45%?5% 1:1 version table 9-4 and figure 9-7 indicate the required clock timing. table 9-4 clock timing v cc = 2.7 to 5.5 v v cc = 5.0 v ?0% item symbol min max min max unit test conditions external 30 70 30 70 % ? 3 5 mhz figure 9-7 clock input duty (a/t cyc ) 40 60 40 60 % ?< 5 mhz external t exr 10 5 ns figure 9-7 clock rise time external t exf ?0 5 ns clock fall time clock duty 40 60 40 60 % ? 3 5 mhz figure 20-4 cycle (t ch /t cyc ) 40 60 40 60 % ?< 5 mhz figure 9-7 external clock input timing a t cyc t exf t exr v cc 0.5 extal 169
9.3 system clock divider the system clock divider divides the frequency (f osc ) by 2 to create the system clock (?. 9.4 duty adjustment circuit when the external clock frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle to create the system clock (?. 170
section 10 i/o ports 10.1 overview the h8/538 and h8/539 have twelve i/o ports. ports 1, 2, 4, 5, 7, b, and c are eight-bit input/output ports. port 3 is a six-bit input/output port. port 6 is a five-bit input/output port. port a is a seven-bit input/output port. port 8 is a four-bit input port. port 9 is an eight-bit input port. these ports are multiplexed with inputs and outputs of the on-chip supporting modules. the functions of ports 1, 2, a, b, and c also differ depending on the operating mode. each port has a data direction register (ddr) for selecting input or output, and a data register (dr) for holding output data. in addition to dr and ddr, port a has a bus release control register (brcr), and ports b and c have pull-up transistor control registers (pbpcr and pcpcr). ports 1, 2, a, b, and c can drive one ttl load and a 90-pf capacitive load. ports 3 to 7 can drive one ttl load and a 30-pf capacitive load. ports 3 and 5 can drive leds (with 10-ma current sink). ports 4 and 5 have schmitt-trigger input circuits. some of the pin functions in ports 6, 7, and a differ between the h8/538 and h8/539. pwm output pin functions have been added to ports 6 and 7 of the h8/539, and both serial communication input/output and pwm output pin functions have been added to port a. all functions of ports 1 to 5, 8, 9, b, and c are identical in the h8/538 and h8/539. functions of ports 6, 7, and a are identical unless stated otherwise. table 10-1 summarizes ports 1 to c of the h8/539, giving the pin names and functions in each mode. table 10-2 summarizes ports 1 to c of the h8/538, giving the pin names and functions in each mode. 171
table 10-1 ports 1 to c, pin names, and functions in each mode (h8/539) 172 mode 7 modes modes (single- port description pins 1 and 6 mode 2 3 and 5 mode 4 chip mode) port 1 8-bit input/ p1 7 ?1 0 / data bus (d 15 to d 8 ) general- output port d 15 ? 8 purpose input/output port 2 8-bit input/ p2 7 ?2 0 / data bus general- data bus data bus general- output port d 7 ? 0 (d 7 to d 0 ) purpose (d 7 to d 0 ) (d 7 to d 0 ) purpose input/ input/output output port 3 6-bit input/ p3 5 ?3 0 / output (t2oc 2/1 , t1oc 4/3/2/1 ) from 16-bit integrated-timer output port t2oc 2 , t2oc 1 , pulse unit (ipu), and general-purpose input/output t1oc 4 ?1oc 1 port 4 8-bit input/ p4 7 /t7ioc 2 , input and output (t7ioc 2/1 , t6ioc 2/1 , t5ioc 2/1 , t4ioc 2/1 ) for output port p4 6 /t7ioc 1 , 16-bit integrated-timer pulse unit (ipu), and general-purpose p4 5 /t6ioc 2 , input/output p4 4 /t6ioc 1 , p4 3 /t5ioc 2 , p4 2 /t5ioc 1 , p4 1 /t4ioc 2 , p4 0 /t4ioc 1 port 5 8-bit input/ p5 7 ?5 0 / input and output (t3ioc 2/1 , t2ioc 2/1 , t1ioc 4/3/2/1 ) for 16-bit output port t3ioc 2 , t3ioc 1 , integrated-timer pulse unit (ipu), and general-purpose input/output t2ioc 2 , t2ioc 1 , t1ioc 4 ?1ioc 1 port 6 5-bit input/ p6 4 /tclk 3 , clock input (tclk 3/2/1 ) for 16-bit integrated-timer pulse unit output port p6 3 /tclk 2 , (ipu), external interrupt input ( irq 3/2 ), pwm timer output (pw 3 ), p6 2 /tclk 1 , and general-purpose input/output p6 1 /irq 3 , p6 0 /irq 2 /pw 3 port 7 8-bit input/ p7 7 /sck 2 /pw 2 , input and output (sck 2/1 , txd 2/1 , rxd 2/1 ) for serial output port p7 6 /sck 1 /pw 1 , communication interfaces 1 and 2 (sci1/2), external interrupt p7 5 /rxd 2 , input ( irq 1/0 ), a/d converter trigger input ( adtrg ), pwm timer p7 4 /txd 2 , output (pw 2/1 ), and general-purpose input/output p7 3 /rxd 1 , p7 2 /txd 1 , p7 1 /irq 1 / adtrg, p7 0 /irq 0 port 8 4-bit input p8 3 ?8 0 / analog input for a/d converter (an 11 to an 8 ) and general- port an 11 ?n 8 purpose input port 9 8-bit input p9 7 ?9 0 / analog input for a/d converter (an 7 to an 0 ) and general-purpose port an 7 ?n 0 input expanded minimum expanded maximum modes modes
table 10-1 ports 1 to c, pin names, and functions in each mode (h8/539) (cont) 173 mode 7 modes modes (single- port description pins 1 and 6 mode 2 3 and 5 mode 4 chip mode) port a 7-bit input/ pa 6 /t3oc 2 / output from 16-bit integrated-timer pulse unit 16-bit output port back/txd 3 , (ipu), input and output (txd 3 , rxd 3 ) for serial integrated- pa 5 /t3oc 1 / communication interface 3 (sci3), general- timer pulse breq/rxd 3 , purpose input/output, and back , breq , and unit (ipu) pa 4 /wait wait input and output if enabled by settings in output, serial bus release control register (brcr), wait control communica- register (wcr), and port a control register tion interface (pacr) 3 (sci3) input and output (txd 3 , rxd 3 ), and general- purpose input/output (pa 4 : general- purpose input/output only) pa 3 /a 19 / output (t5oc 2/1 , page page page t5oc 2 /sck 3 , t4oc 2/1 ) from 16-bit address address address pa 2 /a 18 / integrated-timer pulse output output (a 19 output (a 19 t5oc 1 /pw 3 , unit (ipu), and general- (a 19 to a 16 ) to a 16 ), to a 16 ), pa 1 /a 17 / purpose input/output serial com- serial com- t4oc 2 /pw 2 , munication munication pa 0 /a 16 / interface interface t4oc 1 /pw 1 3 (sci3) 3 (sci3) input/output input/output (sck 3 ), (sck 3 ), output output (pw 1/2/3 ) (pw 1/2/3 ) from pwm from pwm timers timers (pw 1/2/3 ), (pw 1/2/3 ), and and general- general- purpose purpose input/output input/output port b 8-bit input/ pb 7 ?b 0 / address address address address general- output port a 15 ? 8 output output output output purpose (a 15 to a 0 )(a 15 to a 0 ) (a 15 to a 0 )(a 15 to a 0 ) input/output when when ddr = 1, ddr = 1, port c 8-bit input/ pc 7 ?c 0 / general- general- output port a 7 ? 0 purpose purpose input when input when ddr = 0 ddr = 0 expanded minimum expanded maximum modes modes
174 table 10-2 ports 1 to c, pin names, and functions in each mode (h8/538) mode 7 modes modes (single- port description pins 1 and 6 mode 2 3 and 5 mode 4 chip mode) port 1 8-bit input/ p1 7 ?1 0 / data bus (d 15 to d 8 ) general- output port d 15 ? 8 purpose input/output port 2 8-bit input/ p2 7 ?2 0 / data bus general- data bus data bus general- output port d 7 ? 0 (d 7 to d 0 ) purpose (d 7 to d 0 ) (d 7 to d 0 ) purpose input/ input/output output port 3 6-bit input/ p3 5 ?3 0 / output (t2oc 2/1 , t1oc 4/3/2/1 ) from 16-bit integrated-timer output port t2oc 2 , t2oc 1 , pulse unit (ipu), and general-purpose input/output t1oc 4 ?1oc 1 port 4 8-bit input/ p4 7 /t7ioc 2 , input and output (t7ioc 2/1 , t6ioc 2/1 , t5ioc 2/1 , t4ioc 2/1 ) for output port p4 6 /t7ioc 1 , 16-bit integrated-timer pulse unit (ipu), and general-purpose p4 5 /t6ioc 2 , input/output p4 4 /t6ioc 1 , p4 3 /t5ioc 2 , p4 2 /t5ioc 1 , p4 1 /t4ioc 2 , p4 0 /t4ioc 1 port 5 8-bit input/ p5 7 ?5 0 / input and output (t3ioc 2/1 , t2ioc 2/1 , t1ioc 4/3/2/1 ) for 16-bit output port t3ioc 2 , t3ioc 1 , integrated-timer pulse unit (ipu), and general-purpose input/output t2ioc 2 , t2ioc 1 , t1ioc 4 ?1ioc 1 port 6 5-bit input/ p6 4 /tclk 3 , clock input (tclk 3/2/1 ) for 16-bit integrated-timer pulse unit output port p6 3 /tclk 2 , (ipu), external interrupt input (irq 3/2 ), and general-purpose p6 2 /tclk 1 , input/output p6 1 /irq 3 , p6 0 /irq 2 port 7 8-bit input/ p7 7 /sck 2 , input and output (sck 1/2 , txd 1/2 , rxd 1/2 ) for serial output port p7 6 /sck 1 , communication interfaces 1 and 2 (sci1/2), external interrupt p7 5 /rxd 2 , input (irq 1/0 ), a/d converter trigger input (adtrg), and p7 4 /txd 2 , general-purpose input/output p7 3 /rxd 1 , p7 2 /txd 1 , p7 1 /irq 1 / adtrg, p7 0 /irq 0 port 8 4-bit input p8 3 ?8 0 / analog input for a/d converter (an 11 to an 8 ) and general- port an 11 ?n 8 purpose input port 9 8-bit input p9 7 ?9 0 / analog input for a/d converter (an 7 to an 0 ) and general-purpose port an 7 ?n 0 input expanded minimum expanded maximum modes modes
table 10-2 ports 1 to c, pin names, and functions in each mode (h8/538) (cont) 175 mode 7 modes modes (single- port description pins 1 and 6 mode 2 3 and 5 mode 4 chip mode) port a 7-bit input/ pa 6 /t3oc 2 / output from 16-bit integrated-timer pulse unit output port back, (ipu), general-purpose input/output, and back, pa 5 /t3oc 1 / breq, and wait input and output if enabled breq, by settings in bus release control register (brcr) pa 4 /wait and wait control register (wcr) pa 3 /a 19 /t5oc 2 , output (t5oc 2/1 , page page pa 2 /a 18 /t5oc 1 , t4oc 2/1 ) from 16-bit address address pa 1 /a 17 /t4oc 2 , integrated-timer pulse output (a 19 output (a 19 pa 0 /a 16 /t4oc 1 unit (ipu), and general- to a 16 ) to a 16 ) purpose input/output when ddr = 1, general- purpose input when ddr = 0 port b 8-bit input/ pb 7 ?b 0 / address address address address general- output port a 15 ? 8 output output output output purpose (a 15 to a 0 )(a 15 to a 0 ) (a 15 to a 0 )(a 15 to a 0 ) input/output when when ddr = 1, ddr = 1, port c 8-bit input/ pc 7 ?c 0 / general- general- output port a 7 ? 0 purpose purpose input when input when ddr = 0 ddr = 0 expanded minimum expanded maximum modes modes 16-bit integrated- timer pulse unit (ipu) output, and general- purpose input/output (pa 4 : general- purpose input/output only)
10.2 port 1 10.2.1 overview port 1 is an eight-bit general-purpose input/output port in mode 7. in modes 1 to 6, port 1 is a data bus (d 15 to d 8 ). pins in port 1 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. figure 10-1 summarizes the pin functions. figure 10-2 shows examples of output loads for port 1. figure 10-1 port 1 pin functions figure 10-2 examples of port 1 output loads port 1 p1 7 /d 15 p1 6 /d 14 p1 5 /d 13 p1 4 /d 12 p1 3 /d 11 p1 2 /d 10 p1 1 /d 9 p1 0 /d 8 (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port 1 2 k w port 1 176
10.2.2 register descriptions table 10-3 summarizes the registers of port 1. table 10-3 port 1 registers (1) port 1 data direction register: the port 1 data direction register (p1ddr) is an eight-bit register. each bit selects input or output for one pin in port 1. these input/output designations are valid only in mode 7. a pin in port 1 becomes an output pin if the corresponding p1ddr bit is set to 1, and an input pin if this bit is cleared to 0. p1ddr is a write-only register. all bits always return the value 1 when read. p1ddr is initialized to h'00 by a reset and in hardware standby mode. p1ddr is not initialized in software standby mode. (2) port 1 data register: the port 1 data register (p1dr) is an eight-bit register that stores data for pins p1 0 to p1 7 . p1dr is used only in mode 7. in modes 1 to 6, the bit values in p1dr cannot be modified and always read 1. when a bit in p1ddr is set to 1, the corresponding p1dr bit value is output at the corresponding pin. if port 1 is read the value in p1dr is returned, regardless of the actual state of the pin. address name abbreviation r/w initial value h'fe80 port 1 data direction register p1ddr w h'00 h'fe82 port 1 data register p1dr r/w h'00 bit initial value r/w 7 0 p1 7 ddr p1 3 ddr p1 6 ddr 543210 0000000 wwwwwwww 6 p1 5 ddr p1 4 ddr p1 2 ddr p1 1 ddr p1 0 ddr bit initial value r/w 7 0 p1 7 p1 3 p1 6 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 p1 5 p1 4 p1 2 p1 1 p1 0 177
when a bit in p1ddr is cleared to 0, it is possible to write to the corresponding p1dr bit but the value is not output at the pin. if p1dr is read the value at the pin is returned, regardless of the value written in p1dr. p1dr is initialized to h'00 by a reset and in hardware standby mode. p1dr is not initialized in software standby mode. 10.2.3 pin functions in each mode the functions of port 1 differ between the externally expanded modes (modes 1 to 6) and single- chip mode (mode 7). the pin functions in each mode are described below. (1) pin functions in externally expanded modes (modes 1 to 6): the settings in p1ddr are ignored. port 1 automatically becomes a bidirectional data bus. figure 10-3 shows the pin functions in modes 1 to 6. figure 10-3 pin functions in modes 1 to 6 (bidirectional data bus) port 1 d 15 (bidirectional data bus) d 14 (bidirectional data bus) d d 12 (bidirectional data bus) d 11 (bidirectional data bus) d 10 (bidirectional data bus) d 9 (bidirectional data bus) d 8 (bidirectional data bus) pin functions 13 178
(2) pin functions in single-chip mode (mode 7): port 1 consists of general-purpose input/output pins. input or output can be selected separately for each pin. a pin becomes an output pin if the corresponding p1ddr bit is set to 1 and an input pin if this bit is cleared to 0. figure 10-4 shows the pin functions in mode 7. figure 10-4 pin functions in mode 7 (3) software standby mode: transition to software standby does not change the pin functions in single-chip mode. in the externally expanded modes, port 1 is in the high-impedance state during software standby. port 1 p1 7 (input/output pin) p1 6 (input/output pin) p1 5 (input/output pin) p1 4 (input/output pin) p1 3 (input/output pin) p1 2 (input/output pin) p1 1 (input/output pin) p1 0 (input/output pin) pin functions 179
10.2.4 port 1 read/write operations p1dr and p1ddr have different read/write functions depending on whether port 1 is used as a data bus (d 15 to d 8 ) or for general-purpose input or output (p1 7 to p1 0 ). the operating states and functions of port 1 are described next. (1) data bus (modes 1 to 6): figure 10-5 shows a block diagram illustrating the data-bus function. table 10-4 indicates register read/write data. when port 1 operates as a data bus, the values in the port 1 data register (p1dr) have no effect on the bus lines. when read, p1dr returns all 1s. figure 10-5 data bus: d 15 to d 8 (modes 1 to 6) table 10-4 register read/write data (2) input port (mode 7): figure 10-6 shows a block diagram illustrating the general-purpose input function. table 10-5 indicates register read/write data. values written in the port 1 data register (p1dr) have no effect on general-purpose input lines. when read, p1dr returns the value at the pin. read write p1dr always 1 don? care p1dr write read v cc data bus internal data bus d 15 ? 8 180
figure 10-6 input port (mode 7) table 10-5 register read/write data (3) output port (mode 7): figure 10-7 shows a block diagram illustrating the general-purpose output function. table 10-6 indicates register read/write data. the value written in the port 1 data register (p1dr) is output at the pin. when read, p1dr returns the value written in p1dr. figure 10-7 output port (mode 7) table 10-6 register read/write data read write p1dr p1dr value value output at pin read/ write internal data bus p1dr p1 7 ?1 0 read write p1dr pin value don? care p1dr write read internal data bus p1 7 ?1 0 181
10.3 port 2 10.3.1 overview port 2 is an eight-bit general-purpose input/output port in modes 2 and 7. in modes 1, 3, 4, 5, and 6, port 2 is a data bus (d 7 to d 0 ). pins in port 2 can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. figure 10-8 summarizes the pin functions. figure 10-9 shows examples of output loads for port 2. figure 10-8 port 2 pin functions figure 10-9 examples of port 2 output loads (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port 2 2 k w port 2 port 2 p2 7 /d 7 p2 6 /d 6 p2 5 /d 5 p2 4 /d 4 p2 3 /d 3 p2 2 /d 2 p2 1 /d 1 p2 0 /d 0 182
10.3.2 register descriptions table 10-7 summarizes the registers of port 2. table 10-7 port 2 registers (1) port 2 data direction register: the port 2 data direction register (p2ddr) is an eight-bit register. each bit selects input or output for one pin in port 2. these input/output designations are valid only in modes 2 and 7. a pin in port 2 becomes an output pin if the corresponding p2ddr bit is set to 1, and an input pin if this bit is cleared to 0. p2ddr is a write-only register. all bits always return the value 1 when read. p2ddr is initialized to h'00 by a reset and in hardware standby mode. p2ddr is not initialized in software standby mode. (2) port 2 data register: the port 2 data register (p2dr) is an eight-bit register that stores data for pins p2 7 to p2 0 . p2dr is used only in modes 2 and 7. in modes 1, 3, 4, 5, and 6, the bit values in p2dr cannot be modified and always read 1. when a bit in p2ddr is set to 1, the corresponding p2dr bit value is output at the corresponding pin. if port 2 is read the value in p2dr is returned, regardless of the actual state of the pin. bit initial value r/w 7 0 p2 7 p2 3 p2 6 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 p2 5 p2 4 p2 2 p2 1 p2 0 bit initial value r/w 7 0 p2 7 ddr p2 3 ddr p2 6 ddr 543210 0000000 wwwwwwww 6 p2 5 ddr p2 4 ddr p2 2 ddr p2 1 ddr p2 0 ddr address name abbreviation r/w initial value h'fe81 port 2 data direction register p2ddr w h'00 h'fe83 port 2 data register p2dr r/w h'00 183
when a bit in p2ddr is cleared to 0, it is possible to write to the corresponding p2dr bit but the value is not output at the pin. if p2dr is read the value at the pin is returned, regardless of the value written in p2dr. p2dr is initialized to h'00 by a reset and in hardware standby mode. p2dr is not initialized in software standby mode. 10.3.3 pin functions in each mode the functions of port 2 differ between modes 1, 3, 4, 5, and 6 on one hand, and modes 2 and 7 on the other hand. the pin functions in each mode group are described below. (1) pin functions in modes 1, 3, 4, 5, and 6: the settings in p2ddr are ignored. port 2 automatically becomes a bidirectional data bus. figure 10-10 shows the pin functions in modes 1, 3, 4, 5, and 6. figure 10-10 pin functions in modes 1, 3, 4, 5, and 6 (2) pin functions in modes 2 and 7: port 2 consists of general-purpose input/output pins. input or output can be selected separately for each pin. a pin becomes an output pin if the corresponding p2ddr bit is set to 1 and an input pin if this bit is cleared to 0. figure 10-11 shows the pin functions in modes 2 and 7. port 2 d 7 (bidirectional data bus) d 6 (bidirectional data bus) d 5 (bidirectional data bus) d 4 (bidirectional data bus) d 3 (bidirectional data bus) d 2 (bidirectional data bus) d 1 (bidirectional data bus) d 0 (bidirectional data bus) pin functions 184
figure 10-11 pin functions in modes 2 and 7 (3) software standby mode: transition to software standby does not change the pin functions in single-chip mode. in the externally expanded modes, port 2 is in the high-impedance state during software standby. 10.3.4 port 2 read/write operations p2dr and p2ddr have different read/write functions depending on whether port 2 is used as a data bus (d 7 to d 0 ) or for general-purpose input or output (p2 7 to p2 0 ). the operating states and functions of port 2 are described next. (1) data bus (all pins: modes 1, 3, 4, 5, and 6): figure 10-12 shows a block diagram illustrating the data-bus function. table 10-8 indicates register read/write data. when port 2 operates as a data bus, the values in the port 2 data register (p2dr) have no effect on the bus lines. when read, p2dr returns all 1s. figure 10-12 data bus: d 7 to d 0 (modes 1, 3, 4, 5, and 6) port 2 p2 7 (input/output pin) p2 6 (input/output pin) p2 5 (input/output pin) p2 4 (input/output pin) p2 3 (input/output pin) p2 2 (input/output pin) p2 1 (input/output pin) p2 0 (input/output pin) pin functions p2dr write read v cc data bus internal data bus d 7 ? 0 185
table 10-8 register read/write data (2) input port (modes 2 and 7): figure 10-13 shows a block diagram illustrating the general- purpose input function. table 10-9 indicates register read/write data. values written in the port 2 data register (p2dr) have no effect on general-purpose input lines. when read, p2dr returns the value at the pin. figure 10-13 input port (modes 2 and 7) table 10-9 register read/write data (3) output port (modes 2 and 7): figure 10-14 shows a block diagram illustrating the general- purpose output function. table 10-10 indicates register read/write data. the value written in the port 2 data register (p2dr) is output at the pin. when read, p2dr returns the value written in p2dr. figure 10-14 output port (modes 2 and 7) p2dr write read internal data bus p2 7 ?2 0 read write p2dr always 1 don? care read write p2dr pin value don? care read/ write internal data bus p2dr p2 7 ?2 0 186
table 10-10 register read/write data 10.4 port 3 10.4.1 overview port 3 is a six-bit input/output port that is multiplexed with output compare pins (t2oc 2 , t2oc 1 , t1oc 4 to t1oc 1 ) of the 16-bit integrated-timer pulse unit (ipu). figure 10-15 summarizes the pin functions. pins in port 3 can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair or led (with 10-ma current sink). figure 10-15 port 3 pin functions figure 10-16 shows examples of output loads for port 3. read write p2dr p2dr value value output at pin port 3 p3 5 (input/output)/t2oc 2 (output) p3 4 (input/output)/t2oc 1 (output) p3 3 (input/output)/t1oc 4 (output) p3 2 (input/output)/t1oc 3 (output) p3 1 (input/output)/t1oc 2 (output) p3 0 (input/output)/t1oc 1 (output) 187
figure 10-16 examples of port 3 output loads 10.4.2 register descriptions table 10-11 summarizes the registers of port 3. table 10-11 port 3 registers (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port 3 2 k w port 3 v cc led port 3 600 w (3) led driving circuit address name abbreviation r/w initial value h'fe84 port 3 data direction register p3ddr w h'c0 h'fe86 port 3 data register p3dr r/w h'c0 188
(1) port 3 data direction register: the port 3 data direction register (p3ddr) is an eight-bit register. each bit selects input or output for one pin. a pin in port 3 becomes an output pin if the corresponding p3ddr bit is set to 1, and an input pin if this bit is cleared to 0. p3ddr is a write-only register. all bits always return the value 1 when read. p3ddr is initialized to h'c0 by a reset and in hardware standby mode. p3ddr is not initialized in software standby mode. (2) port 3 data register: the port 3 data register (p3dr) is an eight-bit register that stores data for pins p3 5 to p3 0 . when a bit in p3ddr is set to 1, the corresponding p3dr bit value is output at the corresponding pin. if port 3 is read the value in p3dr is returned, regardless of the actual state of the pin. when a bit in p3ddr is cleared to 0, it is possible to write to the corresponding p3dr bit but the value is not output at the pin. if p3dr is read the value at the pin is returned, regardless of the value written in p3dr. p3dr is initialized to h'c0 by a reset and in hardware standby mode. p3dr is not initialized in software standby mode. 10.4.3 pin functions in each mode in all modes port 3 can be used for general-purpose input or output, or for the output compare function of the 16-bit integrated-timer pulse unit (ipu). bit initial value r/w 7 1 ?3 3 ddr 543210 1000000 wwwwww 6 p3 5 ddr p3 4 ddr p3 2 ddr p3 1 ddr p3 0 ddr bit initial value r/w 7 1 ?3 3 543210 1000000 r/w r/w r/w r/w r/w r/w 6 p3 5 p3 4 p3 2 p3 1 p3 0 189
(1) pin functions in modes 1 to 7: when a pin is used for ipu output, the setting in p3ddr is ignored. t1oc 1 to t1oc 4 , t2oc 1 , or t2oc 2 output is selected automatically. for methods of selecting pin functions, see appendix d ?in function selection. (2) software standby mode: transition to software standby mode initializes the on-chip supporting modules, so port 3 becomes an input or output port according to p3ddr and p3dr. 10.4.4 port 3 read/write operations p3dr and p3ddr have different read/write functions depending on whether port 3 is used for the output compare function (t1oc 1 to t1oc 4 , t2oc 1 , t2oc 2 ) of the 16-bit integrated-timer pulse unit (ipu) or general-purpose input or output (p3 5 to p3 0 ). the operating states and functions of port 3 are described next. (1) input port (modes 1 to 7): figure 10-17 shows a block diagram illustrating the general- purpose input function. table 10-12 indicates register read/write data. values written in the port 3 data register (p3dr) have no effect on general-purpose input lines. when read, p3dr returns the value at the pin. figure 10-17 input port (modes 1 to 7) table 10-12 register read/write data (2) output port (modes 1 to 7): figure 10-18 shows a block diagram illustrating the general- purpose output function. table 10-13 indicates register read/write data. the value written in the port 3 data register (p3dr) is output at the pin. when read, p3dr returns the value written in p3dr. p3dr write read internal data bus p3 5 ?3 0 read write p3dr pin value don? care 190
figure 10-18 output port (modes 1 to 7) table 10-13 register read/write data (3) timer output pins (modes 1 to 7): figure 10-19 shows a block diagram illustrating the timer output function. table 10-14 indicates register read/write data. when a pin in port 3 is used for timer output, the setting in the port 3 data direction register (p3ddr) is ignored. the value in the port 3 data register (p3dr) has no effect on the timer output. when read, p3dr returns the timer output level (t1oc 1 to t1oc 4 , t2oc 1 , or t2oc 2 ). figure 10-19 timer output pins (modes 1 to 7) table 10-14 register read/write data read/ write internal data bus p3dr p3 5 ?3 0 read write p3dr p3dr value value output at pin p3dr write read internal data bus t1oc 1? t2oc 1, 2 timer output read write p3dr pin value don? care 191
10.5 port 4 10.5.1 overview port 4 is an eight-bit input/output port that is multiplexed with output compare and input capture pins (t7ioc 2/1 , t6ioc 2/1 , t5ioc 2/1 , t4ioc 2/1 ) of the 16-bit integrated-timer pulse unit (ipu). figure 10-20 summarizes the pin functions. pins in port 4 can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. p4 7 to p4 0 have schmitt-trigger input circuits. figure 10-20 port 4 pin functions figure 10-21 shows examples of output loads for port 4. figure 10-21 examples of port 4 output loads port 4 p4 7 (input/output)/t7ioc 2 (input/output) p4 6 (input/output)/t7ioc 1 (input/output) p4 5 (input/output)/t6ioc 2 (input/output) p4 4 (input/output)/t6ioc 1 (input/output) p4 3 (input/output)/t5ioc 2 (input/output) p4 2 (input/output)/t5ioc 1 (input/output) p4 1 (input/output)/t4ioc 2 (input/output) p4 0 (input/output)/t4ioc 1 (input/output) (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port 4 2 k w port 4 192
10.5.2 register descriptions table 10-15 summarizes the registers of port 4. table 10-15 port 4 registers (1) port 4 data direction register: the port 4 data direction register (p4ddr) is an eight-bit register. each bit selects input or output for one pin. a pin in port 4 becomes an output pin if the corresponding p4ddr bit is set to 1, and an input pin if this bit is cleared to 0. p4ddr is a write-only register. all bits always return the value 1 when read. p4ddr is initialized to h'00 by a reset and in hardware standby mode. p4ddr is not initialized in software standby mode. (2) port 4 data register: the port 4 data register (p4dr) is an eight-bit register that stores data for pins p4 7 to p4 0 . when a bit in p4ddr is set to 1, the corresponding p4dr bit value is output at the corresponding pin. if port 4 is read the value in p4dr is returned, regardless of the actual state of the pin. when a bit in p4ddr is cleared to 0, it is possible to write to the corresponding p4dr bit but the value is not output at the pin. if p4dr is read the value at the pin is returned, regardless of the value written in p4dr. address name abbreviation r/w initial value h'fe85 port 4 data direction register p4ddr w h'00 h'fe87 port 4 data register p4dr r/w h'00 bit initial value r/w 7 0 p4 7 ddr p4 3 ddr p4 6 ddr 543210 0000000 wwwwwwww 6 p4 5 ddr p4 4 ddr p4 2 ddr p4 1 ddr p4 0 ddr bit initial value r/w 7 0 p4 7 p4 3 p4 6 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 p4 5 p4 4 p4 2 p4 1 p4 0 193
p4dr is initialized to h'00 by a reset and in hardware standby mode. p4dr is not initialized in software standby mode. 10.5.3 pin functions in each mode in all modes port 4 can be used for general-purpose input or output, or for the input capture and output compare functions of the 16-bit integrated-timer pulse unit (ipu). (1) pin functions in modes 1 to 7: when a pin is used for the ipu output-compare function, the setting in p4ddr has no effect. t4ioc 1 , t4ioc 2 , t5ioc 1 , t5ioc 2 , t6ioc 1 , t6ioc 2 , t7ioc 1 , or t7ioc 2 output is selected automatically. when the ipu input capture function is selected, the p4ddr setting is valid and the pin can simultaneously function as a general-purpose input or output port. for methods of selecting pin functions, see appendix d ?in function selection. (2) software standby mode: transition to software standby mode initializes the on-chip supporting modules, so port 4 becomes an input or output port according to p4ddr and p4dr. 10.5.4 port 4 read/write operations p4dr and p4ddr have different read/write functions depending on whether port 4 is used for the input capture or output compare function (t4ioc 1/2 , t5ioc 1/2 , t6ioc 1/2 , t7ioc 1/2 ) of the 16-bit integrated-timer pulse unit (ipu) or for general-purpose input or output (p4 7 to p4 0 ). the operating states and functions of port 4 are described next. (1) input port (modes 1 to 7): figure 10-22 shows a block diagram illustrating the general- purpose input function. table 10-16 indicates register read/write data. values written in the port 4 data register (p4dr) have no effect on general-purpose input lines. when read, p4dr returns the value at the pin. figure 10-22 input port (modes 1 to 7) p4dr write read internal data bus p4 7 ?4 0 194
table 10-16 register read/write data (2) output port (modes 1 to 7): figure 10-23 shows a block diagram illustrating the general- purpose output function. table 10-17 indicates register read/write data. the value written in the port 4 data register (p4dr) is output at the pin. when read, p4dr returns the value written in p4dr. figure 10-23 output port (modes 1 to 7) table 10-17 register read/write data (3) timer output pins (modes 1 to 7): figure 10-24 shows a block diagram illustrating the output compare function. table 10-18 indicates register read/write data. when a pin in port 4 is used for output compare, the value in the port 4 data register (p4dr) has no effect on the timer output. when read, p4dr returns the timer output level (t4ioc 1 , t4ioc 2 , t5ioc 1 , t5ioc 2 , t6ioc 1 , t6ioc 2 , t7ioc 1 , or t7ioc 2 ). figure 10-24 output compare pins (modes 1 to 7) read write p4dr pin value don? care read/ write internal data bus p4dr p4 7 ?4 0 read write p4dr p4dr value value output at pin p4dr write read internal data bus t4ioc 1, 2 timer output t5ioc 1, 2 t6ioc 1, 2 t7ioc 1, 2 195
table 10-18 register read/write data (4) timer input combined with general-purpose output (modes 1 to 7): figure 10-25 shows a block diagram illustrating the input capture function when combined with general-purpose output. table 10-19 indicates register read/write data. an input capture pin can also function as an output port, in which case the output value is input to the timer. figure 10-25 input capture combined with general-purpose output (modes 1 to 7) table 10-19 register read/write data (5) timer input combined with general-purpose input (modes 1 to 7): figure 10-26 shows a block diagram illustrating the input capture function when combined with general-purpose input. table 10-20 indicates register read/write data. an input capture pin can also be read as an input port, to monitor the timer input level at t4ioc 1 , t4ioc 2 , t5ioc 1 , t5ioc 2 , t6ioc 1 , t6ioc 2 , t7ioc 1 , or t7ioc 2 . figure 10-26 input capture combined with general-purpose input (modes 1 to 7) read write p4dr pin value don? care read/ write p4dr timer input t4ioc 1, 2 t5ioc 1, 2 t6ioc 1, 2 t7ioc 1, 2 internal data bus read write p4dr p4dr value value output at pin p4dr write read internal data bus t4ioc 1, 2 timer input t5ioc 1, 2 t6ioc 1, 2 t7ioc 1, 2 196
table 10-20 register read/write data 10.6 port 5 10.6.1 overview port 5 is an eight-bit input/output port that is multiplexed with output compare and input capture pins (t3ioc 2/1 , t2ioc 2/1 , t1ioc 4/3/2/1 ) of the 16-bit integrated-timer pulse unit (ipu). figure 10-27 summarizes the pin functions. pins in port 5 can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair or led (with 10-ma current sink). inputs are schmitt-triggered. figure 10-27 port 5 pin functions figure 10-28 shows examples of output loads for port 5. read write p4dr timer input don? care port 5 p5 7 (input/output)/t3ioc 2 (input/output) p5 6 (input/output)/t3ioc 1 (input/output) p5 5 (input/output)/t2ioc 2 (input/output) p5 4 (input/output)/t2ioc 1 (input/output) p5 3 (input/output)/t1ioc 4 (input/output) p5 2 (input/output)/t1ioc 3 (input/output) p5 1 (input/output)/t1ioc 2 (input/output) p5 0 (input/output)/t1ioc 1 (input/output) 197
figure 10-28 examples of port 5 output loads 10.6.2 register descriptions table 10-21 summarizes the registers of port 5. table 10-21 port 5 registers (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port 5 2 k w port 5 v cc led port 5 600 w (3) led driving circuit address name abbreviation r/w initial value h'fe88 port 5 data direction register p5ddr w h'00 h'fe8a port 5 data register p5dr r/w h'00 198
(1) port 5 data direction register: the port 5 data direction register (p5ddr) is an eight-bit register. each bit selects input or output for one pin. a pin in port 5 becomes an output pin if the corresponding p5ddr bit is set to 1, and an input pin if this bit is cleared to 0. p5ddr is a write-only register. all bits always return the value 1 when read. p5ddr is initialized to h'00 by a reset and in hardware standby mode. p5ddr is not initialized in software standby mode. (2) port 5 data register: the port 5 data register (p5dr) is an eight-bit register that stores data for pins p5 7 to p5 0 . when a bit in p5ddr is set to 1, the corresponding p5dr bit value is output at the corresponding pin. if port 5 is read the value in p5dr is returned, regardless of the actual state of the pin. when a bit in p5ddr is cleared to 0, it is possible to write to the corresponding p5dr bit but the value is not output at the pin. if p5dr is read the value at the pin is returned, regardless of the value written in p5dr. p5dr is initialized to h'00 by a reset and in hardware standby mode. p5dr is not initialized in software standby mode. 10.6.3 pin functions in each mode in all modes port 5 can be used for general-purpose input or output, or for the input capture and output compare functions of the 16-bit integrated-timer pulse unit (ipu). bit initial value r/w 7 0 p5 7 ddr p5 3 ddr p5 6 ddr 543210 0000000 wwwwwwww 6 p5 5 ddr p5 4 ddr p5 2 ddr p5 1 ddr p5 0 ddr bit initial value r/w 7 0 p5 7 p5 3 p5 6 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 p5 5 p5 4 p5 2 p5 1 p5 0 199
(1) pin functions in modes 1 to 7: when a pin is used for the ipu output compare function, the setting in p5ddr is ignored. t1ioc 1 to t1ioc 4 , t2ioc 1 , t2ioc 2 , t3ioc 1 , or t3ioc 2 output is selected automatically. when the ipu input capture function is selected, the p5ddr setting is valid and the pin can simultaneously function as a general-purpose input or output port. for methods of selecting pin functions, see appendix d ?in function selection. (2) software standby mode: transition to software standby mode initializes the on-chip supporting modules, so port 5 becomes an input or output port according to p5ddr and p5dr. 10.6.4 port 5 read/write operations p5dr and p5ddr have different read/write functions depending on whether port 5 is used for the input capture or output compare function (t1ioc 1/2/3/4 , t2ioc 1/2 , t3ioc 1/2 ) of the 16-bit integrated-timer pulse unit (ipu) or for general-purpose input or output. the operating states and functions of port 5 are described next. (1) input port (modes 1 to 7): figure 10-29 shows a block diagram illustrating the general- purpose input function. table 10-22 indicates register read/write data. values written in the port 5 data register (p5dr) have no effect on general-purpose input lines. when read, p5dr returns the value at the pin. figure 10-29 input port (modes 1 to 7) table 10-22 register read/write data (2) output port (modes 1 to 7): figure 10-30 shows a block diagram illustrating the general- purpose output function. table 10-23 indicates register read/write data. the value written in the port 5 data register (p5dr) is output at the pin. when read, p5dr returns the value written in p5dr. p5dr write read internal data bus p5 7 ?5 0 read write p5dr pin value don? care 200
figure 10-30 output port (modes 1 to 7) table 10-23 register read/write data (3) timer output pins (modes 1 to 7): figure 10-31 shows a block diagram illustrating the output compare function. table 10-24 indicates register read/write data. when a pin in port 5 is used for output compare, the value in the port 5 data register (p5dr) has no effect on the timer output. p5dr can be read to monitor the timer output level (t1ioc 1 to t1ioc 4 , t2ioc 1 , t2ioc 2 , t3ioc 1 , t3ioc 2 ). figure 10-31 output compare pins (modes 1 to 7) table 10-24 register read/write data read/ write internal data bus p5dr p5 7 ?5 0 read write p5dr p5dr value value output at pin p5dr write read internal data bus t1ioc 1? timer output t2ioc 1, 2 t3ioc 1, 2 read write p5dr pin value don? care 201
(4) timer input combined with general-purpose output (modes 1 to 7): figure 10-32 shows a block diagram illustrating the input capture function when combined with general-purpose output. table 10-25 indicates register read/write data. an input capture pin can also function as an output port, in which case the output value is input to the timer. figure 10-32 input capture combined with general-purpose output (modes 1 to 7) table 10-25 register read/write data (5) timer input combined with general-purpose input (modes 1 to 7): figure 10-33 shows a block diagram illustrating the input capture function when combined with general-purpose input. table 10-26 indicates register read/write data. an input capture pin can also be read as an input port, to monitor the timer input level at t1ioc 1 to t1ioc 4 , t2ioc 1 , t2ioc 2 , t3ioc 1 , or t3ioc 2 . figure 10-33 input capture combined with general-purpose input (modes 1 to 7) table 10-26 register read/write data read/ write p5dr timer input t1ioc 1? t2ioc 1, 2 t3ioc 1, 2 internal data bus read write p5dr p5dr value timer input p5dr write read internal data bus t1ioc 1? timer input t2ioc 1, 2 t3ioc 1, 2 read write p5dr pin value don? care 202
10.7 port 6 10.7.1 overview port 6 is a five-bit input/output port that is multiplexed with the external clock pins (tclk 3/2/1 ) of the 16-bit integrated-timer pulse unit (ipu), with external interrupt pins (irq 3 and irq 2 ), and with a pwm timer output pin (pw 3 ). figure 10-34 (a) and (b) summarizes the pin functions. pins in port 6 can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. the h8/538 does not have a pwm timer output pin function. figure 10-34 (a) port 6 pin functions (h8/538) figure 10-34 (b) port 6 pin functions (h8/539) port 6 p6 4 (input/output)/tclk 3 (input) p6 3 (input/output)/tclk 2 (input) p6 2 (input/output)/tclk 1 (input) p6 1 (input/output)/irq 3 (input) p6 0 (input/output)/irq 2 (input) port 6 p6 4 (input/output)/tclk 3 (input) p6 3 (input/output)/tclk 2 (input) p6 2 (input/output)/tclk 1 (input) p6 1 (input/output)/irq 3 (input) p6 0 (input/output)/irq 2 (input)/pw 3 (output) 203
figure 10-35 shows examples of output loads for port 6. figure 10-35 examples of port 6 output loads 10.7.2 register descriptions table 10-27 summarizes the registers of port 6. table 10-27 port 6 registers address name abbreviation r/w initial value h'fe89 port 6 data direction register p6ddr w h'e0 h'fe8b port 6 data register p6dr r/w h'e0 h'fedb port 6/7 control register * p67cr r/w h'3e note: * p67cr is not present in the h8/538. (1) port 6 data direction register: the port 6 data direction register (p6ddr) is an eight-bit register. each bit selects input or output for one pin. a pin in port 6 becomes an output pin if the corresponding p6ddr bit is set to 1, and an input pin if this bit is cleared to 0. p6ddr is a write-only register. all bits always return the value 1 when read. 204 (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port 6 2 k w port 6 bit i nitial value r /w 7 1 ?6 3 ddr 543210 1100000 ww www 6 ?6 4 ddr p6 2 ddr p6 1 ddr p6 0 ddr
p6ddr is initialized to h'e0 by a reset and in hardware standby mode. p6ddr is not initialized in software standby mode. (2) port 6 data register: the port 6 data register (p6dr) is an eight-bit register that stores data for pins p6 4 to p6 0 . when a bit in p6ddr is set to 1, the corresponding p6dr bit value is output at the corresponding pin. when a bit in p6ddr is cleared to 0, it is possible to write to the corresponding p6dr bit but the value is not output at the pin. if p6dr is read the value at the pin is returned, regardless of the value written in p6dr. p6dr is initialized to h'e0 by a reset and in hardware standby mode. p6dr is not initialized in software standby mode. (3) port 6/7 control register: the port 6/7 control register (p67cr) is an eight-bit register that controls the functions of pin p6 0 in port 6 and pins p7 7 and p7 6 in port 7. p67cr is present only in the h8/539. it is not present in the h8/538. bits 7 and 6?w 2 enable and pw 1 enable (pw2e, pw1e): these bits control the pwm output function of pins p7 7 /sck 2 /pw 2 and p7 6 /sck 1 /pw 1 in port 7. when bits pw2e and pw1e are set to 1, these pins can be used for pw 2 and pw 1 output and cannot be used for sck 2 and sck 1 output. bit 0?w 3 enable (pw3e): controls the pwm output function of pin p6 0 /irq 2 /pw 3 in port 6. when bit pw3e is set to 1, this pin can be used for pw 3 output. 205 bit initial value r/w 7 1 ?6 3 543210 1100000 r/w r/w r/w r/w r/w 6 ?6 4 p6 2 p6 1 p6 0 bit initial value r/w 7 0 pw2e pw1e 543210 0111110 r/w r/w r r r r r r/w 6 pw3e
10.7.3 pin functions in each mode (1) pin functions in modes 1 to 7: when a pin is used for ipu external clock input (tclk 3/2/1 ) or external interrupt input (irq 3/2 ), it can simultaneously function as a general-purpose input or output port. when a pin is used for pwm timer output (pw 3 ), the p6ddr setting is disregarded and the pw 3 function is selected. for methods of selecting pin functions, see appendix d ?in function selection.?the pwm timer output pin function is not present in the h8/538. (2) software standby mode: transition to software standby mode initializes the on-chip supporting modules, so port 6 becomes an input or output port according to p6ddr and p6dr. 10.7.4 port 6 read/write operations p6dr and p6ddr have different read/write functions depending on whether port 6 is used for external clock input (tclk 3/2/1 ) to the 16-bit integrated-timer pulse unit (ipu), external interrupt input (irq 3/2 ), pwm timer output (pw 3 ), or general-purpose input or output (p6 4 to p6 0 ). the operating states and functions of port 6 are described next. (1) input port (modes 1 to 7): figure 10-36 shows a block diagram illustrating the general- purpose input function. table 10-28 indicates register read/write data. values written in the port 6 data register (p6dr) have no effect on general-purpose input lines. when read, p6dr returns the value at the pin. figure 10-36 input port (modes 1 to 7) table 10-28 register read/write data read write p6dr pin value don? care 206 p6dr write read internal data bus p6 4 ?6 0
(2) output port (modes 1 to 7): figure 10-37 shows a block diagram illustrating the general- purpose output function. table 10-29 indicates register read/write data. the value written in the port 6 data register (p6dr) is output at the pin. when read, p6dr returns the value written in p6dr. figure 10-37 output port (modes 1 to 7) table 10-29 register read/write data (3) irq 3 or irq 2 input combined with general-purpose output (p6 1 , p6 0 : modes 1 to 7): figure 10-38 shows a block diagram illustrating the irq 3 and irq 2 input function of p6 1 and p6 0 when combined with general-purpose output. table 10-30 indicates register read/write data. when p6 1 and p6 0 are used for irq 3 and irq 2 input they can also function as general-purpose output ports. if the general-purpose output function is used, however, output of a falling edge will cause an interrupt. figure 10-38 irq 3 or irq 2 input combined with general-purpose output (modes 1 to 7) read/ write internal data bus p6dr p6 4 ?6 0 read write p6dr p6dr value value output at pin read/ write p6dr irq3 or irq2 input irq 2 , irq 3 internal data bus 207
table 10-30 register read/write data (4) irq 3 or irq 2 input combined with general-purpose input (p6 1 , p6 0 : modes 1 to 7): figure 10-39 shows a block diagram illustrating the irq 3 and irq 2 input function when combined with general-purpose input. table 10-31 indicates register read/write data. when p6 1 and p6 0 are used for irq 3 and irq 2 input they can also be read as general-purpose input ports, to monitor the input level at irq 3 or irq 2 . figure 10-39 irq 3 or irq 2 input combined with general-purpose input (modes 1 to 7) table 10-31 register read/write data (5) timer clock input combined with general-purpose output (p6 4 to p6 2 : modes 1 to 7): figure 10-40 shows a block diagram illustrating the tclk 3 to tclk 1 input function of p6 4 to p6 2 when combined with general-purpose output. table 10-32 indicates register read/write data. when p6 4 to p6 2 are used for tclk 3 , tclk 2 , and tclk 1 input they can also function as general-purpose output ports. read write p6dr p6dr value value output at pin p6dr write read internal data bus irq 2 , irq 3 irq3 or irq2 input read write p6dr pin value don? care 208
figure 10-40 tclk 3 to tclk 1 input combined with general-purpose output (modes 1 to 7) table 10-32 register read/write data (6) timer clock input combined with general-purpose input (p6 4 to p6 2 : modes 1 to 7): figure 10-41 shows a block diagram illustrating the tclk 3 to tclk 1 input function of p6 4 to p6 2 when combined with general-purpose input. table 10-33 indicates register read/write data. when p6 4 to p6 2 are used for tclk 3 , tclk 2 , and tclk 1 input they can also be read as general- purpose input ports, to monitor the input level at tclk 3 to tclk 1 . figure 10-41 tclk 3 to tclk 1 input combined with general-purpose input (modes 1 to 7) table 10-33 register read/write data read/ write p6dr tclk 3 to tclk 1 input tclk 3? internal data bus read write p6dr p6dr value value output at pin p6dr write read internal data bus tclk 3? tclk 3 to tclk 1 input read write p6dr pin value don? care 209
(7) pw 3 output combined with general-purpose input (p6 0 : modes 1 to 7, h8/539 only): figure 10-42 shows a block diagram illustrating the pw 3 output function of p6 0 when combined with general-purpose input. table 10-34 indicates register read/write data. when p6 0 is used for pw 3 output it can also be read as a general-purpose input port, to monitor the state of the pw 3 pin. figure 10-42 pw 3 output combined with general-purpose input (modes 1 to 7) table 10-34 register read/write data read write p6dr pin value don? care p6dr write read internal data bus pw3 pw 3 output 210
10.8 port 7 10.8.1 overview port 7 is an eight-bit input/output port that is multiplexed with the serial clock input/output pins (sck 2 and sck 1 ), transmit data output pins (txd 2 and txd 1 ), and receive data input pins (rxd 2 and rxd 1 ) of the serial communication interface (sci), with pwm timer output pins (pw 1 and pw 2 ), with external interrupt pins (irq 1 and irq 0 ), and with the external trigger pin ( adtrg ) of the a/d converter. figure 10-43 (a) and (b) summarizes the pin functions. pins in port 7 can drive one ttl load and a 30-pf capacitive load. they can also drive a darlington transistor pair. the h8/538 does not have pwm timer output pin functions. figure 10-43 (a) port 7 pin functions (h8/538) figure 10-43 (b) port 7 pin functions (h8/539) port 7 p7 7 (input/output)/sck 2 (input/output) p7 6 (input/output)/sck 1 (input/output) p7 5 (input/output)/rxd 2 (input) p7 4 (input/output)/txd 2 (output) p7 3 (input/output)/rxd 1 (input) p7 2 (input/output)/txd 1 (output) p7 1 (input/output)/irq 1 (input)/adtrg (input) p7 0 (input/output)/irq 0 (input) port 7 p7 7 (input/output)/sck 2 (input/output)/pw 2 (output) p7 6 (input/output)/sck 1 (input/output)/pw 1 (output) p7 5 (input/output)/rxd 2 (input) p7 4 (input/output)/txd 2 (output) p7 3 (input/output)/rxd 1 (input) p7 2 (input/output)/txd 1 (output) p7 1 (input/output)/irq 1 (input)/adtrg (input) p7 0 (input/output)/irq 0 (input) 211
figure 10-44 shows examples of output loads for port 7. figure 10-44 examples of port 7 output loads 10.8.2 register descriptions table 10-35 summarizes the registers of port 7. table 10-35 port 7 registers address name abbreviation r/w initial value h'fe8c port 7 data direction register p7ddr w h'00 h'fe8e port 7 data register p7dr r/w h'00 h'fede port 6/7 control register * p67cr r/w h'3e note: * p67cr is not present in the h8/538. (1) port 7 data direction register: the port 7 data direction register (p7ddr) is an eight-bit register. each bit selects input or output for one pin. a pin in port 7 becomes an output pin if the corresponding p7ddr bit is set to 1, and an input pin if this bit is cleared to 0. p7ddr is a write-only register. all bits always return the value 1 when read. p7ddr is initialized to h'00 by a reset and in hardware standby mode. p7ddr is not initialized in software standby mode. bit initial value r/w 7 0 p7 7 ddr p7 3 ddr p7 6 ddr 543210 0000000 wwwwwwww 6 p7 5 ddr p7 4 ddr p7 2 ddr p7 1 ddr p7 0 ddr 212 (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port 7 2 k w port 7
(2) port 7 data register: the port 7 data register (p7dr) is an eight-bit register that stores data for pins p7 7 to p7 0 . when a bit in p7ddr is set to 1, the corresponding p7dr bit value is output at the corresponding pin. if port 7 is read the value in p7dr is returned, regardless of the actual state of the pin. when a bit in p7ddr is cleared to 0, it is possible to write to the corresponding p7dr bit but the value is not output at the pin. if p7dr is read the value at the pin is returned, regardless of the value written in p7dr. p7dr is initialized to h'00 by a reset and in hardware standby mode. p7dr is not initialized in software standby mode. (3) port 6/7 control register: the port 6/7 control register (p67cr) is an eight-bit register that controls the functions of pin p6 0 in port 6 and pins p7 7 and p7 6 in port 7. p67cr is present only in the h8/539. it is not present in the h8/538. bits 7 and 6?w 2 enable and pw 1 enable (pw2e, pw1e): these bits control the pwm output function of pins p7 7 /sck 2 /pw 2 and p7 6 /sck 1 /pw 1 in port 7. when bits pw2e and pw1e are set to 1, these pins can be used for pw 2 and pw 1 output and cannot be used for sck 2 and sck 1 output. bit 0?w 3 enable (pw3e): controls the pwm output function of pin p6 0 /irq 2 /pw 3 in port 6. when bit pw3e is set to 1, this pin can be used for pw 3 output. 213 bit initial value r/w 7 0 p7 7 p7 3 p7 6 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 p7 5 p7 4 p7 2 p7 1 p7 0 bit initial value r/w 7 0 pw2e pw1e 543210 0111110 r/w r/w r r r r r r/w 6 pw3e
10.8.3 pin functions in each mode (1) pin functions in modes 1 to 7: when a pin is used for input or output by the serial communication interface (sci) or a pwm timer, the p7ddr setting is disregarded and the pin is used for serial clock input or output (sck 2/1 ), transmit data output (txd 2/1 ), receive data input (rxd 2/1 ), or pwm timer output (pw 1/2 ). when p7 1 and p7 0 are used for external interrupt input (irq 1 and irq 0 ), they can simultaneously function as general-purpose input or output ports. p7 1 can also function as the external trigger signal ( adtrg ) for the a/d converter. for methods of selecting pin functions, see appendix d ?in function selection. (2) software standby mode: transition to software standby mode initializes the on-chip supporting modules, so port 7 becomes an input or output port according to p7ddr and p7dr. 10.8.4 port 7 read/write operations p7dr and p7ddr have different read/write functions depending on whether port 7 is used for output of transmit data (txd 1/2 ), input of receive data (rxd 1/2 ), input or output of serial clocks (sck 1/2 ) for the serial communication interface, pwm timer output (pw 2/1 ), external interrupt input (irq 1/0 ), or general-purpose input or output. the operating states and functions of port 7 are described next. (1) input port (modes 1 to 7): figure 10-45 shows a block diagram illustrating the general- purpose input function. table 10-36 indicates register read/write data. values written in the port 7 data register (p7dr) have no effect on general-purpose input lines. when read, p7dr returns the value at the pin. figure 10-45 input port (modes 1 to 7) 214 p7dr write read internal data bus p7 7 ?7 0
table 10-36 register read/write data read write p7dr pin value don? care (2) output port (modes 1 to 7): figure 10-46 shows a block diagram illustrating the general- purpose output function. table 10-37 indicates register read/write data. the value written in the port 7 data register (p7dr) is output at the pin. when read, p7dr returns the value written in p7dr. figure 10-46 output port (modes 1 to 7) table 10-37 register read/write data read write p7dr p7dr value value output at pin (3) irq 1 or irq 0 input combined with general-purpose output (p7 1 , p7 0 : modes 1 to 7): figure 10-47 shows a block diagram illustrating the irq 1 and irq 0 input function when combined with general-purpose output. table 10-38 indicates register read/write data. when p7 1 and p7 0 are used for irq 1 and irq 0 input they can also function as general-purpose output ports. if the general-purpose output function is used, however, output of a falling edge will cause an interrupt. 215 read/ write internal data bus p7dr p7 7 ?7 0
figure 10-47 irq 1 or irq 0 input combined with general-purpose output (modes 1 to 7) table 10-38 register read/write data read write p7dr p7dr value value output at pin (4) irq 1 or irq 0 input combined with general-purpose input (p7 1 , p7 0 : modes 1 to 7): figure 10-48 shows a block diagram illustrating the irq 1 and irq 0 input function when combined with general-purpose input. table 10-39 indicates register read/write data. when p7 1 and p7 0 are used for irq 1 and irq 0 input they can also be read as general-purpose input ports, to monitor the input level at irq 1 or irq 0 . figure 10-48 irq 1 or irq 0 input combined with general-purpose input (modes 1 to 7) table 10-39 register read/write data read write p7dr pin value don? care p7dr write read internal data bus irq 1 , irq 0 irq1 or irq0 input 216 read/ write p7dr irq1 or irq0 input irq 1 , irq 0 internal data bus
(5) txd 2 and txd 1 output (p7 4 and p7 2 : modes 1 to 7): figure 10-49 shows a block diagram illustrating the txd 2 and txd 1 output function. table 10-40 indicates register read/write data. when p7 4 and p7 2 are used for txd 2 and txd 1 output, the value written in p7dr is ignored, but p7dr can be read to monitor the levels at the txd 2 and txd 1 pins. figure 10-49 txd 2 and txd 1 output (modes 1 to 7) table 10-40 register read/write data (6) rxd 2 and rxd 1 input (p7 5 and p7 3 : modes 1 to 7): figure 10-50 shows a block diagram illustrating the rxd 2 and rxd 1 input function. table 10-41 indicates register read/write data. when p7 5 and p7 3 are used for rxd 2 and rxd 1 input, the value written in p7dr is ignored, but p7dr can be read to monitor the levels at the rxd 2 and rxd 1 pins (to detect the line break state, for example). figure 10-50 rxd 2 and rxd 1 input (modes 1 to 7) p7dr write read internal data bus txd 2 , txd 1 transmit data output read write p7dr pin value don? care p7dr write read internal data bus rxd 2 , rxd 1 receive data input 217
table 10-41 register read/write data (7) sck 2 and sck 1 pins (p7 7 and p7 6 : modes 1 to 7): figure 10-51 shows a block diagram illustrating the sck 2 and sck 1 input/output function. table 10-42 indicates register read/write data. when p7 7 and p7 6 are used for sck 2 and sck 1 input or output, the value written in p7dr is ignored, but p7dr can be read to monitor the levels at the sck 2 and sck 1 pins. figure 10-51 sck 2 and sck 1 pins (modes 1 to 7) table 10-42 register read/write data read write p7dr pin value don? care p7dr write read internal data bus sck 2 , sck 1 serial clock input or output read write p7dr pin value don? care 218
(8) pw 2 and pw 1 output (p7 7 and p7 6 : modes 1 to 7, h8/539 only): figure 10-52 shows a block diagram illustrating the pwm output function. table 10-43 indicates register read/write data. when p7 7 and p7 6 function as pw 2 and pw 1 , data written in the port 7 data register (p7dr) is not output at the pins, but p7dr can be read to monitor the levels of the pw 2 and pw 1 pins. figure 10-52 pw 2 and pw 1 output (modes 1 to 7) table 10-43 register read/write data read write p7dr pin value don? care 219 p7dr write read internal data bus pw 1 , pw 2 pwm output
10.9 port 8 10.9.1 overview port 8 is a four-bit input port that is multiplexed with analog input pins of the a/d converter. figure 10-53 summarizes the pin functions. figure 10-53 port 8 pin functions 10.9.2 register descriptions table 10-44 summarizes the registers of port 8. since port 8 is used only for input, there is no data direction register. table 10-44 port 8 registers (1) port 8 data register: the port 8 data register (p8dr) is an eight-bit register that indicates the values of pins p8 3 to p8 0 . port 8 p8 3 /an 11 (input) p8 2 /an 10 (input) p8 1 /an 9 (input) p8 0 /an 8 (input) address name abbreviation r/w initial value h'fe8f port 8 data register p8dr r bit initial value r/w 7 1 ?8 3 543210 111 r r r r 6 p8 2 p8 1 p8 0 220
p8dr is a read-only register. it cannot be written. the upper four bits of p8dr are reserved bits that always return the value 1 when read. 10.9.3 port 8 read operation figure 10-54 shows a block diagram of port 8. while being used for analog input, port 8 can also function as a general-purpose input port. when read, p8dr returns the values at the pins. if p8dr is read when the a/d converter is sampling an analog input, however, the pin being sampled is read as 1. figure 10-54 analog input and general-purpose input (modes 1 to 7) read an 11 to an 8 input internal data bus p8 3 ?8 0 221
10.10 port 9 10.10.1 overview port 9 is an eight-bit input port that is multiplexed with analog input pins of the a/d converter. figure 10-55 summarizes the pin functions. figure 10-55 port 9 pin functions 10.10.2 register descriptions table 10-45 summarizes the registers of port 9. since port 9 is used only for input, there is no data direction register. table 10-45 port 9 registers (1) port 9 data register: the port 9 data register (p9dr) is an eight-bit register that indicates the values of pins p9 7 to p9 0 . p9dr is a read-only register. it cannot be written. port 9 p9 7 /an 7 (input) p9 6 /an 6 (input) p9 5 /an 5 (input) p9 4 /an 4 (input) p9 3 /an 3 (input) p9 2 /an 2 (input) p9 1 /an 1 (input) p9 0 /an 0 (input) address name abbreviation r/w initial value h'fe92 port 9 data register p9dr r bit initial value r/w 7 p9 7 p9 3 p9 6 543210 rrrrrrrr 6 p9 5 p9 4 p9 2 p9 1 p9 0 222
10.10.3 port 9 read operation figure 10-56 shows a block diagram of port 9. while being used for analog input, port 9 can also function as a general-purpose input port. when read, p9dr returns the values at the pins. if p9dr is read when the a/d converter is sampling an analog input, however, the pin being sampled is read as 1. figure 10-56 analog input and general-purpose input (modes 1 to 7) read an 7 to an 0 input internal data bus p9 7 ?9 0 223
10.11 port a 10.11.1 overview port a is a seven-bit input/output port that is multiplexed with output compare pins (t5oc 2/1 , t4oc 2/1 , t3oc 2/1 ) of the 16-bit integrated-timer pulse unit (ipu), pins for the breq , back , and wait signals, pwm timer output pins (pw 1/2/3 ), serial communication interface 3 input and output pins (txd 3 , rxd 3 , sck 3 ), and the page address bus (a 19 to a 16 ). figure 10-57 (a) and (b) summarizes the pin functions. pins in port a can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. in the h8/538, port a does not have pwm timer output and serial communication input/output functions. figure 10-57 (a) port a pin functions (h8/538) figure 10-57 (b) port a pin functions (h8/539) port a pa 6 (input/output)/t3oc 2 (output)/back (output) pa 5 (input/output)/t3oc 1 (output)/breq (input) pa 4 (input/output)/wait (input) pa 3 (input/output)/t5oc 2 (output)/a 19 (output) pa 2 (input/output)/t5oc 1 (output)/a 18 (output) pa 1 (input/output)/t4oc 2 (output)/a 17 (output) pa 0 (input/output)/t4oc 1 (output)/a 16 (output) port a pa 6 (input/output)/t3oc 2 (output)/back (output)/txd 3 (output) pa 5 (input/output)/t3oc 1 (output)/breq (input)/rxd 3 (output) pa 4 (input/output)/wait (input) pa 3 (input/output)/t5oc 2 (output)/a 19 (output)/sck 3 (input/output) pa 2 (input/output)/t5oc 1 (output)/a 18 (output)/pw 3 (output) pa 1 (input/output)/t4oc 2 (output)/a 17 (output)/pw 2 (output) pa 0 (input/output)/t4oc 1 (output)/a 16 (output)/pw 1 (output) 224
figure 10-58 shows examples of output loads for port a. figure 10-58 examples of port a output loads 10.11.2 register descriptions table 10-46 summarizes the registers of port a. table 10-46 port a registers address name abbreviation r/w initial value h'fe91 port a data direction register paddr w h'80 h'fe93 port a data register padr r/w h'80 h'feda port a control register * pacr r/w h'90 note: * pacr is not present in the h8/538. (1) port a data direction register: the port a data direction register (paddr) is an eight-bit register. each bit selects input or output for one pin. a pin in port a becomes an output pin if the corresponding paddr bit is set to 1, and an input pin if this bit is cleared to 0. paddr is a write-only register. all bits always return the value 1 when read. 225 (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port a 2 k w port a bit initial value r/w 7 1 ?a 3 ddr pa 6 ddr 543210 0000000 wwwwwww 6 pa 5 ddr pa 4 ddr pa 2 ddr pa 1 ddr pa 0 ddr
paddr is initialized to h'80 by a reset and in hardware standby mode. paddr is not initialized in software standby mode. (2) port a data register: the port a data register (padr) is an eight-bit register that stores data for pins pa 6 to pa 0 . when a bit in paddr is set to 1, the corresponding padr bit value is output at the corresponding pin. if port a is read the value in padr is returned, regardless of the actual state of the pin. when a bit in paddr is cleared to 0, it is possible to write to the corresponding padr bit but the value is not output at the pin. if padr is read the value at the pin is returned, regardless of the value written in padr. padr is initialized to h'80 by a reset and in hardware standby mode. padr is not initialized in software standby mode. (3) port a control register: the port a control register (pacr) is an eight-bit register that controls the functions of pin pa 6 to pa 0 . pacr is present only in the h8/539. it is not present in the h8/538. bits 6, 5, and 3?xd 3 enable, rxd 3 enable, and sck 3 enable (txd3e, rxd3e, sck3e): these bits control the txd 3 , rxd 3 , and sck 3 functions of pins pa 6 /t3oc 2 / back /txd 3 , pa 5 /t3oc 1 / breq /rxd 3 , and pa 3 /t5oc 2 /a 19 /sck 3 in port a. when bits txd3e, rxd3e, and sck3e are set to 1, pins pa 6 , pa 5 , and pa 3 can be used for txd 3 output, rxd 3 input, and sck 3 input or output. bits 2 to 0?w 3 enable, pw 2 enable, and pw 1 enable, (pw3e, pw2e, pw1e): these bits control the pw 3/2/1 functions of pins pa 2 /t5oc 1 /a 18 /pw 3 , pa 1 /t4oc 2 /a 17 /pw 2 , and pa 0 /t4oc 1 /a 16 /pw 1 in port a. when bits pw3e, pw2e, and pw1e are set to 1, these pins can be used for pw 3 output, pw 2 output, and pw 1 output. bit initial value r/w 7 1 ?a 3 pa 6 543210 0000000 r/w r/w r/w r/w r/w r/w r/w 6 pa 5 pa 4 pa 2 pa 1 pa 0 bit initial value r/w 7 1 sck3e txd3e 543210 0010000 r r/w r/w r r/w r/w r/w r/w 6 rxd3e pw3e pw2e pw1e 226
10.11.3 pin functions in each mode port a has different functions in different operating modes. a description for each mode is given next. the serial communication interface 3 input/output pin functions (sck 3 , txd 3 , rxd 3 ) and pwm output pin functions (pw 3 , pw 2 , pw 1 ) are unavailable in the h8/538. the h8/538 does not have pacr. (1) pin functions in modes 1, 2, and 6: port a can be used for the output-compare function (t3oc 2/1 , t4oc 2/1 , t5oc 2/1 ) of the 16-bit integrated-timer pulse unit (ipu), bus control ( breq and back ), serial communication interface 3 input and output (sck 3 , txd 3 , rxd 3 ), pwm timer output (pw 3 , pw 2 , pw 1 ), wait signal input ( wait ), and general-purpose output. when a pin is used for output compare, bus control, serial communication interface 3 input or output, pwm timer output, or wait signal input, the paddr setting is ignored. the priority of pin functions for pa 5 /t3oc 1 / breq /rxd 3 and pa 6 /t3oc 2 / back /txd 3 is: bus control > txd 3 , rxd 3 > output compare > general-purpose output the txd 3 and rxd 3 pin functions are available when bits txd3e and rxd3e are set to 1 in the port a control register (pacr). when these bits are set to 1, the corresponding pins cannot be used for output compare. the priority of pin functions for pa 3 /t5oc 2 /sck 3 , pa 2 /t5oc 1 /pw 3 , pa 1 /t4oc 2 /pw 2 , and pa 0 /t4oc 1 /pw 1 is: sck 3 , pw 3/2/1 > output compare > general-purpose output the sck 3 , pw 3 , pw 2 , and pw 1 pin functions are available when bits sck3e, pw3e, pw2e, and pw1e, respectively, are set to 1 in pacr. when these bits are set to 1, the corresponding pins cannot be used as output compare pins. for methods of selecting pin functions, see appendix d ?in function selection. figure 10-59 shows the functions of port a in modes 1, 2, and 6. 227
figure 10-59 port a pin functions in modes 1, 2, and 6 (h8/539) (2) pin functions in modes 3 and 5: port a has pins that can be used for the output compare function (t3oc 2/1 ) of the 16-bit integrated-timer pulse unit (ipu), bus control ( breq and back ), serial communication interface 3 input and output (txd 3 , rxd 3 ), wait signal input ( wait ), or general-purpose input or output, and pins that are used for page address output (a 19 to a 16 ). when a pin is used for output compare, bus control, serial communication input/output, or wait signal input, the paddr setting is ignored. the priority of pin functions for pa 5 /t3oc 1 / breq /rxd 3 and pa 6 /t3oc 2 / back /txd 3 is: txd 3 , rxd 3 > bus control > output compare > general-purpose output the txd 3 and rxd 3 pin functions are available when bits txd3e and rxd3e are set to 1 in the port a control register (pacr). when these bits are set to 1, the corresponding pins cannot be used for output compare. for methods of selecting pin functions, see appendix d ?in function selection. figure 10-60 shows the functions of port a in modes 3 and 5. 228 port a pa 6 /t3oc 2 /back/txd 3 pa 5 /t3oc 1 /breq/rxd 3 pa 4 /wait pa 3 /t5oc 2 /sck 3 pa 2 /t5oc 1 /pw 3 pa 1 /t4oc 2 /pw 2 pa 0 /t4oc 1 /pw 1
figure 10-60 port a pin functions in modes 3 and 5 (h8/539) (3) pin functions in mode 4: port a has pins that can be used for the output compare function (t3oc 2/1 ) of the 16-bit integrated-timer pulse unit (ipu), bus control ( breq and back ), serial communication interface 3 input and output (sck 3 , txd 3 , rxd 3 ), pwm timer output (pw 1 , pw 2 , pw 3 ), wait signal input ( wait ), page address output (a 19 to a 16 ), and general-purpose input or output. when a pin is used for output compare, bus control, serial communication input/output, pwm timer output, or wait signal input, the paddr setting is ignored. the priority of pin functions for pa 5 /t3oc 1 / breq /rxd 3 and pa 6 /t3oc 2 / back /txd 3 is: bus control > txd 3 , rxd 3 > output compare > general-purpose output the txd 3 and rxd 3 pin functions are available when bits txd3e and rxd3e are set to 1 in the port a control register (pacr). when these bits are set to 1, the corresponding pins cannot be used for output compare. the priority of pin functions for pa 3 /a 19 /sck 3 , pa 2 /a 18 /pw 3 , pa 1 /a 17 /pw 2 , and pa 0 /a 16 /pw 1 is: sck 3 , pw 3/2/1 > address bus > general-purpose input the sck 3 , pw 3 , pw 2 , and pw 1 functions of pins pa 3 to pa 0 are available when bits sck3e, pw3e, pw2e, and pw1e are set to 1 in the port a control register (pacr). when these bits are set to 1, the corresponding pins cannot be used for page address output. when bits sck3e, pw3e, pw2e, and pw1e are cleared to 0 in pacr, these pins are used for page address output if the corresponding paddr bit is set to 1, and for general-purpose input if the corresponding paddr bit is cleared to 0. pa 6 /t3oc 2 /back/txd 3 pa 5 /t3oc 1 /breq/rxd 3 pa 4 /wait a 19 (page address bus) a 18 (page address bus) a 17 (page address bus) a 16 (page address bus) port a 229
for methods of selecting pin functions, see appendix d ?in function selection. figure 10-61 shows the functions of port a in mode 4. figure 10-61 port a pin functions in mode 4 (h8/539) (4) pin functions in mode 7: port a can be used for the output compare function (t3oc 2/1 , t4oc 2/1 , t5oc 2/1 ) of the 16-bit integrated-timer pulse unit (ipu), serial communication interface 3 input and output (sck 3 , txd 3 , rxd 3 ), pwm timer output (pw 1 , pw 2 , pw 3 ), and general- purpose input or output. when a pin is used for serial communication interface 3 input or output, pwm timer output, or output compare, the paddr setting is ignored. the priority of pin functions for pa 6 /t3oc 2 /txd 3 and pa 5 /t3oc 1 /rxd 3 is: txd 3 , rxd 3 > output compare > general-purpose output the txd 3 and rxd 3 pin functions are available when bits txd3e and rxd3e are set to 1 in the port a control register (pacr). when these bits are set to 1, the corresponding pins cannot be used for output compare. the priority of pin functions for pa 3 /t5oc 2 /sck 3 , pa 2 /t5oc 1 /pw 3 , pa 1 /t4oc 2 /pw 2 , and pa 0 /t4oc 1 /pw 1 is: sck 3 , pw 3/2/1 > output compare > general-purpose input the sck 3 , pw 3 , pw 2 , and pw 1 pin functions are available when bits sck3e, pw3e, pw2e, and pw1e, respectively, are set to 1 in pacr. when these bits are set to 1, these pins cannot be used as output compare pins. for methods of selecting pin functions, see appendix d ?in function selection. pa 6 /t3oc 2 /back/txd 3 pa 5 /t3oc 1 /breq/rxd 3 pa 4 /wait pa 3 (input)/a 19 (page address bus)/sck 3 pa 2 (input)/a 18 (page address bus)/pw 3 pa 1 (input)/a 17 (page address bus)/pw 2 pa 0 (input)/a 16 (page address bus)/pw 1 port a 230
figure 10-62 shows the functions of port a in mode 7. figure 10-62 port a pin functions in mode 7 (h8/539) 10.11.4 port a read/write operations padr and paddr have different read/write functions depending on whether port a is used for bus control ( breq , back ), wait signal input ( wait ), the output compare function (t5oc 2/1 , t4oc 2/1 , t3oc 2/1 ) of the 16-bit integrated-timer pulse unit (ipu), serial communication interface 3 input or output (sck 3 , txd 3 , rxd 3 ), or general-purpose input or output. the operating states and functions of port a are described next. (1) input port (pa 6 to pa 4 in modes 1 to 7; pa 3 to pa 0 in modes 1, 2, 4, 6, and 7): figure 10- 63 shows a block diagram illustrating the general-purpose input function. table 10-47 indicates register read/write data. values written in the port a data register (padr) have no effect on general-purpose input lines. when read, padr returns the value at the pin. figure 10-63 input port (modes 1 to 7) 231 pa 6 /t3oc 2 /txd 3 pa 5 /t3oc 1 /rxd 3 pa 4 pa 3 /t5oc 2 /sck 3 pa 2 /t5oc 1 /pw 3 pa 1 /t4oc 2 /pw 2 pa 0 /t4oc 1 /pw 1 port a padr write read internal data bus pa 6 ?a 0
table 10-47 register read/write data read write padr pin value don? care (2) output port (pa 6 to pa 4 in modes 1 to 7; pa 3 to pa 0 in modes 1, 2, 6, and 7): figure 10-64 shows a block diagram illustrating the general-purpose output function. table 10-48 indicates register read/write data. the value written in the port a data register (padr) is output at the pin. when read, padr returns the value written in padr. figure 10-64 output port (modes 1 to 7) table 10-48 register read/write data read write padr padr value value output at pin (3) breq pin (pa 5 : modes 1 to 6): figure 10-65 shows a block diagram illustrating the breq function. table 10-49 indicates register read/write data. when pa 5 is used for breq input, the value written in the port a data register (padr) has no effect. figure 10-65 breq input pin (modes 1 to 6) 232 read/ write internal data bus padr pa 6 ?a 0 padr write read internal data bus breq breq input
table 10-49 register read/write data (4) back pin (pa 6 : modes 1 to 6): figure 10-66 shows a block diagram illustrating the back function. table 10-50 indicates register read/write data. when pa 6 is used for back output, the value written in the port a data register (padr) has no effect. figure 10-66 back output pin (modes 1 to 6) table 10-50 register read/write data read write padr pin value don? care padr write read internal data bus back back output read write padr pin value don? care 233
(5) wait pin (pa 4 : modes 1 to 6): figure 10-67 shows a block diagram illustrating the wait function. table 10-51 indicates register read/write data. when pa 6 is used for wait input, the value written in the port a data register (padr) has no effect. figure 10-67 wait input pin (modes 1 to 6) table 10-51 register read/write data (6) timer output pins (pa 6 , pa 5 , pa 3 to pa 0 : modes 1 to 7): figure 10-68 shows a block diagram illustrating the timer output function. table 10-52 indicates register read/write data. when pa 6 , pa 5 , and pa 3 to pa 0 are used for t3oc 2 , t3oc 1 , t5oc 2 , t5oc 1 , t4oc 2 , and t4oc 1 output, values written in the port a data register (padr) have no effect on the timer output. padr can be read to monitor the timer output level (t3oc 2 , t3oc 1 , t5oc 2 , t5oc 1 , t4oc 2 , t4oc 1 ). figure 10-68 output compare pins (modes 1 to 7) padr write read internal data bus wait wait input read write padr pin value don? care padr write read internal data bus t3oc 2, 1 timer output t5oc 1, 2 t4oc 1, 2 234
table 10-52 register read/write data (7) page address bus (pa 3 to pa 0 : modes 3 to 5): figure 10-69 shows a block diagram illustrating the page-address-bus function. table 10-53 indicates register read/write data. when pa 3 to pa 0 are used for a 19 to a 16 output, values written in the port a data register (padr) have no effect. when read, padr returns the value written in padr. figure 10-69 page address bus (modes 3 to 5) table 10-53 register read/write data padr read/ write page address a 19 ? 16 internal data bus read write padr padr value don? care read write padr pin value don? care 235
(8) txd 3 output (pa 6 : modes 1, 2, 4, 6, and 7) (h8/539 only): figure 10-70 shows a block diagram illustrating the txd 3 output function. table 10-54 indicates register read/write data. when pa 6 is used for txd 3 output, the value written in padr is ignored, but padr can be read to monitor the level at the txd 3 pin. figure 10-70 txd 3 output (modes 1, 2, 4, 6, and 7) table 10-54 register read/write data read write padr pin value don? care (9) rxd 3 input (pa 5 : modes 1, 2, 4, 6, and 7) (h8/539 only): figure 10-71 shows a block diagram illustrating the rxd 3 input function. table 10-55 indicates register read/write data. when pa 5 is used for rxd 3 input, the value written in padr is ignored, but padr can be read to monitor the level at the rxd 3 pin. figure 10-71 rxd 3 input (modes 1, 2, 4, 6, and 7) 236 padr write read internal data bus txd 3 transmit data output padr write read internal data bus rxd 3 receive data input
table 10-55 register read/write data read write padr pin value don? care (10) sck 3 pin (pa 3 : modes 1, 2, 4, 6, and 7) (h8/539 only): figure 10-72 shows a block diagram illustrating the sck 3 input/output function. table 10-56 indicates register read/write data. when pa 3 is used for sck 3 input or output, the value written in padr is ignored, but padr can be read to monitor the level at the sck 3 pin. figure 10-72 sck 3 pins (modes 1, 2, 4, 6, and 7) table 10-56 register read/write data read write padr pin value don? care 237 padr write read internal data bus sck 3 serial clock input or output
10.12 port b 10.12.1 overview port b is an-eight-bit input/output port. figure 10-73 summarizes the pin functions. port b is an address bus (a 15 to a 8 ) in modes 1, 3, 5, and 6. in modes 2 and 4 port b can be used for address output (a 15 to a 8 ) or general-purpose input. in mode 7 port b is a general-purpose input/output port. pins in port b can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. they have software-programmable built-in pull-up transistors. figure 10-73 port b pin functions figure 10-74 shows examples of output loads for port b. figure 10-74 examples of port b output loads port b pb 7 (input/output) /a 15 (output) pb 6 (input/output) /a 14 (output) pb 5 (input/output) /a 13 (output) pb 4 (input/output) /a 12 (output) pb 3 (input/output) /a 11 (output) pb 2 (input/output) /a 10 (output) pb 1 (input/output) /a 9 (output) pb 0 (input/output) /a 8 (output) (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port b 2 k w port b 238
10.12.2 register descriptions table 10-57 summarizes the registers of port b. table 10-57 port b registers (1) port b data direction register: the port b data direction register (pbddr) is an-eight-bit register. each bit selects input or output for one pin. a pin in port b becomes an output pin if the corresponding pbddr bit is set to 1, and an input pin if this bit is cleared to 0. pbddr is a write-only register. all bits always return the value 1 when read. pbddr is initialized to h'00 by a reset and in hardware standby mode. pbddr is not initialized in software standby mode. (2) port b data register: the port b data register (pbdr) is an-eight-bit register that stores data for pins pb 7 to pb 0 . when a bit in pbddr is set to 1, the corresponding pbdr bit value is output at the corresponding pin. if port b is read the value in pbdr is returned, regardless of the actual state of the pin. when a bit in pbddr is cleared to 0, it is possible to write to the corresponding pbdr bit but the address name abbreviation r/w initial value h'fe94 port b data direction register pbddr w h'00 h'fe96 port b data register pbdr r/w h'00 h'fe98 port b pull-up transistor control register pbpcr r/w h'00 bit initial value r/w 7 0 pb 7 ddr pb 3 ddr pb 6 ddr 543210 0000000 wwwwwwww 6 pb 5 ddr pb 4 ddr pb 2 ddr pb 1 ddr pb 0 ddr bit initial value r/w 7 0 pb 7 pb 3 pb 6 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 pb 5 pb 4 pb 2 pb 1 pb 0 239
value is not output at the pin. if pbdr is read the value at the pin is returned, regardless of the value written in pbdr. pbdr is initialized to h'00 by a reset and in hardware standby mode. pbdr is not initialized in software standby mode. (3) port b pull-up transistor control register: the port b pull-up transistor control register (pbpcr) is an-eight-bit register that turns the mos pull-up transistors of pb 7 to pb 0 on and off. pbpcr is ignored in modes 1 to 6 and used only in mode 7. when a pbddr bit is cleared to 0, if the corresponding pbpcr bit is set to 1, the built-in pull-up transistor is turned on. pbpcr is initialized to h'00 by a reset and in hardware standby mode. pbpcr is not initialized in software standby mode. 10.12.3 pin functions in each mode port b has one set of functions in modes 1, 3, 5, and 6, another set of functions in modes 2 and 4, and another set of functions in mode 7. a description for each mode group is given next. (1) pin functions in modes 1, 3, 5, and 6: port b is used for address output (a 15 to a 8 ). the pbddr settings are ignored. figure 10-75 shows the pin functions in modes 1, 3, 5, and 6. bit initial value r/w 7 0 pb 7 pon pb 3 pon pb 6 pon 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 pb 5 pon pb 4 pon pb 2 pon pb 1 pon pb 0 pon 240
figure 10-75 pin functions in modes 1, 3, 5, and 6 (2) pin functions in modes 2 and 4: port b can be used for address output (a 15 to a 8 ) or general-purpose input. a pin is used for address output if the corresponding pbddr bit is set to 1, and for general-purpose input if this bit is cleared to 0. figure 10-76 shows the pin functions in modes 2 and 4. figure 10-76 pin functions in modes 2 and 4 a 15 (address bus) a 14 (address bus) a 13 (address bus) a 12 (address bus) a 11 (address bus) a 10 (address bus) a 9 (address bus) a 8 (address bus) port b port b pb 7 (input)/a 15 (address bus) pb 6 (input)/a 14 (address bus) pb 5 (input)/a 13 (address bus) pb 4 (input)/a 12 (address bus) pb 3 (input)/a 11 (address bus) pb 2 (input)/a 10 (address bus) pb 1 (input)/a 9 (address bus) pb 0 (input)/a 8 (address bus) 241
(3) pin functions in mode 7: port b consists of general-purpose input/output pins. input or output can be selected separately for each pin. a pin becomes an output pin if the corresponding pbddr bit is set to 1 and an input pin if this bit is cleared to 0. figure 10-77 shows the pin functions in mode 7. figure 10-77 pin functions in mode 7 10.12.4 built-in pull-up transistors port b has built-in mos pull-up transistors that can be controlled by software. to turn an input pull-up transistor on, clear its pbddr bit to 0 and set its pbpcr bit to 1. the input pull-up transistors are turned off by a reset and in hardware standby mode. table 10-58 summarizes the states of the input pull-ups in each mode. table 10-58 pull-up transistor states in each mode port b pb 7 (input/output pin) pb 6 (input/output pin) pb 5 (input/output pin) pb 4 (input/output pin) pb 3 (input/output pin) pb 2 (input/output pin) pb 1 (input/output pin) pb 0 (input/output pin) hardware other modes (including mode reset standby mode software standby mode) 1? off off off 7 on/off 242
10.12.5 port b read/write operations pbdr and pbddr have different read/write functions depending on whether port b is used for address output (a 15 to a 8 ) or general-purpose input or output. the operating states and functions of port b are described next. (1) input port (all pins: modes 2 and 4): figure 10-78 shows a block diagram illustrating the general-purpose input function. table 10-59 indicates register read/write data. values written in the port b data register (pbdr) have no effect on general-purpose input lines. when read, pbdr returns the value at the pin. figure 10-78 input port (modes 2 and 4) table 10-59 register read/write data (2) input port with internal pull-up (all pins: mode 7): figure 10-79 shows a block diagram illustrating the general-purpose input function and built-in input pull-up transistors. table 10-60 indicates register read/write data. values written in the port b data register (pbdr) have no effect on general-purpose input lines. when read, pbdr returns the value at the pin. when a bit in the port b pull-up transistor control register (pbpcr) is set to 1, the corresponding pbdr bit always reads 1. pbdr write read internal data bus pb 7 ?b 0 read write pbdr pin value don? care 243
figure 10-79 input port with built-in pull-up transistors (mode 7) table 10-60 register read/write data (3) output port (all pins: mode 7): figure 10-80 shows a block diagram illustrating the general-purpose output function. table 10-61 indicates register read/write data. the value written in the port b data register (pbdr) is output at the pin. when read, pbdr returns the value written in pbdr. figure 10-80 output port (mode 7) write pbdr write read internal data bus pb 7 ?b 0 pbpcr read write pbdr pin value, or always 1 * don? care pbpcr pbpcr value 0/1 * note: * if set to 1, the corresponding pbdr bit always reads 1. read/ write internal data bus pbdr pb 7 ?b 0 244
table 10-61 register read/write data (4) address bus (all pins: modes 1 to 6): figure 10-81 shows a block diagram illustrating the address-bus function. table 10-62 indicates register read/write data. when port b is used as an address bus, values written in the port b data register (pbdr) have no effect on the bus lines. when read, pbdr returns the value written in pbdr. figure 10-81 address bus (modes 1 to 6) table 10-62 register read/write data read write pbdr pbdr value value output at pin pbdr read/ write address a 15 ? 8 internal data bus read write pbdr pbdr value don? care 245
10.13 port c 10.13.1 overview port c is an-eight-bit input/output port. figure 10-82 summarizes the pin functions. port c is an address bus (a 7 to a 0 ) in modes 1, 3, 5, and 6. in modes 2 and 4 port c can be used for address output (a 7 to a 0 ) or general-purpose input. in mode 7 port c is a general-purpose input/output port. pins in port c can drive one ttl load and a 90-pf capacitive load. they can also drive a darlington transistor pair. they have software-programmable built-in pull-up transistors. figure 10-82 port c pin functions figure 10-83 shows examples of output loads for port c. figure 10-83 examples of port c output loads port c pc 7 (input/output)/a 7 (output) pc 6 (input/output)/a 6 (output) pc 5 (input/output)/a 5 (output) pc 4 (input/output)/a 4 (output) pc 3 (input/output)/a 3 (output) pc 2 (input/output)/a 2 (output) pc 1 (input/output)/a 1 (output) pc 0 (input/output)/a 0 (output) (1) one ttl load or four ls-ttl loads (2) darlington transistor pair hd7404 etc. hd74ls04 etc. darlington pair port c 2 k w port c 246
10.13.2 register descriptions table 10-63 summarizes the registers of port c. table 10-63 port c registers (1) port c data direction register: the port c data direction register (pcddr) is an-eight-bit register. each bit selects input or output for one pin. a pin in port c becomes an output pin if the corresponding pcddr bit is set to 1, and an input pin if this bit is cleared to 0. pcddr is a write-only register. all bits always return the value 1 when read. pcddr is initialized to h'00 by a reset and in hardware standby mode. pcddr is not initialized in software standby mode. (2) port c data register: the port c data register (pcdr) is an-eight-bit register that stores data for pins pc 7 to pc 0 . when a bit in pcddr is set to 1, the corresponding pcdr bit value is output at the corresponding pin. if port c is read the value in pcdr is returned, regardless of the actual state of the pin. when a bit in pcddr is cleared to 0, it is possible to write to the corresponding pcdr bit but the address name abbreviation r/w initial value h'fe95 port c data direction register pcddr w h'00 h'fe97 port c data register pcdr r/w h'00 h'fe99 port c pull-up transistor control register pcpcr r/w h'00 bit initial value r/w 7 0 pc 7 ddr pc 3 ddr pc 6 ddr 543210 0000000 wwwwwwww 6 pc 5 ddr pc 4 ddr pc 2 ddr pc 1 ddr pc 0 ddr bit initial value r/w 7 0 pc 7 pc 3 pc 6 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 pc 5 pc 4 pc 2 pc 1 pc 0 247
value is not output at the pin. if pcdr is read the value at the pin is returned, regardless of the value written in pcdr. pcdr is initialized to h'00 by a reset and in hardware standby mode. pcdr is not initialized in software standby mode. (3) port c pull-up transistor control register: the port c pull-up transistor control register (pcpcr) is an-eight-bit register that turns the mos pull-up transistors of pc 7 to pc 0 on and off. pcpcr is ignored in modes 1 to 6 and used only in mode 7. when a pcddr bit is cleared to 0, if the corresponding pcpcr bit is set to 1, the built-in pull-up transistor is turned on. pcpcr is initialized to h'00 by a reset and in hardware standby mode. pcpcr is not initialized in software standby mode. 10.13.3 pin functions in each mode port c has one set of functions in modes 1, 3, 5, and 6, another set of functions in modes 2 and 4, and another set of functions in mode 7. a description for each mode group is given next. (1) pin functions in modes 1, 3, 5, and 6: port c is used for address output (a 7 to a 0 ). the pcddr settings are ignored. figure 10-84 shows the pin functions in modes 1, 3, 5, and 6. bit initial value r/w 7 0 pc 7 pon pc 3 pon pc 6 pon 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 pc 5 pon pc 4 pon pc 2 pon pc 1 pon pc 0 pon 248
figure 10-84 pin functions in modes 1, 3, 5, and 6 (2) pin functions in modes 2 and 4: port c can be used for address output (a 7 to a 0 ) or general-purpose input. a pin is used for address output if the corresponding pcddr bit is set to 1, and for general-purpose input if this bit is cleared to 0. figure 10-85 shows the pin functions in modes 2 and 4. figure 10-85 pin functions in modes 2 and 4 a 7 (address bus) a 6 (address bus) a 5 (address bus) a 4 (address bus) a 3 (address bus) a 2 (address bus) a 1 (address bus) a 0 (address bus) port c port c pc 7 (input)/a 7 (address bus) pc 6 (input)/a 6 (address bus) pc 5 (input)/a 5 (address bus) pc 4 (input)/a 4 (address bus) pc 3 (input)/a 3 (address bus) pc 2 (input)/a 2 (address bus) pc 1 (input)/a 1 (address bus) pc 0 (input)/a 0 (address bus) 249
(3) pin functions in mode 7: port c consists of general-purpose input/output pins. input or output can be selected separately for each pin. a pin becomes an output pin if the corresponding pcddr bit is set to 1 and an input pin if this bit is cleared to 0. figure 10-86 shows the pin functions in mode 7. figure 10-86 pin functions in mode 7 10.13.4 built-in mos pull-up transistors port c has built-in mos pull-up transistors that can be controlled by software. to turn an input pull-up transistor on, clear its pcddr bit to 0 and set its pcpcr bit to 1. the input pull-up transistors are turned off by a reset and in hardware standby mode. table 10-64 summarizes the states of the input pull-ups in each mode. table 10-64 pull-up transistor states in each mode port c pc 7 (input/output pin) pc 6 (input/output pin) pc 5 (input/output pin) pc 4 (input/output pin) pc 3 (input/output pin) pc 2 (input/output pin) pc 1 (input/output pin) pc 0 (input/output pin) hardware other modes (including mode reset standby mode software standby mode) 1? off off off 7 on/off 250
10.13.5 port c read/write operations pcdr and pcddr have different read/write functions depending on whether port c is used for address output (a 7 to a 0 ) or general-purpose input or output. the operating states and functions of port c are described next. (1) input port (all pins: modes 2 and 4): figure 10-87 shows a block diagram illustrating the general-purpose input function. table 10-65 indicates register read/write data. values written in the port c data register (pcdr) have no effect on general-purpose input lines. when read, pcdr returns the value at the pin. figure 10-87 input port (modes 2 and 4) table 10-65 register read/write data (2) input port with internal pull-up (all pins: mode 7): figure 10-88 shows a block diagram illustrating the general-purpose input function of port c using the built-in input pull-up transistors. table 10-66 indicates register read/write data. values written in the port c data register (pcdr) have no effect on general-purpose input lines. when read, pcdr returns the value at the pin. when a bit in the port c pull-up transistor control register (pcpcr) is set to 1, the corresponding pcdr bit always reads 1. pcdr write read internal data bus pc 7 ?c 0 read write pcdr pin value don? care 251
figure 10-88 input port with built-in pull-up transistors (mode 7) table 10-66 register read/write data (3) output port (all pins: mode 7): figure 10-89 shows a block diagram illustrating the general-purpose output function. table 10-67 indicates register read/write data. the value written in the port c data register (pcdr) is output at the pin. when read, pcdr returns the value written in pcdr. figure 10-89 output port (mode 7) write pcdr write read internal data bus pc 7 ?c 0 pcpcr read write pcdr pin value, or always 1 * don? care pcpcr pcpcr value 0/1 * note: * if set to 1, the corresponding pcdr bit always reads 1. read/ write internal data bus pcdr pc 7 ?c 0 252
table 10-67 register read/write data (4) address bus (all pins: modes 1 to 6): figure 10-90 shows a block diagram illustrating the address-bus function. table 10-68 indicates register read/write data. when port c is used as an address bus, values written in the port c data register (pcdr) have no effect on the bus lines. when read, pcdr returns the value written in pcdr. figure 10-90 address bus (modes 1 to 6) table 10-68 register read/write data read write pcdr pcdr value value output at pin pcdr read/ write address a 7 ? 0 internal data bus read write pcdr pcdr value don? care 253
10.14 ?pin 10.14.1 overview the ?pin outputs the system clock. the ?pin can drive one ttl load and a 90-pf capacitive load. 10.14.2 register description table 10-69 summarizes the ?pin control register. table 10-69 ?pin registers address name abbreviation r/w initial value h'fe9a ?control register * ?r r/w h'ff note: * cr is not present in the h8/538. (1) ?control register: the ?control register (?r) is an eight-bit register that enables or disables output of the system clock (?. bit 7? output enable (?e): enables or disables output of the system clock (?. the ?e bit is initialized in standby mode. it is not initialized by a reset. the h8/538 does not have a system clock output disable function. caution: do not disable system clock output except in single-chip mode (mode 7). if system clock (? output is disabled in an expanded mode (modes 1-6), external data input and output will not be performed correctly. bit 7 ?e description 0 system clock (? output is disabled 1 system clock (? output is enabled (initial value) 254 bit initial value r/w 7 1 ?e 543210 1111111 r/w r r r r r r r 6
section 11 16-bit integrated-timer pulse unit 11.1 overview the built-in 16-bit integrated-timer pulse unit (ipu) has seven channels and three types of timers. the ipu can output 28 independent waveforms, or output 12 waveforms and process 16 pulse inputs or outputs. it can also provide multi-phase pwm output, automatically measure pulse widths and periods, count input from a two-phase encoder, and start the a/d converter. 11.1.1 features the ipu features are listed below. twelve waveform outputs and sixteen pulse inputs or outputs sixteen registers with software-assignable output compare or input capture functions twenty-eight independent comparators channel output compare registers output compare/input capture registers ch1 4 4 ch2? 2 2 ch6, 7 2 selection of sixteen counter clock sources (external clock sources are shared by all channels): ? ?2, ?4, ?8, ?16, ?32, ?64, ?128, ?256, ?512, ?1024, ?2048, ?4096, tclk1, tclk2, tclk3 input capture function rising edge, falling edge, or both edges pulse output one-shot, toggle, or pwm output counter synchronization function software can write to two or more timer counters simultaneously. counters can be cleared simultaneously by compare match or input capture. 255
pwm output mode one-phase, two-phase, or three-phase pwm output (up to nine-phase pwm output using the counter synchronization function) auto-measure function two timer channels can be coordinated for automatic measurement of pulse width or frequency and for two-phase encoder counting thirty-five interrupt sources 16 compare match/input capture interrupts, 12 compare match interrupts, and 7 overflow interrupts: total 35 sources. the compare match/input capture interrupts and overflow interrupts are independently vectored. the compare match interrupts have one interrupt vector per two interrupt sources. the compare match/input capture interrupts and compare match interrupts can start the data transfer controller (dtc) to transfer data. 11.1.2 block diagram figure 11-1 shows a block diagram of the ipu. figure 11-1 ipu block diagram ch1 ch2 ch3 ch4 ch5 ch6 ch7 tmdra adtrg interrupt control counter control and pulse i/o control unit 16-bit timer bus interface on-chip data bus tmdra: timer mode register a (8 bits) tmdrb: timer mode register b (8 bits) tstr: timer start register (8 bits) module data bus t1imi1 to t7imi2, t1cmi1 to t5cmi2, t1ovi to t7ovi (interrupt signals) t1oc 1 ?5oc 2 t1ioc 1 ?7ioc 2 tclk1? ?4096 tmdrb tstr clock selector 256
11.1.3 input/output pins table 11-1 summarizes the ipu pins. table 11-1 ipu pins channel pin name input/output function 1 t1ioc 1 input/output t1gr1 output compare/input capture pin (multiplexed with pwm output) t1ioc 2 input/output t1gr2 output compare/input capture pin (multiplexed with pwm output) t1oc 1 output t1dr1 output compare pin (multiplexed with pwm output) t1oc 2 output t1dr2 output compare pin t1ioc 3 input/output t1gr3 output compare/input capture pin t1ioc 4 input/output t1gr4 output compare/input capture pin t1oc 3 output t1dr3 output compare pin t1oc 4 output t1dr4 output compare pin 2 t2ioc 1 input/output t2gr1 output compare/input capture pin (multiplexed with pwm output) t2ioc 2 input/output t2gr2 output compare/input capture pin (multiplexed with pwm output) t2oc 1 output t2dr1 output compare pin t2oc 2 output t2dr2 output compare pin 3 t3ioc 1 input/output t3gr1 output compare/input capture pin (multiplexed with pwm output) t3ioc 2 input/output t3gr2 output compare/input capture pin (multiplexed with pwm output) t3oc 1 output t3dr1 output compare pin t3oc 2 output t3dr2 output compare pin 4 t4ioc 1 input/output t4gr1 output compare/input capture pin t4ioc 2 input/output t4gr2 output compare/input capture pin t4oc 1 output t4dr1 output compare pin t4oc 2 output t4dr2 output compare pin 257
11.2 timer counters and compare/capture registers the ipu has seven 16-bit timer counters (tcnts), one for each channel. each counter can be accessed 16 bits at a time. each of the seven channels has 16-bit capture and compare registers. a capture register latches the tcnt value when an external capture signal is received or an event occurs. compare register contents are compared with the tcnt value at all times, and a compare match signal and/or interrupt is generated when the two match. the configuration of each channel will be described next. table 11-1 ipu pins (cont) channel pin name input/output function 5 t5ioc 1 input/output t5gr1 output compare/input capture pin t5ioc 2 input/output t5gr2 output compare/input capture pin t5oc 1 output t5dr1 output compare pin t5oc 2 output t5dr2 output compare pin 6 t6ioc 1 input/output t6gr1 output compare/input capture pin (multiplexed with pwm output) t6ioc 2 input/output t6gr2 output compare/input capture pin 7 t7ioc 1 input/output t7gr1 output compare/input capture pin (multiplexed with pwm output) t7ioc 2 input/output t7gr2 output compare/input capture pin external tclk 1 input external clock 1 input pin (a phase input for clock phase measurement mode) tclk 2 input external clock 2 input pin (b phase input for phase measurement mode) tclk 3 input external clock 3 bit initial value 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 tcnt r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 258
11.3 channel 1 registers channel 1 has four general registers used for both input capture and output compare, and four dedicated registers used only for output compare. the input capture/output compare registers function as output compare registers after a reset. they can be switched over to input capture by setting bits ieg41 to ieg10 in the timer control registers. channel 1 can simultaneously generate a maximum of eight waveforms, or can simultaneously generate four waveforms and measure four waveforms. three-phase pwm output is possible in pwm mode. see section 11.8, ?xamples of timer operation?for details. figure 11-2 shows a block diagram of channel 1. figure 11-2 channel 1 block diagram tcrl tsrah toera tcra tsrbh tsrbl toerb tsral tcrh clock selector control logic comparator 16-bit counter tclk1? ?4096 t1oc 1 ?1oc 4 t1ioc 1 ?1ioc 4 module data bus control registers bus interface on-chip data bus gr1 (icr/ocr) gr2 (icr/ocr) dr1 (ocr) dr2 (ocr) gr3 (icr/ocr) gr4 (icr/ocr) dr3 (ocr) dr4 (ocr) gr1 to gr4: input capture/output compare registers (16 bits 4) dr1 to dr4: output compare registers (16 bits 4) tcrh and tcrl: timer control register (8 bits 2) tsrah and tsral: timer status register a (8 bits 2) tcra: timer control register a (8 bits) tsrbh and tsrbl: timer status register b (8 bits 2) toera: timer output enable register a (8 bits) toerb: timer output enable register b (8 bits) 259
11.3.1 register configuration table 11-2 summarizes the channel 1 registers. table 11-2 channel 1 registers chan- abbre- initial nel address name viation r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value 1 ff20 timer control t1crh r/w ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 register (high) ff21 timer control t1crl r/w cclr2 cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'80 register (low) ff22 timer status t1srah r/w ovie cmie2 cmie1 imie2 imie1 h'e0 register a (high) ff23 timer status t1sral r/w ovf cmf2 cmf1 imf2 imf1 h'e0 register a (low) ff24 timer output t1oera r/w doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 enable register a ff25 timer mode tmdra r/w md6? md4? md3? md2? sync3 sync2 sync1 sync0 h'00 register a ff26 timer counter t1cnth r/w h'00 register (high) ff27 timer counter t1cntl r/w h'00 register (low) ff28 general t1gr1h r/w h'ff register 1 (high) ff29 general t1gr1l r/w h'ff register 1 (low) ff2a general t1gr2h r/w h'ff register 2 (high) ff2b general t1gr2l r/w h'ff register 2 (low) ff2c dedicated t1dr1h r/w h'ff register 1 (high) ff2d dedicated t1dr1l r/w h'ff register 1 (low) ff2e dedicated t1dr2h r/w h'ff register 2 (high) ff2f dedicated t1dr2l r/w h'ff register 2 (low) ff30 timer start tstr r/w str7 str6 str5 str4 str3 str2 str1 h'80 register ff31 timer control t1cra r/w ieg41 ieg40 ieg31 ieg30 h'f0 register a 260
table 11-2 channel 1 registers (cont) chan- abbre- initial nel address name viation r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value ff32 timer status t1srbh r/w cmie4 cmie3 imie4 imie3 h'f0 register b (high) ff33 timer status t1srbl r/w cmf4 cmf3 imf4 imf3 h'f0 register b (low) ff34 timer output t1oerb r/w doe41 doe40 doe31 doe30 goe41 goe40 goe31 goe30 h'00 enable register b ff35 timer mode tmdrb r/w mdf pwm4 pwm3 pwm2 pwm1 pwm0 h'c0 register b ff38 general t1gr3h r/w h'ff register 3 (high) ff39 general t1gr3l r/w h'ff register 3 (low) ff3a general t1gr4h r/w h'ff register 4 (high) ff3b general t1gr4l r/w h'ff register 4 (low) ff3c dedicated t1dr3h r/w h'ff register 3 (high) ff3d dedicated t1dr3l r/w h'ff register 3 (low) ff3e dedicated t1dr4h r/w h'ff register 4 (high) ff3f dedicated t1dr4l r/w h'ff register 4 (low) 261
11.3.2 timer control register (high) timer control register high (tcrh) is an eight-bit readable/writable register that selects the timer clock source. each channel has one tcrh. the bit structure of tcrh in channel 1 is shown next. (1) bits 7 and 6?eserved: read-only bits, always read as 1. (2) bits 5 and 4?lock edge 1/0 (ckeg1/0): these bits select the external clock edge. ckeg1/0 can be set to increment the count on the rising edge, falling edge, or both edges of the external clock. when tpsc3 to tpsc0 are set so as not to select an external clock source, ckeg1 and ckeg0 are ignored. for further details, see section 11.8.7, ?xternal event counting. bit initial value r/w 7 1 tpsc3 543210 1000000 r r r/w r/w r/w r/w r/w r/w 6 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tcrh timer prescaler 3? these bits select the clock source clock edge 1/0 these bits select the external clock edge reserved bits bit 5 bit 4 ckeg1 ckeg0 description 0 0 increment on rising edge (initial value) 0 1 increment on falling edge 1 0 increment on both edges 11 262
(3) bits 3 to 0?imer prescaler (tpsc3 to tpsc0): these bits select the clock source. one of 16 clock sources can be selected, as listed next. bit 3 bit 2 bit 1 bit 0 tpsc3 tpsc2 tpsc1 tpsc0 description 0000 (100 ns) * (initial value) 0001/2 (200 ns) * 0010/4 (400 ns) * 0011/8 (800 ns) * 0100 ?16 (1.6 ?) * 0101 ?32 (3.2 ?) * 0110 ?64 (6.4 ?) * 0111 ?128 (12.8 ?) * 1000 ?256 (25.6 ?) * 1001 ?512 (51.2 ?) * 1010 ?1024 (102.4 ?) * 1011 ?2048 (204.8 ?) * 1100 ?4096 (409.6 ?) * 1101 external clock (tclk 1 ) 1110 external clock (tclk 2 ) 1111 external clock (tclk 3 ) note: * values in parentheses are resolution values for a 10-mhz clock rate. 263
11.3.3 timer control register (low) timer control register low (tcrl) is an eight-bit readable/writable register that selects register functions and input capture edges, and selects the timer counter clear source. channel 1 has two timer control registers (low), designated tcrl and tcra. the bit structure of tcrl in channel 1 is shown next. (1) bit 7 ?eserved: read-only bit, always read as 1. bit initial value r/w 7 1 ieg21 cclr2 543210 0000000 r/w r/w r/w r/w r/w r/w r/w 6 cclr1 cclr0 ieg20 ieg11 ieg10 tcrl reserved bit counter clear 2? these bits select the counter clear source input capture edge 21/20/11/10 these bits select register functions and the valid edges of input capture signals 264
(2) bits 6 to 4?ounter clear 2 to 0 (cclr2/1/0): these bits select the counter clear source. when cclr2 is 0 and either cclr1 or cclr0 is set to 1, or both cclr1 and cclr0 are set to 1, the counter is cleared in synchronization with the clearing of a timer pair selected in timer mode register a (tmda). if gr1 or gr3 is used as a compare register the counter is cleared by compare match. if gr1 or gr3 is used as a capture register the counter is cleared by input capture. for further details, see section 11.8.4, ?ounter clearing function?and section 11.8.6, ?ynchronizing mode. (3) bits 3 and 2?nput capture edge 21/20 (ieg21/20): these bits select the function of gr2 and the valid edge of the input capture signal. a reset clears bits ieg21 and ieg20 to 0, disabling input capture and making gr2 an output compare register. if ieg21 or ieg20 is set to 1, or both ieg21 and ieg20 are set to 1, gr2 becomes an input capture register. for further details, see section 11.8.3, ?nput capture function. bit 3 bit 2 ieg21 ieg20 description 0 0 gr2 is not used for input capture (initial value) * 0 1 gr2 captures rising edge of input capture signal 1 0 gr2 captures falling edge of input capture signal 1 1 gr2 captures both edges of input capture signal note: * gr2 becomes an output compare register. bit 6 bit 5 bit 4 cclr2 cclr1 cclr0 description 0 0 0 counter not cleared (initial value) 0 0 1 synchronized counter clearing enabled 010 011 1 0 0 counter cleared on gr1 compare match or capture 1 0 1 counter cleared on dr2 compare match 1 1 0 counter cleared on gr3 compare match or capture 1 1 1 counter cleared on dr4 compare match 265
(4) bits 1 and 0?nput capture edge 11/10 (ieg11/10): these bits select the function of gr1 and the valid edge of the input capture signal. a reset clears bits ieg11 and ieg10 to 0, disabling input capture and making gr1 an output compare register. if ieg11 or ieg10 is set to 1, or both ieg11 and ieg10 are set to 1, gr1 becomes an input capture register. for further details, see section 11.8.3, ?nput capture function. tcra is an eight-bit readable/writable register. the bit structure of tcra in channel 1 is shown next. (1) bits 7 to 4 ?eserved: read-only bits, always read as 1. bit initial value r/w 7 1 ieg41 543210 1110000 r/w r/w r/w r/w 6 ieg40 ieg31 ieg30 tcra reserved bits input capture edge 41/40/31/30 these bits select register functions and the valid edges of input capture signals bit 1 bit 0 ieg11 ieg10 description 0 0 gr1 is not used for input capture (initial value) * 0 1 gr1 captures rising edge of input capture signal 1 0 gr1 captures falling edge of input capture signal 1 1 gr1 captures both edges of input capture signal note: * gr1 becomes an output compare register. 266
(2) bits 3 and 2?nput capture edge 41/40 (ieg41/40): these bits select the function of gr4 and the valid edge of the input capture signal. a reset clears bits ieg41 and ieg40 to 0, disabling input capture and making gr4 an output compare register. if ieg41 or ieg40 is set to 1, or both ieg41 and ieg40 are set to 1, gr4 becomes an input capture register. for further details, see section 11.8.3, ?nput capture function. (3) bits 1 and 0?nput capture edge 31/30 (ieg31/30): these bits select the function of gr3 and the valid edge of the input capture signal. a reset clears bits ieg31 and ieg30 to 0, disabling input capture and making gr3 an output compare register. if ieg31 or ieg30 is set to 1, or both ieg31 and ieg30 are set to 1, gr3 becomes an input capture register. for further details, see section 11.8.3, ?nput capture function. bit 1 bit 0 ieg31 ieg30 description 0 0 gr3 is not used for input capture (initial value) * 0 1 gr3 captures rising edge of input capture signal 1 0 gr3 captures falling edge of input capture signal 1 1 gr3 captures both edges of input capture signal note: * gr3 becomes an output compare register. bit 3 bit 2 ieg41 ieg40 description 0 0 gr4 is not used for input capture (initial value) * 0 1 gr4 captures rising edge of input capture signal 1 0 gr4 captures falling edge of input capture signal 1 1 gr4 captures both edges of input capture signal note: * gr4 becomes an output compare register. 267
11.3.4 timer status register (high) timer status register high (tsrh) is an eight-bit readable/writable register that enables and disables timer interrupts. after ovie, cmie2, cmie1, imie2, or imie1 is set to 1 in tsrh, an interrupt is requested when ovf, cmf2, cmf1, imf2, or imf1 is set to 1 in tsrl. channel 1 has two timer status registers (high), designated tsrah and tsrbh. channels 2 to 7 have one tsrh each. the bit structure of tsrah in channel 1 is shown next. (1) bits 7 to 5?eserved: read-only bits, always read as 1. bit initial value r/w 7 1 cmie2 543210 1100000 r/w r/w r/w r/w r/w 6 ovie cmie1 imie2 imie1 tsrah reserved bits input capture/ compare match interrupt enable 2/1 these bits enable and disable gr2 and gr1 compare match and input capture interrupts compare match interrupt enable 2/1 these bits enable and disable dr2 and dr1 compare match interrupts overflow interrupt enable enables or disables timer overflow interrupts 268
(2) bit 4?verflow interrupt enable (ovie): enables or disables the counter overflow interrupt. for further details, see section 11.9.1, ?nterrupt timing. (3) bit 3?ompare match interrupt enable 2 (cmie2): enables or disables the dr2 compare match interrupt. for further details, see section 11.9.1, ?nterrupt timing. (4) bit 2?ompare match interrupt enable 1 (cmie1): enables or disables the dr1 compare match interrupt. for further details, see section 11.9.1, ?nterrupt timing. (5) bit 1?nput capture/compare match interrupt enable 2 (imie2): enables or disables the gr2 compare match or input capture interrupt. for further details, see section 11.9.1, ?nterrupt timing. bit 2 cmie1 description 0 dr1 compare match interrupt is disabled (initial value) 1 dr1 compare match interrupt is enabled bit 1 imie2 description 0 gr2 compare match or input capture interrupt is disabled (initial value) 1 gr2 compare match or input capture interrupt is enabled bit 3 cmie2 description 0 dr2 compare match interrupt is disabled (initial value) 1 dr2 compare match interrupt is enabled bit 4 ovie description 0 counter overflow interrupt is disabled (initial value) 1 counter overflow interrupt is enabled 269
(6) bit 0?nput capture/compare match interrupt enable 1 (imie1): enables or disables the gr1 compare match or input capture interrupt. for further details, see section 11.9.1, ?nterrupt timing. tsrbh is an eight-bit readable/writable register. the bit structure of tsrbh in channel 1 is shown next. (1) bits 7 to 4?eserved: read-only bits, always read as 1. bit initial value r/w 7 1 cmie4 543210 1110000 r/w r/w r/w r/w 6 cmie3 imie4 imie3 tsrbh input capture/ compare match interrupt enable 4/3 these bits enable and disable gr2 and gr1 compare match and input capture interrupts compare match interrupt enable 4/3 these bits enable and disable dr4 and dr3 compare match interrupts reserved bits bit 0 imie1 description 0 gr1 compare match or input capture interrupt is disabled (initial value) 1 gr1 compare match or input capture interrupt is enabled 270
(2) bit 3?ompare match interrupt enable 4 (cmie4): enables or disables the dr4 compare match interrupt. for further details, see section 11.9.1, ?nterrupt timing. (3) bit 2?ompare match interrupt enable 3 (cmie3): enables or disables the dr3 compare match interrupt. for further details, see section 11.9.1, ?nterrupt timing. (4) bit 1?nput capture/compare match interrupt enable 4 (imie4): enables or disables the gr4 compare match or input capture interrupt. for further details, see section 11.9.1, ?nterrupt timing. (5) bit 0?nput capture/compare match interrupt enable 3 (imie3): enables or disables the gr3 compare match or input capture interrupt. for further details, see section 11.9.1, ?nterrupt timing. bit 1 imie4 description 0 gr4 compare match or input capture interrupt is disabled (initial value) 1 gr4 compare match or input capture interrupt is enabled bit 0 imie3 description 0 gr3 compare match or input capture interrupt is disabled (initial value) 1 gr3 compare match or input capture interrupt is enabled bit 2 cmie3 description 0 dr3 compare match interrupt is disabled (initial value) 1 dr3 compare match interrupt is enabled bit 3 cmie4 description 0 dr4 compare match interrupt is disabled (initial value) 1 dr4 compare match interrupt is enabled 271
11.3.5 timer status register (low) timer status register low (tsrl) is an eight-bit readable/writable register that indicates timer status. writing to tsrl is restricted to clearing a flag to 0 after reading the 1 value of that flag. after ovie, cmie2, cmie1, imie2, or imie1 is set to 1 in tsrh, an interrupt is requested when ovf, cmf2, cmf1, imf2, or imf1 is set to 1 in tsrl. channel 1 has two timer status registers (low), designated tsral and tsrbl. channels 2 to 7 have one tsrl each. the bit structure of tsral in channel 1 is shown next. (1) bits 7 to 5?eserved: read-only bits, always read as 1. bit initial value r/w 7 1 cmf2 543210 1100000 r/w r/w r/w r/w r/w 6 ovf cmf1 imf2 imf1 tsral input capture/ compare match flag 2/1 flags indicating gr2 and gr1 compare match or input capture compare match flag 2/1 flags indicating dr2 and dr1 compare match overflow flag flag indicating timer overflow reserved bits 272
(2) bit 4?verflow flag (ovf): set to 1 when the counter overflows from h'ffff to h'0000. for further details, see section 11.9.1, ?nterrupt timing. (3) bit 3?ompare match flag 2 (cmf2): set to 1 when the counter value matches the dr2 value. for further details, see section 11.9.1, ?nterrupt timing. (4) bit 2?ompare match flag 1 (cmf1): set to 1 when the counter value matches the dr1 value. for further details, see section 11.9.1, ?nterrupt timing. (5) bit 1?nput capture/compare match flag 2 (imf2): set to 1 when the counter value matches the gr2 value, or the counter value is captured to gr2. for further details, see section 11.9.1, ?nterrupt timing. bit 2 cmf1 description 0 1. cleared by reading cmf1 after cmf1 is set to 1, then writing 0 in cmf1 (initial value) 2. cleared when the dtc is activated by a cmi1 interrupt 1 set when dr1 compare match occurs bit 1 imf2 description 0 1. cleared by reading imf2 after imf2 is set to 1, then writing 0 in imf2 (initial value) 2. cleared when the dtc is activated by an imi2 interrupt 1 set when gr2 input capture or compare match occurs bit 3 cmf2 description 0 1. cleared by reading cmf2 after cmf2 is set to 1, then writing 0 in cmf2 (initial value) 2. cleared when the dtc is activated by a cmi2 interrupt 1 set when dr2 compare match occurs bit 4 ovf description 0 cleared by reading ovf after ovf is set to 1, then writing 0 in ovf (initial value) 1 set when counter overflow occurs 273
(6) bit 0?nput capture/compare match flag 1 (imf1): set to 1 when the counter value matches the gr1 value, or the counter value is captured to gr1. for further details, see section 11.9.1, ?nterrupt timing. tsrbl is an eight-bit readable/writable register. the bit structure of tsrbl in channel 1 is shown next. (1) bits 7 to 4?eserved: read-only bits, always read as 1. bit initial value r/w 7 1 cmf4 543210 1110000 r/w r/w r/w r/w 6 cmf3 imf4 imf3 tsrbl input capture/ compare match flag 4/3 flags indicating gr4 and gr3 compare match or input capture compare match flag 4/3 flags indicating dr4 and dr3 compare match reserved bits bit 0 imf1 description 0 1. cleared by reading imf1 after imf1 is set to 1, then writing 0 in imf1 (initial value) 2. cleared when the dtc is activated by an imi1 interrupt 1 set when gr1 input capture or compare match occurs 274
(2) bit 3?ompare match flag 4 (cmf4): set to 1 when the counter value matches the dr4 value. for further details, see section 11.9.1, ?nterrupt timing. (3) bit 2?ompare match flag 3 (cmf3): set to 1 when the counter value matches the dr3 value. for further details, see section 11.9.1, ?nterrupt timing. (4) bit 1?nput capture/compare match flag 4 (imf4): set to 1 when the counter value matches the gr4 value, or the counter value is captured to gr4. for further details, see section 11.9.1, ?nterrupt timing. (5) bit 0?nput capture/compare match flag 3 (imf3): set to 1 when the counter value matches the gr3 value, or the counter value is captured to gr3. for further details, see section 11.9.1, ?nterrupt timing. bit 1 imf4 description 0 1. cleared by reading imf4 after imf4 is set to 1, then writing 0 in imf4 (initial value) 2. cleared when the dtc is activated by an imi4 interrupt 1 set when gr4 input capture or compare match occurs bit 0 imf3 description 0 1. cleared by reading imf3 after imf3 is set to 1, then writing 0 in imf3 (initial value) 2. cleared when the dtc is activated by an imi3 interrupt 1 set when gr3 input capture or compare match occurs bit 2 cmf3 description 0 1. cleared by reading cmf3 after cmf3 is set to 1, then writing 0 in cmf3 (initial value) 2. cleared when the dtc is activated by a cmi3 interrupt 1 set when dr3 compare match occurs bit 3 cmf4 description 0 1. cleared by reading cmf4 after cmf4 is set to 1, then writing 0 in cmf4 (initial value) 2. cleared when the dtc is activated by a cmi4 interrupt 1 set when dr4 compare match occurs 275
11.3.6 timer output enable register the timer output enable register (toer) is an eight-bit readable/writable register that enables or disables output of compare match signals and selects the output level. channel 1 has two timer output enable registers, designated toera and toerb. channels 2 to 7 have one toer each. the bit structure of toera in channel 1 is shown next. for the selection of general register (gr) functions, see section 11.3.3, ?imer control register (low). bit initial value r/w 7 0 doe21 goe21 doe20 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 doe11 doe10 goe20 goe11 goe10 toera general register output enable 11/10 these bits enable and disable output of the counter-gr1 compare match signal, and select the output level general register output enable 21/20 these bits enable and disable output of the counter-gr2 compare match signal, and select the output level dedicated register output enable 11/10 these bits enable and disable output of the counter-dr1 compare match signal, and select the output level dedicated register output enable 21/20 these bits enable and disable output of the counter-dr2 compare match signal, and select the output level 276
(1) bits 7 and 6?edicated register output enable 21/20 (doe21/20): these bits enable and disable output of the counter-dr2 compare match signal, and select the output level. for further details, see section 11.8.2, ?election of output level. (2) bits 5 and 4?edicated register output enable 11/10 (doe11/10): these bits enable and disable output of the counter-dr1 compare match signal, and select the output level. for further details, see section 11.8.2, ?election of output level. (3) bits 3 and 2?eneral register output enable 21/20 (doe21/20): these bits enable and disable output of the counter-gr2 compare match signal, and select the output level. when gr2 is used for input capture, however, compare match signal output is disabled regardless of the setting of goe21 and goe20. bits 3 and 2 are thus ignored except when ieg21 = ieg20 = 0. for further details, see section 11.8.2, ?election of output level. bit 5 bit 4 doe11 doe10 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 bit 3 bit 2 goe21 goe20 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 bit 7 bit 6 doe21 doe20 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 277
(4) bits 1 and 0?eneral register output enable 11/10 (doe11/10): these bits enable and disable output of the counter-gr1 compare match signal, and select the output level. when gr1 is used for input capture, however, compare match signal output is disabled regardless of the setting of goe11 and goe10. bits 1 and 0 are thus ignored except when ieg11 = ieg10 = 0. for further details, see section 11.8.2, ?election of output level. toerb is an eight-bit readable/writable register. the bit structure of toerb in channel 1 is shown next. for the selection of general register (gr) functions, see section 11.3.3, ?imer control register (low). bit initial value r/w 7 0 doe41 goe41 doe40 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 doe31 doe30 goe40 goe31 goe30 toerb general register output enable 31/30 these bits enable and disable output of the counter-gr3 compare match signal, and select the output level general register output enable 41/40 these bits enable and disable output of the counter-gr4 compare match signal, and select the output level dedicated register output enable 31/30 these bits enable and disable output of the counter-dr3 compare match signal, and select the output level dedicated register output enable 41/40 these bits enable and disable output of the counter-dr4 compare match signal, and select the output level bit 1 bit 0 goe11 goe10 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 278
(1) bits 7 and 6?edicated register output enable 41/40 (doe41/40): these bits enable and disable output of the counter-dr4 compare match signal, and select the output level. for further details, see section 11.8.2, ?election of output level. (2) bits 5 and 4?edicated register output enable 31/30 (doe31/30): these bits enable and disable output of the counter-dr3 compare match signal, and select the output level. for further details, see section 11.8.2, ?election of output level. (3) bits 3 and 2?eneral register output enable 41/40 (goe41/40): these bits enable and disable output of the counter-gr4 compare match signal, and select the output level. when gr4 is used for input capture, however, compare match signal output is disabled regardless of the setting of goe41 and goe40. bits 3 and 2 are thus ignored except when ieg41 = ieg40 = 0. for further details, see section 11.8.2, ?election of output level. bit 5 bit 4 doe31 doe30 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 bit 3 bit 2 goe41 goe40 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 bit 7 bit 6 doe41 doe40 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 279
(4) bits 1 and 0?eneral register output enable 31/30 (goe31/30): these bits enable and disable output of the counter-gr3 compare match signal, and select the output level. when gr3 is used for input capture, however, compare match signal output is disabled regardless of the setting of goe31 and goe30. bits 1 and 0 are thus ignored except when ieg31 = ieg30 = 0. for further details, see section 11.8.2, ?election of output level. bit 1 bit 0 goe31 goe30 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 280
11.4 channel 2 to 5 registers channels 2 to 5 each have two general registers used for output compare and input capture, and two dedicated registers used only for output compare. the general registers function as output compare registers after a reset. they can be switched over to input capture by setting bits ieg21 to ieg10 in the timer control registers. each of channels 2 to 5 can simultaneously generate a maximum of four waveforms, or can simultaneously generate two waveforms and measure two waveforms. in programmed periodic counting mode, channels 2 to 4 are used for setting the measurement period, and channel 5 is used to measure the waveform. channels 2 and 3 can provide two-phase pwm output. see section 11.8, ?xamples of timer operation?for details. figure 11-3 shows a block diagram of channels 2 to 5. figure 11-3 block diagram of channels 2 to 5 on-chip data bus bus interface tcrh * tsrh toer tcrl tsrl control registers t2oc 1 ?2oc 2 t2ioc 1 ?2ioc 2 module data bus clock selector control logic comparator tclk1? ?4096 gr1 and gr2: output compare/input capture registers (16 bits 2) dr1 and dr2: output compare registers (16 bits 2) tcrh and tcrl: timer control registers (8 bits 2) tsrh and tsrl: timer status registers (8 bits 2) toer: timer output enable register (8 bits) note: the diagram shows 16-bit timer channel 2. note: * for tcrh, see section 11.3.2, ?imer control register (high). 16-bit counter gr1 (icr/ocr) gr2 (icr/ocr) dr1 (ocr) dr2 (ocr) 281
11.4.1 register configuration table 11-3 summarizes the registers of channels 2 and 3. table 11-3 registers of channels 2 and 3 chan- abbre- initial nel address name viation r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value 2 ff40 timer control t2crh r/w ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 register (high) ff41 timer control t2crl r/w cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 register (low) ff42 timer status t2srh r/w ovie cmie2 cmie1 imie2 imie1 h'e0 register (high) ff43 timer status t2srl r/w ovf cmf2 cmf1 imf2 imf1 h'e0 register (low) ff44 timer output t2oer r/w doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 enable register ff46 timer counter t2cnth r/w h'00 register (high) ff47 timer counter t2cntl r/w h'00 register (low) ff48 general t2gr1h r/w h'ff register 1 (high) ff49 general t2gr1l r/w h'ff register 1 (low) ff4a general t2gr2h r/w h'ff register 2 (high) ff4b general t2gr2l r/w h'ff register 2 (low) ff4c dedicated t2dr1h r/w h'ff register 1 (high) ff4d dedicated t2dr1l r/w h'ff register 1 (low) ff4e dedicated t2dr2h r/w h'ff register 2 (high) ff4f dedicated t2dr2l r/w h'ff register 2 (low) 282
table 11-3 registers of channels 2 and 3 (cont) chan- abbre- initial nel address name viation r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value 3 ff50 timer control t3crh r/w ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 register (high) ff51 timer control t3crl r/w cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 register (low) ff52 timer status t3srh r/w ovie cmie2 cmie1 imie2 imie1 h'e0 register (high) ff53 timer status t3srl r/w ovf cmf2 cmf1 imf2 imf1 h'e0 register (low) ff54 timer output t3oer r/w doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 enable register ff56 timer counter t3cnth r/w h'00 register (high) ff57 timer counter t3cntl r/w h'00 register (low) ff58 general t3gr1h r/w h'ff register 1 (high) ff59 general t3gr1l r/w h'ff register 1 (low) ff5a general t3gr2h r/w h'ff register 2 (high) ff5b general t3gr2l r/w h'ff register 2 (low) ff5c dedicated t3dr1h r/w h'ff register 1 (high) ff5d dedicated t3dr1l r/w h'ff register 1 (low) ff5e dedicated t3dr2h r/w h'ff register 2 (high) ff5f dedicated t3dr2l r/w h'ff register 2 (low) 283
table 11-4 summarizes the registers of channels 4 and 5. table 11-4 registers of channels 4 and 5 chan- abbre- initial nel address name viation r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value 4 ff60 timer control t4crh r/w ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 register (high) ff61 timer control t4crl r/w cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 register (low) ff62 timer status t4srh r/w ovie cmie2 cmie1 imie2 imie1 h'e0 register (high) ff63 timer status t4srl r/w ovf cmf2 cmf1 imf2 imf1 h'e0 register (low) ff64 timer output t4oer r/w doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 enable register ff66 timer counter t4cnth r/w h'00 register (high) ff67 timer counter t4cntl r/w h'00 register (low) ff68 general t4gr1h r/w h'ff register 1 (high) ff69 general t4gr1l r/w h'ff register 1 (low) ff6a general t4gr2h r/w h'ff register 2 (high) ff6b general t4gr2l r/w h'ff register 2 (low) ff6c dedicated t4dr1h r/w h'ff register 1 (high) ff6d dedicated t4dr1l r/w h'ff register 1 (low) ff6e dedicated t4dr2h r/w h'ff register 2 (high) ff6f dedicated t4dr2l r/w h'ff register 2 (low) 284
table 11-4 registers of channels 4 and 5 (cont) chan- abbre- initial nel address name viation r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value 5 ff70 timer control t5crh r/w ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 register (high) ff71 timer control t5crl r/w cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 register (low) ff72 timer status t5srh r/w ovie cmie2 cmie1 imie2 imie1 h'e0 register (high) ff73 timer status t5srl r/w ovf cmf2 cmf1 imf2 imf1 h'e0 register (low) ff74 timer output t5oer r/w doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 enable register ff76 timer counter t5cnth r/w h'00 register (high) ff77 timer counter t5cntl r/w h'00 register (low) ff78 general t5gr1h r/w h'ff register 1 (high) ff79 general t5gr1l r/w h'ff register 1 (low) ff7a general t5gr2h r/w h'ff register 2 (high) ff7b general t5gr2l r/w h'ff register 2 (low) ff7c dedicated t5dr1h r/w h'ff register 1 (high) ff7d dedicated t5dr1l r/w h'ff register 1 (low) ff7e dedicated t5dr2h r/w h'ff register 2 (high) ff7f dedicated t5dr2l r/w h'ff register 2 (low) 285
11.4.2 timer control register (low) timer control register low (tcrl) is an eight-bit readable/writable register. for timer control register high (tcrh), see section 11.3.2, ?imer control register (high).? the bit structure of tcrl in channels 2 to 5 is shown next. (1) bits 7 and 6 ?eserved: read-only bits, always read as 1. (2) bits 5 and 4?ounter clear 1 and 0 (cclr1/0): these bits select the counter clear source. when cclr1 = cclr0 = 1, the counter is cleared in synchronization with the clearing of the paired timer selected in timer mode register a. if gr1 is used as a compare register the counter is cleared by compare match. if gr1 is used as a capture register the counter is cleared by input capture. bit initial value r/w 7 1 ieg21 543210 1000000 r/w r/w r/w r/w r/w r/w 6 cclr1 cclr0 ieg20 ieg11 ieg10 tcrl input capture edge 21/20/11/10 these bits select register functions and the valid edges of input capture signals counter clear 1/0 these bits select the counter clear source reserved bits bit 5 bit 4 cclr1 cclr0 description 0 0 counter not cleared (initial value) 0 1 counter cleared on gr1 compare match or capture 1 0 counter cleared on dr2 compare match * 1 1 synchronous clearing of counter enabled note: * in channels 6 and 7 the counter is cleared on gr2 compare match or capture. 286
for further details, see section 11.8.4, ?ounter clearing function?and section 11.8.6, ?ynchronizing mode. (3) bits 3 and 2?nput capture edge 21/20 (ieg21/20): these bits select the function of gr2 and the valid edge of the input capture signal. a reset clears bits ieg21 and ieg20 to 0, disabling input capture and making gr2 an output compare register. if ieg21 or ieg20 is set to 1, or both ieg21 and ieg20 are set to 1, gr2 becomes an input capture register. for further details, see section 11.8.3, ?nput capture function. (4) bits 1 and 0?nput capture edge 11/10 (ieg11/10): these bits select the function of gr1 and the valid edge of the input capture signal. a reset clears bits ieg11 and ieg10 to 0, disabling input capture and making gr1 an output compare register. if ieg11 or ieg10 is set to 1, or both ieg11 and ieg10 are set to 1, gr1 becomes an input capture register. for further details, see section 11.8.3, ?nput capture function. bit 3 bit 2 ieg21 ieg20 description 0 0 gr2 is not used for input capture (initial value) * 0 1 gr2 captures rising edge of input capture signal 1 0 gr2 captures falling edge of input capture signal 1 1 gr2 captures both edges of input capture signal note: * gr2 becomes an output compare register. bit 1 bit 0 ieg11 ieg10 description 0 0 gr1 is not used for input capture (initial value) * 0 1 gr1 captures rising edge of input capture signal 1 0 gr1 captures falling edge of input capture signal 1 1 gr1 captures both edges of input capture signal note: * gr1 becomes an output compare register. 287
11.4.3 timer status register (high) timer status register high (tsrh) is an eight-bit readable/writable register. after ovie, cmie2, cmie1, imie2, or imie1 is set to 1 in tsrh, an interrupt is requested when ovf, cmf2, cmf1, imf2, or imf1 is set to 1 in tsrl. the bit structure of tsrh in channels 2 to 5 is shown next. (1) bits 7 to 5?eserved: read-only bits, always read as 1. (2) bit 4?verflow interrupt enable (ovie): enables or disables the counter overflow interrupt. for further details, see section 11.9.1, ?nterrupt timing. bit initial value r/w 7 1 cmie2 543210 1100000 r/w r/w r/w r/w r/w 6 ovie cmie1 imie2 imie1 tsrh reserved bits input capture/ compare match interrupt enable 2/1 these bits enable and disable gr2 and gr1 compare match and input capture interrupts compare match interrupt enable 2/1 these bits enable and disable dr2 and dr1 compare match interrupts overflow interrupt enable enables or disables timer overflow interrupts bit 4 ovie description 0 counter overflow interrupt is disabled (initial value) 1 counter overflow interrupt is enabled 288
(3) bit 3?ompare match interrupt enable 2 (cmie2): enables or disables the dr2 compare match interrupt. for further details, see section 11.9.1, ?nterrupt timing. (4) bit 2?ompare match interrupt enable 1 (cmie1): enables or disables the dr1 compare match interrupt. for further details, see section 11.9.1, ?nterrupt timing. (5) bit 1?nput capture/compare match interrupt enable 2 (imie2): enables or disables the gr2 compare match or input capture interrupt. for further details, see section 11.9.1, ?nterrupt timing. (6) bit 0?nput capture/compare match interrupt enable 1 (imie1): enables or disables the gr1 compare match or input capture interrupt. for further details, see section 11.9.1, ?nterrupt timing. bit 3 cmie2 description 0 dr2 compare match interrupt is disabled (initial value) 1 dr2 compare match interrupt is enabled bit 2 cmie1 description 0 dr1 compare match interrupt is disabled (initial value) 1 dr1 compare match interrupt is enabled bit 1 imie2 description 0 gr2 input capture or compare match interrupt is disabled (initial value) 1 gr2 input capture or compare match interrupt is enabled bit 0 imie1 description 0 gr1 input capture or compare match interrupt is disabled (initial value) 1 gr1 input capture or compare match interrupt is enabled 289
11.4.4 timer status register (low) timer status register low (tsrl) is an eight-bit readable/writable register. after ovie, cmie2, cmie1, imie2, or imie1 is set to 1 in tsrh, an interrupt is requested when ovf, cmf2, cmf1, imf2, or imf1 is set to 1 in tsrl. writing to tsrl is restricted to clearing a flag to 0 after reading the 1 value of that flag. the bit structure of tsrl in channels 2 to 5 is shown next. (1) bits 7 to 5?eserved: read-only bits, always read as 1. (2) bit 4?verflow flag (ovf): set to 1 when the counter overflows from h'ffff to h'0000. for further details, see section 11.9.1, ?nterrupt timing. bit initial value r/w 7 1 cmf2 543210 1100000 r/w r/w r/w r/w r/w 6 ovf cmf1 imf2 imf1 tsrl input capture/ compare match flag 2/1 flags indicating gr2 and gr1 compare match or input capture compare match flag 2/1 flags indicating dr2 and dr1 compare match overflow flag flag indicating counter overflow reserved bits bit 4 ovf description 0 cleared by reading ovf after ovf is set to 1, then writing 0 in ovf (initial value) 1 set when counter overflow occurs 290
(3) bit 3?ompare match flag 2 (cmf2): set to 1 when the counter value matches the dr2 value. for further details, see section 11.9.1, ?nterrupt timing. (4) bit 2?ompare match flag 1 (cmf1): set to 1 when the counter value matches the dr1 value. for further details, see section 11.9.1, ?nterrupt timing. (5) bit 1?nput capture/compare match flag 2 (imf2): set to 1 when the counter value matches the gr2 value, or the counter value is captured to gr2. for further details, see section 11.9.1, ?nterrupt timing. (6) bit 0?nput capture/compare match flag 1 (imf1): set to 1 when the counter value matches the gr1 value, or the counter value is captured to gr1. for further details, see section 11.9.1, ?nterrupt timing. bit 2 cmf1 description 0 1. cleared by reading cmf1 after cmf1 is set to 1, then writing 0 in cmf1 (initial value) 2. cleared when the dtc is activated by a cmi1 interrupt 1 set when dr1 compare match occurs bit 1 imf2 description 0 1. cleared by reading imf2 after imf2 is set to 1, then writing 0 in imf2 (initial value) 2. cleared when the dtc is activated by an imi2 interrupt 1 set when gr2 input capture or compare match occurs bit 0 imf1 description 0 1. cleared by reading imf1 after imf1 is set to 1, then writing 0 in imf1 (initial value) 2. cleared when the dtc is activated by an imi1 interrupt 1 set when gr1 input capture or compare match occurs bit 3 cmf2 description 0 1. cleared by reading cmf2 after cmf2 is set to 1, then writing 0 in cmf2 (initial value) 2. cleared when the dtc is activated by a cmi2 interrupt 1 set when dr2 compare match occurs 291
11.4.5 timer output enable register the timer output enable register (toer) is an eight-bit readable/writable register. the bit structure of toer in channels 2 to 5 is shown next. for the selection of general register (gr) functions, see section 11.3.3, ?imer control register (low). (1) bits 7 and 6?edicated register output enable 21/20 (doe21/20): these bits enable and disable output of the counter-dr2 compare match signal, and select the output level. for further details, see section 11.8.2, ?election of output level. bit initial value r/w 7 0 doe21 goe21 doe20 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 doe11 doe10 goe20 goe11 goe10 toer general register output enable 11/10 these bits enable and disable output of the counter-gr1 compare match signal, and select the output level general register output enable 21/20 these bits enable and disable output of the counter-gr2 compare match signal, and select the output level dedicated register output enable 11/10 these bits enable and disable output of the counter-dr1 compare match signal, and select the output level dedicated register output enable 21/20 these bits enable and disable output of the counter-dr2 compare match signal, and select the output level bit 7 bit 6 doe21 doe20 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 1 1 toggle on compare match * note: * channels 2 and 3 do not have an output toggle function. if these bits are set to 11, the output goes to 1 on compare match. 292
(2) bits 5 and 4?edicated register output enable 11/10 (doe11/10): these bits enable and disable output of the counter-dr1 compare match signal, and select the output level. for further details, see section 11.8.2, ?election of output level. (3) bits 3 and 2?eneral register output enable 21/20 (goe21/20): these bits enable and disable output of the counter-gr2 compare match signal, and select the output level. when gr2 is used for input capture, however, compare match signal output is disabled regardless of the setting of goe21 and goe20. bits 3 and 2 are thus ignored except when ieg21 = ieg20 = 0. for further details, see section 11.8.2, ?election of output level. bit 5 bit 4 doe11 doe10 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 1 1 toggle on compare match * note: * channels 2 and 3 do not have an output toggle function. if these bits are set to 11, the output goes to 1 on compare match. bit 3 bit 2 goe21 goe20 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 1 1 toggle on compare match * note: * channels 2 and 3 do not have an output toggle function. if these bits are set to 11, the timer outputs 1 on compare match. 293
(4) bits 1 and 0?eneral register output enable 11/10 (goe11/10): these bits enable and disable output of the counter-gr1 compare match signal, and select the output level. when gr1 is used for input capture, however, compare match signal output is disabled regardless of the setting of goe11 and goe10. bits 1 and 0 are thus ignored except when ieg11 = ieg10 = 0. for further details, see section 11.8.2, ?election of output level. bit 1 bit 0 goe11 goe10 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 1 1 toggle on compare match * note: * channels 2 and 3 do not have an output toggle function. if these bits are set to 11, the timer outputs 1 on compare match. 294
11.5 channel 6 and 7 registers channels 6 and 7 each have two general registers used for output compare and input capture. the general registers function as output compare registers after a reset. they can be switched over to input capture by setting bits ieg21 to ieg10 in the timer control registers. each of channels 6 and 7 can simultaneously measure two waveforms and generate one waveform. channels 6 and 7 can each be used to measure waveforms in programmed periodic counting mode. the timer counter in channel 7 can count up or down according to the phase of two external clock signals in phase counting mode. channels 6 and 7 can provide single-phase pwm output in pwm output mode. see section 11.8, ?xamples of timer operation?for details. figure 11-4 shows a block diagram of channels 6 and 7. figure 11-4 block diagram of channels 6 and 7 on-chip data bus bus interface tcrh * 1 tsrh toer tcrl * 2 tsrl control registers t6ioc 1 ?6ioc 2 module data bus clock selector control logic comparator tclk1? ?4096 16-bit counter gr1 (icr/ocr) gr2 (icr/ocr) gr1 and gr2: output compare/input capture registers (16 bits 2) tcrh and tcrl: timer control registers (8 bits 2) tsrh and tsrl: timer status registers (8 bits 2) toer: timer output enable register (8 bits) note: the diagram shows 16-bit timer channel 6. for tcrh, see section 11.3.2, ?imer control register (high). for tcrl, see section 11.4.2, ?imer control register (high). notes: 1. 2. 295
11.5.1 register configuration table 11-5 summarizes the registers of channels 6 and 7. table 11-5 registers of channels 6 and 7 chan- abbre- initial nel address name viation r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value 6 ff80 timer control t6crh r/w ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 register (high) ff81 timer control t6crl r/w cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 register (low) ff82 timer status t6srh r/w ovie imie2 imie1 h'f8 register (high) ff83 timer status t6srl r/w ?vf imf2 imf1 h'f8 register (low) ff84 timer output t6oer r/w goe21 goe20 goe11 goe10 h'f0 enable register ff86 timer counter t6cnth r/w h'00 register (high) ff87 timer counter t6cntl r/w h'00 register (low) ff88 general t6gr1h r/w h'ff register 1 (high) ff89 general t6gr1l r/w h'ff register 1 (low) ff8a general t6gr2h r/w h'ff register 2 (high) ff8b general t6gr2l r/w h'ff register 2 (low) 296
table 11-5 registers of channels 6 and 7 (cont) chan- abbre- initial nel address name viation r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value 7 ff90 timer control t7crh r/w ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 register (high) ff91 timer control t7crl r/w cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 register (low) ff92 timer status t7srh r/w ovie imie2 imie1 h'f8 register (high) ff93 timer status t7srl r/w ?vf imf2 imf1 h'f8 register (low) ff94 timer output t7oer r/w goe21 goe20 goe11 goe10 h'f0 enable register ff96 timer counter t7cnth r/w h'00 register (high) ff97 timer counter t7cntl r/w h'00 register (low) ff98 general t7gr1h r/w h'ff register 1 (high) ff99 general t7gr1l r/w h'ff register 1 (low) ff9a general t7gr2h r/w h'ff register 2 (high) ff9b general t7gr2l r/w h'ff register 2 (low) 297
11.5.2 timer status register (high) timer status register high (tsrh) is an eight-bit readable/writable register. after ovie, imie2, or imie1 is set to 1 in tsrh, an interrupt is requested when ovf, imf2, or imf1 is set to 1 in tsrl. for timer control register high and low, see section 11.3.2, ?imer control register (high)?and section 11.4.2, ?imer control register (low).? the bit structure of tsrh in channels 6 and 7 is shown next. (1) bits 7 to 3?eserved: read-only bits, always read as 1. (2) bit 2?verflow interrupt enable (ovie): enables or disables the counter overflow interrupt. for further details, see section 11.9.1, ?nterrupt timing. bit initial value r/w 7 1 543210 1111000 r/w r/w r/w 6 ovie imie2 imie1 tsrh input capture/ compare match interrupt enable 2/1 these bits enable and disable compare match and input capture interrupts overflow interrupt enable enables or disables timer overflow interrupts reserved bits bit 2 ovie description 0 counter overflow interrupt is disabled (initial value) 1 counter overflow interrupt is enabled 298
(3) bit 1?nput capture/compare match interrupt enable 2 (imie2): enables or disables the gr2 compare match or input capture interrupt. for further details, see section 11.9.1, ?nterrupt timing. (4) bit 0?nput capture/compare match interrupt enable 1 (imie1): enables or disables the gr1 compare match or input capture interrupt. for further details, see section 11.9.1, ?nterrupt timing. bit 0 imie1 description 0 gr1 input capture or compare match interrupt is disabled (initial value) 1 gr1 input capture or compare match interrupt is enabled bit 1 imie2 description 0 gr2 input capture or compare match interrupt is disabled (initial value) 1 gr2 input capture or compare match interrupt is enabled 299
11.5.3 timer status register (low) timer status register low (tsrl) is an eight-bit readable/writable register. after ovie, imie2, or imie1 is set to 1 in tsrh, an interrupt is requested when ovf, imf2, or imf1 is set to 1 in tsrl. writing to tsrl is restricted to clearing a flag to 0 after reading the 1 value of that flag. the bit structure of tsrl in channels 6 and 7 is shown next. (1) bits 7 to 3?eserved: read-only bits, always read as 1. (2) bit 2?verflow flag (ovf): set to 1 when the counter overflows from h'ffff to h'0000 or when the counter in channel 7 underflows from h'0000 to h'ffff in phase counting mode. for further details, see section 11.9.1, ?nterrupt timing. bit initial value r/w 7 1 543210 1111000 r/w r/w r/w 6 ovf imf2 imf1 tsrl input capture/ compare match interrupt enable 2/1 flags indicating gr2 and gr1 compare match or input capture overflow flag flag indicating counter overflow reserved bits bit 2 ovf description 0 cleared by reading ovf after ovf is set to 1, then writing 0 in ovf (initial value) 1 set when counter overflow occurs 300
(3) bit 1?nput capture/compare match flag 2 (imf2): set to 1 when the counter value matches the gr2 value, or the counter value is captured to gr2. for further details, see section 11.9.1, ?nterrupt timing. (4) bit 0?nput capture/compare match flag 1 (imf1): set to 1 when the counter value matches the gr1 value, or the counter value is captured to gr1. for further details, see section 11.9.1, ?nterrupt timing. bit 1 imf2 description 0 1. cleared by reading imf2 after imf2 is set to 1, then writing 0 in imf2 (initial value) 2. cleared when the dtc is activated by an imi2 interrupt 1 set when gr2 input capture or compare match occurs bit 0 imf1 description 0 1. cleared by reading imf1 after imf1 is set to 1, then writing 0 in imf1 (initial value) 2. cleared when the dtc is activated by an imi1 interrupt 1 set when gr1 input capture or compare match occurs 301
11.5.4 timer output enable register the timer output enable register (toer) is an eight-bit readable/writable register. the bit structure of toer in channels 6 and 7 is shown next. for the selection of general register (gr) functions, see section 11.3.3, ?imer control register (low). (1) bits 7 to 4?eserved: read-only bits, always read as 1. bit initial value r/w 7 1 goe21 543210 1110000 r/w r/w r/w r/w 6 goe20 goe11 goe10 toer general register output enable 11/10 these bits enable and disable output of the counter-gr1 compare match signal, and select the output level general register output enable 21/20 these bits enable and disable output of the counter-gr2 compare match signal, and select the output level reserved bits 302
(2) bits 3 and 2?eneral register output enable 21/20 (goe21/20): these bits enable and disable output of the counter-gr2 compare match signal, and select the output level. when gr2 is used for input capture, however, compare match signal output is disabled regardless of the setting of goe21 and goe20. bits 3 and 2 are thus ignored except when ieg21 = ieg20 = 0. for further details, see section 11.8.2, ?election of output level. (3) bits 1 and 0?eneral register output enable 11/10 (goe11/10): these bits enable and disable output of the counter-gr1 compare match signal, and select the output level. when gr1 is used for input capture, however, compare match signal output is disabled regardless of the setting of goe11 and goe10. bits 1 and 0 are thus ignored except when ieg11 = ieg10 = 0. for further details, see section 11.8.2, ?election of output level. bit 1 bit 0 goe11 goe10 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 bit 3 bit 2 goe21 goe20 description 0 0 compare match signal output is disabled (initial value) 0 1 output 0 on compare match 1 0 output 1 on compare match 11 303
11.6 ipu register descriptions 11.6.1 timer mode register a timer mode register a (tmdra) is an eight-bit readable/writable register that selects timer synchronizing and operating modes. the bit structure of tmdra is shown next. (1) bit 7?imer mode 6-7 (md6-7): operates channels 6 and 7 in programmed periodic counting mode. the counter value in channel 7 is captured to gr1 in channel 7 at intervals set in gr2 in channel 6. if channel 7 is externally clocked, the number of external events occurring in regular intervals timed by channel 6 can be counted. for further details see section 11.8.8, ?rogrammed periodic counting mode. bit initial value r/w 7 0 md6-7 sync3 md4-7 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 md3-5 md2-6 sync2 sync1 sync0 tmdra timer synchronizing bits 3-0 these bits synchronize two timers timer mode 6-7, 4-7, 3-5, 2-6 these bits operate two timers in programmed periodic counting mode bit 7 md6-7 description 0 timers 6 and 7 operate normally (initial value) 1 timers 6 and 7 operate in programmed periodic counting mode 304
(2) bit 6?imer mode 4-7 (md4-7): operates channels 4 and 7 in programmed periodic counting mode. the counter value in channel 7 is captured to gr2 in channel 7 at intervals set in dr2 in channel 4. if channel 7 is externally clocked, the number of external events occurring in regular intervals timed by channel 4 can be counted. for further details see section 11.8.8, ?rogrammed periodic counting mode. (3) bit 5?imer mode 3-5 (md3-5): operates channels 3 and 5 in programmed periodic counting mode. the counter value in channel 5 is captured to gr1 in channel 5 at intervals set in dr2 in channel 3. if channel 5 is externally clocked, the number of external events occurring in regular intervals timed by channel 3 can be counted. for further details see section 11.8.8, ?rogrammed periodic counting mode. (4) bit 4?imer mode 2-6 (md2-6): operates channels 2 and 6 in programmed periodic counting mode. the counter value in channel 6 is captured to gr1 in channel 6 at intervals set in dr2 in channel 2. if channel 6 is externally clocked, the number of external events occurring in regular intervals timed by channel 2 can be counted. for further details see section 11.8.8, ?rogrammed periodic counting mode. bit 6 md4-7 description 0 timers 4 and 7 operate normally (initial value) 1 timers 4 and 7 operate in programmed periodic counting mode bit 5 md3-5 description 0 timers 3 and 5 operate normally (initial value) 1 timers 3 and 5 operate in programmed periodic counting mode bit 4 dm2-6 description 0 timers 2 and 6 operate normally (initial value) 1 timers 2 and 6 operate in programmed periodic counting mode 305
(5) bit 3?imer synchronizing bit 3 (sync3): synchronizes two timer channels. when sync3 = 1, timer counters can be preset and cleared in synchronization. if two or more bits among sync3, sync2, sync1, and sync0 are set to 1 simultaneously, all selected timer counters are synchronized. for further details, see section 11.8.6 ?ynchronizing mode. (6) bit 2?imer synchronizing bit 2 (sync2): synchronizes two timer channels. when sync2 = 1, timer counters can be preset and cleared in synchronization. if two or more bits among sync3, sync2, sync1, and sync0 are set to 1 simultaneously, all selected timer counters are synchronized. for further details, see section 11.8.6 ?ynchronizing mode. (7) bit 1?imer synchronizing bit 1 (sync1): synchronizes two timer channels. when sync1 = 1, timer counters can be preset and cleared in synchronization. if two or more bits among sync3, sync2, sync1, and sync0 are set to 1 simultaneously, all selected timer counters are synchronized. for further details, see section 11.8.6 ?ynchronizing mode. (8) bit 0?imer synchronizing bit 0 (sync0): synchronizes two timer channels. bit 3 sync3 description 0 timer counters in channels 6 and 7 operate independently (initial value) 1 timer counters in channels 6 and 7 are synchronized bit 2 sync2 description 0 timer counters in channels 4 and 5 operate independently (initial value) 1 timer counters in channels 4 and 5 are synchronized bit 1 sync1 description 0 timer counters in channels 2 and 3 operate independently (initial value) 1 timer counters in channels 2 and 3 are synchronized bit 0 sync0 description 0 timer counters in channel 1 and other channels operate independently (initial value) 1 timer counters in channel 1 and other channels are synchronized 306
when sync0 = 1, timer counters can be preset and cleared in synchronization. if two or more bits among sync3, sync2, sync1, and sync0 are set to 1 simultaneously, all selected timer counters are synchronized. for further details, see section 11.8.6 ?ynchronizing mode. 11.6.2 timer mode register b timer mode register b (tmdrb) is an eight-bit readable/writable register that selects timer operating modes. the bit structure of tmdrb is shown next. (1) bits 7 and 6?eserved: read-only bits, always read as 1. (2) bit 5?hase counting mode (mdf): operates channel 7 in phase counting mode. for further details see section 11.8.9, ?hase counting mode. bit initial value r/w 7 1 pwm3 543210 1000000 r/w r/w r/w r/w r/w r/w 6 mdf pwm4 pwm2 pwm1 pwm0 tmdrb pwm timer mode 4-0 these bits operate channels 7, 6, 3, 2, and 1 as pulse-width modulators phase counting mode operates channel 7 in phase counting mode reserved bits bit 5 mdf description 0 channel 7 operates normally (initial value) 1 channel 7 operates in phase counting mode 307
(3) bit 4?wm timer mode 4 (pwm4): operates channel 7 as a pulse-width modulator. channel 7 operates as a pulse-width modulator with independent period and duty cycle, providing one pwm output. when pwm4 = 1, settings of goe11 and goe10 in the channel 7 timer output enable register (toer) are ignored. for further details, see section 11.8.5 ?wm output mode. (4) bit 3?wm timer mode 3 (pwm3): operates channel 6 as a pulse-width modulator. channel 6 operates as a pulse-width modulator with independent period and duty cycle, providing one pwm output. when pwm3 = 1, settings of goe11 and goe10 in the channel 6 timer output enable register (toer) are ignored. for further details, see section 11.8.5 ?wm output mode. (5) bit 2?wm timer mode 2 (pwm2): operates channel 3 as a pulse-width modulator. channel 3 operates as a pulse-width modulator with independent period and duty cycle. channel 3 can provide two-phase pwm output. when pwm2 = 1, settings of goe21, goe20, goe11, and goe10 in the channel 3 timer output enable register (toer) are ignored. for further details, see section 11.8.5 ?wm output mode. bit 3 pwm3 description 0 channel 6 operates normally (initial value) 1 channel 6 operates as a pulse-width modulator bit 2 pwm2 description 0 channel 3 operates normally (initial value) 1 channel 3 operates as a pulse-width modulator bit 4 pwm4 description 0 channel 7 operates normally (initial value) 1 channel 7 operates as a pulse-width modulator 308
(6) bit 1?wm timer mode 1 (pwm1): operates channel 2 as a pulse-width modulator. channel 2 operates as a pulse-width modulator with independent period and duty cycle. channel 2 can provide two-phase pwm output. when pwm1 = 1, settings of goe21, goe20, goe11, and goe10 in the channel 2 timer output enable register (toer) are ignored. for further details, see section 11.8.5 ?wm output mode. (7) bit 0?wm timer mode 0 (pwm0): operates channel 1 as a pulse-width modulator. channel 1 operates as a pulse width modulator with independent period and duty cycle. channel 1 can provide three-phase pwm output. when pwm0 = 1, settings of doe11, doe10, goe21, goe20, goe11, and goe10 in the channel 1 timer output enable register (toer) are ignored. for further details, see section 11.8.5 ?wm output mode. bit 0 pwm0 description 0 channel 1 operates normally (initial value) 1 channel 1 operates as a pulse-width modulator bit 1 pwm1 description 0 channel 2 operates normally (initial value) 1 channel 2 operates as a pulse-width modulator 309
11.6.3 timer start register the timer start register (tstr) is an eight-bit readable/writable register that starts and stops the counters. the bit structure of tstr is shown next. (1) bit 7?eserved: read-only bit, always read as 1. (2) bit 6?ounter start 7 (str7): starts and stops the counter in channel 7. (3) bit 5?ounter start 6 (str6): starts and stops the counter in channel 6. (4) bit 4?ounter start 5 (str5): starts and stops the counter in channel 5. bit 4 str5 description 0 timer counter 5 is halted (initial value) 1 timer counter 5 is counting bit 5 str6 description 0 timer counter 6 is halted (initial value) 1 timer counter 6 is counting bit 6 str7 description 0 timer counter 7 is halted (initial value) 1 timer counter 7 is counting bit initial value r/w 7 1 str4 str7 543210 0000000 r/w r/w r/w r/w r/w r/w r/w 6 str6 str5 str3 str2 str1 tstr counter start 7 to 1 reserved bit these bits start and stop the counters 310
(5) bit 3?ounter start 4 (str4): starts and stops the counter in channel 4. (6) bit 2?ounter start 3 (str3): starts and stops the counter in channel 3. (7) bit 1?ounter start 2 (str2): starts and stops the counter in channel 2. (8) bit 0?ounter start 1 (str1): starts and stops the counter in channel 1. bit 0 str1 description 0 timer counter 1 is halted (initial value) 1 timer counter 1 is counting bit 1 str2 description 0 timer counter 2 is halted (initial value) 1 timer counter 2 is counting bit 2 str3 description 0 timer counter 3 is halted (initial value) 1 timer counter 3 is counting bit 3 str4 description 0 timer counter 4 is halted (initial value) 1 timer counter 4 is counting 311
11.7 h8/500 cpu interface some ipu registers can be accessed 16 bits at a time, while others are limited to eight-bit access. these two types of registers differ in their write timing, as explained next. 11.7.1 16-bit accessible registers the timer counters (tcnt), general registers (gr), and dedicated registers (dr) are 16-bit registers. the h8/500 cpu can access these registers a word at a time using a 16-bit data bus. byte access is also possible. figure 11-5 shows an example of word write timing to a timer counter. figure 11-6 shows an example of byte write timing to a timer counter. figure 11-5 example of word write timing for timer counter t 1 t 2 t 3 new value old value new value timer counter address a 19 ? 0 internal write signal internal data bus timer counter value 312
figure 11-6 example of byte write timing for timer counter read and write operations: timer counters, general registers, and dedicated registers can be written and read a word at a time or a byte at a time. figure 11-7 illustrates word read/write operations. figure 11-8 illustrates upper byte read/write operations. figure 11-9 illustrates lower byte read/write operations. figure 11-7 word read/write operations t 1 t 2 t 3 t 3 t 2 t 1 internal write signal internal data bus timer counter value low address high address new value new value old value lower byte only upper byte only a 19 ? 0 16 16 8 8 h8/500 cpu on-chip data bus bus interface module data bus high address low address 313
figure 11-8 upper byte read/write operations figure 11-9 lower byte read/write operations 16 16 8 h8/500 cpu on-chip data bus bus interface high address low address module data bus 16 16 8 h8/500 cpu on-chip data bus bus interface high address low address module data bus 314
11.7.2 eight-bit accessible registers the ipus timer control registers (tcrh, tcrl, and tcra), timer status registers (tsrh and tsrl), timer output enable registers (toer), timer mode register a (tmda), timer mode register b (tmdb), and timer start register (tstr) are eight-bit registers. the h8/500 cpu accesses these registers a byte at a time using an eight-bit data bus. if an instruction specifies word size, two registers are accessed at consecutive addresses, upper byte (even address) first and lower byte (odd address) second. figure 11-10 shows an example of byte write timing to a timer control register. figure 11-11 shows an example of write timing to a timer control register by an instruction specifying word operand size. figure 11-10 example of byte write timing for timer control register t 1 t 2 t 3 new value old value new value timer control register address a 19 ? 0 internal write signal internal data bus timer control register value 315
figure 11-11 example of write timing for timer control register by instruction specifying word operand size read and write operations: table 11-6 lists the byte-accessed registers. figure 11-12 illustrates upper byte read/write operations. figure 11-13 illustrates lower byte read/write operations. table 11-6 eight-bit access registers t 1 t 2 t 3 t 1 t 2 t 3 a 19 ? 0 internal write signal internal data bus timer control register value tcrh address tcrl address new value new value old value updated tcrh updated tcrl abbreviation name byte access word access timer control registers (high) tcrh tcr upper timer control registers (low) tcrl lower timer status registers (high) tsrh tsr upper timer status registers (low) tsrl lower timer output enable registers toer toer upper timer mode registers tmdr tmdr lower timer start registers tstr tstr upper t1crb lower 316
figure 11-12 upper byte read/write operations figure 11-13 lower byte read/write operations 8 8 8 h8/500 cpu on-chip data bus bus interface high address low address module data bus 8 8 8 h8/500 cpu on-chip data bus bus interface high address low address module data bus 317
11.8 examples of timer operation the 16-bit integrated-timer pulse unit (ipu) has several application-oriented operating modes. these are outlined and examples are given below. 11.8.1 examples of counting when a start (str) bit in the timer start register (tstr) is set to 1, the corresponding counter starts counting from h'0000. there are two counting modes: a free-running mode and a periodic mode. figure 11-14 shows the procedure for selecting the counting mode. procedure for selecting counting mode figure 11-14 procedure for selecting counting mode 3 3 2 1 1 2 str bit = 1 set period in dr or gr select clear source cclr 1 00

set the counter? str bit in tstr to 1. periodic counter: set the count period in a dedicated or general register and select the clear source in tcrh. free-running counter: no need to set count period or select clear source. counting mode selection free-running counter periodic counter 318
counter operation: figure 11-15 illustrates counter operations. figure 11-15 counter operation no yes ovf = 1 yes yes no no 5 1 4 2 6 3 str = 1? when an str bit is set to 1, the corresponding counter starts counting up. periodic counter: after incrementing, the counter value is checked against the count period. periodic counter: if the counter value matches the count period, the cmf or imf bit in tsrl is set to 1. free-running counter: after incrementing, counter overflow is checked. free-running counter: if the count has overflowed, the ovf bit in tsrl is set to 1. the timer counter is reset and starts counting up again from zero. periodic counter free-running counter compare match? * overflow? note: * tcnt = count period cmf/imf = 1 tcnt ? 0 1 2 3 4 5 6 hold value counter operation 319
a reset leaves the ipu in free-running mode. figure 11-16 shows an example of free-running counting. the counter starts from h'0000, counts up to h'ffff, then returns to h'0000, at which point the ovf flag is set in timer status register high (tsrh). counting then continues from h'0000. if compare match is selected as a counter clear source, the ipu operates in periodic counting mode. figure 11-17 shows an example of periodic counting. the counter starts from h'0000 and counts up to h'8000. at this point a compare match with dr2 occurs, so the cmf2 flag in tsrh is set to 1 and the counter is automatically cleared. counting then continues from h'0000. figure 11-16 free-running counter operation figure 11-17 periodic counter operation h'0001 h'fffe h'ffff h'0000 h'0001 h'0000 timer counter value str bit (tstr) ovf flag (tsrh) counting starts when str bit is set to 1 overflow flag (ovf) is set when count changes from h'ffff to h'0000 h'7fff h'0001 h'8000 h'ffff h'0000 h'0002 * note: * h'8000 timer counter value str bit (tstr) cmf2 flag (tsrh) dr2 value counting starts when str bit is set to 1 compare match with dr2 sets compare match flag 2 (cmf2) and clears counter cycle length h'8000 is set in dr2 h'0000 h'0001 320
11.8.2 selection of output level compare match signals can be output in three modes: high, low, or toggle. figure 11-18 shows the procedure for selecting the output level. procedure for selecting output level figure 11-18 procedure for selecting output level 1 2 3 4 5 select the counting mode. set a value in a dedicated or general register to select the pulse output time. low output: to have the output go low at compare match, set the goe or doe bits in the timer output enable register (toer) to 01. high output: to have the output go high at compare match, set the goe or doe bits in toer to 10. toggle output: to have the output toggle at compare match, set the goe or doe bits in toer to 11. toggle output is available only on channels 4 and 5. output selection select counting mode set compare value in dr or gr low output high output toggle output goe/doe = 11 (channel 4 or 5) goe/doe = 01 goe/doe = 10 1 2 3 4 5 321
waveform output operation: figure 11-19 illustrates waveform output operations. figure 11-19 waveform output 1 2 3 4 1 2 3 4 or waveform output low output cmf/imf = 1 pin level (low output) high output pin level (high output) toggle output pin level (toggles between low and high) cmf or imf bit in timer status register low (tsrl) is set to 1 at compare match. waveform is output according to setting of timer output enable register (toer). 322
figure 11-20 shows examples of waveform output on channel 4. high output is selected from t4ioc 1 , low output from t4ioc 2 , and toggle output from t4oc 1 . high output is selected by setting bits goe11 and goe10 to 10 in the channel 4 timer output enable register (toer). the ipu drives t4ioc 1 high when the counter matches the value in gr1 (h'0001). low output is selected by setting bits goe21 and goe20 to 01 in the channel 4 toer. the ipu drives t4ioc 2 low when the counter matches the value in gr2 (h'0003). toggle output is selected by setting bits doe11 and doe10 to 11 in the channel 4 toer. the ipu toggles t4oc 1 when the counter matches the value in dr1 (h'0004). the counter is cleared when the count matches the value in dr2 (h'00ff). if high or low output is selected, when compare match occurs, and if the pin is already at the selected output level, the output level does not change. settings toer (channel 4): h'36 tcrl (channel 4): h'e0 (clear on t4dr2 compare match) figure 11-20 example of waveform output on channel 4 0001 0002 0003 0004 00fe 0001 0002 0003 0004 0000 * h'0001 h'0003 h'0004 h'00ff note: * 00ff timer counter value gr1 value gr2 value dr1 value dr2 value output goes high at compare match output goes low at compare match counter is cleared at compare match output toggles at compare match t4ioc 1 (goe11/10 = 11) t4ioc 2 (goe21/20 = 01) t4oc 1 (goe11/10 = 10) 323
11.8.3 input capture function the counter value can be captured into a register when a transition occurs at an input capture pin. capture can take place on the rising edge, falling edge, or both edges. figure 11-21 shows the procedure for selecting the input capture function. procedure for selecting input capture mode figure 11-21 procedure for selecting capture input mode select the counting mode. capture on rising edge: to capture on the rising edge of the capture input signal, set the ieg bits in timer control register low (tcrl) to 01. capture on falling edge: to capture on the falling edge of the capture input signal, set the ieg bits in tcrl to 10. capture on both edges: to capture on both edges of the capture input signal, set the ieg bits in tcrl to 11. input selection select counting mode rising edge falling edge both edges ieg = 01 ieg = 10 ieg = 11 pin level (low input) pin level (high input) pin level (low or high input) 1 2 3 4 1 2 3 4 or 324
capture operation: figure 11-22 illustrates input capture operations. figure 11-22 capture mode operation the capture pin is monitored, and when the edge selected by the ieg bits in timer control register low (tcrl) is detected, the imf bit in timer status register low (tsrl) is set to 1. the counter value is transferred to and held in a general register (gr). capture operation imf bit = 1 counter value ? gr 1 2 1 2 325
figure 11-23 shows an example of pulse input capture at t1ioc 1 , t1ioc 2 , and t1ioc 3 on channel 1. the rising edge of t1ioc 1 is selected by setting bits ieg11 and ieg10 to 01 in channel 1 timer control register low (tcrl). the ipu transfers the counter value (h'0001 and h'0100) to gr1 on the rising edge of the t1ioc 1 input. the falling edge of t1ioc 2 is selected by setting bits ieg21 and ieg20 in channel 1 tcrl to 10. the ipu transfers the counter value (h'0002 and h'0102) to gr2 on the falling edge of the t1ioc 2 input. the rising and falling edges of t1ioc 3 are selected by setting bits ieg31 and ieg30 in channel 1 timer control register a (tcra) to 11. the ipu transfers the counter value (h'0004) on the rising edge and the value (h'0104) on the falling edge of the t1ioc 1 input to gr3. settings tcrl: h'89 tcra: h'f3 figure 11-23 example of input capture on channel 1 0003 0101 0103 0105 h'0000 h'0100 0001 0002 h'0002 h'0102 0100 0102 0004 0104 h'0004 h'0104 timer counter value h'0000 h'0000 h'0001 gr1 value gr2 value gr3 value t1ioc 1 (ieg11/10 = 01) t1ioc 2 (ieg21/20 = 10) t1ioc 3 (ieg31/30 = 11) 326
figure 11-24 shows an example of input capture timing on channel 2. the ipu latches the input capture signal input at the t2ioc 1 pin on the rising edge of the system clock (?. one system clock cycle (1.0t cyc ) after the input capture signal is latched, the counter value (n + 1) is transferred to t2gr1. the imf1 flag in timer status register low (tsrl) is set 1.5t cyc after the input capture signal is latched. the pulse width of the input capture signal must be at least 1.5t cyc . figure 11-24 capture input timing t tics m + 1 m + 1 m n + 1 h'ffff n n + 1 t tics internal capture signal t2ioc 1 tcnt2 t2gr1 imf1 (channel 2) minimum width: 1.5t cyc note: t tics : 50 ns (min) (initial value) 327
11.8.4 counter clearing function a counter can be cleared by input capture or compare match. when compare match is selected as a counter clear source, the count repeats cyclically from h'0000 to the value in the compare register. when input capture is selected as a counter clear source, the counter can be cleared at intervals determined by external events. figure 11-25 shows the procedure for selecting the counter clear source. procedure for selecting counter source figure 11-25 procedure for selecting counter clear source counter clear operation: figure 11-26 illustrates the counter clear operation. figure 11-26 counter clearing operation 1 2 set period in dr or gr set cclr = 01 (ieg = 00) or cclr = 10 * clear on compare match: to clear the counter on compare match, set the clear period in a dedicated or general register, then set the cclr bits in tcrl to 01 or 10. * (the counter operates as a periodic counter.) clear on capture: to clear the counter by input capture, select the input edge or edges in tcrl, then set the cclr bits to 01. * 1 2 cclr = 01 (ieg 1 00) * compare match capture select edge(s) selection of clear source note: * channels 2 to 7. when the counter clear source condition occurs, tcnt is reset to 0 and starts counting up again. if capture is selected, the counter value is first captured to a register, then the counter is cleared. 1 1 counter clear tcnt ? 0 328
figure 11-27 shows an example of counter clearing on channel 4. in this example the channel-4 counter is cleared by input capture at t4ioc 1 . this clear condition is selected by setting cclr1 and cclr0 in channel 4 timer control register low (tcrl) to 01. the rising edge is selected by setting ieg11 and ieg10 to 01. the ipu transfers the counter value (h'0003) on the rising edge of the t4ioc 1 input to gr1, then clears the counter. to clear the counter on dr2 compare match, set cclr1 and cclr0 to 10 in tcrl. settings tcrl (channel 4): h'd4 (to clear on input capture to t4gr1) tcrl (channel 4): h'e0 (to clear on compare match with t4dr2) figure 11-27 example of input counter clearing on channel 4 0001 0002 0001 00fe 0001 0002 0003 0004 0000 * h'0003 h'00ff 0000 h'0003 h'0000 note: * h'00ff timer counter value gr1 value dr2 value counter cleared by input capture counter cleared by compare match t4ioc 1 (ieg = 01) 329
11.8.5 pwm output mode channels 1, 2, 3, 6, and 7 can be used as pulse-width modulators. channel 1 can provide three- phase pwm output, channels 2 and 3 can provide two-phase pwm output, and channels 6 and 7 can provide single-phase pwm output. figure 11-28 shows the procedure for selecting pwm output mode. procedure for selecting pwm mode figure 11-28 procedure for selecting pwm output mode 1 2 3 select periodic counting (cclr 1 00) pwm bit = 1 1 2 3 first set the counting period, pulse set time, and pulse reset time in dedicated (dr) or general (gr) registers. select periodic counting and the counter clear source by setting the cclr bits in timer control register low (tcrl). set the pwm bit in timer mode register b (tmdrb) to 1. pwm mode selection set compare values in dr/gr 330
pwm output operation: figure 11-29 illustrates pwm output operations. figure 11-29 pwm output operation figure 11-30 shows an example of three-phase pwm output on channel 1. the u phase is output at the t1ioc 1 pin. the v phase is output at the t1ioc 2 pin. the w phase is output at the t1oc 1 pin. the ipu sets t1ioc 1 when the timer counter matches gr1 (h'0001), and resets t1ioc 1 when the timer counter matches gr3 (h'00fe). the ipu sets t1ioc 2 when the timer counter matches gr2 (h'0002), and resets t1ioc 2 when the timer counter matches gr4 (h'00fd). the ipu sets t1ioc 3 when the timer counter matches dr1 (h'0003), and resets t1ioc 3 when the timer counter matches dr3 (h'00fc). the ipu clears the counter when the timer counter matches dr4 (h'00ff). yes no u phase set time: the gr1 value is constantly compared with the tcnt value. u phase reset time: the gr3 value is constantly compared with the tcnt value. gr1-tcnt compare match generates a u phase set command. gr3-tcnt compare match generates a u phase reset command. contention decision: contention between u phase set and reset commands is tested; if contention occurs, the output level remains unchanged. if there is no set- reset contention, the output is set or reset. pwm output * u phase u phase set command u phase reset command contention? output remains unchanged u phase gr1: tcnt gr3: tcnt 1 2 3 4 5 6 1 2 3 4 5 6 note: * channel 1: example of u phase in 3-phase pwm output. 331
settings tmdrb: h'c1 (pwm output on channel 1) tcrl: h'f0 (clear on t1dr4 compare match) tcra: h'f0 figure 11-30 example of three-phase pwm output on channel 1 note: * h'00ff 0001 0003 00fe 0000 * h'0001 h'00fe 0002 00fd 00fc 00fb 0001 h'0002 h'00fd h'0003 h'00fc h'00ff 0000 * timer counter value gr1 value (u phase set ) gr3 value (u phase reset ) gr2 value (v phase set ) gr4 value (v phase reset ) dr1 value (w phase set ) dr3 value (w phase reset ) dr4 value (pwm period) t1ioc 1 (u phase) t1ioc 2 (v phase) t1oc 1 (w phase) counter is cleared by compare match pwm 332
in pwm mode the compare registers are paired: one register sets the pulse; the other register resets the pulse. the counter should be set to periodic counting mode. table 11-7 indicates the register pair assigned to each output pin. table 11-7 output pins and register pairs usage notes 1. in pwm output mode, the output levels of pwm output pins cannot be set in the timer output enable register (toer). any output level settings made will be ignored. 2. settings of the ieg bits in timer control register low (tcrl) are valid in pwm output mode. the ieg bits must be cleared to 0. 3. in pwm output mode, periodic counting should be used by selecting a counter clear source in tcrl. table 11-7 lists the registers that can set the pwm period in each channel. channel output pin set reset pwm period 1 t1ioc 1 gr1 gr3 dr2, gr3, dr4 t1ioc 2 gr2 gr4 t1oc 1 dr1 dr3 2 t2ioc 1 gr1 dr1 dr2 t2ioc 2 gr2 dr2 3 t3ioc 1 gr1 dr1 dr2 t3ioc 2 gr2 dr2 6 t6ioc 1 gr1 gr2 gr2 7 t7ioc 1 gr1 gr2 gr2 333
11.8.6 synchronizing mode in synchronizing mode two or more timer counters can be rewritten or cleared simultaneously. figure 11-31 shows the procedure for selecting synchronizing mode. procedure for selecting synchronizing mode figure 11-31 procedure for selecting synchronizing mode sync bit = 1 master or slave? select clear source: cclr bits = 00, 01, or 10 * slave master select synchronized clear: cclr bits = 11 * set desired sync bit(s) in tmdra to 1. synchronized preset: enabled by setting a sync bit to 1. synchronized clear: a function that clears one counter in synchronization with another counter. master: select the clear source. slave: select synchronized reset (cclr = 11). 1 2 3 4 5 selection of synchronizing mode synchronized preset synchronized clear 1 2 3 4 5 note: * channels 2 to 7 334
synchronized operation: figure 11-32 shows an example of synchronized operation of channels 2 and 3. figure 11-32 example of synchronized operation of channels 2 and 3 2 3 4 5 1 2 3 4 5 tcnt2 ? 0 tcnt3 ? 0 tcnt2 ? data tcnt3 ? data counter clear example of synchronized operation of channels 2 and 3 synchronized clear * when a counter clear condition occurs on channel 2, channel 3 is commanded to clear in synchronization. the counters in channels 2 and 3 are cleared simultaneously. example of synchronized operation of channels 2 and 3 synchronizing preset: writing to channel 2 or 3 writes the same value simultaneously into both counters. note: * note: * synchronizing preset * 1 335
figure 11-33 shows an example of the synchronization of timer counters 2 and 3. timer counters 2 and 3 are synchronized by setting the sync1 bit in timer mode register a (tmdra) to 1. the timer counters are synchronously preset by writing a new value to either timer counter 2 or 3; the ipu simultaneously writes the same value in the other timer counter. synchronized clearing is selected by setting cclr1 = cclr0 = 1 as the clear source for timer counter 3. the ipu clears timer counters 2 and 3 simultaneously when timer counter 2 matches t2gr1 (h'00ff). settings t2gr1: h'00ff tmdra: h'02 (sync1 = 1) tcrl (channel 2): h'd0 (clear at compare match with t2gr1) tcrl (channel 3): h'f0 (enabling synchronized clearing) figure 11-33 example of synchronization of timer counters 2 and 3 0001 0000 n 0000 m 0000 0000 0001 0001 00fe 0001 00fe 0001 0000 h'00ff h'ffff h'0000 h'0001 (sync1 =1) 0000 0002 * 1 * 1 n + 1 m + 2 timer counter 2 value timer counter 3 value t2gr1 value (channel 2) tmdra value write to tcnt2 write to tcnt3 write to tcnt2 and tcnt3 (synchronizing preset) tcnt2 and tcnt3 are simultaneously cleared by compare match * 2 timer counter 2 and timer counter 3 are not synchronized synchronization of timer counters 2 and 3 enabled timer counter 2 and timer counter 3 operate in synchronization h'00ff set cclr1 = cclr0 = 1 (synchronized clearing) as the clear source for timer counter 3. notes: 1. 2. 336
11.8.7 external event counting the ipu has three external clock input pins. if external event signals are input at these external clock input pins, external events can be counted. the counter can be set to increment on the rising or falling edge, or on both edges of the external clock signal. the value of an externally clocked counter can be captured at regular intervals to measure external event frequencies. figure 11-34 shows the procedure for selecting external event counting mode. procedure for selecting external event counting mode figure 11-34 procedure for selecting external event counting mode or input selection select external clock rising edge falling edge both edges pin level (high input) pin level (low input) pin level (low or high input) str bit = 1 1 2 3 4 5 ckeg1/0 = 00 ckeg1/0 = 01 ckeg1/0 = 10, 11 1 set the tpsc bits in timer control register high (tcrh) to select an external clock. count on rising edge: to count rising edges of the external clock signal, set bits ckeg1 and ckeg0 to 00 in tcrh. count on falling edge: to count falling edges of the external clock signal, set bits ckeg1 and ckeg0 to 01 in tcrh. count on both edges: to count both rising and falling edges of the external clock signal, set bits ckeg1 and ckeg0 to 10 or 11 in tcrh. counting starts when the corresponding str bit in the timer start register (tstr) is set to 1. 5 4 3 2 337
external event counting operation: counting operations are the same as for an internal clock. for details, see section 11.8.1, ?xamples of counting. figure 11-35 shows an example of external event counting. in this example timer counters 1, 2, and 3 count external event inputs at tclk 1 . in channel 1, the rising edge of tclk 1 is selected by setting the ckeg1 and ckeg0 bits in tcrh to 00. the ipu counts rising edges of tclk 1 . in channel 2, the falling edge of tclk 1 is selected by setting the ckeg1 and ckeg0 bits in tcrh to 01. the ipu counts falling edges of tclk 1 . in channel 3, both edges of tclk 1 are selected by setting the ckeg1 and ckeg0 bits in tcrh to 10 or 11. the ipu counts both rising and falling edges of tclk 1 . settings tcrh (channel 1): h'cd (count rising edges) tcrh (channel 2): h'dd (count falling edges) tcrh (channel 3): h'ed or h'fd (count both rising and falling edges) figure 11-35 example of external event counting tclk 1 h'0001 h'0002 h'0003 h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0001 h'0002 h'0003 h'0004 timer counter 1 value (ckeg = 00) timer counter 2 value (ckeg = 01) timer counter 3 value (ckeg = 10 or 11) incremented on rising edge of tclk 1 incremented on falling edge of tclk 1 incremented on both edges of tclk 1 338
figure 11-36 shows an example of external clock input timing. the ipu latches external clock signals (tclk 1 to tclk 3 ) on the rising edge of the system clock (?. tcnt2 is incremented 1.5 system clock cycles (1.5t cyc ) after the external clock is latched. the pulse width of the external clock signal must be at least 1.5t cyc . figure 11-36 external clock input timing m + 1 m n + 1 t tcks t tcks t tcks : 50 ns (min) tclk 1? internal counter clock minimum width: 1.5t cyc tcnt2 n 339
11.8.8 programmed periodic counting mode in programmed periodic counting mode, the value of an externally clocked counter is captured into a general register by compare match on a different channel. no external input capture signal is needed. figure 11-37 shows the procedure for selecting programmed periodic counting mode. procedure for selecting programmed periodic counting mode figure 11-37 procedure for selecting programmed periodic counting mode 1 2 3 4 setup procedure (channel 6) (channel 2) select external clock select edge(s) select clock source set measurement interval in dr2 select counter clear source md2-6 bit = 1 str bits = 1 1 2 3 4 measurement period setup channel 6: select external event counting mode. select the external clock and edge or edges in timer control register high (tcrh). channel 2: select the period for measuring channel 6. select the clock source in tcrh, then set the measure- ment period in dr2. select dr2 compare match as the counter clear source in timer control register low (tcrl). after setting up channels 2 and 6, set the md2-6 bit in tmdra to 1. operation begins when the str2 and str6 bits are set to 1 in the timer start register (tstr). external event counting 340
programmed periodic counting operation: figure 11-38 shows the programmed periodic counting operation. figure 11-38 operation in programmed periodic counting mode (channel 6) (channel 2) tcnt ? tcnt + 1 tcnt6 ? gr1 tcnt ? 0 1 3 4 2 channel 6: counts external events. channel 2: counts the measurement period and generates compare matches. when a compare match occurs on channel 2, the counter value in channel 6 is captured to gr1. the channel 2 counter is cleared to 0 and starts counting a new measurement period. 1 2 3 4 programmed periodic counting 341
figure 11-39 shows an example of programmed periodic counting. table 11-8 lists the possible combinations of compare-match channels and capture channels. in this example external events are counted over a programmed period using channels 2 and 6. the ipu automatically transfers the value of timer counter 6 (h'0012) to t6gr1 when timer counter 2 matches t2dr2 (h'0100). timer counter 2 is set to be cleared by compare match with t2dr2. settings tcrl (channel 2): h'e0 (cleared by compare match with t2dr2) tcrh (channel 6): h'ed or h'fd (increment on both rising and falling edges) tmdra: h'10 (capture to t6gr1 on compare match with t2dr2) figure 11-39 example of programmed periodic counting * h'0100 h'ffff h'0100 0000 0001 0002 0003 0004 0001 00ff 00fe 00fd 00fc 00fb 00fa 00f9 0 * h'00 h'0012 h'0000 h'0001 h'0010 h'0011 h'0012 0002 h'10 (md2-6 = 1) timer counter 2 value t2dr2 value (channel 2) timer counter 6 value t6gr1 value (channel 6) tmdra value tclk 1 counter is cleared by compare match timer counter 6 value is captured to t6gr1 on compare match in channel 2 note: 342
table 11-8 combinations of compare match channels and capture channels 11.8.9 phase counting mode one application of phase counting mode is control of an ac servo motor. if the output of a two- phase encoder is fed to two external clock pins, the phase relationship between the two clock signals is detected and the counter is incremented or decremented accordingly. phase counting is available only on channel 7. figure 11-40 shows the procedure for selecting phase counting mode. procedure for selecting phase counting mode figure 11-40 procedure for selecting phase counting mode 1 2 mode selection mdf bit = 1 str7 bit = 1 1 set the mdf bit to 1 in timer mode register b (tmdrb) to select phase counting mode. counting begins when the str7 bit is set to 1 in the timer start register (tstr). 2 compare match channel capture channel channel no. register channel no. register md2-6 channel 2 dr2 channel 6 gr1 md3-5 channel 3 dr2 channel 5 gr1 md4-7 channel 4 dr2 channel 7 gr1 md6-7 channel 6 gr2 channel 7 gr2 343
phase counting operation: figure 11-41 shows the phase counting operation. figure 11-41 operation in phase counting mode tclk 1 tclk 1 tclk 2 tclk 2 high low or or tclk 1 tclk 1 tclk 2 tclk 2 high low no yes no yes 1 2 3 4 1 2 3 4 phase counting phase comparison overflow? underflow? ovf ? 1 the phases of tclk 1 and tclk 2 are compared. the channel 7 counter is incremented or decremented according to the counting conditions. when an overflow or underflow occurs, the ovf bit in timer status register low (tsrl) is set to 1. 344
figure 11-42 shows an example in which the counter counts up, overflows, then counts down. in up-counting, the counter counts repeatedly from h'0000 to h'ffff. the ipu sets the overflow flag (ovf) in timer status register low (tsrl) when the count returns from h'ffff to h'0000. for the up/down counting conditions, see figure 11-44 ?ounting conditions?and table 11-9 ?p/down counting conditions. figure 11-42 example of up-counting, overflow, and down-counting 0001 0000 0000 fffe ffff 0002 0001 0002 0000 0001 counting up counting down timer counter 7 value ovf flag (tsrl) overflow flag (ovf) is set to 1 when count changes from h'ffff to h'0000 tclk 1 tclk 2 345
figure 11-43 shows an example in which the counter counts down, underflows, then counts up. in down-counting, the counter counts repeatedly from h'ffff to h'0000. the ipu sets the overflow flag (ovf) in timer status register low (tsrl) when the count returns from h'0000 to h'ffff. for the up/down counting conditions, see figure 11-44 ?ounting conditions?and table 11-9, ?p/down counting conditions. figure 11-43 example of down-counting, underflow, and up-counting 00ff 0100 ffff 0001 0000 00fe fffe fffd ffff fffe counting down counting up timer counter 7 value ovf flag (tsrl) overflow flag (ovf) is set to 1 when count changes from h'0000 to h'ffff tclk 1 tclk 2 346
figure 11-44 shows the counting conditions. table 11-9 indicates the up- and down-counting conditions. the ipu counts all edges of tclk 1 and tclk 2 . figure 11-44 counting conditions table 11-9 up/down counting conditions tclk 2 tclk 1 counter value counting up timer counter 7 counting down time high high low low high low low high counting direction tclk 2 tclk 1 up-counting down-counting 347
figure 11-45 shows the external clock input timing in phase counting mode. the ipu latches the external clock signals on the rising edge of the system clock (?. the counter is incremented 1.5 system clock cycles (1.5t cyc ) after the external clock is latched. the external clock pulse width must be at least 1.5 system clock cycles (1.5t cyc ). the phase difference between tclk 1 and tclk 2 must be at least 1.0t cyc . figure 11-45 external clock input timing in phase counting mode t tcks t tcks t tcks n n + 1 n + 2 tclk1 tclk2 tcnt2 internal counter clock minimum width: 1.5t cyc minimum phase difference: 1.0t cyc minimum phase difference: 1.0t cyc minimum width: 1.5t cyc t tcks : 50 ns (min) t tcks 348
11.9 interrupts the ipu can request three types of interrupts: compare match, input capture, and overflow. the timing of each type of interrupt request is described next. 11.9.1 interrupt timing (1) output compare timing: figure 11-46 shows the timing from counter increment to generation of a compare match interrupt request. one system clock cycle (1.0t cyc ) after timer counter 2 matches the t2gr1 value (n), the ipu sets the input capture/compare match flag (imf). a compare match signal (t2ioc 1 ) is output 0.5t cyc after imf is set. the interrupt request (t2imi1) is generated 0.5t cyc after the t2ioc 1 output. the t2imi1 interrupt request therefore comes 2.0t cyc after the counter is incremented to n. figure 11-46 timing from incrementation to compare match interrupt request 2.0t cyc n ?1 n n + 1 1.0t cyc 1.5t cyc imf2 (tsrl) t2ioc 1 t2imi1 timer counter 2 value internal compare match signal compare match interrupt request n t2gr1 349
(2) input capture timing: figure 11-47 shows the timing from capture signal input to generation of an input capture interrupt request. a maximum 1.5t cyc after input of the capture signal, the ipu transfers the timer counter value (n) to t2gr1. the input capture/compare match flag (imf) is set 0.5t cyc after the input capture transfer. the interrupt request (t2imi1) is generated 1.0t cyc after imf is set. the t2imi1 interrupt request therefore comes a maximum 3.0t cyc after input of the capture signal. figure 11-47 timing from capture input to input capture interrupt request 3.0t cyc (max) n ?1 n n + 1 1.5t cyc (max) 2.0t cyc (max) t2ioc 1 internal capture signal input capture interrupt request t2gr1 t2imi1 imf2 (tsrl) timer counter 2 value n 350
(3) overflow timing: figure 11-48 shows the timing from counter increment to generation of an overflow interrupt request. when the value of timer counter 2 returns from h'ffff to h'0000 the ipu sets the overflow flag (ovf). the interrupt request (t2ovi) is generated 1.0t cyc after ovf is set. in phase counting mode, the ipu sets the overflow flag (ovf) when the timer counter value returns from h'0000 to h'ffff. for usage in phase counting mode, see section 11.8.9 ?hase counting mode. figure 11-48 timing from counter incrementation to overflow interrupt request 11.9.2 interrupt sources and dtc interrupts the ipu has 35 interrupt sources. of these, the compare match interrupt sources and the compare match/input capture interrupt sources can start the data transfer controller (dtc) to transfer data. table 11-10 lists the interrupt sources and indicates which can start the dtc. the exclusive compare match interrupt sources (such as t1cmi1 and t1cmi2) are paired. both sources in each pair share the same vector. data transfer should not be enabled for both interrupt sources at the same time. 1.0t cyc h'ffff h'0000 h'0001 ovf (tsrl) t2ovi overflow interrupt request timer counter 2 value 351
table 11-10 interrupt sources and dtc interrupts interrupt dtc priority channel source description available order 1 t1imi1 gr1 compare match or input capture yes high t1imi2 gr2 compare match or input capture yes t1cmi1/ dr1 or dr2 compare match yes t1cmi2 t1ovi timer counter 1 overflow no t1imi3 gr3 compare match or input capture yes t1imi4 gr4 compare match or input capture yes t1cmi3/ dr3 or dr4 compare match yes t1cmi4 2 t2imi1 gr1 compare match or input capture yes t2imi2 gr2 compare match or input capture yes t2cmi1/ dr1 or dr2 compare match yes t2cmi2 t2ovi timer counter 2 overflow no 3 t3imi1 gr1 compare match or input capture yes t3imi2 gr2 compare match or input capture yes t3cmi1/ dr1 or dr2 compare match yes t3cmi2 t3ovi timer counter 3 overflow no 4 t4imi1 gr1 compare match or input capture yes t4imi2 gr2 compare match or input capture yes t4cmi1/ dr1 or dr2 compare match yes t4cmi2 t4ovi timer counter 4 overflow no 5 t5imi1 gr1 compare match or input capture yes t5imi2 gr2 compare match or input capture yes t5cmi1/ dr1 or dr2 compare match yes t5cmi2 t5ovi timer counter 5 overflow no 6 t6imi1 gr1 compare match or input capture yes t6imi2 gr2 compare match or input capture yes t6ovi timer counter 6 overflow no 7 t7imi1 gr1 compare match or input capture yes t7imi2 gr2 compare match or input capture yes t7ovi timer counter 7 overflow no low 352
11.10 notes and precautions this section describes contention between the compare registers and various ipu operations, and other matters requiring special attention. (1) contention between counter read/write by the h8/500 cpu and ipu operations contention between writing to timer counter by h8/500 cpu (t 3 ) and clearing by compare match: clearing the counter has priority. figure 11-49 contention between writing to timer counter by h8/500 cpu (t 3 ) and clearing by compare match n ?1 n h'0000 t 1 t 2 t 3 masked a 19 ? 0 timer counter value internal counter clear signal internal write signal timer counter address if the internal write signal followed the dotted line, a write would occur on the falling edge of t 3 . the internal counter clear signal masks the write signal, so clearing of the counter takes priority. (the dotted line shows the normal write signal.) 353
contention between writing to timer counter by h8/500 cpu (t 3 ) and clearing by capture input: clearing the counter has priority. figure 11-50 contention between writing to timer counter by h8/500 cpu (t 3 ) and clearing by capture input n h'0000 masked t 1 t 2 t 3 a 19 ? 0 input capture pin timer counter value internal counter clear signal internal write signal timer counter address capture input generates clear signal if the internal write signal followed the dotted line, a write would occur on the falling edge of t 3 . the internal counter clear signal masks the write signal, so clearing of the counter takes priority. (the dotted line shows the normal write signal.) 354
contention between timer counter write (t 3 ) and increment: writing has priority. figure 11-51 contention between timer counter write (t 3 ) by h8/500 cpu and increment t 1 t 2 t 3 internal write signal internal data bus timer counter value internal increment signal timer counter address a 19 ? 0 write data (h'aaaa) n h'aaaa masked if h'aaaa is set in a compare register, a compare match occurs here. the internal write signal masks the increment signal, so writing to the counter takes priority. (the dotted line shows the normal increment signal.) 355
contention between timer counter write (t 3 ) and setting of overflow flag: setting the overflow flag has priority. figure 11-52 contention between timer counter write (t 3 ) by h8/500 cpu and setting of overflow flag a 19 ? 0 t 1 t 2 t 3 h'ffff h'aaaa internal write signal internal data bus timer counter value overflow flag (ovf) timer counter address write data (h'aaaa) writing has priority, so if the write occurs at the instant when the count would have changed from h'ffff to h'0000, the overflow flag (ovf) is not set. 356
contention between timer counter byte write (t 2 ) and increment: if the write is to the upper byte, the new value is written in the upper byte and the lower byte retains its old value. if the write is to the lower byte, the new value is written in the lower byte and the upper byte retains its old value. if the contention occurs at t 3 , however, the byte that is not written is incremented. figure 11-53 contention between timer counter byte write (t 2 ) by h8/500 cpu and increment t 1 t 2 t 3 h'ff h'aa h'00 h'01 h'00 a 19 ? 0 internal write signal internal data bus timer counter value (upper byte) timer counter value (lower byte) internal increment signal timer counter address write data (h'aa) value prior to increment is retained. 357
contention between capture register read (t 3 ) and input capture: the h8/500 cpu reads the data prior to capture. figure 11-54 contention between capture register read (t 3 ) by h8/500 cpu and input capture t 1 t 2 t 3 a 19 ? 0 h'ffff h'aaaa internal read signal internal data bus capture register value input capture pin timer counter address read data (h'ffff) value prior to capture is read data updated by input capture 358
contention between writing to general register or dedicated register by h8/500 cpu (t 3 ) and compare match: compare match does not occur. figure 11-55 contention between writing to general register or dedicated register by h8/500 cpu (t 3 ) and compare match t 1 t 2 t 3 a 19 ? 0 h'0a09 h'0a0a internal write signal internal data bus timer counter value gr or dr value gr or dr address write data (h'0a0a) h'aaaa h'0a0a internal compare match signal masked internal write signal has indicated waveform. write occurs at fall of ?in t 3 state. the internal write signal masks the compare match signal, so compare match does not occur. (dotted line indicates normal compare match signal.) 359
(2) note on writing in synchronizing mode: after a write in synchronizing mode, all 16 bits of all specified counters have the same value as the counter that was written. this is true regardless of the operand size (word or byte). example: when channels 2 and 3 are synchronized word write to channel 2 or word write to channel 3 byte write to channel 2 or byte write to channel 3 ff 00 aa 55 tcnt2 tcnt3 01 01 01 01 tcnt2 tcnt3 upper byte lower byte write h'0101 upper byte lower byte ff 00 aa 55 tcnt2 tcnt3 01 00 01 00 tcnt2 tcnt3 aa 01 aa 01 tcnt2 tcnt3 upper byte lower byte upper byte lower byte write h'01 to upper byte of channel 2 write h'01 to lower byte of channel 3 upper byte lower byte 360
(3) note on compare register setting: the compare match frequency differs depending on whether the timer counter clock source is the system clock (? or another source. when the counter increments on the system clock as in figure 11-56, the compare match frequency is: t = ?(n + 1) (t: compare match frequency. ? system clock frequency. n: value set in compare register.) when the counter increments on a clock source other than the system clock as in figure 11-57, the compare match frequency is: t = ?(d* n) * example: if the counter clock source is ?2, then d = 2. (t: compare match frequency. ? system clock frequency. d: frequency ratio of system clock to counter clock source. n: value set in compare register.) in this case, if h'0000 is set in the compare register, compare match does not occur. figure 11-56 compare match frequency when clock source is system clock h'0000 h'0001 h'0002 n ?1 h'0000 h'0001 n n counter clock source counter value compare match signal (toggle output) frequency: t = ?(n + 1) 361
figure 11-57 compare match frequency when clock source is not system clock h'0000 n ?1 h'0000 h'0001 n ?1 n h'0001 n frequency: t = ?(d n) counter clock source counter value compare match signal (toggle output) 362
rewriting the compare match register in pwm mode: in pwm mode, to shorten the pulse width, two register values must be rewritten within the same cycle. restrictions regarding writing to the register are as described previously. refer to figure 11-58 for a timing diagram of actual rewrite processing (renewal). example: pwm pulse output on channel 1 pulse set: gr1 pulse reset: gr3 setting range gr1: between 0 and 1/2 t cyc . (between 1 and 1/2 t cyc when ?is selected as the clock source.) gr3: between 1/2 t cyc and t cyc . here, t cyc refers to one cycle of the counter. rewriting register to shorten pulse width gr1 rewrite: at gr1, or while 1/2 t cyc < count t cyc . gr3 rewrite: at gr3 or while 0 < count t cyc (1 < count < 1/2 t cyc if ?is the clock source). figure 11-58 timing example of register rewrite in pwm mode 363 t0 t0 t0 t0 t cyc 1/2 t cyc gr1 gr3 gr1 gr3 gr1 gr3 t1ioc 1 counter value compare match compare match gr3 rewrite gr1 rewrite gr3 rewrite gr1 rewrite
note on rewriting the compare match register: to generate a compare match after rewriting the register, the following condition must be satisfied. note that even if the counter value when rewriting the register and the register value after rewriting the register do match, a compare match will not be generated. 1. slowing down compare match timing reg count < reg' ................................ (1) however, if reg ? tcnt, the following condition must be met: count < reg' ........................................... (1') where reg: register value before rewriting count: register value during rewriting reg': register value after rewriting t cyc : counter refresh cycle or overflow cycle 2. speeding up compare match timing reg count t cyc .................................. (2) where reg: register value before rewriting count: register value during rewriting t cyc : counter refresh cycle or overflow cycle 364
section 12 pwm timers (h8/539 only) 12.1 overview the h8/539 has a built-in pulse-width modulation (pwm) timer module with three independent channels (pwm1, pwm2, and pwm3). each pwm timer has an eight-bit timer counter (tcnt) and an eight-bit duty register (dtr). dtr settings can provide pulse output with any duty cycle from 0% to 100%. the h8/538 does not have a built-in pwm timer module. 12.1.1 features the pwm timer features are: selection of eight counter clock sources selection of duty cycles from 0% to 100% with 1/250 resolution selection of direct or inverted pwm output 365
12.1.2 block diagram figure 12-1 shows a block diagram of one pwm timer. figure 12-1 block diagram of pwm timer dtr comparator tcnt tcr pw output control compare match clock clock select internal clock sources ?2 ?8 ?32 ?128 ?256 ?1024 ?2048 ?4096 module data bus bus interface internal data bus legend dtr: tcnt: tcr: duty register timer counter timer control register 366
12.1.3 pin configuration table 12-1 summarizes the pwm timer output pins. table 12-1 pwm timer pins name abbreviation i/o function pwm1 output pin pw 1 output pwm timer 1 pulse output pwm2 output pin pw 2 output pwm timer 2 pulse output pwm3 output pin pw 3 output pwm timer 3 pulse output 12.1.4 register configuration table 12-2 summarizes the internal registers of the pwm timers. table 12-2 pwm timer registers channel name abbreviation r/w initial value address 1 timer control register tcr r/w h'38 h'fec0 duty register dtr r/w h'ff h'fec1 timer counter tcnt r/(w) * h'00 h'fec2 2 timer control register tcr r/w h'38 h'fec4 duty register dtr r/w h'ff h'fec5 timer counter tcnt r/(w) * h'00 h'fec6 3 timer control register tcr r/w h'38 h'fec8 duty register dtr r/w h'ff h'fec9 timer counter tcnt r/(w) * h'00 h'feca note: * can be written and read, but the write function is for test purposes only. do not write to these registers during normal operation. 367
12.2 register descriptions 12.2.1 timer counter the timer counter (tcnt) is an eight-bit up-counter. when the output enable bit (oe) is set to 1 in tcr, tcnt starts counting pulses of the internal clock selected by clock select bits 2 to 0 (cks2 to cks0). after counting from h'00 to h'f9, the count repeats from h'00. tcnt can be written to and read, but the write function is for test purposes only. do not write to tcnt during normal operation, because this may have unpredictable effects. tcnt is initialized to h'00 by a reset and in standby mode, and when the oe bit is cleared to 0. 12.2.2 duty register the duty register (dtr) specifies the duty cycle of the output pulse. any duty cycle from 0% to 100% can be output by setting the corresponding value in dtr. the resolution is 1/250. writing 0 (h'00) in dtr gives a 0% duty cycle. writing 125 (h'7d) gives a 50% duty cycle. writing 250 (h'fa) gives a 100% duty cycle. the dtr and tcnt values are always compared. when the values match, the pwm output is placed in the 0 state. when the tcnt value changes from h'00 to h'01, the pwm output is placed in the 1 state, unless the dtr value is h'00, in which case the duty cycle is 0% and the pwm output remains in the 0 state. dtr is double-buffered. a new value written in dtr does not become valid until after the timer count changes from h'f9 to h'00. while the oe bit is cleared to 0 in tcr, however, new values written in dtr become valid immediately. when dtr is read, the value read is the currently valid value. dtr is initialized to h'ff by a reset and in standby mode. bit initial value r/w 7 1 543210 1111111 r/w r/w r/w r/w r/w 6 r/w r/w r/w bit initial value r/w 7 0 543210 0000000 r/(w) r/(w) r/(w) r/(w) r/(w) 6 r/(w) r/(w) r/(w) 368
12.2.3 timer control register the timer control register (tcr) is an eight-bit readable/writable register that selects the clock input to tcnt and controls pwm output. tcr is initialized to h'38 by a reset and in standby mode. bit 7?utput enable (oe): starts or stops tcnt and controls pwm output. bit 7 oe description 0 pwm output is disabled and the tcnt value is cleared to 0 (initial value) 1 pwm output is enabled and tcnt is counting bit 6?utput select (os): selects direct or inverted pwm output. bit 6 os description 0 direct pwm output (initial value) 1 inverted pwm output bits 5 to 3?eserved: read-only bits, always read as 1. bit initial value r/w 7 oe 0 5 4 3 2 cks2 1 cks1 0 cks0 0111000 r/w r/w r/w r/w r/w 6 os 369
bits 2 to 0?lock select (cks2 to cks0): these bits select one of eight internal clock sources, obtained by dividing the system clock (?, for input to tcnt. bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 ?2 (initial value) 001 /8 0 1 0 ?32 0 1 1 ?128 1 0 0 ?256 1 0 1 ?1024 1 1 0 ?2048 1 1 1 ?4096 the pwm resolution, period, and frequency can be calculated as follows from the frequency of the selected internal clock source. resolution = 1/(internal clock frequency) pwm period = resolution 250 pwm frequency = 1/(pwm period) table 12-3 lists the resolution, pwm period, and pwm frequency for each clock source when the system clock frequency (? is 10 mhz. table 12-3 pwm period and resolution internal clock frequency resolution pwm period pwm frequency ?2 200 ns 50 ? 20 khz ?8 800 ns 200 ? 5 khz ?32 3.2 ? 800 ? 1.25 khz ?128 12.8 ? 3.2 ms 312.5 hz ?256 25.6 ? 6.4 ms 156.3 hz ?1024 102.4 ? 25.6 ms 39.1 hz ?2048 204.8 ? 51.2 ms 19.5 hz ?4096 409.6 ? 102.4 ms 9.8 hz 370
12.3 pwm timer operation pwm timer operation is described below. figure 12-2 shows a timing diagram. (1) direct output (os = 0) when oe = 0 [(a) in figure 12-2] the timer count is held at h'00 and pwm output is disabled. the pin state depends on the port data register (dr) and data direction register (ddr) settings. a value (n) written in dtr becomes valid immediately. when oe is set to 1 tcnt begins counting up, and the pwm output goes to the 1 state. [(b) in figure 12-2] when the count reaches the dtr value, the pwm output goes to the 0 state. [(c) in figure 12-2] if the dtr value is changed (by writing m), the new value becomes valid after tcnt changes from h'f9 to h'00. [(d) in figure 12-2] (2) indirect output (os = 1): the pwm output is inverted. [(e) in figure 12-2] 371
figure 12-2 pwm operation timing n ?1 n + 1 (a) h'00 (b) h'01 h'02 n h'f9 (d) h'00 h'01 n (d) m h'ff (c) (a) * (e) * (b) (c) write n in dtr write m in dtr tcnt input clock oe tcnt dtr (os = 0) pwm output (os = 1) note: * state determined by port dr and ddr settings. 372
12.4 usage notes when using the pwm timers, note the following points. to use port 6, 7, or a for pwm output, first set the appropriate bit (pwm1e, pwm2e, or pwm3e) to 1 in p67cr or pacr. each of these bits can be set independently. the h8/538 does not have a built-in pwm timer module. any necessary changes to bits cks2 to cks0 and os should be made before the oe bit is set to 1. if the dtr value is h'00, the duty cycle is 0% (always 0). if the dtr value is h'fa to h'ff, the duty cycle is 100% (always 1). for inverted output, these output levels are inverted. 373
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section 13 watchdog timer 13.1 overview system operation can be monitored by the on-chip watchdog timer (wdt, one channel). the wdt can generate a reset signal for the entire chip if a system crash allows the timer counter (tcnt) to overflow. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an irq0 interrupt is requested at each counter overflow. the wdt is also used in recovering from software standby mode. 13.1.1 features wdt features are listed below. selection of eight counter clock sources interval timer option timer counter overflow generates a reset signal or interrupt the reset signal is generated in watchdog timer operation. an irq0 interrupt is requested in interval timer operation. overflow reset signal resets the entire chip internally, and can also be output externally the reset signal generated by timer counter overflow during watchdog timer operation resets the entire chip internally. if enabled by the reset output enable bit, an external reset signal can be output to reset other system devices simultaneously. 375
13.1.2 block diagram figure 13-1 shows a block diagram of the wdt. figure 13-1 wdt block diagram 13.1.3 register configuration table 13-1 summarizes the wdt registers. table 13-1 wdt registers rstcsr tcsr tcnt ?2 ?32 ?64 ?128 ?256 ?512 ?2048 ?4096 irq0 (interval timer) interrupt signal reset (internal, external) interrupt control overflow clock reset control clock select read/ write control internal data bus internal clock sources legend tcnt: timer counter tcsr: timer control/status register rstcsr: reset control/status register address write read name abbreviation r/w initial value h'ff10 h'ff10 timer control/status register tcsr r/(w) * h'18 h'ff11 timer counter tcnt r/w h'00 h'ff1f reset control/status register rstcsr r/(w) * h'3f note: * software can write 0 in bit 7 to clear the flag but cannot write 1. 376
13.2 register descriptions the watchdog timer has three registers, which are described next. 13.2.1 timer counter the timer counter (tcnt) is an eight-bit readable and writable* up-counter. the tcnt bit structure is shown next. when the timer enable bit (tme) in the timer control/status register (tcsr) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (cks2 to cks0) in tcsr. when the count overflows (changes from h'ff to h'00), an overflow flag (ovf) in tcsr is set to 1. the timer count is initialized to h'00 by a reset and when the tme bit is cleared to 0. note: * tcnt is write-protected by a password. see section 13.2.4, ?otes on register access for details. bit initial value r/w 7 0 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 377
13.2.2 timer control/status register the timer control/status register (tcsr) is an eight-bit readable and partly writable *1 register. its functions include selecting the timer mode and clock source. the tcsr bit structure is shown next. bits 7 to 5 are initialized to 0 by a reset, in hardware standby mode, and in software standby mode. bits 2 to 0 are initialized to 0 by a reset and in hardware standby mode, but retain their values in software standby mode. notes: 1. tcsr is write-protected by a password. see section 13.2.4 ?otes on register access?for details. 2. software can write 0 in bit 7 to clear the flag, but cannot set this bit to 1. (1) bit 7?verflow flag (ovf): this status flag indicates that the timer counter has overflowed from h'ff to h'00 in interval timer mode. when ovf = 1, an irq0 interrupt is requested. bit initial value r/w 7 0 ovf wt/it 543210 0011000 r/(w) * 2 r/w r/w r/w r/w r/w 6 tme cks2 cks1 cks0 overflow flag status flag indicating overflow timer mode select bit selects the mode timer enable bit enables and disables the timer reserved bits clock select bits these bits select the tcnt clock source bit 7 ovf description 0 cleared by reading ovf after it has been set to 1, (initial value) then writing 0 in ovf 1 set when tcnt over flows 378
(2) bit 6?imer mode select (wt/ it ): selects whether to use the wdt as a watchdog timer or interval timer. if used as an interval timer (wt/ it = 0), the wdt generates an irq0 interrupt request when the timer counter (tcnt) overflows. if used as a watchdog timer (wt/ it = 1), the wdt generates a reset when the timer counter (tcnt) overflows. (3) bit 5?imer enable (tme): enables or disables the timer counter (tcnt). always clear tme to 0 before entering software standby mode. (4) bits 4 and 3?eserved: read-only bits, always read as 1. (5) bits 2 to 0?lock select 2 to 0 (cks2/1/0): these bits select one of eight internal clock sources for input to tcnt. the clock signals are obtained by prescaling the system clock (?. the overflow interval listed in the following table is the time from when tcnt begins counting from h'00 until an overflow occurs. when the wdt operates as an interval timer, irq0 interrupts are requested at this interval. set cks2 to cks0 to the clock settling time before entering software standby mode. bit 6 wt/it description 0 interval timer: irq0 interrupt request (initial value) 1 watchdog timer: reset request bit 5 tme description 0 timer disabled: tcnt is initialized to h'00 and stopped. (initial value) 1 timer enabled: tcnt starts counting. bit 2 bit 1 bit 0 description cks2 cks1 cks0 clock source overflow interval (?= 10 mhz) 0 0 0 ?2 51.2 ? (initial value) 0 0 1 ?32 819.2 ? 0 1 0 ?64 1.6 ms 0 1 1 ?128 3.3 ms 1 0 0 ?256 6.6 ms 1 0 1 ?512 13.1 ms 1 1 0 ?2048 52.4 ms 1 1 1 ?4096 104.9 ms 379
13.2.3 reset control/status register the reset control/status register (rstcsr) is an eight-bit readable and partly writable *1 register that indicates when a reset signal has been generated by wdt overflow, and controls external output of this reset signal. bits 7 and 6 are initialized by input of a reset signal at the res pin. they are not initialized by a reset signal generated by the wdt. notes: 1. tcsr is write-protected by a password. see section 13.2.4, ?otes on register access?for details 2. software can write 0 in bit 7 to clear the flag, but cannot set this bit to 1. (1) bit 7?atchdog timer reset (wrst): indicates that the watchdog timer counter has overflowed and generated a reset signal. this reset signal resets the entire chip. if the reset output enable bit (rstoe)is set to 1, the reset signal is also output (low) at the reso pin to initialize external system devices. bit initial value r/w 7 0 wrst rstoe 543210 0111111 r/(w) * 2 r/w 6 watchdog timer reset bit indicates reset occurrence reset output enable bit enables or disables external reset signal output reserved bits bit 7 wrst description 0 cleared to 0 by reset signal input at res pin, or by software (initial value) 1 set by tcnt overflow when wdt is used as a watchdog timer, generating a reset signal 380
(2) bit 6?eset output enable (rstoe): enables or disables external output at the reso pin of the reset signal generated if the timer counter (tcnt) overflows when the wdt is used as a watchdog timer. (3) bits 5 to 0?eserved: read-only bits, always read as 1. 13.2.4 notes on register access the watchdog timers tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write. the procedures for writing and reading these registers are given below. (1) writing to tcnt and tcsr: these registers must be written by word access. they cannot be written by byte instructions. figure 13-2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. the write data must be contained in the lower byte of the written word. the upper byte must contain h'5a (password for tcnt) or h'a5 (password for tcsr). this transfers the write data from the lower byte to tcnt or tcsr. figure 13-2 format of data written to tcnt and tcsr bit 6 rstoe description 0 reset signal generated by tcnt overflow is not (initial value) output externally 1 reset signal generated by tcnt overflow is output externally h'5a write data 8 7 15 0 h'ff10 h'a5 write data 8 7 15 0 h'ff10 address address 381
(2) writing to rstcsr: rstcsr must be written by word access. it cannot be written by byte instructions. figure 13-3 shows the format of data written to rstcsr. to write 0 in the wrst bit, the write data must have h'a5 in the upper byte and h'00 in the lower byte. the h'00 in the lower byte clears the wrst bit in rstcsr to 0. to write to the rstoe bit, the upper byte must contain h'5a and the lower byte must contain the write data. writing this word transfers a write data value into the rstoe bit. figure 13-3 format of data written to rstcsr (3) reading tcnt, tcsr, and rstcsr: these registers are read like other registers. byte access instructions can be used. the read addresses are h'ff10 for tcsr, h'ff11 for tcnt, and h'ff1f for rstcsr, as listed in table 13-2. table 13-2 read addresses of tcnt, tcsr, and rstcsr h'a5 h'00 8 7 15 0 h'ff1e h'5a write data 8 7 15 0 h'ff1e address address address register h'ff10 tcsr h'ff11 tcnt h'ff1f rstcsr 382
13.3 operation this section describes operations when the wdt is used as a watchdog timer and as an interval timer, and the wdts function in software standby mode. 13.3.1 watchdog timer operation figure 13-4 illustrates watchdog timer operation. to use the wdt as a watchdog timer, set the wt/ it and tme bits to 1. software must prevent tcnt overflow by rewriting the tcnt value (normally by writing h'00) before overflow occurs. if tcnt fails to be rewritten and overflows due to a system crash etc., the chip is internally reset for 518 system clock cycles (518?. the watchdog reset signal can be externally output from the reso pin to reset external system devices. the reset signal is output externally for 132 system clock cycles (132?. external output can be enabled or disabled by the rstoe bit in rstcsr. a watchdog reset has the same vector as a reset generated by input at the res pin. software can distinguish a res reset from a watchdog reset by checking the wrst bit in rstcsr. if a res reset and a watchdog reset occur simultaneously, the res reset always takes priority. figure 13-4 watchdog timer operation reso pin h'ff h'00 ovf = 1 518 132 tcnt count value wdt overflow start h'00 written in tcnt reset tme set to 1 h'00 written in tcnt 383
13.3.2 interval timer operation figure 13-5 illustrates interval timer operation. to use the wdt as an interval timer, clear wt/ it to 0 and set tme to 1. an irq0 request is generated each time the timer count overflows. this function can be used to generate irq0 requests at regular intervals. this irq0 interrupt has a different vector from the interrupt requested by irq 0 input. software does not have to check whether the interrupt request came from the irq 0 pin or the interval timer. figure 13-5 interval timer operation h'ff h'00 wt/it = 0 tme = 1 tcnt count value irq0 request time t irq0 request irq0 request irq0 request irq0 request 384
13.3.3 operation in software standby mode the watchdog timer has a special function in recovery from software standby mode. wdt settings required when software standby mode is used are described next. (1) before transition to software standby mode: the tme bit in the timer control/status register (tcsr) must be cleared to 0 to stop the watchdog timer counter before execution of the sleep instruction. the chip cannot enter software standby mode while the tme bit is set to 1. before entering software standby mode, software should also set bits cks2 to cks0 in tcsr so that the overflow interval is equal to or greater than the settling time of the clock oscillator. (2) recovery from software standby mode: in recovery from software standby mode the wdt operates as follows. when an nmi request signal is received, the clock oscillator starts running and the timer counter (tcnt) starts counting at the rate selected by bits cks2 to cks0 in tcsr before software standby mode was entered. when tcnt overflows (changes from h'ff to h'00), the system clock (? is presumed to be stable and usable, clock signals are supplied to the entire chip, software standby mode ends, and the nmi interrupt-handling routine starts executing. this timer overflow does not set the ovf flag in tcsr to 1, and the tme bit remains cleared to 0. 13.3.4 timing of setting of overflow flag (ovf) figure 13-6 shows the timing of setting of the ovf flag in the timer control/status register (tcsr). the ovf flag is set to 1 when the timer counter overflows. when ovf is set to 1, an irq0 interrupt is requested simultaneously. figure 13-6 timing of setting of ovf tcnt irq0 interrupt h'ff h'00 ovf irq0 interrupt request 385
13.3.5 timing of setting of watchdog timer reset bit (wrst) the wrst bit in the reset control/status register (rstcsr) is valid when wt/ it = 1 and tme = 1. figure 13-7 shows the timing of setting of wrst and the internal reset timing. the wrst bit is set to 1 when the timer count overflows and ovf is set to 1. at the same time an internal reset signal is generated for the entire chip. this internal reset signal clears ovf, but the wrst bit remains set to 1. the reset routine must therefore contain an instruction that clears the wrst bit. figure 13-7 timing of setting of wrst bit and internal reset tcnt ovf wrst h'ff h'00 wdt internal reset 386
13.4 usage notes (1) contention between timer counter (tcnt) write and increment: if a timer counter clock pulse is generated during the t 3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. see figure 13-8. figure 13-8 contention between tcnt write and increment (2) changing cks2 to cks0 values: software should stop the watchdog timer (by clearing the tme bit to 0) before changing the values of bits cks2 to cks0 in the timer control/status register (tcsr). t 1 t 2 t 3 tcnt tcnt n m internal write signal write cycle: cpu writes to tcnt counter write data tcnt clock pulse 387
388
section 14 serial communication interface 14.1 overview the on-chip serial communication interface (sci) has two independent channels in the h8/538, and three independent channels in the h8/539. all channels are functionally identical. the sci supports both asynchronous and clocked synchronous serial communication. it also has a multiprocessor communication function for serial communication among two or more processors. the h8/538 does not have sci3. 14.1.1 features sci features are listed below. selection of asynchronous or synchronous mode a. asynchronous mode the sci can communicate with a uart (universal asynchronous receiver/transmitter), acia (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve selectable serial data communication formats. data length: seven or eight bits stop bit length: one or two bits parity: even, odd, or none multiprocessor bit: one or none receive error detection: parity, overrun, and framing errors break detection: by reading the rxd level directly when a framing error occurs b. clocked synchronous mode serial data communication is synchronized with a clock signal. the sci can communicate with other chips having a clocked synchronous communication function. data length: eight bits receive error detection: overrun errors full duplex communication the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. 389
built-in baud rate generator with selectable bit rates internal or external transmit/receive clock source: baud rate generator or sck pin four types of interrupts transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. the transmit-data-empty and receive-data-full interrupts can be served by the on-chip data transfer controller (dtc) to transfer data. in the h8/539, sci2 and sci3 have the same interrupt vectors. 14.1.2 block diagram figure 14-1 shows a block diagram of the sci. figure 14-1 sci block diagram legend rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register brr: bit rate register module data bus parity generate parity check transmit/ receive control baud rate generator clock external clock bus interface internal data bus rxd rdr tdr rsr tsr ssr scr smr brr ?/4 ?16 ?64 tei txi rxi eri sck txd 390
14.1.3 input/output pins table 14-1 summarizes the serial communication pins for each sci channel. sci channel 3 is not present in the h8/538. table 14-1 sci pins channel pin name abbreviation input/output function 1 serial clock pin sck1 input/output sci1 clock input/output receive data pin rxd1 input sci1 receive data input transmit data pin txd1 output sci1 transmit data output 2 serial clock pin sck2 input/output sci2 clock input/output receive data pin rxd2 input sci2 receive data input transmit data pin txd2 output sci2 transmit data output 3 serial clock pin sck3 input/output sci3 clock input/output receive data pin rxd3 input sci3 receive data input transmit data pin txd3 output sci3 transmit data output 14.1.4 register configuration table 14-2 summarizes the sci registers. these registers select the communication mode (asynchronous or clocked synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. sci channel 3 is not present in the h8/538. 391
table 14-2 channel 1 registers channel address name abbreviation r/w initial value 1 h'fec8 serial mode register smr r/w h'00 h'fec9 bit rate register brr r/w h'ff h'feca serial control register scr r/w h'00 h'fecb transmit data register tdr r/w h'ff h'fecc serial status register ssr r/(w) * h'84 h'fecd receive data register rdr r h'00 2 h'fed0 serial mode register smr r/w h'00 h'fed1 bit rate register brr r/w h'ff h'fed2 serial control register scr r/w h'00 h'fed3 transmit data register tdr r/w h'ff h'fed4 serial status register ssr r/(w) * h'84 h'fed5 receive data register rdr r h'00 3 h'fec0 serial mode register smr r/w h'00 h'fec1 bit rate register brr r/w h'ff h'fec2 serial control register scr r/w h'00 h'fec3 transmit data register tdr r/w h'ff h'fec4 serial status register ssr r/(w) * h'84 h'fec5 receive data register rdr r h'00 note: * software can write 0 to clear flags but cannot write 1. 392
14.2 register descriptions 14.2.1 receive shift register the receive shift register (rsr) receives serial data. data input at the rxd pin are loaded into rsr in the order received, lsb (bit 0) first. in this way the sci converts received data to parallel form. when one byte has been received, it is automatically transferred to the receive data register (rdr). the h8/500 cpu cannot read or write rsr directly. 14.2.2 receive data register the receive data register (rdr) stores serial receive data. the sci completes the reception of one byte of serial data by moving the received data from the receive shift register (rsr) into rdr for storage. rsr is then ready to receive the next data. this double buffering allows the sci to receive data continuously. the h8/500 cpu can read but not write rdr. rdr is initialized to h'00 by a reset and in the standby modes. bit r/w 7 543210 6 bit initial value r/w 7 0 543210 0000000 rrrrrrrr 6 393
14.2.3 transmit shift register the transmit shift register (tsr) transmits serial data. the sci loads transmit data from the transmit data register (tdr) into tsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from tdr into tsr and starts transmitting again. if tdre is set to 1, however, the sci does not load the tdr contents into tsr. the h8/500 cpu cannot read or write tsr directly. 14.2.4 transmit data register the transmit data register (tdr) is an eight-bit register that stores data for serial transmission. when the sci detects that the transmit shift register (tsr) is empty, it moves transmit data written in tdr into tsr and starts serial transmission. continuous serial transmission is possible by writing the next transmit data in tdr during serial transmission from tsr. the h8/500 cpu can always read and write tdr. tdr is initialized to h'ff by a reset and in the standby modes. bit r/w 7 543210 6 bit initial value r/w 7 1 543210 1111111 r/w r/w r/w r/w r/w r/w r/w r/w 6 394
14.2.5 serial mode register the serial mode register (smr) is an eight-bit register that specifies the sci serial communication format and selects the clock source for the baud rate generator. the h8/500 cpu can always read and write smr. smr is initialized to h'00 by a reset and in the standby modes. bit initial value r/w 7 0 c/a stop chr 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 pe o/e mp cks1 cks0 communication mode selects asynchronous or clocked synchronous mode clock select 1/0 these bits select the baud rate generator? clock source multiprocessor mode stop bit length selects stop bit length parity mode selects even or odd parity parity enable selects whether data includes a parity bit character length selects data length in asynchronous mode selects the multipro- cessor function 395
(1) bit 7?ommunication mode (c/ a ): selects whether the sci operates in asynchronous or clocked synchronous mode. (2) bit 6?haracter length (chr): selects seven-bit or eight-bit data in asynchronous mode. in clocked synchronous mode the data length is always eight bits, regardless of the chr setting. (3) bit 5?arity enable (pe): selects whether to add a parity bit to transmit data and check parity of receive data, in asynchronous mode. in clocked synchronous mode the parity bit is neither added nor checked, regardless of the pe setting. bit 7 c/a description 0 asynchronous mode (initial value) 1 clocked synchronous mode bit 6 chr description 0 eight-bit data (initial value) 1 seven-bit data * note: * when seven-bit data is selected, the msb of the transmit data register (bit 7) is not transmitted. bit 5 pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked * note: * when pe is set to 1 an even or odd parity bit is added to transmit data, depending on the parity mode (o/e) setting. receive data parity is checked according to the even/odd (o/e) mode setting. 396
(4) bit 4?arity mode (o/ e ): selects even or odd parity when parity bits are added and checked. the o/ e setting is used only in asynchronous mode and only when the parity enable bit (pe) is set to 1 to enable parity generation and checking. the o/ e setting is ignored in clocked synchronous mode, or in asynchronous mode when parity is disabled. (5) bit 3?top bit length (stop): selects one or two bits as the stop bit length in asynchronous mode. this setting is used only in asynchronous mode. it is ignored in clocked synchronous mode because no stop bits are added. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1 it is treated as a stop bit. if the second stop bit is 0 it is treated as the start bit of the next incoming character. bit 4 o/e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. if even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. receive data must have an even number of 1s in the received character and parity bit combined. 2. if odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. receive data must have an odd number of 1s in the received character and parity bit combined. bit 3 stop description 0 one stop bit * 1 (initial value) 1 two stop bits * 2 notes: 1. in transmitting, a single 1 bit is added at the end of each transmitted character. 2. in transmitting, two 1 bits are added at the end of each transmitted character. 397
(6) bit 2?ultiprocessor mode (mp): selects a multiprocessor format. when a multiprocessor format is selected, settings of the parity enable (pe) and parity mode (o/ e ) bits are ignored. the mp bit setting is used only in asynchronous mode; it is ignored in clocked synchronous mode. for the multiprocessor communication function, see section 14.3.4, ?ultiprocessor communication. (7) bits 1 and 0?lock select 1 and 0 (cks1/0): these bits select the internal clock source of the on-chip baud rate generator. four clock sources are available: ? ?4, ?16, and ?64. for further information on the clock source, bit rate register settings, and bit rate, see section 14.2.8, ?it rate register. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bit 1 bit 0 cks1 cks0 description 0 0 system clock (? (initial value) 0 1 ?4 1 0 ?16 1 1 ?64 398
14.2.6 serial control register the serial control register (scr) enables the sci transmitter and receiver, selects serial clock output in asynchronous mode, enables and disables interrupts, and selects the transmit/receive clock. the h8/500 cpu can always read and write scr. scr is initialized to h'00 by a reset and in the standby modes. bit initial value r/w 7 0 tie mpie rie 543210 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 6 te re teie cke1 cke0 transmit interrupt enable enables and disables transmit-data-empty interrupts (txi) clock enable 1/0 transmit end interrupt enable multiprocessor interrupt enable receive enable enables and disables the receiver transmit enable enables and disables the transmitter receive interrupt enable enables and disables receive-data-full interrupts (rxi) and receive error interrupts (eri) enables and disables multiprocessor interrupts enables and disables transmit-end interrupts (tei) selects the sci clock source 399
(1) bit 7?ransmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the transmit data register empty bit (tdre)* in the serial status register (ssr) is set to 1 due to transfer of serial transmit data from tdr to tsr. (2) bit 6?eceive interrupt enable (rie): enables or disables the receive-data-full interrupt (rxi) requested when the receive data register full bit (rdrf) in the serial status register (ssr) is set to 1 due to transfer of serial receive data from rsr to rdr. also enables or disables receive- error interrupt (eri) requests. (3) bit 5?ransmit enable (te): enables or disables the sci transmitter. bit 7 tie description 0 transmit-data-empty interrupt request (txi) is disabled * (initial value) 1 transmit-data-empty interrupt request (txi) is enabled note: * the txi interrupt request can be cleared by reading tdre after it has been set to 1, then clearing tdre to 0, or by clearing tie to 0. bit 6 rie description 0 receive-data-full interrupt (rxi) and receive-error interrupt (eri) (initial value) requests are disabled * 1 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are enabled note: * rxi and eri interrupt requests can be cleared by reading the rdrf flag or error flag (fer, per, or orer) after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. bit 5 te description 0 transmitter disabled * 1 , txd pin available for general-purpose i/o (initial value) 1 transmitter enabled * 2 , txd used for transmit data output notes: 1. the transmit data register empty bit (tdre) in the serial status register (ssr) is locked at 1. 2. serial transmitting starts when the transfer data register empty (tdre) bit in the serial status register (ssr) is cleared to 0 after writing of transmit data into tdr. select the transmit format in smr before setting te to 1. 400
(4) bit 4?eceive enable (re): enables or disables the sci receiver. (5) bit 3?ultiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie setting is used only in asynchronous mode, and only if the multiprocessor mode bit (mp) in the serial mode register (smr) is set to 1. the mpie setting is ignored in clocked synchronous mode or when the mp bit is cleared to 0. bit 4 re description 0 receiver disabled * 1 , rxd pin available for general-purpose i/o (initial value) 1 receiver enabled * 2 , rxd used for receive data input notes: 1. clearing re to 0 does not affect the receive flags (rdrf, fer, per, orer). these flags retain their previous values. 2. serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in clocked synchronous mode. select the receive format in smr before setting re to 1. bit 3 mpie description 0 multiprocessor interrupts are disabled (normal receive operation) (initial value) 1 multiprocessor interrupts are enabled. * receive-data-full interrupt requests (rxi), receive-error interrupt requests (eri), and setting of the rdrf, fer, and orer status flags in the serial status register (ssr) are disabled. mpie is cleared to 0 when: 1. mpie is cleared to 0, or 2. multiprocessor bit (mpb) is set to 1 in receive data. note: * the sci does not transfer receive data from rsr to rdr, does not detect receive errors, and does not set the rdrf, fer, and orer flags in the serial status register (ssr). when it receives data with the multiprocessor bit (mpb) set to 1, the sci automatically clears mpie to 0, enables rxi and eri interrupts (if the rie bit in scr is set to 1), and allows fer and orer to be set. 401
(6) bit 2?ransmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if tdr does not contain new transmit data when the msb is transmitted. (7) bits 1 and 0?lock enable 1 and 0 (cke1/0): these bits select the sci clock source and enable or disable clock output from the sck pin. depending on the combination of cke1 and cke0, the sck pin can be used for general-purpose input/output, serial clock output, or serial clock input. the cke0 setting is valid only in asynchronous mode, and only when the sci is internally clocked (cke1 = 0). the cke0 setting is ignored in clocked synchronous mode, or when an external clock source is selected (cke1 = 1). select the sci operating mode in the serial mode register (smr) before setting cke1 and cke0. for further details on selection of the sci clock source, see table 14-6 in section 14.3, ?peration. bit 2 teie description 0 transmit-end interrupt (tei) requests are disabled * (initial value) 1 transmit-end interrupt (tei) requests are enabled * note: * the tei request can be cleared by reading the tdre bit in the serial status register (ssr) after it has been set to 1, then clearing tdre to 0, thereby clearing the transmit end (tend) bit to 0; or by clearing the teie bit to 0. bit 1 bit 0 cke1 cke0 description 0 0 asynchronous mode internal clock, sck pin available for general- purpose input/output * 1 clocked synchronous mode internal clock, sck pin used for serial clock output * 1 0 1 asynchronous mode internal clock, sck pin used for clock output * 2 clocked synchronous mode internal clock, sck pin used for serial clock output 1 0 asynchronous mode external clock, sck pin used for clock input * 3 clocked synchronous mode external clock, sck pin used for serial clock input 1 1 asynchronous mode external clock, sck pin used for clock input * 3 clocked synchronous mode external clock, sck pin used for serial clock input notes: 1. initial value 2. the output clock frequency is the same as the bit rate. 3. the input clock frequency is 16 times the bit rate. 402
14.2.7 serial status register the serial status register (ssr) is an eight-bit register containing multiprocessor bit values, and status flags that indicate sci operating status. the h8/500 cpu can always read and write ssr, but cannot write 1 in the status flags (tdre, rdrf, orer, per, and fer). these flags can be cleared to 0 only if they have first been read after being set to 1. bits 2 (tend) and 1 (mpb) are read-only bits that cannot be written. ssr is initialized to h'84 by a reset and in the standby modes. bit initial value r/w 7 1 tdre per rdrf 543210 0000100 r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w 6 orer fer tend mpb mpbt transmit data register empty multiprocessor multiprocessor bit transmit end parity error framing error overrun error status flag indicating detection of a receive overrun error receive data register full status flag indicating that the sci has stored receive data in rdr note: * software can write 0 to clear the flag, but cannot write 1. status flag indicating that the sci has loaded transmit data from tdr into tsr and new data can be written in tdr status flag indicating detection of a receive framing error status flag indicating detection of a receive parity error status flag indicating end of transmission stores received multi- processor bit value bit transfer value of multi- processor bit to be transmitted 403
(1) bit 7?ransmit data register empty (tdre): indicates that the sci has loaded transmit data from tdr into tsr and new data can be written in tdr. (2) bit 6?eceive data register full (rdrf): indicates that rdr contains new receive data. bit 7 tdre description 0 tdr contains valid transmit data tdre is cleared to 0 when: 1. software reads tdre after it has been set to 1, then writes 0 in tdre 2. the dtc writes data in tdr 1 tdr does not contain valid transmit data (initial value) tdre is set to 1 when: 1. the chip is reset or enters standby mode 2. the te bit in the serial control register (scr) is cleared to 0, or 3. tdr contents are loaded into tsr, so new data can be written in tdr bit 6 rdrf description 0 rdr does not contain new receive data (initial value) rdrf is cleared to 0 when: 1. the chip is reset or enters standby mode 2. software reads rdrf after it has been set to 1, then writes 0 in rdrf 3. the dtc reads data from rdr 1 rdr contains new receive data rdrf is set to 1 when serial data are received normally and transferred from rsr to rdr. note: rdr and rdrf are not affected by detection of receive errors or by clearing of the re bit to 0 in the serial control register. they retain their previous contents. if rdrf is still set to 1 when reception of the next data ends, an overrun error (orer) occurs and receive data are lost. 404
(3) bit 5?verrun error (orer): indicates that data reception ended abnormally due to an overrun error. (4) bit 4?raming error (fer): indicates that data reception ended abnormally due to a framing error in asynchronous mode. bit 5 orer description 0 receiving is in progress or has ended normally (initial value) * 1 orer is cleared to 0 when: 1. the chip is reset or enters standby mode 2. software reads orer after it has been set to 1, then writes 0 in orer 1 a receive overrun error occurred * 2 orer is set to 1 if reception of the next serial data ends when rdrf is set to 1 notes: 1. clearing the re bit to 0 in the serial control register does not affect the orer bit, which retains its previous value. 2. rdr continues to hold the receive data before the overrun error, so subsequent receive data are lost. serial receiving cannot continue while orer is set to 1. in clocked synchronous mode, serial transmitting is also disabled. bit 4 fer description 0 receiving is in progress or has ended normally (initial value) * 1 fer is cleared to 0 when: 1. the chip is reset or enters standby mode 2. software reads fer after it has been set to 1, then writes 0 in fer 1 a receive framing error occurred * 2 fer is set to 1 if the stop bit at the end of receive data is checked and found to be 0. notes: 1. clearing the re bit to 0 in the serial control register does not affect the fer bit, which retains its previous value. 2. when the stop bit length is two bits, only the first bit is checked. the second stop bit is not checked. when a framing error occurs the sci transfers the receive data into rdr but does not set rdrf. serial receiving cannot continue while fer is set to 1. in clocked synchronous mode, serial transmitting is also disabled. 405
(5) bit 3?arity error (per): indicates that data reception ended abnormally due to a parity error in asynchronous mode. (6) bit 2?ransmit end (tend): indicates that when the last bit of a serial character was transmitted tdr did not contain new transmit data, so transmission has ended. tend is a read- only bit and cannot be written. bit 3 per description 0 receiving is in progress or has ended normally (initial value) * 1 per is cleared to 0 when: 1. the chip is reset or enters standby mode 2. software reads per after it has been set to 1, then writes 0 in per 1 a receive parity error occurred * 2 per is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (o/e) in the serial mode register (smr). notes: 1. clearing the re bit to 0 in the serial control register does not affect the per bit, which retains its previous value. 2. when a parity error occurs the sci transfers the receive data into rdr but does not set rdrf. serial receiving cannot continue while per is set to 1. in clocked synchronous mode, serial transmitting is also disabled. bit 2 tend description 0 transmission is in progress tend is cleared to 0 when: 1. software reads tdre after it has been set to 1, then writes 0 in tdre 2. the dtc writes data in tdr 1 end of transmission (initial value) tend is set to 1 when: 1. the chip is reset or enters standby mode 2. te is cleared to 0 in the serial control register (scr) 3. tdre is 1 when the last bit of a serial character (1 byte) is transmitted 406
(7) bit 1?ultiprocessor bit (mpb): stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. mpb is a read-only bit and cannot be written. (8) bit 0?ultiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. the mpbt setting is ignored in clocked synchronous mode, when a multiprocessor format is not selected, or when the sci is not transmitting. bit 1 mpb description 0 multiprocessor bit value in receive data is 0 * (initial value) 1 multiprocessor bit value in receive data is 1 note: * if re is cleared to 0 when a multiprocessor format is selected, mpb retains its previous value. bit 0 mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1 407
14.2.8 bit rate register the bit rate register (brr) is an eight-bit register that, together with the cks1 and cks0 bits in the serial mode register (smr) that select the baud rate generator clock source, determines the serial transmit/receive bit rate. the h8/500 cpu can always read and write brr. brr is initialized to h'ff by a reset and in the standby modes. sci1 and sci2 have independent baud rate generator control, so different values can be set in the two channels. table 14-3 shows examples of brr settings in asynchronous mode. table 14-3 examples of bit rates and brr settings in asynchronous mode (1) bit initial value r/w 7 1 543210 1111111 r/w r/w r/w r/w r/w r/w r/w r/w 6 ?(mhz) 1 1.2288 2 2.097152 bit rate error error error error (bits/s) n n (%) n n (%) n n (%) n n (%) 110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 ?.04 150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21 300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21 600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21 1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 ?.70 2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14 4800 0 7 0 0 12 +0.16 0 13 ?.48 9600 0 3 0 19200 0 1 0 31250 0 0 0.00 0 1 0 38400 0 0 0 408
table 14-3 examples of bit rates and brr settings in asynchronous mode (2) table 14-3 examples of bit rates and brr settings in asynchronous mode (3) ?(mhz) 2.4576 3 3.6864 4 bit rate error error error error (bits/s) n n (%) n n (%) n n (%) n n (%) 110 1 174 ?.26 1 212 +0.03 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 ?.34 0 23 0 0 25 +0.16 9600 0 7 0 0 9 ?.34 0 11 0 0 12 +0.16 19200 0 3 0 0 4 ?.34 0 5 0 31250 0 2 0 0 3 0 38400 0 1 0 0 2 0 ?(mhz) 4.9152 5 6 6.144 bit rate error error error error (bits/s) n n (%) n n (%) n n (%) n n (%) 110 2 86 +0.31 2 88 ?.25 2 106 ?.44 2 108 +0.08 150 1 255 0 2 64 +0.16 2 77 0 2 79 0 300 1 127 0 1 129 +0.16 1 155 0 1 159 0 600 0 255 0 1 64 +0.16 1 77 0 1 79 0 1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0 2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0 4800 0 31 0 0 32 ?.36 0 38 +0.16 0 39 0 9600 0 15 0 0 15 +1.73 0 19 ?.34 0 19 0 19200 0 7 0 0 7 +1.73 0 9 0 31250 0 4 ?.70 0 4 0 0 5 0 0 5 +2.40 38400 0 3 0 0 3 +1.73 0 4 0 409
table 14-3 examples of bit rates and brr settings in asynchronous mode (4) ?(mhz) 7.3728 8 9.8304 10 bit rate error error error error (bits/s) n n (%) n n (%) n n (%) n n (%) 110 2 130 ?.07 2 141 +0.03 2 174 ?.26 3 43 +0.88 150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16 300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16 600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16 1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16 2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16 4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16 9600 0 23 0 0 25 +0.16 0 31 0 0 32 ?.36 19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73 31250 0 7 0 0 9 ?.70 0 9 0 38400 0 5 0 0 7 0 0 7 +1.73 307200 0 0 0 312500 0 0 0 table 14-3 examples of bit rates and brr settings in asynchronous mode (5) ?(mhz) 12 12.288 14 14.7456 bit rate error error error error (bits/s) n n (%) n n (%) n n (%) n n (%) 110 2 212 0.03 2 217 0.08 2 248 ?.17 3 64 0.07 150 2 155 0.16 2 159 0.00 2 181 0.16 2 191 0.00 300 2 77 0.16 2 79 0.00 2 90 0.16 2 95 0.00 600 1 155 0.16 1 159 0.00 1 181 0.16 1 191 0.00 1200 1 77 0.16 1 79 0.00 1 90 0.16 1 95 0.00 2400 0 155 0.16 0 159 0.00 0 181 0.16 0 191 0.00 4800 0 77 0.16 0 79 0.00 0 90 0.16 0 95 0.00 9600 0 38 0.16 0 39 0.00 0 45 ?.93 0 47 0.00 19200 0 19 ?.34 0 19 0.00 0 22 ?.93 0 23 0.00 31250 0 11 0.00 0 11 2.40 0 13 0.00 0 14 ?.70 38400 0 9 ?.34 0 9 0.00 0 10 3.57 0 11 0.00 410
table 14-3 examples of bit rates and brr settings in asynchronous mode (6) ?(mhz) 16 bit rate error (bits/s) n n (%) 110 3 70 0.03 150 2 207 0.16 300 2 103 0.16 600 1 207 0.16 1200 1 103 0.16 2400 0 207 0.16 4800 0 103 0.16 9600 0 51 0.16 19200 0 25 0.16 31250 0 15 0.00 38400 0 12 0.16 notes: 1. settings with an error of 1% or less are recommended. 2. the brr setting is calculated as follows: n = [?(64 2 2n? b)] 10 6 ?1 b: bit rate n: brr setting for baud rate generator (0 n 255) ? operation frequency (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 14-4.) table 14-4 clock sources and n smr settings n clock source cks1 cks0 0 0 0 1 ?4 0 1 2 ?16 1 0 3 ?64 1 1 3. error is calculated as follows: error (%) = {?[(n + 1) b 64 2n? ] 10 6 ?1} 100 411
tables 14-5 and 14-6 indicate the maximum bit rates in asynchronous mode for various system clock frequencies. table 14-5 maximum bit rates for various frequencies (asynchronous mode) settings ?(mhz) maximum bit rate (bits/s) n n 1 31250 0 0 1.2288 38400 0 0 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.6608 614400 0 0 20 625000 0 0 412
table 14-6 maximum bit rates with external clock input (asynchronous mode) ?(mhz) external clock input (mhz) maximum bit rate (bits/s) 1 0.2500 15625 1.2288 0.3072 19200 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 413
table 14-7 shows examples of settings in clocked synchronous mode. table 14-7 examples of bit rates and brr settings in synchronous mode table 14-8 clock sources and n ?(mhz) 12481016 bit rate (bits/s) n n n n n n n n n n n n 110 370 250 1 249 2 124 2 249 3 124 3 249 500 1 124 1 249 2 124 2 249 3 124 1 k 0 249 1 124 1 249 1 124 2 249 2.5 k 0 99 0 199 1 99 1 199 1 249 2 99 5 k 0 49 0 99 0 199 1 99 1 124 1 199 10 k 0 24 0 49 0 99 0 199 0 249 1 99 25 k 0 9 0 19 0 39 0 79 0 99 0 159 50 k 0 4 0 9 0 19 0 39 0 49 0 79 100 k 0 4 0 9 0 19 0 24 0 39 250 k 0 0 * 01 03 07 09 015 500 k 0 0 * 01 03 04 07 1 m 0 0 * 01 03 2.5 m 0 0 * blank: no setting available ? setting possible, but error occurs * : continuous transmit/receive not possible note: the brr setting is calculated as follows: n = [?(8 2 2n? b)] 10 6 ?1 b: bit rate n: brr setting for baud rate generator (0 n 255) ? operation frequency (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 14-8.) smr settings n clock source cks1 cks0 0 0 0 1 ?4 0 1 2 ?16 1 0 3 ?64 1 1 414
14.3 operation 14.3.1 overview the sci has an asynchronous mode in which characters are synchronized individually, and a clocked synchronous mode in which communication is synchronized with clock pulses. serial communication is possible in either mode. asynchronous or clocked synchronous mode and the communication format are selected in the serial mode register (smr), as shown in table 14-9. the sci clock source is selected by the c/ a bit in the serial mode register (smr) and the cke1 and cke0 bits in the serial control register (scr), as shown in table 14-10. (1) asynchronous mode data length is selectable: seven or eight bits. parity and multiprocessor bits are selectable. so is the stop bit length (one or two bits). the foregoing selections constitute the communication format. in receiving, it is possible to detect framing errors (fer), parity errors (per), overrun errors (orer), and the break state. an internal or external clock can be selected as the sci clock source. when an internal clock is selected, the sci operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. when an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) (2) clocked synchronous mode the communication format has a fixed eight-bit data length. in receiving, it is possible to detect overrun errors (orer). an internal or external clock can be selected as the sci clock source. when an internal clock is selected, the sci operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. when an external clock is selected, the sci operates on the input serial clock. the on-chip baud rate generator is not used. 415
table 14-9 serial mode register settings and sci communication formats table 14-10 smr and scr settings and sci clock source selection sci communication format multi- stop data parity processor bit c/a chr pe mp stop mode length bit bit length 00000 asynchronous mode 8-bit data absent absent 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 1 0 0 7-bit data absent 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 0 * 1 0 asynchronous mode 8-bit data absent present 1 bit * 1 (multiprocessor format) 2 bits 1 * 0 7-bit data 1 bit * 1 2 bits 1 **** clocked synchronous 8-bit data absent none mode note: asterisks ( * ) in the table indicate don?-care bits. smr settings bit 7 bit 6 bit 5 bit 2 bit 3 smr scr settings sci transmit/receive clock bit 7 bit 1 bit 0 c/a cke1 cke0 mode sck pin function 0 0 0 asynchronous internal general-purpose input/output (sci does not mode use the sck pin) 1 outputs a clock with frequency matching the bit rate 1 0 external 1 1 0 0 internal outputs the serial clock 1 1 0 external inputs the serial clock 1 clocked synchronous mode clock source inputs a clock with frequency 16 times the bit rate 416
14.3.2 operation in asynchronous mode in asynchronous mode each transmitted or received character begins with a start bit and ends with a stop bit. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci are independent, so full duplex communication is possible. the transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 14-2 shows the general format of asynchronous serial communication. in asynchronous serial communication the communication line is normally held in the mark (high) state. the sci monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and stop bit (high), in that order. when receiving in asynchronous mode, the sci synchronizes on the falling edge of the start bit. the sci samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. receive data are latched at the center of each bit. figure 14-2 data format in asynchronous communication (example: 8-bit data with parity and two stop bits) 0d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1 1 0/1 1 1 (lsb) (msb) serial data start bit 1 bit transmit or receive data 7 or 8 bits one data character (frame) mark (idle) state parity bit stop bit 1 bit or no bit 1 or 2 bits 417
(1) transmit/receive formats: table 14-11 shows the 12 communication formats that can be selected in asynchronous mode. the format is selected by settings in the serial mode register (smr). table 14-11 serial communication formats (asynchronous mode) 12 34 56 78 9101112 chr pe mp stop s stop s stop stop s p stop sp stop stop s stop s stop stop s p stop s p stop stop s mpb stop s mpb stop stop s mpb stop s mpb stop stop 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 * * * * 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 smr: serial mode register p: parity bit s: start bit mpb: multiprocessor bit stop: stop bit note: asterisks ( * ) in the table indicate don?-care bits. smr settings serial communication format and frame length 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data 418
(2) clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci transmit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (smr) and bits cke1 and cke0 in the serial control register (scr). see table 14-10. when an external clock is input at the sck pin, it must have a frequency equal to 16 times the desired bit rate. when the sci operates on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to the bit rate. the phase is aligned as in figure 14-3 so that the rising edge of the clock occurs at the center of each transmit data bit. figure 14-3 phase relationship between output clock and serial data (asynchronous mode) (3) transmitting and receiving data sci initialization (asynchronous mode): before transmitting or receiving, software must clear the te and re bits to 0 in the serial control register (scr), then initialize the sci as follows. when changing the communication mode or format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (tsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (rdr), which retain their previous contents. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. sci operation becomes unreliable if the clock is stopped. figure 14-4 is a sample flowchart for initializing the sci. 0d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 0/1 1 1 sck 1 frame serial data 419
figure 14-4 sample flowchart for sci initialization wait no yes start transmitting or receiving start of initialization clear te and re bits to 0 in scr select communication format in smr set value in brr set cke1 and cke0 bits in scr (leaving te and re cleared to 0) 1 bit interval elapsed? set te or re to 1 in scr set rie, tie, teie, and mpie as necessary select the communication format in the serial mode register (smr). write the value corresponding to the bit rate in the bit rate register (brr). select the clock source in the serial control register (scr). leave rie, tie, teie, mpie, te, and re cleared to 0. if clock output is selected, clock output starts immediately after the setting is made in scr. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scr). also set rie, tie, teie, and mpie as necessary. setting te or re enables the sci to use the txd or rxd pin. the initial states are the mark transmit state, and the idle receive state (waiting for a start bit). 1 2 3 4 1 2 3 4 420
transmitting serial data (asynchronous mode): figure 14-5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. figure 14-5 sample flowchart for transmitting serial data yes no yes no yes no yes no tdre = 1? tend = 1? start transmitting read tdre bit in ssr write transmit data in tdr and clear tdre bit to 0 in ssr all data transmitted? read tend bit in ssr output break signal? set dr = 0, ddr = 1 clear te bit in scr to 0 end sci initialization: the transmit data output function of the txd pin is selected automatically. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr) and clear tdre to 0. to output a break signal at the end of serial transmission: set the ddr bit to 1 and the dr bit to 0 (ddr and dr are i/o port registers), then clear te to 0 in scr. 2 3 4 1 2 3 4 initialize 1 to continue transmitting serial data: read the tdre bit to check whether it is safe to write; if so, write data in tdr, then clear tdre to 0. when the dtc is started by a transmit-data-empty interrupt request (txi) to write data in tdr, the tdre bit is checked and cleared automatically. 421
in transmitting serial data, the sci operates as follows. 1. the sci monitors the tdre bit in ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from tdr into the transmit shift register (tsr). 2. after loading the data from tdr into tsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) is set to 1 in scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data are transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits are output, lsb first. c. parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit: one or two 1 bits (stop bits) are output. e. mark state: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit to 1 in ssr, outputs the stop bit, then continues output of 1 bits in the mark state. if the transmit-end interrupt enable bit (teie) in scr is set to 1, a transmit-end interrupt (tei) is requested. figure 14-6 shows an example of sci transmit operation in asynchronous mode. 422
figure 14-6 example of sci transmit operation (8-bit data with parity and one stop bit) 01 1 1 01 tdre tend d 0 d 1 d 7 0/1 0/1 d 0 d 1 d 7 serial data start bit data parity bit stop bit start bit data parity bit stop bit mark (idle) state txi request txi interrupt handler writes data in tdr and clears tdre to 0 txi request tei request 1 frame 423
receiving serial data (asynchronous mode): figure 14-7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. figure 14-7 sample flowchart for receiving serial data yes start receiving read orer, per, and fer in ssr clear re to 0 in scr end per + fer + orer = 1? 1 2 4 5 1 2 3 4 initialize error handling 3 no rdrf = 1? read receive data from rdr, and clear rdrf bit to 0 in ssr yes no finished receiving? yes read rdrf bit in ssr sci initialization: the receive data function of the rxd pin is selected automatically. receive error handling and break detection: if a receive error occurs, read the orer, per, and fer bits in ssr to identify the error. after executing the necessary error handling, clear orer, per, and fer all to 0. receiving cannot resume if orer, per, or fer remains set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. sci status check and receive data read: read the serial status register (ssr), check that rdrf is set to 1, then read receive data from the receive data register (rdr) and clear rdrf to 0. to continue receiving serial data: check rdrf, read rdr, and clear rdrf to 0 before the stop bit of the current frame is received. if the dtc is started by a receive-data-full interrupt (rxi) to read rdr, the rdrf bit is cleared automatically so this step is unnecessary. , 5 no 424
figure 14-7 sample flowchart for receiving serial data (cont) yes yes yes yes no no no no start of error handling clear orer, per, and fer to 0 in ssr overrun error handling break? framing error handling parity error handling clear re to 0 in scr end orer = 1? fer = 1? per = 1? rts 3 425
in receiving, the sci operates as follows. 1. the sci monitors the receive data line. when it detects a start bit, the sci synchronizes internally and starts receiving. 2. receive data are shifted into rsr in order from lsb to msb. 3. the parity bit and stop bit are received. after receiving these bits, the sci makes the following checks: a. parity check: the number of 1s in the receive data must match the even or odd parity setting of the o/ e bit in smr. b. stop bit check: the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. c. status check: rdrf must be 0 so that receive data can be loaded from rsr into rdr. if these checks all pass, the sci sets rdrf to 1 and stores the received data in rdr. if one of the checks fails (receive error), the sci operates as indicated in table 14-12. note: when a receive error flag is set, further receiving is disabled. when receiving resumes after an error flag was set, the rdrf bit is not set to 1. 4. after setting rdrf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in scr, the sci requests a receive-data-full interrupt (rxi). if one of the error flags (orer, per, or fer) is set to 1 and the receive-data-full interrupt enable bit (rie) in scr is also set to 1, the sci requests a receive-error interrupt (eri). figure 14-8 shows an example of sci receive operation in asynchronous mode. table 14-12 receive error conditions and sci operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends while receive data not loaded rdrf is still set to 1 in ssr from rsr into rdr framing error fer stop bit is 0 receive data loaded from rsr into rdr parity error per parity of receive data differs from receive data loaded even/odd parity setting in smr from rsr into rdr 426
figure 14-8 example of sci receive operation (8-bit data with parity and one stop bit) 14.3.3 clocked synchronous operation in clocked synchronous mode, the sci transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. the transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 14-9 shows the general format in clocked synchronous serial communication. 0 1 1 1 0/1 0 0/1 0 rdrf fer d 0 d 1 d 7 d 0 d 1 d 7 framing error, eri request serial data start bit data parity bit stop bit start bit data parity bit stop bit mark (idle) state 1 frame rxi interrupt handler reads data in rdr and clears rdrf to 0 rxi request 427
figure 14-9 data format in clocked synchronous communication in clocked synchronous serial communication, each data bit is placed on the communication line from one falling edge of the serial clock to the next. data are guaranteed valid at the rising edge of the serial clock. in each character, the serial data bits are transmitted in order from lsb (first) to msb (last). after output of the msb, the communication line remains in the state of the msb. in clocked synchronous mode the sci receives data by synchronizing with the rising edge of the serial clock. (1) communication format: the data length is fixed at eight bits. no parity bit or multiprocessor bit can be added. (2) clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected by clearing or setting the cke1 bit in the serial control register (scr). see table 14-10. when the sci operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received character. when the sci is not transmitting or receiving, the clock signal remains in the high state. ** lsb msb note: * high except in continuous transmitting or receiving don? care don? care bit 7 one unit (character or frame) of serial data transfer direction serial data serial clock bit 6 bit 5 bit 0 bit 1 bit 2 bit 3 bit 4 428
(3) transmitting and receiving data sci initialization (clocked synchronous mode): before transmitting or receiving, software must clear the te and re bits to 0 in the serial control register (scr), then initialize the sci as follows. when changing the communication mode or format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (tsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (rdr), which retain their previous contents. figure 14-10 is a sample flowchart for initializing the sci. 429
figure 14-10 sample flowchart for sci initialization wait no yes start transmitting or receiving start of initialization clear te and re bits to 0 in scr set cke1 and cke0 in scr (leaving rie, tie, teie, mpie, te, and re cleared to 0) set value in brr select communication format in smr 1 bit interval elapsed? set te or re to 1 in scr set rie, tie, teie, and mpie as necessary select the clock source in the serial control register (scr). write 0 in rie, tie, teie, mpie, te, and re. write the value corresponding to the bit rate in the bit rate register (brr). select the serial communication format in the serial mode register (smr). wait for at least the interval required to transmit or receive one bit, then set te or re to 1 in the serial control register (scr). also set rie, tie, teie, and mpie as necessary. setting te or re enables the sci to use the txd or rxd pin. 1 2 3 4 1 2 3 4 430
transmitting serial data (clocked synchrous mode): figure 14-11 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. figure 14-11 sample flowchart for serial transmitting yes no yes no yes no tend = 1? sci initialization: the transmit data output function of the txd pin is selected automatically. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr) and clear tdre to 0. start transmitting read tdre bit in ssr write transmit data in tdr and clear tdre bit to 0 in ssr all data transmitted? read tend bit in ssr clear te bit to 0 in scr end tdre = 1? 2 3 1 2 3 initialize 1 to continue transmitting serial data: read the tdre bit to check whether it is safe to write; if so, write data in tdr, then clear tdre to 0. when the dtc is started by a transmit-data-empty interrupt request (txi) to write data in tdr, the tdre bit is checked and cleared automatically. 431
in transmitting serial data, the sci operates as follows. 1. the sci monitors the tdre bit in ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from tdr into the transmit shift register (tsr). 2. after loading the data from tdr into tsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in scr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. if clock output is selected, the sci outputs eight serial clock pulses. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data are output from the txd pin in order from lsb (bit 0) to msb (bit 7). 3. the sci checks the tdre bit when it outputs the msb (bit 7). if tdre is 0, the sci loads data from tdr into tsr and begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in ssr to 1, and after transmitting the msb, holds the transmit data pin (txd) in the msb state. if the transmit-end interrupt enable bit (teie) in scr is set to 1, a transmit-end interrupt (tei) is requested at this time. 4. after the end of serial transmission, the sck pin is held in the high state. figure 14-12 shows an example of sci transmit operation. 432
figure 14-12 example of sci transmit operation tdre tend serial clock transmit direction serial data bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi request txi interrupt handler writes data in tdr and clears tdre to 0 txi request tei request 1 frame 433
receiving serial data (clocked synchronous mode): figure 14-13 shows a sample flowchart for receiving serial data and indicates the procedure to follow. when switching from asynchronous mode to clocked synchronous mode, make sure that orer, per, and fer are cleared to 0. if orer, per, or fer is set to 1 the rdrf bit will not be set and both transmitting and receiving will be disabled. figure 14-13 sample flowchart for serial receiving yes orer = 1? no sci initialization: the receive data function of the rxd pin is selected automatically. receive error handling and break detection: if a receive error occurs, read the orer bit in ssr then, after executing the necessary error handling, clear orer to 0. neither transmitting nor receiving can resume while orer remains set to 1. clear orer to 0 in ssr to continue receiving serial data: check rdrf, read rdr, and clear rdrf to 0 before the msb (bit 7) of the current frame is received. if the dtc is started by a receive-data-full interrupt request (rxi) to read rdr, the rdrf bit is cleared automatically so this step is unnecessary. rts 3 1 3 2 4 5 overrun error handling start of error handling sci status check and receive data read: read the serial status register (ssr), check that rdrf is set to 1, then read receive data from the receive data register (rdr) and clear rdrf to 0. yes start receiving read orer in ssr clear re to 0 in scr end orer = 1? initialize error handling no rdrf = 1? read receive data from rdr, and clear rdrf bit to 0 in ssr yes no finished receiving? yes read rdrf bit in ssr 1 2 3 4 5 , no 434
in receiving, the sci operates as follows. 1. the sci synchronizes with serial clock input or output and initializes internally. 2. receive data are shifted into rsr in order from lsb to msb. after receiving the data, the sci checks that rdrf is 0 so that receive data can be loaded from rsr into rdr. if this check passes, the sci sets rdrf to 1 and stores the received data in rdr. if the check does not pass (receive error), the sci operates as indicated in table 14-12. note: both transmitting and receiving are disabled while a receive error flag is set. the rdrf bit is not set to 1. be sure to clear the error flag. 3. after setting rdrf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in scr, the sci requests a receive-data-full interrupt (rxi). if the orer bit is set to 1 and the receive-data-full interrupt enable bit (rie) in scr is also set to 1, the sci requests a receive- error interrupt (eri). figure 14-14 shows an example of sci receive operation. figure 14-14 example of sci receive operation rdrf orer serial clock transmit direction serial data rxi request rxi interrupt handler reads data in rdr and clears rdrf to 0 rxi request 1 frame overrun error, eri request bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 435
transmitting and receiving serial data simultaneously (clocked synchronous mode): figure 14-15 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. figure 14-15 sample flowchart for simultaneous transmitting and receiving no start transmitting and receiving read tdre bit in ssr clear te and re bits to 0 in scr end tdre = 1? 1 2 4 5 1 2 5 initialize error handling 3 yes orer = 1? no finished transmitting and receiving? yes write transmit data in tdr and clear tdre bit to 0 in ssr * read orer bit in ssr read rdrf bit in ssr no rdrf = 1? read receive data from rdr and clear rdrf bit to 0 in ssr yes yes sci initialization: the transmit data output function of the txd pin and receive data input function of the rxd pin are selected, enabling simultaneous transmitting and receiving. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr) and clear tdre to 0. 3 receive error handling: if a receive error occurs, read the orer bit in ssr then, after executing the necessary error handling, clear orer to 0. neither transmitting nor receiving can resume while orer remains set to 1. sci status check and receive data read: read the serial status register (ssr), check that the rdrf bit is 1, then read receive data from the receive data register (rdr) and clear rdrf to 0 to continue transmitting and receiving serial data: check rdrf, read rdr, and clear rdrf to 0 before the msb (bit 7) of the current frame is received. also read the tdre bit to check whether it is safe to write; if so, write data in tdr, then clear tdre to 0 before the msb (bit 7) of the current frame is transmitted. when the dtc is started by a transmit-data- empty interrupt request (txi) to write data in tdr, the tdre bit is checked and cleared automatically. when the dtc is started by a receive-data-full interrupt request (rxi) to read rdr, the rdrf bit is cleared automatically. note: * 4 in switching from transmitting or receiving to simultaneous transmitting and receiving, clear both te and re to 0, then set both te and re to 1. no 436
14.3.4 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id. a serial communication cycle consists of an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor should start by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor should send transmit data with the multiprocessor bit cleared to 0. when a receiving processor receives data with the multiprocessor bit set to 1, if multiprocessor interrupts are enabled, an interrupt is requested. the interrupt-handling routine should compare the data with the processors own id. if the id matches, the processor should continue to receive data. if the id does not match, the processor should skip further incoming data until it again receives data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 14-16 shows an example of communication among different processors using a multiprocessor format. (1) communication formats: four formats are available. parity-bit settings are ignored when a multiprocessor format is selected. for details see table 14-9. (2) clock: see the description of asynchronous mode. 437
figure 14-16 example of communication among processors using multiprocessor format (sending data h'aa to receiving processor a) h'01 h'aa (id = 01) (id = 02) (id = 03) (id = 04) (mpb = 1) (mpb = 0) transmitting processor receiving processor a serial communication line receiving processor b receiving processor c receiving processor d serial data id-sending cycle: receiving processor address data-sending cycle: data sent to receiving processor specified by id mpb: multiprocessor bit 438
(3) transmitting and receiving data transmitting multiprocessor serial data: figure 14-17 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. figure 14-17 sample flowchart for transmitting multiprocessor serial data yes no yes no yes no tend=1? yes no sci initialization: the transmit data output function of the txd pin is selected automatically. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr). also set mpbt (multiprocessor bit transfer) to 0 or 1 in ssr. finally, clear tdre to 0. to output a break signal at the end of serial transmission: set the ddr bit to 1 and the dr bit to 0 (ddr and dr are i/o port registers), then clear te to 0 in scr. start transmitting read tdre bit in ssr write transmit data in tdr and set mpbt in ssr clear tdre bit to 0 all data transmitted? read tend bit in ssr output break signal? set dr = 0, ddr = 1 clear te bit to 0 in scr end tdre=1? 1 2 3 4 1 2 3 4 initialize to continue transmitting serial data: read the tdre bit to check whether it is safe to write; if so, write data in tdr, then clear tdre to 0. when the dtc is started by a transmit- data-empty interrupt request (txi) to write data in tdr, the tdre bit is checked and cleared automatically. 439
in transmitting serial data, the sci operates as follows. 1. the sci monitors the tdre bit in ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from tdr into the transmit shift register (tsr). 2. after loading the data from tdr into tsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in scr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data are transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits are output, lsb first. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit: one or two 1 bits (stop bits) are output. e. mark state: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in ssr to 1, outputs the stop bit, then continues output of 1 bits in the mark state. if the transmit-end interrupt enable bit (teie) in scr is set to 1, a transmit-end interrupt (tei) is requested at this time. figure 14-18 shows an example of sci transmit operation using a multiprocessor format. 440
figure 14-18 example of sci transmit operation (8-bit data with multiprocessor bit and one stop bit) 01 1 1 0/1 0 1 tdre tend mpb mpb serial data start bit data stop bit start bit data stop bit mark (idle) state txi request txi interrupt handler writes data in tdr and clears tdre to 0 txi request tei request 1 frame d 0 d 1 d 7 d 0 d 1 d 7 0/1 441
receiving multiprocessor serial data: figure 14-19 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. figure 14-19 sample flowchart for receiving multiprocessor serial data yes no yes no no yes no yes yes no rdrf = 1? rdrf = 1? sci initialization: the receive data function of the rxd pin is selected automatically. id receive cycle: set the mpie bit in the serial control register (scr) to 1. sci status check and id check: read the serial status register (ssr), check that rdrf is set to 1, then read receive data from the receive data register (rdr) and compare with the processor's own id. if the id does not match the receive data, set mpie to 1 again and clear rdrf to 0. if the id matches the receive data, clear rdrf to 0. sci status check and data receiving: read ssr, check that rdrf is set to 1, then read data from the receive data register (rdr). receive error handling and break detection: if a receive error occurs, read the orer and fer bits in ssr to identify the error. after executing the necessary error handling, clear both orer and fer to 0. receiving cannot resume while orer or fer remains set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. start receiving set mpie bit to 1 in scr read rdrf bit in ssr read receive data from rdr own id? read orer and fer bits in ssr read rdrf bit in ssr fer or orer = 1? read receive data from rdr finished receiving? clear re to 0 in scr end error handling 1 2 3 4 5 1 2 3 4 5 initialize no yes read orer and fer bits in ssr fer or orer = 1? 442
figure 14-19 sample flowchart for receiving multiprocessor serial data (cont) yes yes yes no no no fer = 1? orer = 1? error handling clear orer and fer bits to 0 in ssr overrun error handling framing error handling? clear re bit to 0 in scr end rts break? 443
figure 14-20 shows an example of sci receive operation using a multiprocessor format. figure 14-20 example of sci receive operation (eight-bit data with multiprocessor bit and one stop bit) 1 1 rdrf mpb mpb mpie rdr value id1 01001 d 0 d 1 d 7 1d 0 d 1 d 7 serial data start bit data (id1) stop bit start bit data (data1) stop bit idle (mark) state rxi request, mpie = 0 rxi handler reads rdr data and clears rdrf to 0 not own id, so mpie is set to 1 again no rxi request, rdr not updated (multiprocessor interrupt) a. own id does not match data b. own id matches data rdrf mpie rdr value id1 id2 data2 01001 d 0 d 1 d 7 1d 0 d 1 d 7 1 1 mpb mpb start bit data (id2) stop bit start bit data (data2) stop bit idle (mark) state serial data rxi request, mpie = 0 rxi handler reads rdr data and clears rdrf to 0 own id, so receiv- ing continues, with data received at each rxi mpie set to 1 again (multiprocessor interrupt) mpb mpb 444
14.4 interrupts and dtc the sci has four interrupt sources in each channel: transmit-end (tei), receive-error (eri), receive-data-full (rxi), and transmit-data-empty (txi). table 14-13 lists the interrupt sources and indicates their priority. table 14-13 sci interrupt sources these interrupts can be enabled and disabled by the tie and rie bits in the serial control register (scr). each interrupt request is sent separately to the interrupt controller. txi is requested when the tdre bit in ssr is set to 1. tei is requested when the tend bit in ssr is set to 1. txi can start the data transfer controller (dtc) to transfer data. tdre is automatically cleared to 0 when the dtc executes the data transfer. tei cannot start the dtc. rxi is requested when the rdrf bit in ssr is set to 1. eri is requested when the orer, per, or fer bit in ssr is set to 1. rxi can start the dtc to transfer data. rdrf is automatically cleared to 0 when the dtc executes the data transfer. eri cannot start the dtc. 14.5 usage notes note the following points when using the sci. (1) tdr write and tdre: the tdre bit in the serial status register (ssr) is a status flag indicating loading of transmit data from tdr into tsr. the sci sets tdre to 1 when it transfers data from tdr to tsr. data can be written into tdr regardless of the state of tdre. if new data are written in tdr when tdre is 0, the old data stored in tdr will be lost because these data have not yet been transferred to tsr. before writing transmit data to tdr, be sure to check that tdre is set to 1. (2) simultaneous multiple receive errors: table 14-14 indicates the state of ssr status flags when multiple receive errors occur simultaneously. when an overrun error occurs the rsr contents are not transferred to rdr, so receive data are lost. interrupt source description dtc availability priority eri receive error (orer, per, or fer) no high rxi receive data register full (rdrf) yes txi transmit data register empty (tdre) yes tei transmit end (tend) no low 445
table 14-14 ssr status flags and transfer of receive data (3) break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so fer is set and the parity error flag (per) may also be set. in the break state the sci receiver continues to operate, so if the fer bit is cleared to 0 it will be set to 1 again. (4) sending a break signal: when te is cleared to 0 the txd pin becomes an i/o port, the level and direction (input or output) of which are determined by the dr and ddr bits. this feature can be used to send a break signal. after the serial transmitter is initialized, the dr value substitutes for the mark state until te is set to 1 (the txd pin function is not selected until te is set to 1). the ddr and dr bits should therefore both be set to 1 beforehand. to send a break signal during serial transmission, clear the dr bit to 0, then clear te to 0. when te is cleared to 0 the transmitter is initialized, regardless of its current state, so the txd pin becomes an output port outputting the value 0. (5) receive error flags and transmitter operation (clocked synchronous mode only): when a receive error flag (orer, per, or fer) is set to 1, the sci will not start transmitting even if te is set to 1. be sure to clear the receive error flags to 0 when starting to transmit. note that clearing re to 0 does not clear the receive error flags. (6) receive data sampling timing in asynchronous mode and receive margin: in asynchronous mode the sci operates on an base clock with 16 times the bit rate frequency. in receiving, the sci synchronizes internally with the falling edge of the start bit, which it samples on the base clock. receive data are latched on the rising edge of the eighth base clock pulse. see figure 14-21. ssr status flags rdrf orer fer per rsr ? rdr receive errors 1100 overrun error 0010 m framing error 0001 m parity error 1110 overrun error + framing error 1101 overrun error + parity error 0011 m framing error + parity error 1111 overrun error + framing error + parity error m : receive data are transferred from rsr to rdr. : receive data are not transferred from rsr to rdr. receive data transfer rsr ? rdr 446
figure 14-21 receive data sampling timing in asynchronous mode the receive margin in asynchronous mode can therefore be expressed as in equation (1). m = {(0.5 ? ) ?(l ?0.5 ? ) f ? (1 + f)} 100% (1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5 the receive margin is 46.875%, as given by equation (2). d = 0.5, f = 0 m = (0.5 ?1/2 16) 100% = 46.875% (2) this is a theoretical value. a reasonable margin to allow in system designs is 20 to 30%. (7) sci channel 3: use of pins for this channel must be enabled by setting bits 6, 5, and 3 in the port a control register (pacr). channel 3 is not present in the h8/538. 07 15 7 00 15 d 0 internal base clock receive data (rxd) synchronization sampling timing data sampling timing 16 clocks 8 clocks start bit d 1 1 2n 1 2n |d ?0.5| n 447
448
section 15 a/d converter 15.1 overview the chip includes a 10-bit successive-approximations a/d converter. software can select a maximum of 12 analog input channels. 15.1.1 features a/d converter features are listed below. ten-bit resolution number of input channels: 12 high-speed conversion conversion time: minimum 13.4 ? per channel (10-mhz system clock, h8/538), minimum 8.3 ? per channel (16-mhz system clock, h8/539) two conversion modes single mode: a/d conversion of one channel scan mode: continuous conversion on one to 12 channels twelve 10-bit a/d data registers a/d conversion results are transferred for storage into 12 a/d data registers. each channel has its own a/d data register. built-in sample-and-hold function a sample-and-hold circuit is built into the a/d converter, permitting a simplified external analog input circuit. a/d conversion interrupt with dtc (data transfer controller) support at the end of a/d conversion, an a/d end interrupt request (adi) can be sent to the h8/500 cpu. the adi interrupt can also be served by the dtc. external triggering a/d conversion can be started by an external trigger signal. selectable analog conversion voltage range the analog voltage conversion range can be set from 3.5 to 5.5 v by input at the v ref pin. a/d conversion can also be started by the ipu. 449
15.1.2 block diagram figure 15-1 shows a block diagram of the a/d converter. figure 15-1 a/d converter block diagram addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addrb addra successive-approximations register module data bus analog multiplexer sample-and-hold circuit a/d conversion control circuit bus interface adcsr adcr on-chip data bus adi interrupt request signal adtrg external trigger signal (or ipu compare match signal) v ref av cc av ss 10 bit d/a an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 8 an 9 an 10 an 11 legend addr0: a/d data register 0 addr1: a/d data register 1 addr2: a/d data register 2 addr3: a/d data register 3 addr4: a/d data register 4 addr5: a/d data register 5 addr6: a/d data register 6 addr7: a/d data register 7 addr8: a/d data register 8 addr9: a/d data register 9 addra: a/d data register a addrb: a/d data register b adcr: a/d control register adcsr: a/d control/status register ?8 ?16 + 450
15.1.3 input/output pins table 15-1 summarizes the a/d converters input pins. the 12 analog input pins (an 0 to an 11 ) are divided into three groups: an 0 to an 3 (group 0), an 4 to an 7 (group 1), and an 8 to an 11 (group 2). the adtrg pin can trigger the start of a/d conversion externally. the a/d converter starts a/d conversion when a low pulse is applied to this pin. av cc and av ss are the power supply for the analog circuits in the a/d converter. v ref is a conversion reference voltage. to protect the reliability of the chip, av cc , av ss , v cc , and v ss should be related as follows: av cc = v cc 10%; av ss = v ss . av cc and av ss must not be left open, even if the a/d converter is not used (include hardware/software stand-by mode). voltages applied to the analog input pins should be in the range av ss ann v ref . table 15-1 a/d converter pins pin name abbreviation input/output function analog power supply av cc input analog power supply analog ground av ss input analog ground and reference voltage reference voltage v ref input analog reference voltage analog input 0 an 0 input analog input pins 0 to 3 (analog group 0) analog input 1 an 1 input analog input 2 an 2 input analog input 3 an 3 input analog input 4 an 4 input analog input pins 4 to 7 (analog group 1) analog input 5 an 5 input analog input 6 an 6 input analog input 7 an 7 input analog input 8 an 8 input analog input pins 8 to 11 (analog group 2) analog input 9 an 9 input analog input 10 an 10 input analog input 11 an 11 input a/d trigger adtrg input external trigger pin for a/d conversion 451
15.1.4 register configuration table 15-2 summarizes the a/d converters registers. table 15-2 a/d converter registers address name abbreviation r/w initial value h'fea0 a/d data register 0 (high/low) addr0(h/l) r h'0000 h'fea2 a/d data register 1 (high/low) addr1(h/l) r h'0000 h'fea4 a/d data register 2 (high/low) addr2(h/l) r h'0000 h'fea6 a/d data register 3 (high/low) addr3(h/l) r h'0000 h'fea8 a/d data register 4 (high/low) addr4(h/l) r h'0000 h'feaa a/d data register 5 (high/low) addr5(h/l) r h'0000 h'feac a/d data register 6 (high/low) addr6(h/l) r h'0000 h'feae a/d data register 7 (high/low) addr7(h/l) r h'0000 h'feb0 a/d data register 8 (high/low) addr8(h/l) r h'0000 h'feb2 a/d data register 9 (high/low) addr9(h/l) r h'0000 h'feb4 a/d data register a (high/low) addra(h/l) r h'0000 h'feb6 a/d data register b (high/low) addrb(h/l) r h'0000 h'feb8 a/d control/status register adcsr r/w * h'00 h'feb9 a/d control register adcr r/w h'1f note: * software can write 0 in bit 7 of the a/d control/status register (adcsr) to clear the flag, but cannot write 1. 452
15.2 register descriptions 15.2.1 a/d data registers 0 to b a/d data registers 0 to b (addr0 to addrb) are 16-bit read-only registers that store the results of a/d conversion of the analog inputs. there are 12 registers, corresponding to analog inputs 0 to 11 (an 0 to an 11 ). the a/d data registers are initialized to h'0000 by a reset and in the standby modes. the on-chip a/d converter converts the analog inputs to 10-bit digital values. the upper eight of the 10 bits are stored in the upper byte of the a/d data register of the selected channel. the lower two bits are stored in the lower byte of the a/d data register. only the two upper bits of the lower byte of an a/d data register are valid. table 15-3 indicates the pairings of analog input channels and a/d data registers. the h8/500 cpu can always read and write the a/d data registers. the upper byte must always be read before the lower byte. it is possible to read only the upper byte of an a/d data register, but it is not possible to read only the lower byte. for further details see section 15.3, ?8/500 cpu interface.? bits 5 to 0 of the a/d data registers are reserved bits that cannot be modified and always read 0. bit initial value r/w 7 0 ad9 ad5 ad8 543210 0000000 rrrrrrrr 6 ad7 ad6 ad4 ad3 ad2 addrnh (upper byte) bit initial value r/w 7 0 ad1 ad0 543210 0000000 rrrrrrrr 6 addrnl (lower byte) 453
table 15-3 analog input channels and a/d data registers 15.2.2 a/d control status register the a/d control status register (adcsr) is an eight-bit readable/writable register that selects the a/d conversion mode. adcsr is initialized to h'00 by a reset and in the standby modes. analog input a/d data analog input a/d data analog input a/d data channel register channel register channel register an 0 addr0 an 4 addr4 an 8 addr8 an 1 addr1 an 5 addr5 an 9 addr9 an 2 addr2 an 6 addr6 an 10 addra an 3 addr3 an 7 addr7 an 11 addrb bit initial value r/w 7 0 adf ch3 adie 543210 0000000 r/(w) * r/w r/w r/w r/w r/w r/w r/w 6 adm1 adm0 ch2 ch1 ch0 a/d end flag indicates end of a/d conversion a/d interrupt enable enables and disables a/d end interrupts these bits select the a/d conversion mode (single and scan modes) a/d mode 1/0 these bits select analog input channels channel select 3? note: * software can write 0 to clear the flag but cannot write 1. 454
(1) bit 7?/d end flag (adf): indicates the end of a/d conversion. adf is initialized to 0 by a reset and in the standby modes. after adf is set to 1, the a/d converter operates differently in single mode and scan mode. in single mode, after loading a digital value into an a/d data register, the a/d converter sets adf to 1 then goes into the idle state. in scan mode, after completing all conversion in one selected analog group, the a/d converter sets adf to 1 then continues converting. software cannot write 1 in adf. (2) bit 6?/d interrupt enable (adie): enables or disables the a/d end interrupt (adi). adie is initialized to 0 by a reset and in the standby modes. when a/d conversion ends and the adf bit in adcsr is set to 1, if adie is also set to 1 an a/d end interrupt (adi) is requested. the adi interrupt request can be cleared by clearing adf to 0 or clearing adie to 0. bit 7 adf description 0 a/d conversion is in progress or the a/d converter is idle (initial value) adf is cleared to 0 when: 1. software reads adf after it has been set to 1, then writes 0 in adf 2. the dtc is started by adi 1 a/d conversion has ended and a digital value has been loaded into one or more a/d data registers adf is set to 1 when: 1. a/d conversion ends in single mode 2. all conversion in one selected analog group ends bit 6 adie description 0 a/d end interrupt (adi) is disabled (initial value) 1 a/d end interrupt (adi) is enabled 455
(3) bits 5 and 4?/d mode 1/0 (adm1/0): these bits select single mode, four-channel scan mode, eight-channel scan mode, or 12-channel scan mode as the a/d conversion mode. adm1 and adm0 are cleared to 00 by a reset and in the standby modes, selecting single mode. to ensure correct operation, always clear adst to 0 before changing the conversion mode. when adm1 and adm0 are cleared to 00, single mode is selected. in single mode one analog channel is converted once. the channel is selected by bits ch3 to ch0 in adcsr. setting adm1 and adm0 to 01 selects four-channel scan mode. in scan mode, one or more channels are converted continuously. the channels converted in scan mode are selected by bits ch3 to ch0 in adcsr. in four-channel scan mode, a/d conversion is performed in the four channels in analog group 0 (an 0 to an 3 ), analog group 1 (an 4 to an 7 ), or analog group 2 (an 8 to an 11 ). setting adm1 and adm0 to 10 selects eight-channel scan mode. a/d conversion is peformed in the eight channels in analog group 0 (an 0 to an 3 ) and analog group 1 (an 4 to an 7 ). setting adm1 and adm0 to 01 selects 12-channel scan mode. a/d conversion is performed in the 12 channels in analog group 0 (an 0 to an 3 ), analog group 1 (an 4 to an 7 ), and analog group 2 (an 8 to an 11 ). for further details on operation in single and scan modes, see section 15.4, ?peration. bit 5 bit 4 adm1 adm0 description 0 0 single mode 0 1 four-channel scan mode (analog group 0, 1, or 2) 1 0 eight-channel scan mode (analog groups 0 and 1) 1 1 twelve-channel scan mode (analog groups 0, 1, and 2) 456
(4) bits 3 to 0?hannel select 3 to 0 (ch3 to ch0): these bits and adm1 and adm0 select the analog input channels. ch3 to ch0 are initialized to 0000 by a reset and in the standby modes. to ensure correct operation, always clear adst to 0 in the a/d control register (adcr) before changing the analog input channel selection. bit 3 bit 2 bit 1 bit 0 analog input channels ch3 ch2 ch1 ch0 single mode four-channel scan mode 0000an 0 (initial value) an 0 01an 1 an 0, 1 10an 2 an 0? 11an 3 an 0? 100an 4 an 4 01an 5 an 4, 5 10an 6 an 4? 11an 7 an 4? 10 * 1 00an 8 an 8 01an 9 an 8, 9 10an 10 an 8?0 11an 11 an 8?1 bit 3 bit 2 bit 1 bit 0 analog input channels ch3 ch2 ch1 ch0 eight-channel scan mode 12-channel scan mode 0000an 0, 4 an 0, 4, 8 01an 0, 1, 4, 5 an 0, 1, 4, 5, 8, 9 10an 0?,4? an 0?, 4?, 8?0 11an 0? an 0?1 100an 0, 4 an 0, 4, 8 01an 0, 1, 4, 5 an 0, 1, 4, 5, 8, 9 10an 0?, 4? an 0?, 4?, 8?0 11an 0? an 0?1 10 * 1 0 0 reserved * 2 an 0, 4, 8 01 an 0, 1, 4, 5, 8, 9 10 an 0?, 4?, 8?0 11 an 0?1 notes: 1. must be cleared to 0. 2. reserved for future expansion. must not be used. 457
15.2.3 a/d control register the a/d control register (adcr) is an eight-bit readable/writable register that controls the start of a/d conversion and selects the a/d clock. adcr is initialized to h'1f by a reset and in the standby modes. bits 4 to 0 of adcr are reserved for future expansion. they cannot be modified and always read 1. (1) bit 7?rigger enable (trge): enables or disables external triggering of a/d conversion. when trge is set to 1, p7 1 automatically becomes the adtrg input pin. trge is initialized to 0 by a reset and in the standby modes. after trge is set to 1, if a low pulse is input at the adtrg pin, the a/d converter detects the falling edge of the pulse and sets the adst bit in adcr to 1. subsequent operation is the same as if software had set the adst bit to 1. external triggering operates only when the adst bit is cleared to 0. when the external trigger function is used, the low pulse input at the adtrg pin must have a width of at least 1.5 system clocks (1.5?. for further details see section 15.4.4, ?xternal triggering of a/d conversion. bit initial value r/w 7 0 trge cks 543210 0011111 r/w r/w r/w 6 adst trigger enable enables and disables external triggering of a/d conversion clock select selects the a/d conversion time a/d start starts and stops a/d conversion reserved bits bit 7 trge description 0 a/d conversion cannot be externally triggered (initial value) 1 a/d conversion can be externally triggered (p7 1 is the adtrg pin.) 458
(2) bit 6?lock select (cks): selects the a/d conversion time. a/d conversion is performed in 266 states when cks is cleared to 0, or in 134 states when cks is set to 1. cks is initialized to 0 by a reset and in the standby modes. to ensure correct operation, always clear adst to 0 before changing the a/d conversion time. (3) bit 5?/d start (adst): starts and stops a/d conversion. a/d conversion starts when adst is set to 1 and stops when adst is cleared to 0. adst is initialized to 0 by a reset and in the standby modes. the adst bit operates differently in single and scan modes. in single mode, adst is cleared to 0 automatically after a/d conversion of one channel. in scan mode, after all selected analog inputs have been converted a/d conversion of all these channels begins again, so adst remains set to 1. when the conversion time or analog input channel selection is changed in scan mode, the adst bit should first be cleared to 0 to halt a/d conversion. before changing the a/d conversion time (cks bit in adcr), operating mode (adm1/0 bits in adcsr), or analog input channel selection (bits ch3 to ch0 in adcsr), always check that the a/d converter is stopped (adst = 0). making these changes while the a/d converter is operating (adst = 1) may produce incorrect values in the a/d data registers. (4) bits 4 to 0?eserved: these bits are reserved for future expansion. they cannot be modified and always read 1. bit 6 cks description 0 conversion time = 266 states (maximum) (initial value) 1 conversion time = 134 states (maximum) bit 5 adst description 0 a/d conversion is stopped (initial value) 1 a/d conversion is in progress clearing conditions: 1. single mode: cleared to 0 automatically at the end of a/d conversion 2. scan mode: check that adf is set to 1 in adcsr, then write 0 in adst 459
15.3 h8/500 cpu interface a/d data registers 0 to b (addr0 to addrb) are 16-bit registers, but they are connected to the h8/500 cpu via an eight-bit on-chip data bus. the upper and lower bytes of an a/d data register are necessarily read separately. to prevent data from changing between the reading of the upper and lower bytes of an a/d data register, the lower byte is read using a temporary register (temp). the upper byte can be read directly. an a/d data register is read as follows. the upper byte must be read first. the h8/500 cpu receives the upper-byte data directly at this time. at the same time, the a/d converter transfers the lower-byte data internally into temp. next, when the lower byte is read, the h8/500 cpu receives the contents of temp. when reading an a/d data register using byte operand size, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read incorrect data may be obtained. when an a/d data register is read using word operand size, the upper byte will automatically be read before the lower byte. figure 15-2 shows the data flow when an a/d data register is read. in the example shown, the upper byte of the a/d data register contains h'aa and the lower byte contains h'40. first the h8/500 cpu reads h'aa directly from the upper byte while h'40 is transferred to temp in the a/d converter. next, when the h8/500 cpu reads the lower byte of the a/d data register, it obtains the temp contents. 460
figure 15-2 a/d data register read operation (reading h'aa40) on-chip bus bus interface module data bus on-chip bus bus interface module data bus (1) addrnh (upper byte) read: addrnh [h'aa] ? h8/500 cpu [h'aa] h8/500 cpu (h'aa) (2) addrnl (lower byte) read: addrnh [h'??] ? not transferred h8/500 cpu (h'40) addrnl [h'??] ? not transferred temp [h'40] ? h8/500 cpu [h'40] addrnl [h'40] ? temp [h'40] addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) addrnl (h'??) addrnh (h'??) a b a a b c c c 461
15.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and scan mode. in single mode, one selected channel is converted once. in scan mode, one or more selected channels are converted repeatedly until the adst bit in the a/d control register (adcr) is cleared to 0. 15.4.1 single mode single mode can be selected to perform one a/d conversion on one channel. single mode is selected by clearing bits adm1 and adm0 to 00 in the a/d control/status register (adcsr). a/d conversion then starts when the adst bit is set to 1 in adcr. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf bit is set to 1 in adcsr. if the adie bit is also set to 1, an adi interrupt is requested. to clear adf to 0, first read adf after adf has been set to 1, then write 0 in adf. if the adi interrupt is served by the data transfer controller (dtc), however, adf is cleared to 0 automatically. figure 15-3 shows a flowchart for selecting analog input channel 1 (an 1 ) and performing a/d conversion in single mode. figure 15-4 is a timing diagram. 462
figure 15-3 flowchart for single mode adf = 1? yes no no yes 1 2 3 4 5 6 7 single mode read a/d data register (while adf = 1 and adst = 0) read adcsr and clear adf to 0 convert again? end (trge = 0, adst = 0, cks = 1) (adie = 0, adm1, 0 = 00, ch3? = 0001) with adst cleared to 0, set trge and cks (the settings shown disable external triggering and select 134- state conversion time). set adm1, adm0 and ch3 to ch0 in adcsr (the settings shown enable adi interrupts, select single mode, and select an1). set adst to 1 to start a/d conversion. wait for adf (a/d end flag) to be set to 1 in adcsr. when adf is set, an adi interrupt is requested and the a/d result processing routine starts . [a/d result processing routine] read the a/d data register. (adst has been cleared to 0 automatically.) read the 1 value of adf, then write 0 to clear adf to 0. to convert the same channel again, go to step . to change the mode or channel, go to step . 1 2 3 4 5 6 7 5 1 3 h'20 ? adcr h'01 ? adcsr 1 ? adst 463
figure 15-4 example of a/d converter operation (single mode, channel 1 selected) addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addra addrb 1 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 2 1 2 adi interrupt request adst bit (adcr bit 5) adf bit (adcsr bit 7) channel 0 (an 0 ) channel 1 (an 1 ) channel 2 (an 2 ) channel 3 (an 3 ) channel 4 (an 4 ) channel 5 (an 5 ) channel 6 (an 6 ) channel 7 (an 7 ) channel 8 (an 8 ) channel 9 (an 9 ) channel 10 (an 10 ) channel 11 (an 11 ) set adst to 1 * adi interrupt request a/d conversion starts adst cleared to 0 clear adf to 0 * set adst to 1 * clear adf to 0 * waiting waiting waiting waiting waiting waiting waiting waiting waiting waiting waiting waiting a/d conversion waiting a/d conversion waiting read conversion result * a/d conversion result conversion result vertical arrows ( ) indicate instructions executed by software. boxes indicate operations performed by the a/d converter. note: * 464
15.4.2 scan mode scan mode can be selected to perform a/d conversion on one or more channels repeatedly (to monitor the channels continuously, for example). scan mode is selected by setting bits adm1 and adm0 in the a/d control/status register (adcsr) to 01, 10, or 11. the 01 setting selects four-channel scan mode. the 10 setting selects eight-channel scan mode. the 11 setting selects 12-channel scan mode. a/d conversion starts when the adst bit in adcr is set to 1. in scan mode the channels are converted in ascending order of channel number (an 0 , an 1 , ? an 11 ). the adst bit remains set to 1 until software clears it to 0. when all conversion in one selected analog group is completed, the adf bit in adcsr is set to 1, then a/d conversion is performed again. if the adie bit in adcsr is set to 1, then when adf is set to 1 an adi interrupt is requested. to clear adf to 0, first read adf after it has been set to 1, then write 0 in adf. if the adi interrupt is served by the data transfer controller (dtc), however, adf is cleared to 0 automatically. figure 15-5 shows a flowchart for selecting analog input channels 0 and 1 (an 0 and an 1 ) and performing a/d conversion in four-channel scan mode. figure 15-6 is a timing diagram. 465
figure 15-5 flowchart for scan mode adf = 1? yes no no yes 1 2 3 4 5 6 7 scan mode read a/d data registers (while adf = 1 and adst = 1) read adcsr and clear adf to 0 continue monitoring? end h'20 ? adcr (trge = 0, adst = 0, cks = 1) adcsr ? h'11 (adie = 0, adm1, 0 = 01, ch3? = 0001) adst 1 with adst cleared to 0, set trge and cks (the settings shown disable external triggering and select 134- state conversion time). set adm1, adm0 and ch3 to ch0 in adcsr (the settings shown enable adi interrupts, select four-channel scan mode, and select an0 and an1). set adst to 1 to start a/d conversion. wait for adf (a/d end flag) to be set to 1 in adcsr. when adf is set, an adi interrupt is requested and the a/d result processing routine starts . [a/d result processing routine] read the a/d data registers. (adst remains set to 1.) read the 1 value of adf, then write 0 to clear adf to 0. to continue monitoring, go to step . to change the mode or channels, go to step . write 0 in adst to stop a/d conversion. 1 2 3 4 5 6 7 5 1 4 8 adst ? 0 8 ? 466
figure 15-6 example of a/d converter operation (four-channel scan mode, channels 0 and 1 selected) addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addra addrb h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 h'0000 adi interrupt request adst bit (adcr bit 5) adf bit (adcsr bit 7) channel 0 (an 0 ) channel 1 (an 1 ) channel 2 (an 2 ) channel 3 (an 3 ) channel 4 (an 4 ) channel 5 (an 5 ) channel 6 (an 6 ) channel 7 (an 7 ) channel 8 (an 8 ) channel 9 (an 9 ) channel 10 (an 10 ) channel 11 (an 11 ) waiting waiting waiting waiting waiting waiting waiting waiting waiting waiting waiting waiting set adst to 1 * a/d conversion starts clear adf to 0 * clear adf to 0 * adi interrupt request continuous a/d conversion waiting a/d conversion a/d conversion waiting a/d conversion waiting a/d conversion a/d conversion waiting read conversion result * a/d conversion result a/d conversion result a/d conversion result a/d conversion result vertical arrows ( ) indicate instructions executed by software. boxes indicate operations performed by the a/d converter. note: * 467
15.4.3 analog input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter starts sampling the analog inputs at a time t d (synchronization delay) after the adst bit is set to 1 in the a/d control register (adcr). figure 15-7 shows the sampling timing. the a/d conversion time (t conv ) includes t d and the analog input sampling time (t spl ). the length of t d varies because it includes time needed to synchronize the a/d converter. the total conversion time therefore varies within the ranges indicated in table 15-4. in scan mode, the t conv values given in table 15-4 apply to the first conversion. in the second and subsequent conversions there is no t d , and t conv is fixed at 256 states when cks = 0 or 128 states when cks = 1. table 15-4 a/d conversion time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max unit synchronization delay t d 10 17 6 9 states input sampling time t spl ?040 a/d conversion time t conv 259 266 131 134 468
figure 15-7 a/d conversion timing adcr a/d conversion time (t conv ) synchronization delay (t d ) (t spl ) write cycle (3 states) a/d synchroni- zation time (max 14 states) address bus internal write signal analog input sampling signal a/d converter adst write timing adf (adcr) idle sample & hold a/d conversion end of a/d conversion analog input sampling time 469
15.4.4 external triggering of a/d conversion a/d conversion can be started by input of an external trigger signal. external triggering is enabled by setting the trge bit to 1 in the a/d control register. when the trge bit is set to 1, p7 1 automatically becomes the adtrg input pin. if a low pulse is input at the adtrg pin in this state, the a/d converter detects the falling edge of the pulse and sets the adst bit to 1. figure 15-8 shows the external trigger input timing. the adst bit is set to 1 one state after the a/d converter samples the falling edge of the adtrg signal. the time from when the adst bit is set to 1 until a/d conversion begins is the same as when software writes 1 in adst. figure 15-8 external trigger input timing 15.4.5 starting a/d conversion by ipu a/d conversion can be started by a compare match in the on-chip integrated-timer pulse unit (ipu). to start a/d conversion by ipu compare match, follow the procedure given next. 1. set bits doe21 and doe20 (bits 7 and 6) to 1,0 in ipu channel 1 timer output enable register a (toera). 2. set the starting time of the a/d converter in ipu channel 1 dedicated register 2 (dr2). 3. set the trge bit to 1 in the a/d control register. 4. clear the extrg bit in the adtrg register (bit 7 at address h'fedc) to 0. after these settings, a/d conversion will start when the ipu channel 1 timer counter value matches dr2. in this case a/d conversion cannot be started by input at the adtrg pin. when the ipu starts a/d conversion, the timing is the same as if the t1oc 2 pin were externally connected to the adtrg pin. see the relevant timing diagrams for these pins. adst = 1 adtrg input (worst case) adtrg input (best case) adst bit (adcr) 1 state adtrg pin sampling timing setup time 3 t irq1s setup time < t irq1s 470
15.5 interrupts and dtc the a/d converter can request an a/d end interrupt (adi) at the end of conversion. adi is enabled when the adie bit is set to 1 in the a/d control/status register (adcsr), and disabled when adie is cleared to 0. if the adi bit in the interrupt controllers data transfer enable register a (dtea) is set to 1, the adi interrupt is served by the data transfer controller (dtc). when the dtc is started by adi to perform a data transfer, the adf bit in adcsr is automatically cleared to 0. for further details on the dtc, see section 7, ?ata transfer controller. 15.6 usage notes when using the a/d converter, note the following points: (1) analog input voltage range: during a/d conversion, the voltages input to the analog input pins should be in the range av ss ann v ref . (2) relationships of av cc and av ss to v cc and v ss : av cc , av ss , v cc , and v ss should be related as follows: av cc = v cc 10%; av ss = v ss . av cc and av ss must not be left open, even if the a/d converter is not used (include hardware/software stand-by mode). (3) v ref input range: the reference voltage input at the v ref pin should be in the range v ref av cc . failure to observe points (1), (2), and (3) above may degrade chip reliability. (4) note on board design: in board layout, separate the digital circuits from the analog circuits as much as possible. particularly avoid layouts in which the signal lines of digital circuits cross or closely approach the signal lines of analog circuits. induction and other effects may cause the analog circuits to operate incorrectly, or may adversely affect the accuracy of a/d conversion. the analog input signals (an 0 to an 11 ), analog reference voltage (v ref ), and analog supply voltage (av cc ) must be separated from digital circuits by the analog ground (av ss ). the analog ground (av ss ) should be connected to a stable digital ground (v ss ) at one point on the board. (5) note on noise: to prevent damage from surges and other abnormal voltages at the analog input pins (an 0 to an 11 ) and analog reference voltage pin (v ref ), connect a protection circuit like the one in figure 15-9 between av cc and av ss . the bypass capacitors connected to av cc and v ref and the filter capacitors connected to an 0 to an 11 must be connected to av ss . if filter capacitors like those in figure 15-9 are connected, the voltage values input to the analog input pins (an 0 to an 11 ) will be smoothed, which may give rise to error. the circuit constants should therefore be selected carefully. 471
(6) to maintain accurate conversion: connect the v ref and av ss pins to a stable power supply or ground. inside the a/d converter, v ref and av ss become inputs to the circuit that generates the comparison voltages during a/d conversion. external disturbances on the v ref and av ss lines will have an adverse effect on accuracy. figure 15-9 example of analog input protection circuit figure 15-10 analog input pin equivalent circuit table 15-5 analog input pin ratings item min max unit analog input capacitance 20 pf allowable signal-source impedance 10 k w 472 h8/53x 0.1 m f 100 w rin av cc v ref an 0?1 av ss * 2 * 1 * 1 0.01 m f 10 m f notes: 1. 2. rin: input impedance to a/d converter 1.0 k w note: numeric values are approximate, except in table 15-5. an 0?1 20 pf
(7) a/d conversion accuracy definitions: a/d conversion accuracy in the h8/538 and h8/539 is defined as follows: resolution: digital output code length of a/d converter offset error: deviation from ideal a/d conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001, excluding quantization error (figure 15-12) full-scale error: deviation from ideal a/d conversion characteristic of analog input voltage required to raise digital output from 1111111110 to 1111111111, excluding quantization error (figure 15-12) quantization error: intrinsic error of the a/d converter; 0.5 lsb (figure 15-11) nonlinearity error: deviation from ideal a/d conversion characteristic in range from zero volts to full scale, exclusive of offset error, full-scale error, and quantization error. absolute accuracy: deviation of digital value from analog input value, including offset error, full-scale error, quantization error, and nonlinearity error. figure 15-11 a/d converter accuracy definitions (1) 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs 001 000 010 011 100 101 110 111 digital output ideal a/d conversion characteristic quantization error analog input voltage 473
figure 15-12 a/d converter accuracy definitions (2) fs digital output full-scale error ideal a/d conversion characteristic nonlinearity error actual a/d conversion characteristic offset error analog input voltage 474
section 16 bus controller 16.1 overview the on-chip bus controller (bsc) can dynamically alter the bus width and the length of the bus cycle. when a 16-bit bus mode is selected by the inputs at the mode pins, the bus controller can reserve part of the address space as a byte access area accessed via an eight-bit bus, switch another part from a three-state bus cycle to a high-speed two-state bus cycle, and switch the eight-bit-bus area to 16-bit access. 16.1.1 features bus controller features are listed below. an eight-bit access area can be defined in the 16-bit bus modes (modes 1, 3, 4, 5*, and 6*) the eight-bit access area consists of addresses greater than the value set in the byte area top register (arbt). (this area does not include the address set in arbt, which is the boundary of the word area.) when an address greater than the arbt value is accessed, only the upper data bus (d 15 to d 8 ) is valid. the access is performed with eight-bit bus width. the arbt setting does not change the bus width of the on-chip rom, on-chip ram, and on-chip register areas. note: * modes 5 and 6 have a 16-bit bus, but when the chip comes out of reset the arbt and ar3t settings are ignored: the entire external address space is accessed in three states via an eight-bit bus. software can enable the arbt and ar3t settings by altering a value in the bus control register (bcr). two-state access area can be defined the three-state-access area consists of addresses equal to or greater than the value set in the three-state area top register (ar3t). (the address set in ar3t is included as the boundary of the three-state area.) when addresses less than the ar3t value are accessed, the bus cycle consists of two states. wait states cannot be inserted in two-state access. the ar3t setting does not change the bus cycle length of the on-chip rom, on-chip ram, and on-chip register areas. areas can be defined in steps of 256 bytes in minimum mode, or 4 kbytes in maximum mode. 475
16.1.2 block diagram figure 16-1 shows a block diagram of the bus controller. figure 16-1 bus controller block diagram arbt ar3t bcr mode 3, 4, or 5 arbt = addr ar3t = addr bcre arbt < addr arbt < addr ar3t < addr ar3t addr on-chip address bus (a 19 to a 16 ) on-chip address bus (a 15 to a 12 ) on-chip address bus (a 11 to a 8 ) on-chip data bus (d 15 to d 8 ) mode 5 or 6 multiplexer multiplexer upper 4 bits lower 4 bits comparator upper 4 bits comparator comparator comparator rom/ram area eight-bit access request three-state access request legend arbt: byte area top register ar3t: three-state area top register bcr: bus control register bcre: bus controller enable lower 4 bits mode 2 on-chip register area * note: * except 16-bit accessible ipu registers. 476
16.1.3 register configuration table 16-1 summarizes the bus controllers registers. the bus controller has three 8-bit registers: a byte area top register (arbt) that designates the boundary of the word area; a three-state area top register (ar3t) that designates the boundary of the three-state-access address space; and a bus control register (bcr) used to switch the bus width in modes 5 and 6. the h8/500 cpu can always read and write arbt, ar3t, and bcr. table 16-1 bus controller registers 16.2 register descriptions 16.2.1 byte area top register the byte area top register (arbt) specifies the boundary address that separates the area accessed with 16-bit bus width from the area accessed using only the upper eight bits of the 16-bit bus. the address set in arbt is the word area boundary: the last address accessed with 16-bit bus width. the bus controller controls the h8/500 cpu so that external addresses exceeding the arbt value are accessed with eight-bit bus width. in expanded maximum mode, the arbt value is treated as bits a 19 to a 12 (the upper eight bits) of the word area boundary address. the word area boundary can be set in minimum 4-kbyte steps. in expanded maximum mode, addresses h'00000 to h'00fff are always a word access area. in expanded minimum mode, the arbt value is treated as bits a 15 to a 8 (the upper eight bits) of the word area boundary address. the word area boundary can be set in minimum 256-byte steps. in expanded minimum mode, addresses h'0000 to h'00ff are always a word access area. address register name abbreviation r/w initial value h'ff16 byte area top register arbt r/w h'ff h'ff17 three-state area top register ar3t r/w h'ee (h'0e) * 1 h'fedf bus control register bcr r/w h'bf (h'3f) * 2 notes: 1. h'0e in modes 3, 4, and 5. 2. h'3f in modes 5 and 6. bit initial value r/w 7 1 543210 1111111 r/w r/w r/w r/w r/w r/w r/w r/w 6 477
the arbt setting applies only to external addresses. it cannot change the bus width of the on- chip rom or ram or on-chip register areas. in mode 2 the arbt setting is ignored: the external address bus has a fixed eight-bit width. in modes 5 and 6 the arbt setting is ignored until the bcre bit is set to 1 in the bus control register (bcr). arbt is initialized to h'ff by a reset and in hardware standby mode. arbt is not initialized in software standby mode. 16.2.2 three-state area top register the three-state area top register (ar3t) specifies the boundary address that separates the area accessed in two states from the area accessed in three states. the address set in ar3t is the three-state area boundary: the first address accessed in three states. the bus controller controls the h8/500 cpu so that external addresses equal to or greater than the arbt value are accessed in three states. wait states cannot be inserted into the two-state-access area. in expanded maximum mode, the ar3t value is treated as bits a 19 to a 12 (the upper eight bits) of the three-state area boundary address. the three-state area boundary can be set in minimum 4-kbyte steps. in expanded maximum mode, addresses h'ff000 to h'fffff are always a three- state-access area. in expanded minimum mode, the ar3t value is treated as bits a 15 to a 8 (the upper eight bits) of the three-state area boundary address. the three-state area boundary can be set in minimum 256-byte steps. in expanded minimum mode, addresses h'ff00 to h'ffff are always a three- state-access area. the ar3t setting applies only to external addresses. it cannot change the bus cycle length of the on-chip rom or ram or on-chip register areas. in mode 2 the ar3t setting is ignored: the external address space is always a three-state-access area. in modes 5 and 6 the ar3t setting is ignored until the bcre bit is set to 1 in the bus control register (bcr). ar3t is initialized to h'ee (modes 1, 2, 6, and 7) or h'0e (modes 3 to 5) by a reset and in hardware standby mode. arbt is not initialized in software standby mode. bit initial value r/w 7 1 (0) * 543210 1 (0) * 1 (0) * 01110 r/w r/w r/w r/w r/w r/w r/w r/w 6 note: * modes 3 to 5 478
16.2.3 bus control register the bus control register (bcr) enables or disables the bus controllers bus control functions in modes 5 and 6, and enables or disables on-chip i/o port functions. bit initial value r/w 7 0 (1) * bcre exiop 0p3t 543210 0111111 r/w (r) * r/w r/w r/w r/w r/w r/w 6 p9ae pcre pbce p12e bus controller enable enables and disables bus control functions of the bus controller zero page three-state forces three-state access to all addresses in page 0 ports 9 and a enable enables and disables reading and writing of ports 9 and a expanded i/o ports pull-up transistor control register enable ports 1 and 2 enable enables and disables reading and writing of ports 1 and 2 enables and disables reading and writing of port b and c pull-up transistor control registers allocates h'0fe9c to h'0fe9f as external addresses ports b and c enable enables and disables reading and writing of ports b and c reserved bit note: * in modes 1, 2, 3, 4, and 7. 479
when the bus controller enable bit (bcre) is set to 1, the bus controller controls the bus according to the values in arbt and ar3t. as an exception, when the zero page three-state bit (0p3t; bit 6) is set to 1, all external addresses in page 0 are placed in the three-state-access area regardless of the ar3t setting. bits 4, 2, 1, and 0 enable or disable reading and writing of on-chip i/o ports. if one of these bits is cleared to 0, the corresponding on-chip i/o ports cannot be accessed. the port addresses become part of the external eight-bit three-state-access area instead. bit 3 is for i/o port expansion. when this bit is cleared to 0, h'0fe9c to h'0fe9f become part of the external eight-bit three-state-access area. for precautions on modifying the bcr value, see section 16.4, ?sage notes. (1) bit 7?us controller enable (bcre): enables or disables bus control functions using the values in arbt and ar3t in modes 5 and 6. (2) bit 6?ero page three-state (0p3t): selects three-state access for all external addresses in page 0, regardless of the ar3t setting. (3) bit 5?eserved: read-only bit, always read as 1. reserved for future use. bit 6 0p3t description 0 the h8/500 cpu accesses external addresses according (initial value) to the arbt and ar3t settings 1 the h8/500 cpu accesses external addresses according to the arbt and ar3t settings except in page 0, where three-state access is selected regardless of the ar3t setting * note: * in mode 7 there is no external address space, so the 0p3t value has no meaning. bit 7 bcre description 0 the h8/500 cpu accesses all external addresses in three states using an eight-bit bus * (initial value in modes 5 and 6) this bit cannot be cleared to 0 in modes 1 to 4 and 7. 1 the h8/500 cpu accesses external addresses according to the arbt and ar3t settings (initial value in modes 1 to 4 and 7; cannot be cleared to 0) note: * access is performed using only the upper eight bits (d 15 to d 8 ) of the 16-bit bus. 480
(4) bit 4?ort 9 and a enable (p9ae): enables or disables reading and writing of ports 9 and a, allowing these i/o ports to be reconfigured off-chip. for details see section 16.3.3, ?/o port expansion function. (5) bit 3?xpanded i/o ports (exiop): enables or disables expansion of i/o ports, allowing i/o ports to be configured off-chip. for details see section 16.3.3, ?/o port expansion function. (6) bit 2?ull-up transistor control register enable (pcre): enables or disables reading and writing of port b and c pull-up transistor control registers (pbpcr and pcpcr). for details see section 16.3.3, ?/o port expansion function. bit 4 p9ae description 0 on-chip ports 9 and a cannot be written or read the dr and ddr addresses of ports 9 and a (h'0fe90 to h'0fe93) become part of the external eight-bit three-state-access area. * 1 on-chip ports 9 and a can be written and read (initial value) note: * cannot be cleared to 0 in mode 7. bit 3 exiop description 0 external i/o ports can be written and read h'0fe9c to h'0fe9f become part of the external eight-bit three-state-access area. * 1 external i/o ports cannot be written or read (initial value) note: * cannot be cleared to 0 in mode 7. bit 2 pcre description 0 port b and c pull-up transistor control registers (pbpcr and pcpcr) cannot be written or read pbpcr and pcpcr addresses (h'0fe98 to h'0fe9b) become part of the external eight-bit three-state-access area. * 1 port b and c pull-up transistor control registers (pbpcr (initial value) and pcpcr) can be written and read note: * cannot be cleared to 0 in mode 7. 481
(7) bit 1?ort b and c enable (pbce): enables or disables reading and writing of ports b and c, allowing these i/o ports to be reconfigured off-chip. for details see section 16.3.3, ?/o port expansion function. (8) bit 0?ort 1 and 2 enable (p12e): enables or disables reading and writing of ports 1 and 2, allowing these i/o ports to be reconfigured off-chip. for details see section 16.3.3, ?/o port expansion function. bit 1 pbce description 0 on-chip ports b and c cannot be written or read the dr and ddr addresses of ports b and c (h'0fe94 to h'0fe97) become part of the external eight-bit three-state-access area. * 1 on-chip ports b and c can be written and read (initial value) note: * cannot be cleared to 0 in mode 7. bit 0 p12e description 0 on-chip ports 1 and 2 cannot be written or read the dr and ddr addresses of ports 1 and 2 (h'0fe80 to h'0fe83) become part of the external eight-bit three-state-access area. * 1 on-chip ports 1 and 2 can be written and read (initial value) note: * cannot be cleared to 0 in mode 7. 482
16.3 operation 16.3.1 operation after reset in each mode figures 16-2 to 16-8 illustrate operation in each mode after a reset. (1) mode 1: has a 16-bit bus. h'0000 to h'edff are a 16-bit two-state-access area. h'ee00 to h'fe7f are a 16-bit three-state-access area. when the on-chip ram is enabled, however, the on- chip ram area is a 16-bit two-state-access area. figure 16-2 bus width and bus cycle length after reset (mode 1) h'0000 h'edff h'f67f h'f680 h'ee00 h'fe80 h'fe7f h'ffff 16 bits external bus area 16 bits, 2 states external bus area 16 bits, 3 states on-chip ram area 16 bits, 2 states (16 bits, 3 states) on-chip register area 8 bits, 3 states h'0000 h'edff h'f67f h'f680 h'ee00 h'fe7f h'ffff 16 bits external bus area 16 bits, 2 states on-chip ram area 16 bits, 2 states (16 bits, 3 states) on-chip ram area 16 bits, 2 states (16 bits, 3 states) on-chip register area 8 bits, 3 states (a) h8/538 (b) h8/539 h'ee7f h'ee80 16 bits, 3 states 483
(2) mode 2 h8/538 the bus is eight bits wide. h'0000 to h'ee7f (on-chip rom) are a 16-bit two-state-access area. h'ee80 to h'fe7f are an eight-bit three-state-access area. h8/539 the bus is eight bits wide. h'0000 to h'3fff (on-chip rom) are a 16-bit two-state-access area. h'4000 to h'fe7f are an eight-bit three-state-access area. when the on-chip ram is enabled, however, the on-chip ram area is a 16-bit two-state- access area. figure 16-3 bus width and bus cycle length after reset (mode 2) 484 h'0000 h'ee7f h'f67f h'f680 h'ee80 h'fe80 h'fe7f h'ffff 8 bits on-chip rom area 16 bits, 2 states external bus area 8 bits, 3 states on-chip ram area 16 bits, 2 states (8 bits, 3 states) on-chip register area 8 bits, 3 states h'0000 h'ee7f h'f67f h'f680 h'ee80 h'fe80 h'fe7f h'ffff 8 bits on-chip rom area 16 bits, 2 states on-chip ram area 16 bits, 2 states (8 bits, 3 states) on-chip ram area 16 bits, 2 states (8 bits, 3 states) on-chip register area 8 bits, 3 states (a) h8/538 (b) h8/539 h'3fff h'4000 external bus area 8 bits, 3 states
(3) mode 3: has a 16-bit bus. h'00000 to h'0dfff are a 16-bit two-state-access area. h'0e000 to h'0fe7f and h'10000 to h'fffff are a 16-bit three-state-access area. when the on-chip ram is enabled, however, the on-chip ram area is a 16-bit two-state-access area. figure 16-4 bus width and bus cycle length after reset (mode 3) h'00000 h'0f67f h'0f680 h'0fe80 h'0fe7f h'0ffff h'10000 h'fffff h'0e000 h'0dfff h'fefff 16 bits external bus area 16 bits, 2 states external bus area 16 bits, 3 states on-chip ram area 16 bits, 2 states (16 bits, 3 states) on-chip register area 8 bits, 3 states external bus area 16 bits, 3 states h'00000 h'0f67f h'0f680 h'0fe80 h'0fe7f h'0ffff h'10000 h'fffff h'0ee80 h'0ee7f 16 bits external bus area 16 bits, 2 states external bus area 16 bits, 3 states on-chip ram area 16 bits, 2 states (16 bits, 3 states) on-chip register area 8 bits, 3 states external bus area 16 bits, 3 states on-chip ram area 16 bits, 2 states (16 bits, 3 states) h'0e000 h'0dfff (a) h8/538 (b) h8/539 485
(4) mode 4 h8/538 the bus is 16 bits wide. h'00000 to h'0ee7f (on-chip rom) are a 16-bit two-state-access area. h'0ee80 to h'0fe7f and h'10000 to h'fffff are a 16-bit three-state-access area. h8/539 the bus is 16 bits wide. h'00000 to h'03fff and h'10000 to h'2ffff (on-chip rom) are 16- bit two-state-access areas. h'04000 to h'0dfff is a 16-bit two-state access area. h'0e000 to h'0fe7f and h'30000 to h'fffff are a 16-bit three-state-access area. when the on-chip ram is enabled, however, the on-chip ram area is a 16-bit two-state- access area. figure 16-5 bus width and bus cycle length after reset (mode 4) 486 h'0ee7f h'0ee80 h'00000 h'0f67f h'0f680 h'0fe80 h'0fe7f h'0ffff h'10000 h'fffff h'fefff 16 bits on-chip rom area 16 bits, 2 states external bus area 16 bits, 3 states on-chip ram area 16 bits, 2 states (16 bits, 3 states) on-chip register area 8 bits, 3 states external bus area 16 bits, 3 states h'0ee7f h'0ee80 h'00000 h'0f67f h'0f680 h'0fe7f h'0ffff h'10000 h'fffff h'2ffff h'30000 16 bits on-chip rom area 16 bits, 2 states external bus area 16 bits, 3 states on-chip ram area 16 bits, 2 states (16 bits, 3 states) on-chip register area 8 bits, 3 states on-chip rom area 16 bits, 2 states on-chip ram area 16 bits, 2 states (16 bits, 3 states) external bus area 16 bits, 2 states external bus area 16 bits, 3 states h'03fff h'04000 h'0dfff h'0e000 (a) h8/538 (b) h8/539
(5) mode 5: has a 16-bit bus. h'00000 to h'fffff are an eight-bit three-state-access area because bcre = 0 in the bus control register (bcr). when the on-chip ram is enabled, however, the on-chip ram area is a 16-bit two-state-access area. figure 16-6 bus width and bus cycle length after reset (mode 5) h'00000 h'0f67f h'0f680 h'0fe80 h'0fe7f h'0ffff h'10000 h'fffff 16 bits external bus area 8 bits, 3 states on-chip ram area 16 bits, 2 states (8 bits, 3 states) on-chip register area 8 bits, 3 states external bus area 8 bits, 3 states h'00000 h'0f67f h'0f680 h'0fe80 h'0fe7f h'0ffff h'10000 h'fffff 16 bits external bus area 8 bits, 3 states on-chip ram area 16 bits, 2 states (8 bits, 3 states) on-chip register area 8 bits, 3 states external bus area 8 bits, 3 states (a) h8/538 (b) h8/539 on-chip ram area 16 bits, 2 states (8 bits, 3 states) h'0ee7f h'0ee80 487
(6) mode 6: has a 16-bit bus. h'0000 to h'fe80 are an eight-bit three-state-access area (bcre = 0 in bcr). when the on-chip ram is enabled, however, the on-chip ram area is a 16-bit two- state-access area. figure 16-7 bus width and bus cycle length after reset (mode 6) 488 h'0000 h'f67f h'f680 h'fe80 h'fe7f h'ffff 16 bits external bus area 8 bits, 3 states on-chip ram area 16 bits, 2 states (8 bits, 3 states) on-chip register area 8 bits, 3 states h'0000 h'f67f h'f680 h'fe80 h'fe7f h'ffff 16 bits external bus area 8 bits, 3 states on-chip ram area 16 bits, 2 states (8 bits, 3 states) on-chip register area 8 bits, 3 states (a) h8/538 (b) h8/539 h'ee7f h'ee80 on-chip ram area 16 bits, 2 states (8 bits, 3 states)
(7) mode 7: has no external bus. h8/538 h'0000 to h'ee7f (on-chip rom) are a 16-bit two-state-access area. h8/539 h'00000 to h'03fff and h'10000 to h'2ffff (on-chip rom) are a 16-bit two-state-access area. when the on-chip ram is enabled, the on-chip ram area is also a 16-bit two-state-access area. figure 16-8 bus width and bus cycle length after reset (mode 7) 489 h'0000 h'ee7f h'f67f h'f680 h'ee80 h'fe80 h'fe7f h'ffff on-chip rom area 16 bits, 2 states on-chip ram area 16 bits, 2 states on-chip register area 8 bits, 3 states h'00000 h'0fe7f h'0fe80 h'0ee80 h'10000 h'0ffff h'2ffff on-chip rom area 16 bits, 2 states on-chip ram area 16 bits, 2 states on-chip rom area 16 bits, 2 states on-chip ram area 16 bits, 2 states on-chip register area 8 bits, 3 states h'03fff h'0f67f h'0f680 (a) h8/538 (b) h8/539
16.3.2 timing of changes in bus areas and bus size changes in the bus areas and bus size take effect in the next bus cycle after the write cycle to arbt or ar3t. figure 16-9 timing of changes in bus controller settings (byte write) internal write signal a 19 ? 0 internal data bus bus area arbt, ar3t, or bcr address setting data old setting new setting t 1 t 2 t 3 490
figure 16-10 timing of changes in bus controller settings (word write) t 1 t 2 t 3 t 1 t 2 t 3 internal write signal a 19 ? 0 internal data bus bus area arbt address ar3t address setting data setting data old setting temporary setting new setting only arbt is modified 491
16.3.3 i/o port expansion function bus control register bits 4 to 0 can be set for i/o port expansion. this function enables ports that become unavailable in expanded modes (modes 1 to 6, ports 1, 2, a, b, and c) to be moved off- chip. figure 16-11 shows an example of i/o port reconfiguration. figure 16-11 example of i/o port reconfiguration (1 bit) h8/538 a 19? rd hwr 74ls02 ck d pr clr q d g oe q res +5 v s y a gnd ddr dr d 15? 74ls74 1/2 (ddr) 74ls373 1/8 (dr) 74ls04 1/6 74ls257 1/6 address decoder data bus port oc 492
16.4 usage notes when using the bus controller, note the following points: (1) restrictions on ar3t and arbt settings: ar3t and arbt settings should satisfy equation (1). ar3t arbt + 1 ?1) no eight-bit, two-state-access area is defined for the h8/538 or h8/539. if ar3t > arbt + 1, eight-bit three-state access is performed. (2) possible partitionings of the address space: the address space can be partitioned in eight ways as follows: 1. two areas: 16 bits, two states; 16 bits, three states 2. two areas: 16 bits, two states; eight bits, three states 3. two areas: 16 bits, three states; eight bits, three states 4. three areas: 16 bits, two states; 16 bits, three states; eight bits, three states 5. one area: eight bits, three states *1 6. three areas: 16 bits, three states (page 0) *2 ; 16 bits, two states; 16 bits, three states 7. three areas: 16 bits, three states (page 0) *2 ; 16 bits, two states; 8 bits, three states 8. four areas: 16 bits, three states (page 0) *2 ; 16 bits, two states; 16 bits, three states; eight bits, three states notes: 1. possible only in modes 5 and 6 when bcre = 0 in the bus control register (bcr). 2. set by the 0p3t bit in bcr. 493
(3) modification of arbt, ar3t, and bcr: when arbt, ar3t, and bcr settings are modified, an invalid bus area may be created temporarily. this may prevent normal program execution. crashes can be avoided by one of the following methods: 1. place routines that modify arbt, ar3t, and bcr in on-chip rom or ram. perform the modification in an area that is not affected by the arbt, ar3t, and bcr settings. the modification can be followed by a jump to any area without crashing. (example 1) 2. place a branch instruction after the instruction that modifies arbt, ar3t, or bcr. after the write to arbt, ar3t, or bcr,* the instruction fetch from the temporary invalid bus area is cleared by execution of the branch instruction, thus preventing a crash. (example 2) note: * to modify both arbt and ar3t simultaneously, a word access instruction is recommended. figure 16-12 program structure for modifying arbt, ar3t, and bcr l1: mov r2,@arbt bra l1 . . . l1:mov r2,@arbt rts mov #ee,r2 bsr l1 . . . on-chip rom or ram arbt modification instruction (subroutine) arbt modification subroutine call crash-avoiding branch instruction jump destination is next instruction example 1: placing the modifying subroutine in on-chip rom or ram example 2: placing a branch instruction after the modifying instruction 494
(4) access types and operation of data bus and control signals: table 16-2 indicates how the data bus and control signals operate in various types of access. table 16-2 (1) data bus and control signal operation in various types of access (mode 2) instruction designations data bus control signals bus operand operand access no. width address size direction a 0 d 15 to d 8 d 7 to d 0 rd hwr lwr 1 8 bits byte area byte write 0 output h l h 2 write 1 output h l h 3 read 0 input l h h 4 read 1 input l h h 5 word write 0 output h l h 1 output h l h 6 read 0 input l h h 1 input l h h notes: 1. how to read the table: 1) bus width: external bus width determined by the operating mode. 2) operand address: area containing the operand address specified in the instruction. examples: arbt > operand address: byte area arbt < operand address: word area 3) operand size: size of operand specified in the instruction. examples: mov.b: byte size mov.w: word size 4) access direction: as below. examples: mov.b rn, : write (cpu ? ) mov.b , rn: read ( ? cpu) 2. when a byte area is addressed by an instruction with word operand size, the cpu accesses memory twice, accessing the even byte first, then the odd byte. instructions that specify word-size operands should always specify an even operand address. not used (port) 495
table 16-2 (2) data bus and control signal operation in various types of access (modes 1, 3, and 6) instruction designations data bus control signals bus operand operand access no. width address size direction a 0 d 15 to d 8 d 7 to d 0 rd hwr lwr 1 16 bits byte area byte write 0 output high h l h impedance 2 1 output high h l h impedance 3 read 0 input don? care l h h 4 1 input don? care l h h 5 word write 0 output high h l h impedance 1 output high h l h impedance 6 read 0 input don? care l h h 1 input don? care l h h notes: 1. how to read the table: 1) bus width: external bus width determined by the operating mode. 2) operand address: area containing the operand address specified in the instruction. examples: arbt > operand address: byte area arbt < operand address: word area 3) operand size: size of operand specified in the instruction. examples: mov.b: byte size mov.w: word size 4) access direction: as below. examples: mov.b rn, : write (cpu ? ) mov.b , rn: read ( ? cpu) 2. when a byte area is addressed by an instruction with word operand size, the cpu accesses memory twice, accessing the even byte first, then the odd byte. instructions that specify word-size operands should always specify an even operand address. 496
table 16-2 (3) data bus and control signal operation in various types of access (modes 1, 3, and 6) instruction designations data bus control signals bus operand operand access no. width address size direction a 0 d 15 to d 8 d 7 to d 0 rd hwr lwr 1 16 bits word area byte write 0 output dummy h l h data 2 1 dummy output h h l data 3 read 0 input don? care l h h 4 1 don? care input l h h 5 word write 0 output output h l l 1 6 read 0 input input l h h 1 notes: 1. how to read the table: 1) bus width: external bus width determined by the operating mode. 2) operand address: area containing the operand address specified in the instruction. examples: arbt > operand address: byte area arbt < operand address: word area 3) operand size: size of operand specified in the instruction. examples: mov.b: byte size mov.w: word size 4) access direction: as below. examples: mov.b rn, : write (cpu ? ) mov.b , rn: read ( ? cpu) 2. instructions that specify word-size operands should always specify an even operand address. 497
figures 16-13 and 16-14 show examples of usage of the h8/539 bus controller in mode 4. 1. ar3t arbt + 1 figure 16-13 example of use of bus controller (h8/539: mode 4) mode 4 h'00000 h'0ee7f h'0ee80 h'0fe80 h'0fe7f h'0ffff 16 bits external bus area on-chip ram area on-chip register area h'10000 external bus area h'fffff bus cycle bus width ar3t arbt 2 states 2 states 3 states 2 states 3 states 16 bits 16 bits 8 bits 16 bits h'2ffff h'30000 on-chip rom area 2 states 16 bits 16 bits 498
2. ar3t > arbt + 1 figure 16-14 example of use of bus controller (h8/539: mode 4) mode 4 h'00000 h'0f67f h'0f680 h'0fe80 h'0fe7f h'2ffff 16 bits external bus area on-chip ram area on-chip register area h'30000 external bus area h'fffff bus cycle bus width arbt ar3t 2 states 2 states 3 states 16 bits 16 bits 8 bits 16 bits 8 bits 2 states 3 states 8 bits, 3 states on-chip rom area 16 bits 2 states 499
500
section 17 ram 17.1 overview the h8/538 has 2 kbytes of on-chip static ram. the h8/539 has 4 kbytes. the ram is connected to the h8/500 cpu by a 16-bit data bus. the h8/500 cpu accesses both byte data and word data in two states, making the ram suitable for rapid data transfer and high-speed computation. in the h8/538, the on-chip ram is assigned to addresses h'f680 to h'fe7f. in the h8/539, the on-chip ram is assigned to addresses h'ee80 to h'fe7f. the ram control register (ramcr) enables this area to be switched between on-chip ram and external memory. 17.1.1 block diagram figure 17-1 shows a block diagram of the h8/538s on-chip ram. figure 17-2 shows a block diagram of the h8/539s on-chip ram. figure 17-1 ram block diagram (h8/538) on-chip data bus (upper) on-chip data bus (lower) 8 8 ramcr on-chip ram (2 kbytes) bus interface and control section rame h'f680 h'f681 h'f682 h'f683 h'f684 h'f685 h'fe7c h'fe7d h'fe7e h'fe7f upper byte (even address) lower byte (odd address) legend ramcr: ram control register 501
figure 17-2 ram block diagram (h8/539) 17.1.2 register configuration the ram is controlled by the ram control register (ramcr). table 17-1 gives the address and initial value of ramcr. table 17-1 ram control register address register name abbreviation r/w initial value h'ff15 ram control register ramcr r/w undetermined 502 on-chip data bus (upper 8 bits) on-chip data bus (lower 8 bits) 8 8 ramcr on-chip ram (4 kbytes) bus interface and control section rame1, 2 h'ee80 h'ee81 h'ee82 h'ee83 h'ee84 h'ee85 h'fe7c h'fe7d h'fe7e h'fe7f upper byte (even address) lower byte (odd address) legend ramcr: ram control register 2
17.2 ram control register the ram control register (ramcr) enables or disables access to the on-chip ram. note: * bit 6 is reserved for chip testing and has an undetermined value when written or read. (1) bits 7 and 5?am enable 1 and 2 (rame1, rame2): these bits enable or disable access to on-chip ram. bit 7 rame1 description 0 on-chip ram (h'f680 to h'fe7f) cannot be accessed 1 on-chip ram (h'f680 to h'fe7f) can be accessed (initial value) bit 5 rame2 description 0 on-chip ram (h'ee80 to h'f67f) cannot be accessed 1 on-chip ram (h'ee80 to h'f67f) can be accessed (initial value) the rame1 and rame2 bits are initialized on the rising edge of the reset signal. they are not initialized in software standby mode. in modes 1 to 6, when the rame1 and rame2 bits are cleared to 0 to disable access to on-chip ram, addresses h'f680 to h'fe7f and h'ee80 to h'f67f become an external memory area. bit initial value r/w 7 1 rame1 543210 * 111111 r/w r/w 6 rame2 reserved bit ram enable bit 1 enables and disables access to on-chip ram (h'f680 to h'fe7f) ram enable bit 2 enables or disables access to on-chip ram (h'ee80 to h'f67f) reserved bits 503
(2) bits 6 and 4 to 0?eserved: bit 6 is reserved by the system for chip testing and has an undetermined value when written or read. bits 4 to 0 are read-only bits that always read 1 and cannot be modified. 17.3 operation 17.3.1 expanded modes (modes 1 to 6) h8/538: in the expanded modes (modes 1 to 6), when the rame1 bit is set to 1, accesses to addresses h'f680 to h'fe7f are directed to the on-chip ram. when the rame1 bit is cleared to 0, accesses to addresses h'f680 to h'fe7f are directed to off-chip memory. h8/539: in the expanded modes (modes 1 to 6), when bits rame1 and rame2 are set to 1, accesses to addresses h'f680 to h'fe7f and h'ee80 to h'f67f are directed to the on-chip ram. when bits rame1 and rame2 are cleared to 0, accesses to addresses h'f680 to h'fe7f and h'ee80 to h'f67f are directed to off-chip memory. 17.3.2 single-chip mode (mode 7) h8/538: in single-chip mode (mode 7), when the rame1 bit is set to 1, accesses to addresses h'f680 to h'fe7f are directed to the on-chip ram. when the rame1 bit is cleared to 0, any type of access to addresses h'f680 to h'fe7f (instruction fetch or data read/write) causes an address error. for the exception handling when an address error occurs, see section 4, ?xception handling. h8/539: in single-chip mode (mode 7), when bits rame1 and rame2 are set to 1, accesses to addresses h'f680 to h'fe7f and h'ee80 to h'f67f are directed to the on-chip ram. when bits rame1 and rame2 are cleared to 0, any type of access to addresses h'f680 to h'fe7f and h'ee80 to h'f67f (instruction fetch or data read/write) causes an address error. for the exception handling when an address error occurs, see section 4, ?xception handling. 504
section 18 rom 18.1 overview the h8/538 has 60 kbytes of on-chip rom (prom or masked rom). the h8/539 has 128 kbytes (prom or masked rom). the rom is connected to the h8/500 cpu by a 16-bit data bus. the h8/500 cpu accesses both byte data and word data in two states, making the rom suitable for rapid data transfer and high-speed computation. in the h8/538 the on-chip rom is assigned to addresses h'0000 to h'ee7f. in the h8/539 the on- chip rom is assigned to addresses h'00000 to h'03fff and h'10000 to h'2ffff, but the rom at addresses h'00000 to h'03fff and the rom at addresses h'10000 to h'13fff are physically the same rom. the mode pins enable the rom area to be switched between on-chip rom and external memory. table 18-1 summarizes the mode pin settings and usage of the rom area. table 18-1 mode pin settings and rom area mode pin setting mode md 2 md 1 md 0 rom area usage mode 0 0 0 0 illegal setting mode 1 0 0 1 external memory area mode 2 0 1 0 on-chip rom area mode 3 0 1 1 external memory area mode 4 1 0 0 on-chip rom area mode 5 1 0 1 external memory area mode 6 1 1 0 external memory area mode 7 1 1 1 on-chip rom area 505
18.1.1 block diagram figure 18-1 shows a block diagram of the h8/538s on-chip rom. figure 18-2 shows a block diagram of the h8/539s on-chip rom. figure 18-1 rom block diagram (h8/538) on-chip data bus (upper) 8 8 on-chip rom (60 kbytes) h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'ee7c h'ee7d h'ee7e h'ee7f on-chip data bus (lower) bus interface and control section operating mode upper byte (even address) lower byte (odd address) 506
figure 18-2 rom block diagram (h8/539) 507 on-chip data bus (upper) 8 8 on-chip rom (128 kbytes) h'10000 h'10001 h'10002 h'10003 h'10004 h'10005 h'2fffc h'2fffd h'2fffe h'2ffff on-chip data bus (lower) bus interface and control section operating mode upper byte (even address) lower byte (odd address) note: the memory area from address h'10000 to h'13fff can also be read at addresses h'00000 to h'03fff. addresses h'00000 to h'03fff are a second mapping of addresses h'10000 to h'13fff.
18.2 prom mode 18.2.1 prom mode setting in prom mode, the versions with on-chip prom (hd6475388 and hd6475398) suspend their microcontroller functions. the on-chip prom can then be programmed using a general-purpose prom programmer. table 18-2 indicates how to select prom mode. table 18-2 selecting prom mode pins setting mode pins: md 2 , md 1 , md 0 low stby and res pins pa 0 and pa 1 high 18.2.2 socket adapter and memory map programs can be written and verified by attaching a special 112-pin/32-pin adapter to the prom programmer. table 18-3 gives ordering information for the socket adapter. figure 18-3 shows a memory map of the h8/538 in prom mode. figure 18-4 shows a memory map of the h8/539 in prom mode. figure 18-5 shows the pin assignments of the 112-pin/32-pin socket adapter. table 18-3 socket adapter microcontroller package socket adapter hd6475388f 112-pin plastic qfp (fp-112) hs5398esh1h hd6475398f 508
figure 18-3 memory map in prom mode (h8/538) figure 18-4 memory map in prom mode (h8/539) 509 h8/538 mcu mode prom mode h'0000 h'0000 h'ee7f h'ee7f on-chip rom area h'00000 h'03fff h'10000 h'13fff h'1ffff h'20000 h'2ffff h'00000 h'03fff h'0ffff h'10000 h'1ffff mcu mode prom mode h8/539 note: in mcu mode, addresses h'00000 to h'03fff are a second mapping of addresses h'10000 to h'13fff. when read, both of these address areas return the same data.
figure 18-5 wiring of 112-pin/32-pin socket adapter legend v pp : program voltage (12.5 v) eo 7 to eo 0 : data input/output ea 16 to ea 0 : address input oe: output enable ce: chip enable pgm: program h8/538/539 (112 pins) pin no. pin name 112-pin/32-pin socket adapter hn27c101 (32 pins) pin no. pin name 19 72 100 66 101 36 37 38 39 40 41 42 43 45 46 47 48 49 50 51 52 54 55 56 57 58 59 60 61 62 63 81?3 84, 85 1, 44, 76 98 10, 26, 35, 53, 73, 99 other than above reso nmi p7 0 pa 4 p7 1 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 pc 0 pc 1 pc 2 pc 3 pc 4 pc 5 pc 6 pc 7 pb 0 pb 1 pb 2 pb 3 pb 4 pb 5 pb 6 pb 7 pa 0 pa 1 md 0 , md 1 , md 2 av cc , v ref v cc av ss nc (open) v ss v pp ea 9 ea 16 ea 15 pgm eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 oe ea 10 ea 11 ea 12 ea 13 ea 14 ce v cc v ss 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 70, 71 res, stby 510
18.3 programming the programming and verifying specifications in prom mode are the same as the specifications of the standard hn27c101 eprom. page programming is not supported, however. the prom programmer must not be set to page mode. table 18-4 indicates how to select the write, verify, and program-inhibit modes in prom mode. table 18-4 mode selection in prom mode pins mode ce oe pgm v pp v cc o 7 to o 0 a 16 to a 0 program l h l v pp v cc data input address input verify l l h data output program-inhibit l l l high-impedance lhh hl l hhh legend l: low voltage level h: high voltage level v pp :v pp voltage level v cc :v cc voltage level 511
18.3.1 programming and verification unused areas of the on-chip prom contain h'ff data (initial value). an efficient, high-speed programming procedure can be used to program and verify prom data. this programming/verification procedure programs the chip quickly without subjecting it to voltage stress and without sacrificing data reliability. figure 18-6 shows the basic high-speed programming flowchart. tables 18-5 and 18-6 list the electrical characteristics of the chip during programming. figure 18-7 shows a timing diagram. figure 18-6 high-speed programming flowchart yes no s = 25 no yes yes no yes start set programming/ verification mode v cc = 6.0 v ?.25 v, v pp = 12.5 v ?.3 v address = 0 program with t pw = 0.2 ms ?% n = 0 n + 1 ? n verification ok? program with t opw = 0.2 n ms last address? set read mode v cc = 5.0 v, v pp = v cc address + 1 ? address all addresses ok? end fail n < s? no 512
table 18-5 dc characteristics in prom mode (preliminary) table 18-6 ac characteristics in prom mode (when v cc = 6.0 v ?.25 v, v pp = 12.5 v 0.3 v, t a = 25? ??) item symbol min typ max unit test conditions address setup time t as 2 s figure 18-7 * oe setup time t oes 2s data setup time t ds 2s address hold time t ah 0s data hold time t dh 2s output disable delay time t df 130 ? v pp setup time t vps 2s pgm pulse width for initial t pw 0.19 0.20 0.21 ms programming pgm pulse width for overwrite t opw 0.19 5.25 ms programming v cc setup time t vcs 2s ce setup time t ces 2s oe output delay time t oe 0 150 ns note: * input pulse level: 0.8 v to 2.2 v input rise time and fall time 20 ns timing reference levels: 1.0 v and 2.0 v for input; 0.8 v and 2.0 v for output (when v cc = 6.0 v ?.25 v, v pp = 12.5 v ?.3 v, v ss = 0 v, t a = 25? ??) item symbol min typ max unit test conditions input high o 7 to o 0 , a 16 to a 0 ,v ih 2.4 v cc + 0.3 v voltage oe, ce, pgm input low o 7 to o 0 , a 16 to a 0 ,v il ?.3 0.8 v voltage oe, ce, pgm output high o 7 to o 0 v oh 2.4 v i oh = ?00 ? voltage output low o 7 to o 0 v ol 0.45 v i ol = 1.6ma voltage input leakage o 7 to o 0 , a 16 to a 0 , | i li | 2 av in = 5.25 v/0.5 v current oe, ce, pgm v cc current i cc 40 ma v pp current i pp 40 ma 513
figure 18-7 prom write/verify timing 18.3.2 programming precautions (1) program with the specified voltages and timing. the programming voltage (v pp ) in prom mode is 12.5 v. if the prom programmer is set to hitachi hn27c101 specifications, v pp will be 12.5 v. applied voltages in excess of the specified values can permanently destroy the chip. be particularly careful about the prom programmers overshoot characteristics. (2) before programming, check that the chip is correctly mounted in the prom programmer. overcurrent damage to the chip can result if the index marks on the prom programmer, socket adapter, and chip are not correctly aligned. (3) don? touch the socket adapter or chip while programming. touching either of these can cause contact faults and write errors. address data v pp v cc ce pgm oe t as t ds write data t vps t vcs v pp v cc v cc v cc +1 t ces t pw t dh t oes t oe t ah t df program verify read data 514
(4) the chip cannot be programmed in page programming mode. select byte programming mode. (5) with the h8/538, specify h'ff data for addresses h'ee80 to h'1ffff. the h8/538 prom size is 60 kbytes. addresses h'ee80 to h'1ffff always read h'ff, so if h'ff is not specified as program data, a verify error will occur. 18.4 reliability of programmed data an effective way to assure the data holding characteristics of the programmed chips is to bake them at 150?c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 18-8 shows the recommended screening procedure. figure 18-8 recommended screening procedure (example) if a series of programming errors occurs while the same prom programmer is in use, stop programming and check the prom programmer and socket adapter for defects. please inform hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking. program chip and verify programmed data bake chip for 48 hours at 150? with power off read and check program v cc = 5.0 v 515
516
section 19 power-down state 19.1 overview the h8/538 and h8/539 have a power-down state that greatly reduces power consumption by halting cpu functions. the power-down state includes three modes: sleep mode, software standby mode, and hardware standby mode. table 19-1 indicates the methods of entering and exiting the power-down modes. table 19-1 power-down mode transition conditions state cpu peripheral i/o clock cpu registers functions ram ports run halt held run held held halt halt held halt and held held initialized halt halt not held halt held high impedance mode sleep mode software standby mode hardware standby mode entering procedure execute sleep instruction set ssby bit in sbycr to 1, then execute sleep instruction low input at stby pin exiting methods ? interrupt ? res ? stby ? nmi ? res ? stby ? stby & res legend sbycr: software standby control register ssby: software standby bit 517
19.2 sleep mode this section describes sleep mode. 19.2.1 transition to sleep mode execution of the sleep instruction causes a transition from the program execution state to sleep mode. immediately after executing the sleep instruction the h8/500 cpu halts, but the contents of its internal registers remain unchanged. the on-chip peripheral modules do not halt in sleep mode. 19.2.2 exit from sleep mode the chip exits sleep mode when it receives an interrupt request, or a low input at the res or stby pin. (1) exit by interrupt: an interrupt terminates sleep mode and starts the interrupt-handling routine or data transfer controller (dtc). the chip does not exit sleep mode if the interrupt priority level is equal to or less than the level set in the h8/500 cpus status register (sr), or if the interrupt is disabled in an on-chip peripheral module. (2) exit by res input: when the res signal goes low, the chip exits from sleep mode to the reset state. (3) exit by stby input: when the stby signal goes low, the chip exits from sleep mode to hardware standby mode. 518
19.3 software standby mode this section describes software standby mode. 19.3.1 transition to software standby mode if software sets the standby bit (ssby) to 1 in the software standby control register (sbycr), then executes the sleep instruction, the chip enters software standby mode. table 19-2 gives register information about sbycr. in software standby mode current dissipation is reduced to an extremely low level because the cpu and on-chip peripheral modules all halt. the on-chip peripheral modules are reset. as long as the specified voltage is supplied, however, cpu register contents, on-chip ram data, and i/o port states are held. table 19-2 standby control register 19.3.2 software standby control register the software standby control register (sbycr) is an eight-bit register that must be set in order to enter software standby mode. the bit structure is described next. address name abbreviation r/w initial value h'ff1a software standby control register sbycr r/w h'7f bit initial value r/w 7 0 ssby 543210 1111111 r/w 6 reserved bits software standby bit enables transition to software standby mode 519
(1) bit 7?oftware standby (ssby): enables transition to software standby mode. the ssby bit cannot be set to 1 while the timer enable bit (tme) is set to 1 in the timer control/status register (tcsr) of the watchdog timer (wdt). before entering software standby mode, software must clear the tme bit to 0. the ssby bit is automatically cleared to 0 when the chip recovers from software standby mode by nmi or reset, or enters hardware standby mode. (2) bits 6 to 0?eserved: read-only bits, always read as 1. 19.3.3 exit from software standby mode the chip can be brought out of software standby mode by input at the nmi, res , or stby pin. (1) recovery by nmi: to recover from software standby mode by nmi input, software must set clock select bits 2 to 0 (cks2 to cks0) in the watchdog timers timer control/status register (tcsr) beforehand to select the oscillator setting time, and must also select the desired nmi input edge. when an nmi interrupt request signal is input, the clock oscillator begins operating. at first clock pulses are supplied only to the watchdog timer. the watchdog timer receives the supplied clock and starts counting. after the oscillator settling time selected by bits cks2 to cks0 in the control/status register (tcsr), the watchdog timer overflows. after the watchdog timer overflows, the clock is supplied to the entire chip, software standby mode ends, and the nmi exception-handling sequence begins. (2) recovery by res input: when software standby mode is exited by res input, clock pulses are supplied to the entire chip as soon as the clock oscillator starts. the clock oscillator starts when the res signal goes low. after the oscillator settling time, when the res signal goes high, the cpu begins executing the reset sequence. the res signal must be held low long enough for the clock to stabilize. (3) recovery by stby input: when the stby signal goes low, the chip exits from software standby mode to hardware standby mode. bit 7 ssby description 0 sleep instruction causes transition to sleep mode. (initial value) 1 sleep instruction causes transition to software standby mode 520
19.3.4 sample application of software standby mode figure 19-1 illustrates nmi timing for software standby mode. ? with the nonmaskable interrupt edge bit (nmieg) in the nmi control register (nmicr) cleared to 0 (falling edge), nmi goes low. - the nmieg bit is set to 1. ? software sets the ssby bit to 1, then executes the sleep instruction. the chip enters software standby mode. when the nmi signal goes high, the chip exits software standby mode. figure 19-1 nmi timing for software standby mode (example) 19.3.5 note the i/o ports are not initialized in software standby mode. if a port is in the high output state, it remains in that state and power reduction is lessened by the amount of current output. 1 2 3 4 clock oscillator nmi nmieg bit ssby bit oscillator settling time nmi interrupt handler nmieg ? 1 ssby ? 1 sleep instruction software standby mode (power-down state) oscillator settling time (t osc2 ) set in wdt nmi interrupt handler wdt count starts wdt count overflows clock oscillator starts 521
19.4 hardware standby mode this section describes hardware standby mode. 19.4.1 transition to hardware standby mode regardless of its current state, the chip enters hardware standby mode whenever the stby pin goes low. hardware standby mode reduces power consumption drastically by halting the cpu and stopping all functions of the on-chip peripheral modules. the on-chip peripheral modules are reset, but as long as the specified voltage is supplied, on-chip ram contents are held. to hold ram contents, the rame bit in the ram control register (ramcr) should be cleared to 0. i/o ports are placed in the high-impedance state. 19.4.2 recovery from hardware standby mode recovery from the hardware standby mode requires inputs on both the stby and res lines. when stby goes high, the clock oscillator begins running. res should be low at this time. after the oscillator settling time, when the res signal goes high, the h8/500 cpu begins executing the reset sequence. the h8/500 cpu then returns to the program execution state, ending hardware standby mode. 19.4.3 timing for hardware standby mode figure 19-2 shows the timing relationships in hardware standby mode. figure 19-2 hardware standby mode timing clock oscillator res stby hardware standby mode (power-down state) oscillator settling time (t osc1 ) 522
section 20 electrical characteristics 20.1 absolute maximum ratings (h8/538) table 20-1 lists the absolute maximum ratings. table 20-1 absolute maximum ratings item symbol value unit power supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +13.5 v input voltage (except ports 8 and 9) v in ?.3 to v cc + 0.3 v input voltage (ports 8 and 9) v in ?.3 to av cc + 0.3 v reference voltage v ref ?.3 to av cc + 0.3 v analog power supply voltage av cc ?.3 to +7.0 v analog input voltage v an ?.3 to av cc + 0.3 v operating temperature t opr regular specifications: ?0 to +75 ? wide-range specifications: ?0 to +85 storage temperature t stg ?5 to +125 ? caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. 523
20.2 electrical characteristics (h8/538) 20.2.1 dc characteristics table 20-2 lists the dc characteristics. table 20-3 lists the permissible output currents. table 20-2 dc characteristics conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 5.0 v 10%, v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) test item symbol min typ max unit conditions input high res , stby , v ih v cc ?0.7 v cc + 0.3 v voltage md 2 ?d 0 extal v cc 0.7 v cc + 0.3 v ports 8 and 9 2.2 av cc + 0.3 v other input pins 2.2 v cc + 0.3 v (except ports 4 and 5) input low res , stby , v il ?.3 0.4 v voltage md 2 ?d 0 other input pins ?.3 0.8 v (except ports 4 and 5) schmitt ports 4 and 5 vt 1.0 2.5 v trigger input vt + 2.0 3.5 v voltages vt + ?vt 0.4 v input leakage reso | i in | 10.0 ? vin = 0.5 to current res , stby , nmi, 1.0 ? v cc ?0.5 v md 0 ?d 2 ports 8 and 9 1.0 ? vin = 0.5 to av cc ?0.5 v leakage ports 1 to 7 | i sti | 1.0 ? vin = 0.5 to current in and a to c av cc ?0.5 v 3-state (off-state) input pull-up ports b and c i p 50 200 ? vin = 0 v transistor current 524
table 20-2 dc characteristics (cont) conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 5.0 v 10%, v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) test item symbol min typ max unit conditions output high all output pins v oh v cc ?0.5 v i oh = voltage ?00 ? 3.5 v i oh = ? ma output low all output pins v ol 0.4 v i ol = 1.6 ma voltage (except reso ) ports 3, 5, b, 1.0 v i ol = 8 ma and c 1.2 v i ol = 10 ma reso 0.4 v i ol = 2.6 ma input reso cin 60 pf vin = 0 v capacitance nmi 30 pf f = 1 mhz all input pins 20 pf t a = 25? except res and nmi current normal i cc 35 60 ma f = 6 mhz dissipation operation 50 80 ma f = 8 mhz 65 100 ma f = 10 mhz sleep mode 16 30 ma f = 6 mhz 20 35 ma f = 8 mhz 24 40 ma f = 10 mhz standby mode 0.01 5.0 ? t a 50? 20.0 ? 50? < t a analog during a/d ai cc 1.2 2.0 ma power supply conversion current idle 0.01 5.0 ? reference during a/d ai cc 0.2 0.5 ma v ref = 5.0 v current conversion idle 0.01 5.0 ? ram standby voltage v ram 2.0 v notes on next page. 525
notes: 1. never leave the av cc , av ss , and v ref pins open. if the a/d converter is not used, connect av cc and v ref to v cc and connect av ss to v ss . 2. current dissipation values are for v ihmin = v cc ?0.5 v and v ilmax = 0.5 v with all output pins unloaded and the on-chip pull-up transistors in the off state. table 20-3 permissible output currents conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 5.0 v 10%, (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) item symbol min typ max unit permissible output low ports 3 and 5 i ol 10 ma current (per pin) reso 3.0 ma other output pins 2.0 ma permissible output low total of 13 pins in ports i ol 40 ma current (total) 3 and 5 total of all output pins, 80 ma including the above permissible output high all output pins i oh 2.0 ma current (per pin) permissible output high total of all output pins i oh 25 ma current (total) notes: 1. to protect chip reliability, do not exceed the output current values in table 20-3. 2. when driving a darlington pair or led, always insert a current-limiting resistor in the output line, as shown in figures 20-1 and 20-2. 526
figure 20-1 darlington pair drive circuit (example) figure 20-2 led drive circuit (example) 527 2 k w port 3 or 5 darlington pair h8/538 600 w led v cc port 3 or 5 h8/538
20.2.2 ac characteristics the ac characteristics of the h8/538 are described below. bus timing parameters are listed in table 20-4. control signal timing parameters are listed in table 20-5. timing parameters of the on- chip peripheral modules are listed in table 20-6. table 20-4 bus timing conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 5.0 v 10%, v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) 6 mhz 8 mhz 10 mhz test item symbol min max min max min max unit conditions clock cycle time t cyc 166.7 2000 125 2000 100 2000 ns fig. 20-7, clock low pulse width t cl 65 45 35 ns fig. 20-8 clock high pulse width t ch 65 45 35 ns clock rise time t cr ?51515ns clock fall time t cf ?51515ns address delay time t ad ?03525ns address hold time t ah 30 25 20 ns address strobe delay time 1 t asd1 ?04035ns address strobe delay time 2 t asd2 ?04040ns read strobe delay time 1 t rdd1 ?04035ns read strobe delay time 2 t rdd2 ?04040ns write strobe delay time 1 t wrd1 ?04040ns write strobe delay time 2 t wrd2 ?04040ns write strobe delay time 3 t wrd3 ?04040ns write data strobe pulse width 1 t wrw1 150 110 90 ns write data strobe pulse width 2 t wrw2 200 150 120 ns address setup time 1 t as1 25 20 20 ns address setup time 2 t as2 25 20 20 ns address setup time 3 t as3 105 80 65 ns read data setup time t rds 40 30 20 ns read data hold time t rdh 000ns read data access time 1 t acc1 160 125 100 ns read data access time 2 t acc2 300 230 200 ns write data delay time t wdd ?56565ns write data setup time t wds 30 15 10 ns write data hold time t wdh 30 25 20 ns 528
table 20-4 bus timing (cont) conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 5.0 v 10%, v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) 6 mhz 8 mhz 10 mhz test item symbol min max min max min max unit conditions wait setup time t wts 40 40 35 ns fig. 20-9 wait hold time t wth 10 10 10 ns bus request setup time t brqs 40 40 40 ns fig. 20-13 bus acknowledge delay time 1 t bacd1 ?06050ns bus acknowledge delay time 2 t bacd2 ?06050ns bus-floating delay time t bzd ? bacd1 ? bacd1 ? bacd1 ns table 20-5 control signal timing conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 5.0 v 10%, v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) 6 mhz 8 mhz 10 mhz test item symbol min max min max min max unit conditions res setup time t ress 200 200 200 ns fig. 20-10 res pulse width t resw 6.0 6.0 6.0 t cyc mode programming setup time t mds 4.0 4.0 4.0 t cyc reso output delay time t resd 200 200 200 ns fig. 20-11 reso output pulse width t resow 132 132 132 t cyc nmi setup time t nmis 150 150 150 ns fig. 20-12 nmi hold time t nmih 10 10 10 ns irq 0 setup time t irq0s 50 50 50 ns irq 1? setup time t irq1s 50 50 50 ns irq 1? hold time t irq1h 10 10 10 ns nmi pulse width (for recovery t nmiw 200 200 200 ns fig. 20-14 from software standby mode) clock oscillator settling time at t osc1 20 20 20 ms reset (crystal) clock oscillator settling time in t osc2 10 10 10 ms fig. 19-1 software standby (crystal) 529
table 20-6 timing of on-chip supporting modules conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ref = 5.0 v 10%, v ss = av ss = 0 v, t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) 6 mhz 8 mhz 10 mhz test module item symbol min max min max min max unit conditions ipu timer output delay t tocd 100 100 100 ns fig. 20-17 time timer input setup t tics 50 50 50 ns time timer clock input t tcks 50 50 50 ns fig. 20-18 setup time timer clock pulse t tckw 1.5 1.5 1.5 t cyc width sci input clock asyn- t scyc 444t cyc fig. 20-19 cycle chronous clocked 6 6 6 t cyc syn- chronous input clock pulse t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t scyc width transmit data delay t txd 100 100 100 ns fig. 20-20 time receive data setup t rxs 100 100 100 ns time (clocked synchronous) receive data hold t rxh 100 100 100 ns time (clocked synchronous) ports output data delay t pwd 50 50 50 ns fig. 20-15 time input data setup t prs 50 50 50 ns time input data hold t prh 50 50 50 ns time 530
figure 20-3 output load circuit 531 r l 5 v r h c h8/538 output pin c = 90 pf: p1, p2, pa, pb, pc, ? as, rd, hwr, lwr p3, p4, p5, p6, p7 c = 30 pf: r l = 2.4 k w r h = 12 k w input/output timing measurement levels ? low: 0.8 v ? high: 2.0 v
20.2.3 a/d conversion characteristics table 20-7 lists the a/d conversion characteristics of the h8/538. table 20-7 a/d converter characteristics conditions: v cc = av cc = 5.0 v ?0%, v ss = av ss = 0 v, v ref = 5.0 v ?0% (v ref av cc ), t a = ?0 to +75? (regular specifications), t a = ?0 to +85? (wide-range specifications) 6 mhz 8 mhz 10 mhz item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion time 22.23 16.75 13.4 ? analog input 20 20 20 pf capacitance permissible 10 10 10 k w signal-source impedance nonlinearity error ?.0 ?.0 ?.0 lsb offset error ?.0 ?.0 ?.0 lsb full-scale error ?.0 ?.0 ?.0 lsb quantization error ?/2 ?/2 ?/2 lsb absolute accuracy ?.5 ?.5 ?.5 lsb 532
?preliminary 20.3 absolute maximum ratings (h8/539) table 20-8 lists the absolute maximum ratings. table 20-8 absolute maximum ratings item symbol value unit power supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +13.0 v input voltage (except ports 8 and 9) v in ?.3 to v cc + 0.3 v input voltage (ports 8 and 9) v in ?.3 to av cc + 0.3 v reference voltage v ref ?.3 to av cc + 0.3 v analog power supply voltage av cc ?.3 to +7.0 v analog input voltage v an ?.3 to av cc + 0.3 v operating temperature t opr regular specifications: ?0 to +75 ? wide-range specifications: ?0 to +85 storage temperature t stg ?5 to +125 ? caution: permanent damage to the chip may result if absolute maximum ratings are exceeded. 533
?preliminary 20.4 electrical characteristics (h8/539) 20.4.1 dc characteristics tables 20-9 to 20-11 list the dc characteristics. table 20-12 lists the permissible output currents. table 20-9 dc characteristics [low-voltage specifications (2.7-v version)] conditions: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) test item symbol min typ max unit conditions input high res , stby , v ih v cc 0.9 v cc + 0.3 v voltage md 2 ?d 0 extal v cc 0.7 v cc + 0.3 v ports 8 and 9 2.2 av cc + 0.3 v other input pins 2.2 v cc + 0.3 v (except ports 4 and 5) input low res , stby , v il ?.3 v cc 0.1 v voltage md 2 ?d 0 other input pins ?.3 0.8 v v cc 3 4.0 v (except ports 4 and 5) ?.3 v cc 0.2 v v cc < 4.0 v schmitt ports 4 and 5 vt v cc 0.2 v cc 0.5 v trigger input vt + v cc 0.4 v cc 0.7 v voltages vt + ?vt v cc 0.07 v input leakage reso | i in | 10.0 ? vin = 0.5 to current res , stby , nmi, 1.0 ? v cc ?0.5 v md 0 ?d 2 ports 8 and 9 1.0 ? vin = 0.5 to av cc ?0.5 v leakage ports 1 to 7 | i sti | 1.0 ? vin = 0.5 to current in and a to c av cc ?0.5 v 3-state (off-state) 534
?preliminary table 20-9 dc characteristics [low-voltage specifications (2.7-v version)] (cont) conditions: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) test item symbol min typ max unit conditions input pull-up ports b and c i p 15 300 ? vin = 0 v transistor current output high all output pins v oh v cc ?0.4 v i oh = voltage ?00 ? v cc ?1.0 v i oh = ? ma output low all output pins v ol 0.4 v i ol = 1.2 ma voltage (except reso ) ports 3 and 5 1.0 v i ol = 5 ma reso 0.4 v i ol = 1.6 ma input reso cin 60 pf vin = 0 v capacitance nmi 50 pf f = 1 mhz all input pins 20 pf t a = 25? except reso , nmi current normal i cc * 1 50 80 ma f = 8 mhz, dissipation operation v cc = 5.5 v 27 44 ma f = 8 mhz, v cc = 3.0 v sleep mode 20 35 ma f = 8 mhz, v cc = 5.5 v 11 19 ma f = 8 mhz, v cc = 3.0 v standby mode 0.01 5.0 ? t a 50? 20.0 ? 50? < t a analog during a/d ai cc 1.2 2.0 ma av cc = 5.0 v power supply conversion 0.7 1.2 ma av cc = 3.0 v current idle 0.01 5.0 ? 535
?preliminary table 20-9 dc characteristics [low-voltage specifications (2.7-v version)] (cont) conditions: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) test item symbol min typ max unit conditions reference during a/d ai cc 0.2 0.5 ma v ref = 5.0 v current conversion 0.1 0.3 ma v ref = 3.0 v idle 0.01 5.0 ? ram standby voltage v ram 2.0 v notes: 1. never leave the av cc , av ss , and v ref pins open. if the a/d converter is not used, connect av cc and v ref to v cc and connect av ss to v ss . 2. current dissipation values are for v ihmin = v cc ?0.5 v and v ilmax = 0.5 v with all output pins unloaded and the on-chip pull-up transistors in the off state. 536
?preliminary table 20-10 dc characteristics [low-voltage specifications (3.0-v version)] conditions: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) test item symbol min typ max unit conditions input high res , stby , v ih v cc 0.9 v cc + 0.3 v voltage md 2 ?d 0 extal v cc 0.7 v cc + 0.3 v ports 8 and 9 2.2 av cc + 0.3 v other input pins 2.2 v cc + 0.3 v (except ports 4 and 5) input low res , stby , v il ?.3 v cc 0.1 v voltage md 2 ?d 0 other input pins ?.3 0.8 v v cc 3 4.0 v (except ports 4 and 5) ?.3 v cc 0.2 v 4 v < v cc < 5.5 v schmitt ports 4 and 5 vt v cc 0.2 v cc 0.5 v v cc < 4.0 v trigger input vt + v cc 0.4 v cc 0.7 v voltages vt + ?vt v cc 0.07 v input leakage reso | i in | 10.0 ? vin = 0.5 to current res , stby , nmi, 1.0 ? v cc ?0.5 v md 0 ?d 2 ports 8 and 9 1.0 ? vin = 0.5 to av cc ?0.5 v leakage ports 1 to 7 | i sti | 1.0 ? vin = 0.5 to current in and a to c av cc ?0.5 v 3-state (off-state) 537
?preliminary table 20-10 dc characteristics [low-voltage specifications (3.0-v version)] (cont) conditions: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) test item symbol min typ max unit conditions input pull-up ports b and c i p 15 300 ? vin = 0 v transistor current output high all output pins v oh v cc ?0.5 v i oh = voltage ?00 ? v cc ?1.0 v i oh = ? ma output low all output pins v ol 0.4 v i ol = 1.6 ma voltage (except reso ) ports 3 and 5 1.0 v i ol = 5 ma reso 0.4 v i ol = 1.2 ma input reso cin 60 pf vin = 0 v capacitance nmi 50 pf f = 1 mhz all input pins 20 pf t a = 25? except reso , nmi current normal i cc * 1 65 100 ma f = 10 mhz, dissipation operation v cc = 5.5 v 36 55 ma f = 10 mhz, v cc = 3.0 v sleep mode 24 40 ma f = 10 mhz, v cc = 5.5 v 13 22 ma f = 10 mhz, v cc = 3.0 v standby mode 0.01 5.0 ? t a 50? 20.0 ? 50? < t a analog during a/d ai cc 1.2 2.0 ma av cc = 5.0 v power supply conversion 0.7 1.2 ma av cc = 3.0 v current idle 0.01 5.0 ? 538
?preliminary table 20-10 dc characteristics [low-voltage specifications (3.0-v version)] (cont) conditions: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) test item symbol min typ max unit conditions reference during a/d ai cc 0.2 0.5 ma v ref = 5.0 v current conversion 0.1 0.3 ma v ref = 3.0 v idle 0.01 5.0 ? ram standby voltage v ram 2.0 v notes: 1. never leave the av cc , av ss , and v ref pins open. if the a/d converter is not used, connect av cc and v ref to v cc and connect av ss to v ss . 2. current dissipation values are for v ihmin = v cc ?0.5 v and v ilmax = 0.5 v with all output pins unloaded and the on-chip pull-up transistors in the off state. 539
?preliminary table 20-11 dc characteristics [5-v version] conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, (v ref av cc) , v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) test item symbol min typ max unit conditions input high res , stby , v ih v cc ?0.7 v cc + 0.3 v voltage md 2 ?d 0 extal v cc 0.7 v cc + 0.3 v ports 8 and 9 2.2 av cc + 0.3 v other input pins 2.2 v cc + 0.3 v (except ports 4 and 5) input low res , stby , v il ?.3 0.4 v voltage md 2 ?d 0 other input pins ?.3 0.8 v (except ports 4 and 5) schmitt ports 4 and 5 vt 1.0 2.5 v trigger input vt + 2.0 3.5 v voltages vt + ?vt 0.4 v input leakage reso | i in | 10.0 ? vin = 0.5 to current res , stby , nmi, 1.0 ? v cc ?0.5 v md 0 ?d 2 ports 8 and 9 1.0 ? vin = 0.5 to av cc ?0.5 v leakage ports 1 to 7 | i sti | 1.0 ? vin = 0.5 to current in and a to c av cc ?0.5 v 3-state (off-state) input pull-up ports b and c i p 50 300 ? vin = 0 v transistor current output high all output pins v oh v cc ?0.5 v i oh = voltage ?00 ? 3.5 v i oh = ? ma 540
?preliminary table 20-11 dc characteristics [5-v version] (cont) conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) test item symbol min typ max unit conditions output low all output pins v ol 0.4 v i ol = 1.6 ma voltage (except reso ) ports 3, 5, b, 1.0 v i ol = 8 ma and c 1.2 v i ol = 10 ma reso 0.4 v i ol = 2.6 ma input reso cin 60 pf vin = 0 v capacitance nmi 50 pf f = 1 mhz all input pins 20 pf t a = 25? except reso , nmi current normal i cc 100 158 ma f = 16 mhz dissipation operation sleep mode 60 88 ma f = 16 mhz standby mode 0.01 5.0 ? t a 50? 20.0 ? 50? < t a analog during a/d ai cc 1.2 2.0 ma power supply conversion current idle 0.01 5.0 ? reference during a/d ai cc 0.2 0.5 ma v ref = 5.0 v current conversion idle 0.01 5.0 ? ram standby voltage v ram 2.0 v notes: 1. never leave the av cc , av ss , and v ref pins open. if the a/d converter is not used, connect av cc and v ref to v cc and connect av ss to v ss . 2. current dissipation values are for v ihmin = v cc ?0.5 v and v ilmax = 0.5 v with all output pins unloaded and the on-chip pull-up transistors in the off state. 541
?preliminary table 20-12 permissible output currents condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition c: v cc = 5.0 v ?0%, av cc = 5.0 v ?0%, v ref = 5.0 v ?0% (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) item symbol min typ max unit permissible output low ports 3 and 5 i ol 10 ma current (per pin) reso 3.0 ma other output pins 2.0 ma permissible output low total of 13 pins in ports i ol 40 ma current (total) 3 and 5 total of all output pins, 80 ma including the above permissible output high all output pins i oh 2.0 ma current (per pin) permissible output high total of all output pins i oh 25 ma current (total) notes: 1. to protect chip reliability, do not exceed the output current values in table 20-12. 2. when driving a darlington pair or led, always insert a current-limiting resistor in the output line, as shown in figures 20-4 and 20-5. 542
?preliminary figure 20-4 darlington pair drive circuit (example) figure 20-5 led drive circuit (example) due to high-speed design, the h8/538 ztat fabrication process differs from the fabrication process of the h8/538 masked-rom version, h8/539 ztat version, and h8/539 masked-rom version. this may cause differences in some specification values, operating margins, and noise margins, requiring attention to board design when the h8/538 ztat version is replaced by the h8/538 masked-rom version, h8/539 ztat version, or h8/539 masked-rom version. 600 w led v cc port 3 or 5 543 2 k w port 3 or 5 darlington pair
?preliminary 20.4.2 ac characteristics the ac characteristics of the h8/539 are described below. bus timing parameters are listed in table 20-13. control signal timing parameters are listed in table 20-14. timing parameters of the on-chip supporting modules are listed in table 20-15. table 20-13 bus timing condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition c: v cc = 5.0 v ?0%, av cc = 5.0 v ?0%, v ref = 5.0 v ?0%, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test item symbol min max min max min max unit conditions clock cycle time t cyc 125 500 100 500 62.5 500 ns fig. 20-7, clock low pulse width t cl 30 25 20 ns fig. 20-8 clock high pulse width t ch 30 25 20 ns clock rise time t cr ?52015ns clock fall time t cf ?52015ns address delay time t ad ?04025 * ns address hold time t ah 20 15 10 ns address strobe delay time 1 t asd1 ?03525ns address strobe delay time 2 t asd2 ?04025ns read strobe delay time 1 t rdd1 ?03525ns read strobe delay time 2 t rdd2 ?04025ns write strobe delay time 1 t wrd1 ?04025ns write strobe delay time 2 t wrd2 ?04025ns write strobe delay time 3 t wrd3 ?04025ns write data strobe pulse width 1 t wrw1 110 90 50 ns write data strobe pulse width 2 t wrw2 150 120 70 ns address setup time 1 t as1 20 20 10 ns note: * except when recovering from the bus-released state. 544
?preliminary table 20-13 bus timing (cont) condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition c: v cc = 5.0 v ?0%, av cc = 5.0 v ?0%, v ref = 5.0 v ?0%, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test item symbol min max min max min max unit conditions address setup time 2 t as2 20 20 10 ns fig. 20-7, address setup time 3 t as3 80 65 30 ns fig. 20-8 read data setup time t rds 30 20 15 ns read data hold time t rdh 000ns read data access time 1 t acc1 110 80 60 ns read data access time 2 t acc2 220 190 120 ns write data delay time t wdd ?56555ns write data setup time t wds 15 10 5 ns write data hold time t wdh 25 20 10 ns wait setup time t wts 40 35 25 ns fig. 20-9 wait hold time t wth 10 10 10 ns bus request setup time t brqs 40 40 30 ns fig. 20-13 bus acknowledge delay time 1 t bacd1 ?05030ns bus acknowledge delay time 2 t bacd2 ?05030ns bus-floating delay time t bzd ? bacd1 ? bacd1 ? bacd1 ns 545
?preliminary table 20-14 control signal timing condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition c: v cc = 5.0 v ?0%, av cc = 5.0 v ?0%, v ref = 5.0 v ?0%, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test item symbol min max min max min max unit conditions res setup time t ress 200 200 200 ns fig. 20-10 res pulse width t resw 6.0 6.0 6.0 t cyc mode programming setup time t mds 4.0 4.0 4.0 t cyc reso output delay time t resd 200 200 200 ns fig. 20-11 reso output pulse width t resow 132 132 132 t cyc nmi setup time t nmis 150 150 150 ns fig. 20-12 nmi hold time t nmih 10 10 10 ns irq 0 setup time t irq0s 50 50 30 ns irq 1? setup time t irq1s 50 50 30 ns irq 1? hold time t irq1h 10 10 10 ns nmi pulse width (for recovery t nmiw 200 200 200 ns fig. 20-14 from software standby mode) clock oscillator settling time at t osc1 20 20 20 ms reset (crystal) clock oscillator settling time in t osc2 10 10 10 ms fig. 19-1 software standby (crystal) 546
?preliminary table 20-15 timing of on-chip supporting modules condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition c: v cc = 5.0 v ?0%, av cc = 5.0 v ?0%, v ref = 5.0 v ?0%, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test module item symbol min max min max min max unit conditions ipu timer output delay t tocd 100 100 100 ns fig. 20-17 time timer input setup t tics 50 50 30 ns time timer clock input t tcks 50 50 30 ns fig. 20-18 setup time timer clock pulse t tckw 1.5 1.5 1.5 t cyc width sci input clock asyn- t scyc 444t cyc fig. 20-19 cycle chronous clocked 6 6 6 t cyc syn- chronous input clock pulse t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t scyc width transmit data delay t txd 100 100 100 ns fig. 20-20 time receive data setup t rxs 100 100 100 ns time (clocked synchronous) receive data hold t rxh 100 100 100 ns time (clocked synchronous) 547
?preliminary table 20-15 timing of on-chip supporting modules (cont) condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition c: v cc = 5.0 v ?0%, av cc = 5.0 v ?0%, v ref = 5.0 v ?0%, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition a condition b condition c 8 mhz 10 mhz 16 mhz test item symbol min max min max min max unit conditions ports output data t pwd ?050?0nsv cc 3 4.5 v fig. 20-15 delay time 100 100 100 v cc < 4.5 v input data t prs 50 50 30 ns setup time input data t prh 50 50 30 ns hold time pwm timer output t pwdd 100 100 100 ns fig. 20-16 delay time 548
?preliminary figure 20-6 output load circuit 549 r l 5 v r h c h8/539 output pin c = 90 pf: p1, p2, pa, pb, pc, ? as, rd, hwr, lwr p3, p4, p5, p6, p7 c = 30 pf: r l = 2.4 k w r h = 12 k w input/output timing measurement levels ? low: 0.8 v ? high: 2.0 v
?preliminary 20.4.3 a/d conversion characteristics table 20-16 lists the a/d conversion characteristics of the h8/539. table 20-17 lists the permissible signal-source impedance for the a/d converter. table 20-16 a/d converter characteristics condition a: v cc = 2.7 to 5.5 v, av cc = 2.7 to 5.5 v, v ref = 2.7 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition b: v cc = 3.0 to 5.5 v, av cc = 3.0 to 5.5 v, v ref = 3.0 to 5.5 v (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) condition c: v cc = 5.0 v ?0%, av cc = 5.0 v ?0%, v ref = 5.0 v ?0% (v ref av cc ), v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition a * 1 condition b * 2 condition c 8 mhz 10 mhz 16 mhz item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion time 16.75 13.4 8.38 ? analog input 20 20 20 pf capacitance nonlinearity error ?.5 ?.5 ?.0 lsb offset error ?.5 ?.5 ?.0 lsb full-scale error ?.5 ?.5 ?.0 lsb quantization error ?/2 ?/2 ?/2 lsb absolute accuracy ?.0 ?.0 ?.5 lsb notes: maximum operating frequency of a/d converter: 1. av cc = 2.7 to 3.0 v, 8 mhz (conversion time: 16.75 ?) 2. av cc = 3.0 to 4.5 v, 10 mhz (conversion time: 13.4 ?) table 20-17 a/d converter characteristics: allowable signal-source impedance item conditions min typ max unit allowable 8.38 ? conversion time < 13.4 ? 5 k signal-source 2.7 v av cc < 4.5 v impedance other conditions 10 550
20.5 operational timing this section shows timing diagrams of h8/538 and h8/539 operations. 20.5.1 bus timing this section gives the following bus timing diagrams: 1. basic bus cycle: two-state access figure 20-7 shows the timing of the external two-state access cycle. 2. basic bus cycle: three-state access figure 20-8 shows the timing of the external three-state access cycle. 3. basic bus cycle: three-state access with one wait state figure 20-9 shows the timing of the external three-state access cycle with one wait state inserted. 551
figure 20-7 basic bus cycle: two-state access t 1 t 2 t cyc t ch t cl t cf t cr t ad t as1 t asd1 t as1 t rdd1 t ah t ah t rdd2 t rdh t rds t acc1 t as2 t ah t wdh t wdd t wrw1 t wrd2 t wrd1 t asd2 a 19 ? 0 d 15 ? 0 (read) d 15 ? 0 (write) as rd (read) hwr, lwr (write) 552
figure 20-8 basic bus cycle: three-state access t 1 t 2 t acc2 t as3 t wds t wrw2 t 3 t wrd3 a 19 ? 0 as rd (read) d 15 ? 0 (read) hwr, lwr (write) d 15 ? 0 (write) 553
figure 20-9 basic bus cycle: three-state access with one wait state t 1 t 2 t w t 3 tt wth t wth wts t wts a 19 ? 0 as rd (read) d 15 ? 0 (read) hwr, lwr (write) d 15 ? 0 (write) wait 554
20.5.2 control signal timing this section gives the following control signal timing diagrams: 1. reset input timing figure 20-10 shows the reset input timing. 2. reset output timing figure 20-11 shows the reset output timing. 3. interrupt input timing figure 20-12 shows the input timing for nmi, irq 0 , and irq 1 to irq 3 . 4. bus-release mode timing figure 20-13 shows the bus-release mode timing. figure 20-10 reset input timing figure 20-11 reset output timing res md 2 ?d 0 t resw t t t mds ress ress reso t resow t resd t resd 555
figure 20-12 interrupt input timing figure 20-13 bus-release mode timing t nmis t nmih t irq1s t irq1h t irq0s nmi irq 1 ?rq 3 irq 0 t bacd1 t bacd2 t brqs t brqs t bzd t bzd breq back a 19 ? 0 , as, rd, hwr, lwr 556
20.5.3 clock timing this section gives the following clock timing diagram: 1. oscillator settling timing figure 20-14 shows the oscillator settling timing. figure 20-14 oscillator settling timing t osc1 t osc1 v cc stby res 557
20.5.4 i/o port timing this section gives the following h8/539 i/o port input/output timing diagram: 1. i/o port input/output timing figure 20-15 shows the i/o port input/output timing. figure 20-15 i/o port input/output timing 20.5.5 pwm timer timing this section gives the following h8/539 pwm timer output timing diagram: 1. pwm timer output timing figure 20-16 shows the pwm timer output timing. figure 20-16 pwm timer output timing t prh t prs t pwd t 1 t 2 t 3 ports 1 to c (read) ports 1 to 7 and a to c (write) t pwdd tcnt pw1 to pw3 compare match 558
20.5.6 ipu timing this section gives the following ipu timing diagrams: 1. ipu input/output timing figure 20-17 shows the ipu input/output timing. 2. ipu external clock input timing figure 20-18 shows the ipu external clock input timing. figure 20-17 ipu input/output timing figure 20-18 ipu clock input timing t tocd t tics output compare * 1 input capture * 2 t1oc 1 to t5oc 2 and t1ioc 1 to t7ioc 2 t1ioc 1 to t7ioc 2 notes: 1. 2. t tcks tclk 1 ?clk 3 t tckw t tckw 559
20.5.7 sci input/output timing this section gives the following sci timing diagrams: 1. sci input clock timing figure 20-19 shows the sci input clock timing. 2. sci input/output timing (clocked synchronous mode) figure 20-20 shows the sci input/output timing in clocked synchronous mode. figure 20-19 sck input clock timing figure 20-20 sci input/output timing t sckw sck 1 , sck 2 t scyc sck 3 1 * note: h8/539 only t txd t rxs t rxh sck 1 , sck 2 txd 1 , txd , 2 txd rxd 1 , rxd , 2 rxd t scyc sck 3 , * (transmit data) 3 (receive data) 3 * note: h8/539 only * 560
appendix a instruction set a.1 instruction list operand notation rd general register (destination) rs general register (source) rn general register (ead) destination operand (eas) source operand ccr condition code register n n (negative) bit in ccr z z (zero) bit in ccr v v (overflow) bit in ccr c c (carry) bit in ccr cr control register pc program counter cp code page register sp stack pointer fp frame pointer #imm immediate data disp displacement + add subtract multiply divide logical and logical or ? exclusive logical or ? move ? exchange logical not 561
condition code notation changed according to execution result 0 cleared to 0 previous value remains unchanged varies depending on conditions 562
(short format) mnemonic operation size ccr bits b/w n zvc mov:g (eas) rd rs (ead) #imm (ead) b/w 0 #imm rd @(d:8,fp) rd rs @(d:8,fp) mov:e #imm rd (short format) mov:i mov: f (@aa:8) rd mov:l (short format) rs (@aa:8) mov:s (short format) @sp+ rn (register list) ldm (short format) rn (register list) @?p rs rd rd (upper byte) rd (lower byte) not available in h8/538 and h8/539 not available in h8/538 and h8/539 rd+ (eas) rd (ead) +#imm (ead) (#imm = ?, ?) rd+ (eas) rd (rd is always word size) stm xch swap (movtpe) (movfpe) add:g add:q adds addx dadd sub subs subx dsub mulxu rd+ (eas) +c rd (rd) 10 + (rs) 10 +c (rd) 10 rd?(eas) rd rd?(eas) rd rd?(eas) ?c rd (rd) 10 ?(rs) 10 ? (rd) 10 rd (eas) rd (unsigned) rd ?(eas) rd (unsigned) rd ?(eas), set ccr flags (ead) ?#imm, set ccr flags divxu cmp:g data transfer instructions arithmetic instructions 8 8 16 16 16 ?8 32 ?6 (short format) 0 b/w 0 w0 b/w 0 b/w 0 w w 0 w b b/w b/w b/w b/w b b/w b/w b/w b b/w 0 0 b/w 0 b/w b 563
mnemonic operation size ccr bits b/w n zvc cmp:e cmp:i exts extu tst neg clr tas rd ?#imm, set ccr flags (short format) rd ?#imm, set ccr flags (short format) ( of ) ( of ) 0 ( of ) (ead) ?0, set ccr flags 0?(ead) (ead) 0 (ead) b arithmetic instructions (ead) ?0, set ccr flags (1) 2 ( of ) c0 msb lsb 0 msb lsb c0 msb lsb 0c msb lsb c msb lsb c msb lsb msb lsb c msb lsb c b/w b/w 0 b/w 0 b/w 0 b/w 0 b/w 0 b/w 0 b/w 0 shal shar shll shlr rotl rotr rotxl rotxr shift instructions 0 w b 0 0 b 0 0 0 b/w 0 0 b/w 0 b/w 1 00 0 b 0 0 564
mnemonic operation size ccr bits b/w n zvc and or xor not rd (eas) rd rd (eas) rd rd (eas) rd ?ead) (ead) b/w 0 bcc if condition is true then pc + disp pc else next; bset bclr btst bnot ? of ) z 1 ( of ) ? of ) z 0 ( of ) ? of ) z ? of ) z ( of ) logic instructions bit manipulation instructions b/w 0 b/w 0 b/w 0 b/w b/w b/w branch instructions mnemonic bra (bt) brn (bf) bhi bls bcc (bhs) bcs (blo) bne beq bvc bvs bpl bmi bge blt bgt ble description always (true) never (false) high low or same carry clear (high or same) carry set (low) not equal equal overflow clear overflow set plus minus greater or equal less than greater than less or equal condition true false c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 z (n v) = 1 b/w 565
mnemonic operation size ccr bits b/w n zvc jmp pjmp bsr mnemonic operation size ccr bits b/w n zvc jsr pjsr rts prts rtd prtd scb scb/f scb/ne scb/eq if condition is true then next; else rn ?1 rn; if rn = ? then next else pc + disp pc; effective address pc effective address cp, pc pc @ ?sp pc + disp pc pc @ ?sp effective address pc pc @ ?sp cp @ ?sp effective address cp, pc @sp + pc @sp + cp @sp + pc @sp + pc sp + #imm sp @sp + cp @sp + pc sp + #imm sp mnemonic scb/f scb/ne scb/eq description not equal equal condition false z = 0 z = 1 branch instructions 566
mnemonic operation size ccr bits b/w n zvc trapa mnemonic operation size ccr bits b/w n zvc pc @?p (if max. mode then cp @?p) sr @?p (if max. mode then cp) pc trap/vs if v bit = 1 then trap else next; rte @sp + sr (if max. mode @sp + cp) @sp + pc link fp (r6) @ ?sp sp fp (r6) sp + #imm sp unlk fp (r6) sp @sp + fp sleep ldc stc andc orc xorc nop normal operating mode power-down state (eas) cr cr (ead) cr #imm cr cr #imm cr cr #imm cr pc + 1 pc system control instructions note: * depends on the control register. b/w * b/w * b/w * b/w * b/w * 567
a.2 machine-language instruction codes tables a-1 (a) to (d) indicate the machine-language code for each instruction. how to read tables a-1 (a) to (d): the general format consists of an effective address (ea) field followed by an operation code (op) field. bytes 2, 3, 5, and 6 are not present in all instructions. in special-format instructions the operation code field precedes the effective address field. 123456 effective adress field operation code field mov:g.b ,rd mov:g.w ,rd mov:g.b rs, mov:g.w rs, mov:g.b #xx:8, mov:g.w #xx:16, ldm.w @sp+, instruction data transfer addres- sing mode effective address (ea) field rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 2 3 1010szrrr 1101szrrr 1110szrrr 1111szrrr 1011szrrr 1100szrrr 0000sz101 0001sz101 00000100 00001100 disp disph address address (high) data data (high) displ address (low) data (low) operation code (op) field 456 10000rdrdrd 10000rdrdrd 10010rsrsrs 10010rsrsrs 00000110 00000111 00000010 data data (high) register list data (low) 2 2 2 2 2 2 3 4 3 3 3 3 4 5 4 4 4 4 5 6 2 2 2 2 3 4 2 2 2 2 3 4 2 3 3 3 3 4 5 4 4 4 4 5 6 effective address (ea) field operation code (op) field byte length of instruction shading indicates addressing modes that cannot be specified in the instruction. 3 4 568
the following notation is used in the tables: sz: operand size designation (byte or word) sz = 0: byte size sz = 1: word size rrr: general register number ccc: control register number rrr 000 001 010 011 100 101 110 111 15 8 7 015 0 r0 r1 r2 r3 r4 r5 r6 r7 not used not used not used not used not used not used not used not used r0 r1 r2 r3 r4 r5 r6 r7 sz = 0 (byte) sz = 1 (word) 15 0 ccc 000 15 8 7 0 not used ccr not used not used not used br ep dp not used tp 001 111 110 101 100 011 010 sr sz = 0 (byte) sz = 1 (word) (disallowed * ) (disallowed * ) (disallowed * ) (disallowed * ) (disallowed * ) (disallowed * ) (disallowed * ) (disallowed * ) (disallowed * ) (disallowed * ) note: * do not use combinations marked as disallowed, since they may cause incorrect operation. 569
d: direction of transfer d = 0: load d = 1: store register list: a byte in which bits indicate general registers as follows. #vec: four bits specifying a vector number from 0 to 15. these vector numbers designate vector addresses as follows: bit 7 r7 r3 r6 543210 6 r5 r4 r2 r1 r0 vector address #vec minimum mode maximum mode 0 h'0020?'0021 h'0040?'0043 1 h'0022?'0023 h'0044?'0047 2 h'0024?'0025 h'0048?'004b 3 h'0026?'0027 h'004c?'004f 4 h'0028?'0029 h'0050?'0053 5 h'002a?'002b h'0054?'0057 6 h'002c?'002d h'0058?'005b 7 h'002e?'002f h'005c?'005f 8 h'0030?'0031 h'0060?'0063 9 h'0032?'0033 h'0064?'0067 a h'0034?'0035 h'0068?'006b b h'0036?'0037 h'006c?'006f c h'0038?'0039 h'0070?'0073 d h'003a?'003b h'0074?'0077 e h'003c?'003d h'0078?'007b f h'003e?'003f h'007c?'007f 570
examples of machine-language instruction codes example 1: add:g.b @r0, r1 example 2: add:g.w @h'11:8, r1 ea field op field remarks table a-1 1101szrrr 00100r d r d r d add:g.b @rs, rd instruction code instruction code 11010000 00100001 sz = 0 (byte) rs = r0, rd = r1 h'd021 ea field op field remarks table a-1 0000sz101 00010001 00100r d r d r d add:g.w @aa:8, rd instruction code instruction code 00001101 00010001 00100001 sz = 1 (word) aa = h'11, rd = r1 h'0d1121 571
table a-1 (a) machine-language instruction codes [general format] (1) 572 mov:g.b ,rd mov:g.w ,rd mov:g.b rs, mov:g.w rs, mov:g.b #xx:8, mov:g.w #xx:8, mov:g.w #xx:16, ldm.w @sp+, stm.w , @?p xch.w rs,rd swap.b rd (movtpe.b rs,) * 1 (movfpe.b ,rd) * 1 add:g.b ,rd add:g.w ,rd add:q.b #1, * 2 add:q.w #1, * 2 add:q.b #2, * 2 add:q.w #2, * 2 add:q.b #?, * 2 add:q.w #?, * 2 add:q.b #?, * 2 add:q.w #?, * 2 adds.b ,rd adds.w ,rd addx.b ,rd addx.w ,rd instruction data transfer arithmetic operations addres- sing mode effective address (ea) field rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 2 3 1010szrrr 1101szrrr 1110szrrr 1111szrrr 1011szrrr 1100szrrr 0000sz101 0001sz101 00000100 00001100 disp disph address address (high) data data (high) displ address (low) data (low) operation code (op) field 456 10000r d r d r d 10000r d r d r d 10010r s r s r s 10010r s r s r s 00000110 00000110 00000111 00000010 00010010 10010r d r d r d 00010000 00000000 00000000 00100r d r d r d 00100r d r d r d 00001000 00001000 00001001 00001001 00001100 00001100 00001101 00001101 00101r d r d r d 00101r d r d r d 10100r d r d r d 10100r d r d r d data data data (high) register list register list 10010r s r s r s 10000r d r d r d data (low) not available in the h8/538 and h8/539. short format. notes: 1. 2. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 4 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 4 4 5 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 5 5 6 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 2 2 3 3 4 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 4 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 4 4 5 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 5 5 6 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 4 4 4 4
table a-1 (a) machine-language instruction codes [general format] (cont) (2) 573 dadd.b rs,rd sub.b ,rd sub.w ,rd subs.b ,rd subs.w ,rd subx.b ,rd subx.w ,rd dsub.b rs,rd mulxu.b ,rd mulxu.w ,rd divxu.b ,rd divxu.w ,rd cmp:g.b ,rd cmp:g.w ,rd cmp:g,b #xx, cmp:g.w #xx, exts.b rd extu.b rd tst.b tst.w neg.b neg.w clr.b clr.w tas.b instruction arithmetic operations addres- sing mode effective address (ea) field rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 2 3 1010szrrr 1101szrrr 1110szrrr 1111szrrr 1011szrrr 1100szrrr 0000sz101 0001sz101 00000100 00001100 disp disph address address (high) data data (high) displ address (low) data (low) operation code (op) field 456 00000000 00110r d r d r d 00110r d r d r d 00111r d r d r d 00111r d r d r d 10110r d r d r d 10110r d r d r d 00000000 10101r d r d r d 10101r d r d r d 10111r d r d r d 10111r d r d r d 01110r d r d r d 01110r d r d r d 00000100 00000101 00010001 00010010 00010110 00010110 00010100 00010100 00010011 00010011 00010111 10100r d r d r d 10110rdrdrd data data (high) data (low) 3 2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 4 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 4 5 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 5 6 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 4 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 4 5 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 5 6 4 4 4 4 4 4 4 3 3 3 3 3 3 4 4 4 4 4 4
table a-1 (a) machine-language instruction codes [general format] (3) 574 shal.b shal.w shar.b shar.w shll.b shll.w shlr.b shlr.w rotl.b rotl.w rotr.b rotr.w rotxl.b rotxl.w rotxr.b rotxr.w and.b ,rd and.w ,rd or.b ,rd or.w ,rd xor.b ,rd xor.w ,rd not.b not.w instruction shift logic operations addres- sing mode effective address (ea) field rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 2 3 1010szrrr 1101szrrr 1110szrrr 1111szrrr 1011szrrr 1100szrrr 0000sz101 0001sz101 00000100 00001100 disp disph address address (high) data data (high) displ address (low) data (low) operation code (op) field 456 00011000 00011000 00011001 00011001 00011010 00011010 00011011 00011011 00011100 00011100 00011101 00011101 00011110 00011110 00011111 00011111 01010r d r d r d 01010r d r d r d 01000r d r d r d 01000r d r d r d 01100r d r d r d 01100r d r d r d 00010101 00010101 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 4 4 4
table a-1 (a) machine-language instruction codes [general format] (4) 575 bset.b #xx, bset.w #xx, bset.b rs, bset.w rs, bclr.b #xx, bclr.w #xx, bclr.b rs, bclr.w rs, btst.b #xx, btst.w #xx, btst.b rs, btst.w rs, bnot.b #xx, bnot.w #xx, bnot.b rs, bnot.w rs, ldc.b ,cr ldc.w ,cr stc.b cr, stc.w cr, andc.b #xx:8, cr andc.w #xx:16, cr orc.b #xx:8, cr orc.w #xx16, cr xorc.b #xx:8, cr xorc.w #xx:16, cr instruction bit operations system control addres- sing mode effective address (ea) field rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 2 3 1010szrrr 1101szrrr 1110szrrr 1111szrrr 1011szrrr 1100szrrr 0000sz101 0001sz101 00000100 00001100 disp disph address address (high) data data (high) displ address (low) data (low) operation code (op) field 456 1100 data 1100 data 01001r s r s r s 01001r s r s r s 1101 data 1101 data 01011r s r s r s 01011r s r s r s 1111 data 1111 data 01111r s r s r s 01111r s r s r s 1110 data 1110 data 01101r s r s r s 01101r s r s r s 10001ccc 10001ccc 10011ccc 10011ccc 01011ccc 01011ccc 01001ccc 01001ccc 01101ccc 01101ccc 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 4 4 4 4
table a-1 (b) machine-language instruction codes [special format: short format] machine-language code instruction 1 2 3 4 mov:e.b #xx8, rd 2 01010r d r d r d data mov:i.w #xx16, rd 3 01011r d r d r d data (high) data (low) mov:l.b @aa:8, rd 2 01100r d r d r d address (low) mov:l.w @aa:8, rd 2 01101r d r d r d address (low) mov:s.b rs, @aa:8 2 01110r s r s r s address (low) mov:s.w rs, @aa:8 2 01111r s r s r s address (low) mov:f.b @(d:8,r6), rd 2 10000r d r d r d disp mov:f.w @(d:8,r6), rd 2 10001r d r d r d disp mov:f.b rs, @(d:8, r6) 2 10010r s r s r s disp mov:f.w rs, @(d:8, r6) 2 10011r s r s r s disp cmp:e #xx8, rd 2 01000r d r d r d data cmp:i #xx16, rd 3 01001r d r d r d data (high) data (low) byte length 576
table a-1 (c) machine-language instruction codes [special format: branch instructions] (1) machine-language code instruction 1 2 3 4 bcc d:8 bra (bt) 2 00100000 disp brn (bf) 00100001 disp bhi 00100010 disp bls 00100011 disp bcc (bhs) 00100100 disp bcs (blo) 00100101 disp bne 00100110 disp beq 00100111 disp bvc 00101000 disp bvs 00101001 disp bpl 00101010 disp bmi 00101011 disp bge 00101100 disp blt 00101101 disp bgt 00101110 disp ble 00101111 disp bcc d:16 bra (bt) 3 00110000 disp h disp l brn (bf) 00110001 disp h disp l bhi 00110010 disp h disp l bls 00110011 disp h disp l bcc (bhs) 00110100 disp h disp l bcs (blo) 00110101 disp h disp l bne 00110110 disp h disp l beq 00110111 disp h disp l bvc 00111000 disp h disp l bvs 00111001 disp h disp l bpl 00111010 disp h disp l bmi 00111011 disp h disp l bge 00111100 disp h disp l byte length 577
table a-1 (c) machine-language instruction codes [special format: branch instructions] (2) machine-language code instruction 1 2 3 4 bcc d:16 blt 3 00111101 disp h disp l bgt 00111110 disp h disp l ble 00111111 disp h disp l jmp @rn 2 00010001 11010rrr jmp @aa:16 3 00010000 address (high) address (low) jmp @(d:8, rn) 3 00010001 11100rrr disp jmp @(d:16, rn) 4 00010001 11110rrr disp h disp l bsr d:8 2 00001110 disp bsr d:16 3 00011110 disp h disp l jsr @rn 2 00010001 11011rrr jsr @aa:16 3 00011000 address (high) address (low) jsr @(d:8, rn) 3 00010001 11101rrr disp jsr @(d:16, rn) 4 00010001 11111rrr disp h disp l rts 1 00011001 rtd #xx:8 2 00010100 data rtd #xx:16 3 00011100 data (high) data (low) scb/cc rn,disp scb/f 3 00000001 10111rrr disp scb/ne 00000110 10111rrr disp scb/eq 00000111 10111rrr disp pjmp @aa:24 4 00010011 page address (high) address (low) pjmp @rn 2 00010001 11000rrr pjsr @aa:24 4 00000011 page address (high) address (low) pjsr @rn 2 00010001 11001rrr prts 2 00010001 00011001 prtd #xx:8 3 00010001 00010100 data prtd #xx:16 4 00010001 00011100 data (high) data (low) byte length 578
table a-1 (d) machine-language instruction codes [special format: system control instructions] instruction machine-language code 12 3 4 trapa #xx 2 00001000 0001 #vec trap/vs 1 00001001 pte 1 00001010 link fp,#xx:8 2 00010111 data link fp,#xx:16 3 00011111 data (high) data (low) unlk fp 1 00001111 sleep 1 00011010 nop 1 00000000 byte length 579
580 a.3 operation code map tables a-2 to a-6 show a map of the machine-language instruction codes. the map includes the effective adress (ea) and operation code (op) fields but not the effective address extension. table a-2 first byte of instruction code hi lo 0123456789abcdef nop scb/f jmp bra d:8 bra d:16 brn brn ldm stm bhi bhi pjsr @aa:24 pjmp @aa:24 bls bls bcc bcc bcs bcs bne bne beq beq bvc bvc #xx:8 #xx:8 @aa:8.b @aa:16.b scb/ne scb/eq #xx:8 link trapa jsr trap/vs rts bvs bvs rte sleep bpl bmi bpl bmi bge bge rtd #xx:16 #xx:16 @aa:8.w @aa:16.w blt blt bgt bgt bsr d:16 d:8 bsr unlk link #xx:16 ble ble r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 mov:i #xx:16,rn mov:e #xx:8,rn mov:l.b @aa:8,rn mov:s.b rn,@aa:8 mov:f.b @(d:8,r6),rn mov:f.b rn@(d:8,r6) rn (byte) @?n @rn+ @rn @(d:8,rn) (byte) (byte) (byte) (byte) (byte) @(d:16,rn) 0 1 2 3 4 5 6 7 8 9 a b c d e f mov:l.w @aa:8,rn mov:s.w rn,@aa:8 mov:f.w @(d:8,r6),rn mov:f.w rn,@(d:8,r6) rn (word) (word) @rn+ @rn @(d:8,rn) @(d:16,rn) (word) (word) (word) (word) cmp:e #xx:8, rn cmp:i #xx:16, rn rtd @?n table a-6 table a-6 * table a-5 table a-4 table a-6 table a-6 table a-4 table a-5 table a-4 table a-4 table a-3 table a-4 table a-4 table a-4 table a-4 table a-4 table a-3 table a-4 table a-4 table a-4 table a-4 table a-4 note: * h'11 is the first byte of the machine-language code of the following instructions: jmp, jsr, pjmp, and pjsr in register indirect addressing mode; jmp and jsr in register indirect addressing mode with displacement; prts and prtd. note: references to tables a-3 to a-6 indicate the table giving the second or a subsequent byte of the machine-language code.
581 table a-3 second byte of axxx instruction codes hi lo 01 234 56 789 a bc d ef 0 1 2 3 4 extu swap tst tas neg not add:q shal shar #2 shll r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 5 6 7 8 9 a b c d e f exts clr add:q #1 shlr rotl rotr rotxl rotxr add:q #? add:q #? add adds sub or and xor cmp mov xch addx subx subs bset (register indirect specification of bit number) bclr (register indirect specification of bit number) bnot (register indirect specification of bit number) btst (register indirect specification of bit number) ldc stc mulxu divxu b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 bset (direct specification of bit number) bclr (direct specification of bit number) bnot (direct specification of bit number) btst (direct specification of bit number) table a-6 * note: * prefix code of the dadd and csub instructions. table a-6 gives the third byte of the instruction code.
582 table a-4 second byte of 05xx, 15xx, 0dxx, 1dxx, bxxx, cxxx, dxxx, exxx, and fxxx instruction codes hi lo 01 234 56 789 a bc d ef 0 1 2 3 4 tst neg not mov shal shar #2 shll r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 5 6 7 8 9 a b c d e f clr add:q #xx:16 shlr rotl rotr rotxl rotxr add:q #? add:q #? add adds sub or and xor cmp mov mov addx subx subs bset (register indirect specification of bit number) bclr (register indirect specification of bit number) bnot (register indirect specification of bit number) btst (register indirect specification of bit number) ldc stc mulxu divxu b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 bset (direct specification of bit number) bclr (direct specification of bit number) bnot (direct specification of bit number) btst (direct specification of bit number) table a-6 * note: * prefix code of the dadd and dsub instructions. table a-6 gives the third byte of the instruction code. (load) (store) cmp #xx:16 mov #xx:8 tas cmp #xx:8 #1 add:q
583 table a-5 second byte of 04xx and 0cxx instruction codes hi lo 01 234 56 789 a bc d ef 0 1 2 3 4 r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 5 6 7 8 9 a b c d e f add adds sub or and xor cmp mov addx subx subs orc andc xorc ldc mulxu divxu
584 table a-6 second or third byte of 11xx, 01xx, 06xx, 07xx, and xx00xx instruction codes hi lo 01 23456789 a bcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f (movfpe) * dadd dsub prtd #xx:8 prts prtd #xx:16 r0 r1 r2 r3 r4 r6 r7 r5 pjsr @rn jsr @rn jsr @ (d:8,rn) jsr @ (d:16,rn) jmp @ (d:16,rn) jmp @ (d:8,rn) jmp @rn pjmp @rn (movtpe) * scb r0 r1 r2 r3 r4 r6 r7 r5 note: * not available in the h8/538 and h8/539.
a.4 number of states required for execution tables a-7 (1) to (6) indicate the number of states required to execute each instruction in each addressing mode. these tables are read as explained below. the values of i, j, and k are used to calculate the number of execution states when the instruction is fetched from an external address or an operand is written or read at an external address. formulas for calculating the number of states are given on the next page. how to read table a-7 585 3 4 instruction addressing mode i j k 1 5 5 7 7 rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 add.b add.w add:q.b add:q.w dadd 1 2 2 4 1 1 1 1 2 1 2 2 2 2 4 2 5 5 7 7 3 6 6 8 8 1 5 5 7 7 1 6 6 8 8 2 5 5 7 7 3 6 6 8 8 2 3 j + k is the number of instruction fetches i is the total number of bytes written or read when the operand is in memory shading in the i column indicates that the instruction cannot have a memory operand. shading in these columns indicates addressing modes that cannot be specified for the instruction.
calculation of number of states required for execution (h8/538 and h8/539): one state is one cycle of the system clock (?. when ?= 10 mhz, one state is 100 ns. instruction fetch operand read/write formula 16-bit-bus, 16-bit-bus, 2-state-access (value in table a-7) + (value in table a-8) 2-state-access area area or general register 16-bit-bus, 3-state-access byte (value in table a-7) + (value in area table a-8) + i word (value in table a-7) + (value in table a-8) + i/2 byte (value in table a-7) + (value in table a-8) + i word (value in table a-7) + (value in table a-8) + 2i 16-bit-bus, 16-bit-bus, 2-state-access (value in table a-7) + (value in table a-8) + 3-state-access area area or general register (j + k)/2 16-bit-bus, 3-state-access byte (value in table a-7) + (value in area table a-8) + i + (j + k)/2 word (value in table a-7) + (value in table a-8) + (i + j + k)/2 byte (value in table a-7) + (value in table a-8) + i + (j + k)/2 word (value in table a-7) + (value in table a-8) + 2i + (j + k)/2 8-bit-bus, 16-bit-bus, 2-state-access (value in table a-7) + 2 + (j + k) 3-state-access area area or general register byte (value in table a-7) + i + 2 (j + k) word (value in table a-7) + i/2 + 2 (j + k) byte (value in table a-7) + i + 2 (j + k) word (value in table a-7) + 2 (i + j + k) notes: 1. when an instruction is fetched from the 16-bit-bus access area, the number of states differs by 1 or 2 depending on whether the instruction is stored at an even or odd address. this point should be noted in software timing routines and other situations in which the precise number of states must be known. 2. if wait states or tp states are inserted in access to the 3-state-access area, add the necessary number of states. 3. when an instruction is fetched from the 16-bit-bus 3-state-access area, fractions in the term (j + k)/2 should be rounded up. 8-bit-bus, 2-state-access area or on-chip supporting module 8-bit-bus, 2-state-access area or on-chip supporting module 586 8-bit-bus, 2-state-access area or on-chip supporting module 16-bit-bus, 3-state-access area
examples of calculation of number of states required for execution example 1: instruction fetched from 16-bit-bus, 2-state-access area example 2: instruction fetched from 16-bit-bus, 2-state-access area example 3: instruction fetched from 8-bit-bus, 3-state-access area formula (value in table operand start a-7) + (value in execution read/write address address code mnemonic table a-8) states even h'0100 d821 add @r0,r1 5 + 1 6 odd h'0101 d821 add @r0,r1 5 + 0 5 16-bit-bus, 2-state- access area or general register assembler notation formula (value in table operand start a-7) + (value in execution read/write address address code mnemonic table a-8) + 2i states even h'fc00 11d8 jsr @r0 9 + 0 + 2 213 odd h'fc01 11d8 jsr @r0 9 + 1 + 2 214 on-chip supporting module or 8-bit-bus, 3-state- access area (word) assembler notation formula operand (value in table execution read/write address code mnemonic a-7) + 2 (j + k) states h'9002 d821 add @r0,r1 5 + 2 (1 + 1) 9 16-bit-bus, 2-state- access area or general register assembler notation 587
example 4: instruction fetched from 16-bit-bus, 2-state-access area formula (value in table a-7) + (value in operand start table a-8) + execution read/write address address code mnemonic (j + k)/2 states even h'0100 d821 add @r0,r1 5 + 1 + (1 + 1)/2 7 odd h'0101 d821 add @r0,r1 5 + 0 + (1 + 1)/2 6 16-bit-bus, 2-state- access area or general register assembler notation 588
table a-7 number of states required for instruction execution (1) 3 4 4 4 4 9 4 instruction addressing mode i j k 1 5 5 7 7 5 5 5 5 5 5 7 7 7 7 7 7 5 5 5 5 5 5 6 7 rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 add:g.b ,rd add:g.w ,rd add:q.b #xx, add:q.w #xx, adds.b ,rd adds.w ,rd addx.b ,rd addx.w ,rd and.b ,rd and.w ,rd andc #xx,cr bclr.b #xx, bclr.w #xx, bnot.b #xx, bnot.w #xx, bset.b #xx, bset.w #xx, btst.b #xx, btst.w #xx, clr.b clr.w cmp:g.b ,rd cmp:g.w ,rd cmp:g.b #xx:8, cmp:g.b #xx:16, 1 2 2 4 1 2 1 2 1 2 2 4 2 4 2 4 1 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 1 2 2 2 2 3 3 2 2 2 2 4 4 4 4 4 4 3 3 2 2 2 2 2 5 5 7 7 5 5 5 5 5 5 7 7 7 7 7 7 5 5 5 5 5 5 6 7 3 6 6 8 8 6 6 6 6 6 6 8 8 8 8 8 8 6 6 6 6 6 6 7 8 1 5 5 7 7 5 5 5 5 5 5 7 7 7 7 7 7 5 5 5 5 5 5 6 7 1 6 6 8 8 6 6 6 6 6 6 8 8 8 8 8 8 6 6 6 6 6 6 7 8 2 5 5 7 7 5 5 5 5 5 5 7 7 7 7 7 7 5 5 5 5 5 5 6 7 3 6 6 8 8 6 6 6 6 6 6 8 8 8 8 8 8 6 6 6 6 6 6 7 8 2 3 3 3 3 5 3 * * * * * * * * note: * rs can also be specified for the source operand. 589
table a-7 number of states required for instruction execution (2) 3 3 28 6 4 3 instruction addressing mode i j k 1 23 29 6 7 5 5 7 8 rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 cmp:e #xx:8,rd cmp:i #xx:16,rd dadd rs,rd divxu.b ,rd divxu.w ,rd dsub rs,rd exts rd extu rd ldc.b ,cr ldc.w ,cr mov:g.b mov:g.w mov:g.b #xx:8, mov:g.w #xx:16, mov:e #xx:8,rd mov:i #xx:16,rd mov:l.b @aa:8,rd mov:l.w @aa:8,rd mov:s.b rs,@aa:8 mov:s.w rs,@aa:8 mov:f.b @(d:8,r6),rd mov:f.w @(d:8,r6),rd mov:f.b rs,@(d:8,r6) mov:fw rs,@(d:8,r6) 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 0 0 2 1 1 2 1 1 1 1 1 1 2 3 0 0 0 0 0 0 0 0 0 0 1 4 20 26 4 3 3 3 4 2 2 2 23 29 6 7 5 5 7 8 5 5 5 5 3 24 30 7 8 6 6 8 9 1 23 29 6 7 5 5 7 8 1 24 30 7 8 6 6 8 9 2 23 29 6 7 5 5 7 8 5 5 5 5 3 24 30 7 8 6 6 8 9 2 2 21 4 3 2 590
table a-7 number of states required for instruction execution (3) 3 25 4 9 instruction addressing mode i j k 1 13 20 13 20 19 25 7 7 7 7 5 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 (movfpe ,rd) * (movtpe rs,) * mulxu.b ,rd mulxu.w ,rd neg.b neg.w not.b not.w or.b ,rd or.w ,rd orc #xx,cr rotl.b rotl.w rotr.b rotr.w rotxl.b rotxl.w rotxr.b rotxr.w shal.b shal.w shar.b shar.w shill.b shll.w 0 0 1 2 2 4 2 4 1 2 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 13 20 13 20 19 25 7 7 7 7 5 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 3 14 21 14 21 20 26 8 8 8 8 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1 13 20 13 20 19 25 7 7 7 7 5 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 1 14 21 14 21 20 26 8 8 8 8 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 13 20 13 20 19 25 7 7 7 7 5 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 3 14 21 14 21 20 26 8 8 8 8 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 18 3 5 note: * not available in the h8/538 and h8/539. 591
table a-7 number of states required for instruction execution (4) 3 4 4 4 4 9 instruction addressing mode i j k 1 7 7 7 7 5 5 5 5 5 5 7 5 5 5 5 rn @rn @(d:8,rn) @(d:16,rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 shlr.b shlr.w stc.b cr, stc.w cr, sub.b ,rd sub.w ,rd subs.b ,rd subs.w ,rd subx.b ,rd subx.w ,rd swap rd tas tst.b tst.w xch rs,rd xor.b ,rd xor.w ,rd xorc #xx,cr 2 4 1 2 1 2 1 2 1 2 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 4 4 2 2 3 3 2 2 3 4 2 2 4 2 2 2 7 7 7 7 5 5 5 5 5 5 7 5 5 6 6 3 8 8 8 8 6 6 6 6 6 6 8 6 6 5 5 1 7 7 7 7 5 5 5 5 5 5 7 5 5 5 5 1 8 8 8 8 6 6 6 6 6 6 8 6 6 6 6 2 7 7 7 7 5 5 5 5 5 5 7 5 5 5 5 3 8 8 8 8 6 6 6 6 6 6 8 6 6 6 6 2 3 3 3 3 5 1 2 6 7 10 11 6 8 10 12 1 1 1 1 1 1 20 25 20 25 8 8 23 28 23 28 11 11 23 28 23 28 11 11 24 29 24 29 12 12 23 28 23 28 11 11 24 29 24 29 12 12 23 28 23 28 11 11 24 29 24 29 12 12 21 21 9 27 27 10 divxu.b zero divide, minimum mode divxu.b zero divide, maximum mode divxu.w zero divide, minimum mode divxu.w zero divide, maximum mode divxu.b overflow divxu.w overflow memory operand register operand or immediate data note: * * 592
table a-7 number of states required for instruction execution (5) instruction (condition) execution states condition false, branch not taken condition true, branch taken condition false, branch not taken condition true, branch taken d:8 d:16 @aa:16 @rn @(d:8,rn) @(d:16,rn) @aa:16 @rn @(d:8,rn) @(d:16,rn) #xx:8 #xx:16 #xx:8 #xx:16 minimum mode maximum mode condition true, branch not taken count = ?, branch not taken other conditions, branch taken until transition to sleep mode minimum mode maximum mode note: * n: number of registers in register list bcc d:8 bcc d:16 bsr jmp jsr ldm link nop rtd rte rts scb sleep stm trapa i j + k 3 7 3 7 9 9 7 6 7 8 9 9 9 10 6 + 4n * 6 7 2 9 9 13 15 8 3 4 8 2 6 + 3n * 17 22 2 2 2 2 2 2 2n 2 2 2 2 4 6 2 2n 6 10 2 5 3 6 4 5 5 5 5 6 5 5 5 6 2 2 3 1 4 5 4 4 4 3 3 6 0 2 4 4 593
table a-7 number of states required for instruction execution (6) table a-8 (a) correction values (branch instructions) table a-8 (b) correction values (general instructions, for each addressing mode) instruction condition execution states v = 0, branch not taken v = 1, branch taken, minimum mode v = 1, branch taken, maximum mode @aa:24 @rn @aa:24 @rn #xx:8 #xx:16 trap/vs unlk pjmp pjsr prts prtd i j + k 3 18 23 5 9 8 15 13 12 13 13 6 10 2 4 4 4 4 4 1 4 4 1 6 5 6 5 5 5 6 instruction branch address correction bsr,jmp,jsr,rts,rtd,rte trapa,pjmp,pjsr,prts,prtd bcc,scb,trap/vs (if branch is taken) even odd even odd 0 1 0 1 instruction mov.b #xx:8 mov.w #xx:16 start address all other insructions even odd even odd even odd rn @rn @(d:8, rn @(d:16, rn @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 1 2 0 1 0 1 1 0 2 0 1 1 1 2 0 1 0 1 1 2 0 1 0 1 1 2 0 1 0 1 1 0 2 0 1 1 1 2 0 1 0 0 0 0 0 0 0 594
a.5 instruction set a.5.1 features features of the h8/500 cpu instruction set are as follows: general-register architecture highly orthogonal instruction set supports register-register and register-memory operations oriented toward c language a.5.2 instruction types the h8/500 cpu instruction set consists of 63 instructions. table a-9 classifies the instruction set. table a-9 instruction types number of type instructions instructions data transfer mov ldm stm xch swap movtpe movfpe 7 arithmetic operations add sub adds subs addx subx dadd dsub 17 mulxu divxu cmp exts extu tst neg clr ta s logic operations and or xor not 4 shift shal shar shll shlr rotl rotr rotxl 8 rotxr bit manipulation bset bclr btst bnot 4 branch bcc * jmp pjmp bsr jsr pjsr rts prts rtd 11 prtd scb(/f/ne/eq) system control trapa trap/vs rte sleep ldc stc andc orc 12 xorc nop link unlk note: * bcc is the generic designation for a conditional branch instruction. 595
a.5.3 basic instruction formats (1) general format: this format consists of an effective address (ea) field, an effective address extension field, and an operation code (op) field. the effective address is placed before the operation code because this results in faster execution of the instruction. table a-10 describes the three fields of the general instruction format. table a-10 fields in general instruction format example 1: instruction with prefix code: dadd instruction (2) special format : in this format the operation code comes first, followed by the effective address field and effective address extension. this format is used in branching instructions, system control instructions, and some short-format instructions that can be executed faster if the operation is specified before the operand. table a-11 describes the three fields of the special instruction format. effective address field effective address extension operation code name byte length description ea field 1 information used to calculate the effective address of an operand ea extension 0? byte length is defined in ea field displacement value, immediate data, or absolute address op field 1? defines the operation carried out on the operand some instructions (dadd, dsub, movfpe, movtpe) have an extended format in which the operand code is preceded by a one-byte prefix code (example 1) r r r 0 0 1 0 10 0 0 0 0 0 0 0r r r 0 0 1 0 1 effective address prefix code operation code operation code effective address field effective address extension 596
table a-11 fields in special instruction format a.5.4 data transfer instructions there are seven data transfer instructions. the function of each instruction is described next. (1) mov instruction: transfers data between two general registers, or between a general register and memory. can also transfer immediate data to a register or memory. operation: (eas) ? (ead), #imm ? (ead) instructions and operand sizes: the following table lists the possible combinations. name byte length description op field 1? defines the operation performed by the instruction ea field and ea 0? information used to calculate an effective address extension (ead) registers (cpu) memory example: mov:g.w rs, ead rs size instruction b/w b w mov:g m mov:e m mov:f m mov:i m mov:l m mov:s m b: byte w: word 597
(2) ldm instruction (w): loads data saved on the stack into one or more registers. multiple registers can be loaded simultaneously. operation: @sp+ (stack) ? rn (register list) instructions and operand sizes: the operand size is always word size. (3) stm instruction (w): saves data onto the stack. multiple registers can be saved simultaneously. operation: rn (register list) ? @?p (stack) instructions and operand sizes: the operand size is always word size. registers (cpu) memory example: ldm r0?2, @sp+ sp (old sp) r0 r1 r2 r0 r1 r2 r3 registers (cpu) memory example: stm @?p, r0?2 sp (old sp) r0 r1 r2 r0 r1 r2 r3 598
(4) xch instruction (w): exchanges data between two general registers. operation: rs ? rd, rd ? rs instructions and operand sizes: the operand size is always word size. (5) swap instruction (w): exchanges data between the upper and lower bytes of a general register. operation: rd (upper byte) ? rd (lower byte) instructions and operand sizes: the operand size is always byte size. registers (cpu) example: xch r0, r2 r0 r1 r2 r3 r0 r1 r2 r3 a ba b registers (cpu) example: swap r0 r0 r1 r2 r3 r0 r1 r2 r3 a b a b 599
(6) movtpe instruction (b): transfers general register contents to memory in synchronization with the e clock. (note: the h8/538 and h8/539 do not output an e clock). operation: rn ? (ead) instructions and operand sizes: the operand size is always byte size. (7) movfpe instruction (b): transfers memory contents to a general register in synchronization with the e clock. (note: the h8/538 and h8/539 do not output an e clock). operation: (eas) ? rd instructions and operand sizes: the operand size is always byte size. (ead) registers (cpu) memory example: movtpe rs, ead rs (eas) registers (cpu) memory example: movfpe eas, rd rd 600
a.5.5 arithmetic instructions there are 17 arithmetic instructions. the function of each instruction is described next. (1) add instruction (b/w) (2) sub instruction (b/w) (3) adds instruction (b/w) (4) subs instruction (b/w) these instructions perform addition and subtraction on data in two general registers, data in a general register and memory, data in a general register and immediate data, or data in memory and immediate data. operation: rd (eas) ? rd, (ead) #imm ? (ead) instructions and operand sizes: byte or word operand size can be selected. (5) addx instruction (b/w) (6) subx instruction (b/w) these instructions perform addition and subtraction with carry on data in two general registers, data in a general register and memory, or data in a general register and immediate data. registers (cpu) example: add.w #1, rd rd 1 a + 1 alu a 601
operation: rd (eas) c ? rd instructions and operand sizes: byte or word operand size can be selected. (7) dadd instruction (b) (8) dsub instruction (b) these instructions perform decimal addition and subtraction on data in two general registers. operation: (rd) 10 (rs) 10 ? ? (rd) 10 instructions and operand sizes: the operand size is always byte size. registers (cpu) example: addx.w #1, rd rd 1 a + 1 + c alu a c ccr registers (cpu) example: dadd rs, rd rd alu b a rs (a + b + c) 10 c ccr 602
(9) mulxu instruction (b/w): performs 8-bit 8-bit or 16-bit 16-bit unsigned multiplication on data in a general register and data in another general register or memory, or on data in a general register and immediate data. operation: rd (eas) ? rd instructions and operand sizes: byte or word operand size can be selected. (10) divxu instruction (b/w): performs 16-bit 8-bit or 32-bit 16-bit unsigned division on data in a general register and data in another general register or memory, or on data in a general register and immediate data. operation: rd (eas) ? rd instructions and operand sizes: byte or word operand size can be selected. registers (cpu) example: mulxu.b rs, rd rd alu b a rs rd b rs result a b registers (cpu) example: divxu.b rs, rd rd a b alu b a rs rd b rs result 603
(11) cmp instruction: compares data in a general register with data in another general register or memory, or with immediate data, or compares immediate data with data in memory. operation: rd ?(eas), (ead) ?#imm instructions and operand sizes: the following table lists the possible combinations. registers (cpu) example: cmp:g.b rs, rd rd a? alu a b rs ccr left unchanged size instruction b/w b w cmp:g m cmp:e m cmp:i m b: byte w: word 604
(12) exts instruction (b): converts byte data in a general register to word data by extending the sign bit. operation: ( of ) ? ( of ) instructions and operand sizes: the operand size is always byte size. (13) extu instruction (b): converts byte data in a general register to word data by padding with zero bits. operation: 0 ? ( of ) instructions and operand sizes: the operand size is always byte size. registers (cpu) example: exts r0 r0 r0 (before execution) (after execution) 15 8 7 0 15 8 7 0 1 0 1 1 0 1 0 1 don? care 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 sign extension registers (cpu) example: extu r0 r0 r0 (before execution) (after execution) 15 8 7 0 15 8 7 0 1 0 1 1 0 1 0 1 don? care 1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 zero extension 605
(14) tst instruction (b/w): compares general register or memory contents with zero. operation: (ead) ?0 instructions and operand sizes: byte or word operand size can be selected. (15) neg instruction (b/w): obtains the twos complement of general register or memory contents. operation: 0 ?(ead) ? (ead) instructions and operand sizes: byte or word operand size can be selected. registers (cpu) example: tst.w r0 r0 a? alu a ccr left unchanged 0 registers (cpu) example: neg.w r0 r0 0? alu a 0 r0 2? complement 606
(16) clr instruction (b/w): clears general register or memory contents to zero. operation: 0 ? (ead) instructions and operand sizes: byte or word operand size can be selected. (17) tas instruction (b): tests general register or memory contents, then sets the most significant bit (bit 7) to 1. operation: (ead) ?0, (1) 2 ? ( of ) instructions and operand sizes: the operand size is always byte size. registers (cpu) example: clr.w r0 r0 r0 (before execution) (after execution) 15 0 15 0 don? care 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cleared to zero registers (cpu) example: tas r0 r0 a? alu a ccr 0 r0 (after execution) 15 0 1 set to 1 8 7 don? care * * * * * * * 607
a.5.6 logic instructions there are four logic instructions. the function of each instruction is described next. (1) and instruction (b/w): performs a logical and operation on a general register and another general register, memory, or immediate data. operation: rd (eas) ? rd instructions and operand sizes: byte or word operand size can be selected. (2) or instruction (b/w): performs a logical or operation on a general register and another general register, memory, or immediate data. operation: rd (eas) ? rd instructions and operand sizes: byte or word operand size can be selected. registers (cpu) example: and.b rs, rd rd alu rs result rd rs a b b a b registers (cpu) example: or.w rs, rd rd alu b a rs result rd b rs a b 608
(3) xor instruction (b/w): performs a logical exclusive or operation on a general register and another general register, memory, or immediate data. operation: rd ? (eas) ? rd instructions and operand sizes: byte or word operand size can be selected. (4) not instruction (b/w): takes the ones complement of general register or memory contents. operation: (ead) ? (ead) instructions and operand sizes: byte or word operand size can be selected. registers (cpu) example: xor.w rs, rd rd a + b alu b a rs result rd b rs registers (cpu) example: not.w rd rd ? alu a 1? complement rd 609
a.5.7 shift instructions there are eight shift instructions. the function of each instruction is described next. (1) shal instruction (b/w) (2) shar instruction (b/w) these instructions perform an arithmetic shift operation on general register or memory contents. operation: (ead) arithmetic shift ? (ead) instructions and operand sizes: byte or word operand size can be selected. (3) shll instruction (b/w) (4) shlr instruction (b/w) these instructions perform a logic shift operation on general register or memory contents. example: shal.w rd msb lsb c (ccr) example: shar.w rd msb lsb c(ccr) (0) 2 610
operation: (ead) logic shift ? (ead) instructions and operand sizes: byte or word operand size can be selected. (5) rotl instruction (b/w) (6) rotr instruction (b/w) these instructions rotate general register or memory contents. operation: (ead) rotate ? (ead) instructions and operand sizes: byte or word operand size can be selected. example: shll.w rd msb lsb c (ccr) example: shlr.w rd msb lsb c(ccr) (0) 2 (0) 2 example: rotl.w rd msb lsb c (ccr) example: rotr.w rd msb lsb c(ccr) 611
(7) rotxl instruction (b/w) (8) rotxr instruction (b/w) these instructions rotate general register or memory contents through the carry bit. operation: (ead) rotate through carry ? (ead) instructions and operand sizes: byte or word operand size can be selected. a.5.8 bit manipulation instructions there are four bit manipulation instructions. the function of each instruction is described next. example: rotxl .w rd msb lsb c (ccr) example: rotxr.w rd msb lsb c (ccr) 612
(1) bset instruction (b/w): tests a specified bit in a general register or memory, then sets the bit to 1. the bit is specified by immediate data or a bit number in a general register. operation: ( of ) ? z 1 ? ( of ) instructions and operand sizes: byte or word operand size can be selected. (2) bclr instruction (b/w): tests a specified bit in a general register or memory, then clears the bit to 0. the bit is specified by immediate data or a bit number in a general register. operation: ( of ) ? z 0 ? ( of ) instructions and operand sizes: byte or word operand size can be selected. registers (cpu) example: bset.w h'e, r1 r1 alu 14 a 1 r1 14 1 z (ccr) ? registers (cpu) example: bclr.w h'e, r1 r1 alu 14 a z (ccr) ? 0 r1 14 0 613
(3) bnot instruction (b/w): tests a specified bit in a general register or memory, then inverts the bit. the bit is specified by immediate data or a bit number in a general register. operation: ( of ) ? z ? ( of ) instructions and operand sizes: byte or word operand size can be selected. (4) btst instruction (b/w): tests a specified bit in a general register or memory. the bit is specified by immediate data or a bit number in a general register. operation: ( of ) ? z instructions and operand sizes: byte or word operand size can be selected. registers (cpu) example: bnot.w h'e, r1 r1 alu 14 a z (ccr) ? r1 14 ? registers (cpu) example: btst.w h'e, r1 r1 alu 14 a ? left unchanged z (ccr) 614
a.5.9 branch instructions there are 11 branch instructions. the function of each instruction is described next. (1) bcc instruction (?: branches if the condition specified in the instruction is true. operation: if condition is true then pc + disp ? pc else next; note: this instruction cannot branch across a page boundary. disp bra bra instruction old pc start of next instruction label new pc pc + disp ? pc disp example: bra label start instruction 615
addressing of branch destination: specified by an eight-bit or 16-bit displacement. (2) jmp instruction (?: branches unconditionally to a specified address in the same page. operation: ? pc addressing of branch destination: register indirect, register indirect with eight-bit or 16-bit displacement, or 16-bit direct addressing. note: this instruction cannot branch across a page boundary. mnemonic description condition bra (bt) always (true) true brn (bf) never (false) false bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs oveflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 @label:16 jmp jmp instruction label new pc @label: 16 ? pc start of instruction example: jmp @label 616
(3) pjmp instruction (?: branches unconditionally to a specified address in a specified page. operation: ? cp, pc addressing of branch destination: register indirect or 24-bit direct addressing. note: this instruction is invalid in minimum mode. (4) bsr instruction (?: branches to a subroutine at a specified address in the same page. operation: pc ? @?p, pc + disp ? pc addressing of branch destination: specified by an eight-bit or 16-bit displacement. note: this instruction cannot branch across a page boundary. pjmp pjmp instruction start of instruction example: pjmp @r2 r2 r3 r2 ? cp r3 ? pc new cp, pc high low @r2 disp bsr bsr instruction old pc start of next instruction label new pc pc + disp ? pc disp start of instruction example: bsr label old pc new sp old sp 617
(5) jsr instruction (?: branches to a subroutine at a specified address in the same page. operation: pc ? @?p, ? pc addressing of branch destination: register indirect, register indirect with eight-bit or 16-bit displacement, or 16-bit direct addressing. note: this instruction cannot branch across a page boundary. (6) pjsr instruction (?: branches to a subroutine at a specified address in a specified page. operation: pc ? @?p, cp ? @?p, ? pc addressing of branch destination: register indirect or 24-bit direct addressing. note: this instruction is invalid in minimum mode. @r2 jsr jsr instruction example: jsr @r2 old pc new sp old sp @r2 ? pc start of next instruction start of instruction old pc new pc r2 r3 r2 ? cp r3 ? pc new cp, pc high low @r2 pjsr pjsr instruction example: pjsr @r2 old pc new tp:sp old tp:sp old pc start of next instruction start of instruction old cp, pc 618
(7) rts instruction (?: returns from a subroutine in the same page. operation: @sp+ ? pc rts can return from a subroutine called by a bsr or jsr instruction. (8) prts instruction (?: returns from a subroutine in another page. operation: @sp+ ? pc, @sp+ ? cp prts can return from a subroutine called by a pjsr instruction. @r2 jsr example: rts new pc new sp old sp old pc rts start of next instruction new pc jsr instruction new cp, pc @r2 pjsr pjsr instruction prts example: prts new pc old tp:sp new cp old cp, pc new tp:sp start of next instruction 619
(9) rtd instruction (?: returns from a subroutine in the same page and adjusts the stack pointer. operation: @sp+ ? pc, sp + #imm ? sp rtd can return from a subroutine called by a bsr or jsr instruction. the stack-pointer adjustment is specified by eight-bit or 16-bit immediate data. note: the immediate data must have an even value. if the stack pointer is set to an odd address, an address error will occur when the stack is accessed. @r2 jsr jsr instruction example: rtd #xx:8 new pc old sp old pc new pc rtd #xx:8 new sp sp+#xx:8 start of next instruction 620
(10) prtd instruction (?: returns from a subroutine in another page and adjusts the stack pointer. operation: @sp+ ? pc, @sp+ ? cp, sp + #imm ? sp prtd can return from a subroutine called by a pjsr instruction. the stack-pointer adjustment is specified by eight-bit or 16-bit immediate data. note: the immediate data must have an even value. if the stack pointer is set to an odd address, an address error will occur when the stack is accessed. @r2 pjsr pjsr instruction start of next instruction example: prtd #xx:8 old sp old cp, pc new cp, pc prtd #xx:8 sp+#xx:8 new pc new cp new sp 621
(11) scb instruction: controls a loop using a loop counter and/or a specified termination condition. operation: if condition is true then next else rn ?1 ? rn; if rn = ? then next else pc + disp ? pc; addressing of branch destination: specified by an eight-bit displacement. example: scb/f r2, label r2 disp loop counter 1 r2? = end of loop 1 pc+disp ? pc disp scb/f instruction start of next instruction start of instruction scb/f label old pc description instruction function condition scb/f false scb/ne not equal z = 0 scb/eq equal z = 1 622
a.5.10 system control instructions there are 12 system control instructions. the function of each instruction is described next. (1) trapa instruction (?: generates a trap exception with a specified vector number. operation: pc ? @?p, (maximum mode: cp ? @?p), sr ? @?p ? pc (maximum mode: ? cp) trapa #4 vector example: trapa #4 trapa #4 h'0028 h'0029 old pc old pc old sr sr old sp new sp new pc start of next instruction start of instruction pc l pc h 623
(2) trap/vs instruction (?: generates a trap exception if the v bit is set to 1. operation: if v bit of ccr = 1 then pc ? @?p, (maximum mode: cp ? @?p), sr ? @?p ? pc (maximum mode: ? cp) else next; trap/vs vector example: trap/vs trapa h'0008 h'0009 pc h pc l old pc old pc old sr sr old sp new sp new pc (v = 1) start of next instruction start of instruction 624
(3) rte instruction (?: returns from an exception-handling routine. operation: @sp+ ? pc, (maximum mode: @sp+ ? cp), @sp+ ? sr trapa #4 vector example: rte trapa #4 rte h'0028 h'0029 new pc new pc new sr sr new sp pc h pc l start of next instruction old sp 625
(4) link instruction (?: creates a stack frame. operation: fp (r6) ? @?p, sp ? fp (r6), sp + #imm ? sp stack frame area: specified by eight-bit or 16-bit immediate data. link instruction example: link fp, #? r6 link disp r6 return pc initial sp (= fp) old fp data 1 old sp initial sp (= fp) old fp old fp area b (fp ?4) area a (fp ?2) new fp new sp stack frame created by link instruction area c (fp ?6) r7 r7 old sp new fp new sp old sp + #imm ? sp 626
(5) unlk instruction (?: releases a stack frame created by the link instruction. operation: fp (r6) ? sp, @sp+ ? fp (r6) (6) sleep instruction (?: causes a transition to a power-down state. (7) ldc instruction (b/w): moves immediate data or general register or memory contents into a specified control register. operation: (eas) ? cr instructions and operand sizes: the operand size depends on the control register. unlk instruction example: unlk fp unlk new fp new sp new fp old fp old sp r6 r6 old fp r7 r7 old sp new fp new sp stack frame released by unlk instruction return pc initial sp (= fp) data 1 area b (fp ?4) area a (fp ?2) area c (fp ?6) initial sp (= fp) @sp+ ? fp general register example: ldc.b r1, dp r1 cp dp tp page registers 627
(8) stc instruction (b/w): moves specified control register data to a general register or memory. operation: cr ? (ead) instructions and operand sizes: the operand size depends on the control register. (9) andc instruction (b/w): logically ands a control register with immediate data. operation: cr #imm ? cr instructions and operand sizes: the operand size depends on the control register. general register example: stc.b dp, r1 r1 cp dp tp page registers dp general register example: andc.w r1, sr r1 status register sr alu sr r1 628
(10) orc instruction (b/w): logically ors a control register with immediate data. operation: cr #imm ? cr instructions and operand sizes: the operand size depends on the control register. (11) xorc instruction (b/w): logically exclusive-ors a control register with immediate data. operation: cr ? #imm ? cr instructions and operand sizes: the operand size depends on the control register. (12) nop instruction (?: only increments the program counter. operation: pc + 1 ? pc general register example: orc.w r1, sr r1 status register sr alu sr r1 general register example: xorc.w r1, sr r1 status register sr alu sr r1 629
a.5.11 short-format instructions the add, cmp, and mov instructions have special short formats. the short formats are a byte shorter than the corresponding general formats, and most of them execute one state faster. table a-12 lists these short formats together with the equivalent general formats. table a-12 short-format instructions and equivalent general formats short-format execution equivalent general- execution instruction length states * 2 format instruction length states * 2 add: q #xx, rd * 1 2 2 add: g #xx: 8, rd 3 3 cmp: e #xx: 8, rd 2 2 cmp: g.b #xx: 8, rd 3 3 cmp: i #xx: 16, rd 3 3 cmp: g.w #xx: 16, rd 4 4 mov: e #xx: 8, rd 2 2 mov: g.b #xx: 8, rd 3 3 mov: i #xx: 16, rd 3 3 mov: g.w #xx: 16, rd 4 4 mov: l @aa: 8, rd 2 5 mov: g @aa: 8, rd 3 5 mov: s rs, @aa: 8 2 5 mov: g rs, @aa: 8 3 5 mov: f @ (d; 8, r6), rd 2 5 mov: g @ (d: 8, r6), rd 3 5 mov: f rs, @ (d: 8, r6) 2 5 mov: g rs, @ (d: 8, r6) 3 5 notes: 1. the add:q instruction accepts other destination operands in addition to a general register. 2. number of execution states for access to on-chip memory. 630
631 appendix b initial values of cpu registers table b-1 register values after reset exception handling register initial value minimum mode maximum mode undetermined undetermined loaded from vector table loaded from vector table h'070 * h'070 * undetermined * the last four bits (n, v, z, and c) are undetermined. * the last four bits (n, v, z, and c) are undetermined. loaded from vector table dp, ep, and tp: undetermined undetermined undetermined 15 0 r0 r1 r2 r3 r4 r5 r6 (fp) r7 (sp) 15 0 15 0 pc sr ccr 8 7 7 0 cp dp ep tp br t i 2 i 1 i 0 n v z c 7 0 cp:
appendix c on-chip registers bit names h'fe80 port 1 p1ddr p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr h'00 h'fe81 port 2 p2ddr p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr h'00 h'fe82 port 1 p1dr p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 h'00 h'fe83 port 2 p2dr p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 h'00 h'fe84 port 3 p3ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr h'c0 h'fe85 port 4 p4ddr p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr h'00 h'fe86 port 3 p3dr p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 h'c0 h'fe87 port 4 p4dr p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 h'00 h'fe88 port 5 p5ddr p5 7 ddr p5 6 ddr p5 5 ddr p5 4 ddr p5 3 ddr p5 2 ddr p5 1 ddr p5 0 ddr h'00 h'fe89 port 6 p6ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr h'e0 h'fe8a port 5 p5dr p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 h'00 h'fe8b port 6 p6dr p6 4 p6 3 p6 2 p6 1 p6 0 h'e0 h'fe8c port 7 p7ddr p7 7 ddr p7 6 ddr p7 5 ddr p7 4 ddr p7 3 ddr p7 2 ddr p7 1 ddr p7 0 ddr h'00 h'fe8d h'ff h'fe8e port 7 p7dr p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 h'00 h'fe8f port 8 p8dr p8 3 p8 2 p8 1 p8 0 undeter- mined (continued on next page) address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value 632
633 (continued from previous page) bit names h'fe90 h'ff h'fe91 port a paddr pa 6 ddr pa 5 ddr pa 4 ddr pa 3 ddr pa 2 ddr pa 1 ddr pa 0 ddr h'80 h'fe92 port 9 p9dr p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 undeter- mined h'fe93 port a padr pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 h'80 h'fe94 port b pbddr pb 7 ddr pb 6 ddr pb 5 ddr pb 4 ddr pb 3 ddr pb 2 ddr pb 1 ddr pb 0 ddr h'00 h'fe95 port c pcddr pc 7 ddr pc 6 ddr pc 5 ddr pc 4 ddr pc 3 ddr pc 2 ddr pc 1 ddr pc 0 ddr h'00 h'fe96 port b pbdr pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 h'00 h'fe97 port c pcdr pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 h'00 h'fe98 port b pbpcr pb 7 pon pb 6 pon pb 5 pon pb 4 pon pb 3 pon pb 2 pon pb 1 pon pb 0 pon h'00 h'fe99 port c pcpcr pc 7 pon pc 6 pon pc 5 pon pc 4 pon pc 3 pon pc 2 pon pc 1 pon pc 0 pon h'00 h'fe9a ?r * croe h'ff h'fe9b h'ff h'fe9c h'ff h'fe9d h'ff h'fe9e h'ff h'fe9f h'ff note: * ?r is not present in the h8/538. (continued on next page) address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
634 (continued from previous page) bit names h'fea0 a/d addr0h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'fea1 addr0l ad 1 ad 0 h'00 h'fea2 addr1h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'fea3 addr1l ad 1 ad 0 h'00 h'fea4 addr2h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'fea5 addr2l ad 1 ad 0 h'00 h'fea6 addr3h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'fea7 addr3l ad 1 ad 0 h'00 h'fea8 addr4h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'fea9 addr4l ad 1 ad 0 h'00 h'feaa addr5h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'feab addr5l ad 1 ad 0 h'00 h'feac addr6h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'fead addr6l ad 1 ad 0 h'00 h'feae addr7h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'feaf addr7l ad 1 ad 0 h'00 legend (continued on next page) a/d: a/d converter address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
635 (continued from previous page) bit names h'feb0 a/d addr8h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'feb1 addr8l ad 1 ad 0 h'00 h'feb2 addr9h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'feb3 addr9l ad 1 ad 0 h'00 h'feb4 addrah ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'feb5 addral ad 1 ad 0 h'00 h'feb6 addrbh ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'00 h'feb7 addrbl ad 1 ad 0 h'00 h'feb8 adcsr adf adie adm1 adm0 ch3 ch2 ch1 ch0 h'00 h'feb9 adcr trge cks adst h'1f h'feba h'ff h'febb h'ff h'febc h'ff h'febd h'ff h'febe h'ff h'febf h'ff legend (continued on next page) a/d: a/d converter address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
636 (continued from previous page) bit names h'fec0 sci3 * smr c/a chr pe o/e stop mp cks1 cks0 h'00 h'fec1 brr h'ff h'fec2 scr tie rie te re mpie teie cke1 cke0 h'00 h'fec3 tdr h'ff h'fec4 ssr tdre rdrf orer fer per tend mpb mpbt h'84f h'fec5 rdr h'00 h'fec6 h'ff h'fec7 undeter- mined h'fec8 sci1 smr c/a chr pe o/e stop mp cks1 cks0 h'00 h'fec9 brr h'ff h'feca scr tie rie te re mpie teie cke1 cke0 h'00 h'fecb tdr h'ff h'fecc ssr tdre rdrf orer fer per tend mpb mpbt h'84 h'fecd rdr h'00 h'fece h'ff h'fecf undeter- mined legend (continued on next page) sci1: serial communication interface 1 sci3: serial communication interface 3 note: * sci3 is not present in the h8/538. if this register is not present, the initial value is h'ff. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
637 (continued from previous page) bit names h'fed0 sci2 smr c/a chr pe o/e stop mp cks1 cks0 h'00 h'fed1 brr h'ff h'fed2 scr tie rie te re mpie teie cke1 cke0 h'00 h'fed3 tdr h'ff h'fed4 ssr tdre rdrf orer fer per tend mpb mpbt h'84 h'fed5 rdr h'00 h'fed6 h'ff h'fed7 undeter- mined h'fed8 h'ff h'fed9 h'ff h'feda port a * 1 pacr txd3e rxd3e sck3e pw3e pw2e pw1e h'90 h'fedb port 6/7 * 1 p67cr pw2e pw1e pw3e h'3e h'fedc adtrg extrg h'ff h'fedd h'ff h'fede intc irqfr irq3f irq2f irq1f h'f1 h'fedf bsc bcr bcre 0p3t p9ae exiop pcre pbce p12e h'3f * 2 legend (continued on next page) sci2: serial communication interface 2 intc: interrupt controller bsc: bus controller notes: 1. pacr and p67cr are not present in the h8/538. if this register is not present, the initial value is h'ff. 2. initial value in modes 5 and 6. in modes 1 to 4 and mode 7 the initial value is h'bf. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
638 (continued from previous page) bit names h'fee0 h'ff h'fee1 h'ff h'fee2 h'ff h'fee3 h'ff h'fee4 h'ff h'fee5 h'ff h'fee6 h'ff h'fee7 h'ff h'fee8 h'ff h'fee9 h'ff h'feea h'ff h'feeb h'ff h'feec h'ff h'feed h'ff h'feee h'ff h'feef h'ff (continued on next page) address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
639 (continued from previous page) bit names h'fef0 pwm1 * tcr oe os cks2 cks1 cks0 h'38 h'fef1 dtr h'ff h'fef2 tcnt h'00 h'fef3 h'ff h'fef4 pwm2 * tcr oe os cks2 cks1 cks0 h'38 h'fef5 dtr h'ff h'fef6 tcnt h'00 h'fef7 h'ff h'fef8 pwm3 * tcr oe os cks2 cks1 cks0 h'38 h'fef9 dtr h'ff h'fefa tcnt h'00 h'fefb h'ff h'fefc h'ff h'fefd h'ff h'fefe h'ff h'feff h'ff legend (continued on next page) pwm: pulse width modulation note: * pwm1, pwm2, and pwm3 are not present in the h8/538. the initial value is h'ff. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
640 (continued from previous page) bit names h'ff00 intc ipra 0 0 h'00 h'ff01 iprb 0 0 h'00 h'ff02 iprc 0 0 h'00 h'ff03 iprd 0 0 h'00 h'ff04 ipre 0 0 h'00 h'ff05 iprf 0 0 h'00 h'ff06 dtc undeter- mined h'ff07 undeter- mined h'ff08 dtea 0 adi (irq0) irq0 0 irq3 irq2 irq1 h'00 h'ff09 dteb 0 t1cmi1,2 t1imi2 t1imi1 0 t1cmi3,4 t1imi4 t1imi3 h'00 h'ff0a dtec 0 t2cmi1,2 t2imi2 t2imi1 0 t3cmi1,2 t3imi2 t3imi1 h'00 h'ff0b dted 0 t4cmi1,2 t4imi2 t4imi1 0 t5cmi1,2 t5imi2 t5imi1 h'00 h'ff0c dtee 0 0 t6imi2 t6imi1 0 0 t7imi2 t7imi1 h'00 h'ff0d dtef 0 ti1 ri1 0 0 ti2 ri2 0 h'00 h'ff0e undeter- mined h'ff0f undeter- mined legend (continued on next page) intc: interrupt controller dtc: data transfer controller address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
641 (continued from previous page) bit names h'ff10 wdt (tcsr) * 1 ovf wt/it tme cks2 cks1 cks0 h'18 h'ff11 tcnt * 1 h'00 h'ff12 h'ff h'ff13 h'ff h'ff14 wsc wcr wms1 wms0 wc1 wc0 h'f3 h'ff15 ramcr ramcr rame1 rame2 * 3 undeter- mined h'ff16 bsc arbt h'ff h'ff17 ar3t h'0e * 2 h'ff18 h'ff h'ff19 mdcr mds2 mds1 mds0 undeter- mined h'ff1a sbycr ssby h'7f h'ff1b brcr brle h'fe h'ff1c nmicr nmieg h'fe h'ff1d irqcr irq3e irq2e irq1e irq0e h'f0 h'ff1e (write cr) h'ff1f rstcsr wrst rstoe h'3f legend (continued on next page) wdt: watchdog timer wsc: wait-state controller ramcr: ram controller bsc: bus controller notes: 1. these registers are write-protected by a password. see section 13.2.4 , ?otes on register access?for details. 2. initial value in modes 5 and 6. in modes 1 to 4 and mode 7 the initial value is h'ee. 3. bit rame2 is not present in the h8/538. in the h8/538 this bit always reads 1. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
642 (continued from previous page) bit names h'ff20 t1crh ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 h'ff21 t1crl cclr2 cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'80 h'ff22 t1srah ovie cmie2 cmie1 imie2 imie1 h'e0 h'ff23 t1sral ovf cmf2 cmf1 imf2 imf1 h'e0 h'ff24 t1oera doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 h'ff25 tmdra md6-7 md4-7 md3-5 md2-6 sync3 sync2 sync1 sync0 h'00 h'ff26 t1cnth * h'00 h'ff27 t1cntl * h'00 h'ff28 t1gr1h * h'ff h'ff29 t1gr1l * h'ff h'ff2a t1gr2h * h'ff h'ff2b t1gr2l * h'ff h'ff2c t1dr1h * h'ff h'ff2d t1dr1l * h'ff h'ff2e t1dr2h * h'ff h'ff2f t1dr2l * h'ff legend (continued on next page) ipu: 16-bit integrated timer pulse unit note: * these registers support 16-bit access. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value ipu channel 1
643 (continued from previous page) bit names h'ff30 tstr str7 str6 str5 str4 str3 str2 str1 h'80 h'ff31 t1cra ieg41 ieg40 ieg31 ieg30 h'f0 h'ff32 t1srbh cmie4 cmie3 imie4 imie3 h'f0 h'ff33 t1srbl cmf4 cmf3 imf4 imf3 h'f0 h'ff34 t1oerb doe41 doe40 doe31 doe30 goe41 goe40 goe31 goe30 h'00 h'ff35 tmdrb mdf pwm4 pwm3 pwm2 pwm1 pwm0 h'c0 h'ff36 h'ff h'ff37 h'ff h'ff38 t1gr3h * h'ff h'ff39 t1gr3l * h'ff h'ff3a t1gr4h * h'ff h'ff3b t1gr4l * h'ff h'ff3c t1dr3h * h'ff h'ff3d t1dr3l * h'ff h'ff3e t1dr4h * h'ff h'ff3f t1dr4l * h'ff legend (continued on next page) ipu: 16-bit integrated timer pulse unit note: * these registers support 16-bit access. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value ipu channel 1
644 (continued from previous page) bit names h'ff40 t2crh ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 h'ff41 t2crl cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 h'ff42 t2srh ovie cmie2 cmie1 imie2 imie1 h'e0 h'ff43 t2srl ovf cmf2 cmf1 imf2 imf1 h'e0 h'ff44 t2oer doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 h'ff45 h'ff h'ff46 t2cnth * h'00 h'ff47 t2cntl * h'00 h'ff48 t2gr1h * h'ff h'ff49 t2gr1l * h'ff h'ff4a t2gr2h * h'ff h'ff4b t2gr2l * h'ff h'ff4c t2dr1h * h'ff h'ff4d t2dr1l * h'ff h'ff4e t2dr2h * h'ff h'ff4f t2dr2l * h'ff legend (continued on next page) ipu: 16-bit integrated timer pulse unit note: * these registers support 16-bit access. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value ipu channel 2
645 (continued from previous page) bit names h'ff50 t3crh ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 h'ff51 t3crl cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 h'ff52 t3srh ovie cmie2 cmie1 imie2 imie1 h'e0 h'ff53 t3srl ovf cmf2 cmf1 imf2 imf1 h'e0 h'ff54 t3oer doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 h'ff55 h'ff h'ff56 t3cnth * h'00 h'ff57 t3cntl * h'00 h'ff58 t3gr1h * h'ff h'ff59 t3gr1l * h'ff h'ff5a t3gr2h * h'ff h'ff5b t3gr2l * h'ff h'ff5c t3dr1h * h'ff h'ff5d t3dr1l * h'ff h'ff5e t3dr2h * h'ff h'ff5f t3dr2l * h'ff legend (continued on next page) ipu: 16-bit integrated timer pulse unit note: * these registers support 16-bit access. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value ipu channel 3
646 (continued from previous page) bit names h'ff60 t4crh ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 h'ff61 t4crl cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 h'ff62 t4srh ovie cmie2 cmie1 imie2 imie1 h'e0 h'ff63 t4srl ovf cmf2 cmf1 imf2 imf1 h'e0 h'ff64 t4oer doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 h'ff65 h'ff h'ff66 t4cnth * h'00 h'ff67 t4cntl * h'00 h'ff68 t4gr1h * h'ff h'ff69 t4gr1l * h'ff h'ff6a t4gr2h * h'ff h'ff6b t4gr2l * h'ff h'ff6c t4dr1h * h'ff h'ff6d t4dr1l * h'ff h'ff6e t4dr2h * h'ff h'ff6f t4dr2l * h'ff legend (continued on next page) ipu: 16-bit integrated timer pulse unit note: * these registers support 16-bit access. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value ipu channel 4
647 (continued from previous page) bit names h'ff70 t5crh ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 h'ff71 t5crl cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 h'ff72 t5srh ovie cmie2 cmie1 imie2 imie1 h'e0 h'ff73 t5srl ovf cmf2 cmf1 imf2 imf1 h'e0 h'ff74 t5oer doe21 doe20 doe11 doe10 goe21 goe20 goe11 goe10 h'00 h'ff75 h'ff h'ff76 t5cnth * h'00 h'ff77 t5cntl * h'00 h'ff78 t5gr1h * h'ff h'ff79 t5gr1l * h'ff h'ff7a t5gr2h * h'ff h'ff7b t5gr2l * h'ff h'ff7c t5dr1h * h'ff h'ff7d t5dr1l * h'ff h'ff7e t5dr2h * h'ff h'ff7f t5dr2l * h'ff legend (continued on next page) ipu: 16-bit integrated timer pulse unit note: * these registers support 16-bit access. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value ipu channel 5
648 (continued from previous page) bit names h'ff80 t6crh ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 h'ff81 t6crl cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 h'ff82 t6srh ovie imie2 imie1 h'f8 h'ff83 t6srl ovf imf2 imf1 h'f8 h'ff84 t6oer goe21 goe20 goe11 goe10 h'00 h'ff85 h'ff h'ff86 t6cnth * h'00 h'ff87 t6cntl * h'00 h'ff88 t6gr1h * h'ff h'ff89 t6gr1l * h'ff h'ff8a t6gr2h * h'ff h'ff8b t6gr2l * h'ff h'ff8c h'ff h'ff8d h'ff h'ff8e h'ff h'ff8f h'ff legend (continued on next page) ipu: 16-bit integrated timer pulse unit note: * these registers support 16-bit access. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value ipu channel 6
649 (continued from previous page) bit names h'ff90 t7crh ckeg1 ckeg0 tpsc3 tpsc2 tpsc1 tpsc0 h'c0 h'ff91 t7crl cclr1 cclr0 ieg21 ieg20 ieg11 ieg10 h'c0 h'ff92 t7srh ovie imie2 imie1 h'f8 h'ff93 t7srl ovf imf2 imf1 h'f8 h'ff94 t7oer goe21 goe20 goe11 goe10 h'00 h'ff95 h'ff h'ff96 t7cnth * h'00 h'ff97 t7cntl * h'00 h'ff98 t7gr1h * h'ff h'ff99 t7gr1l * h'ff h'ff9a t7gr2h * h'ff h'ff9b t7gr2l * h'ff h'ff9c h'ff h'ff9d h'ff h'ff9e h'ff h'ff9f h'ff legend (continued on next page) ipu: 16-bit integrated timer pulse unit note: * these registers support 16-bit access. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value ipu channel 7
650 (continued from previous page) bit names h'ffa0 mult * mltcr clr s_on sign mul mac h'38 h'ffa1 mltbr h'00 h'ffa2 mltar h'00 h'ffa3 mltmar h'00 h'ffa4 h'ff h'ffa5 h'ff h'ffa6 h'ff h'ffa7 h'ff h'ffa8 h'ff h'ffa9 h'ff h'ffaa h'ff h'ffab h'ff h'ffac h'ff h'feed h'ff h'ffae h'ff h'ffaf h'ff legend (continued on next page) mult: multiplier note: * mult is not present in the h8/538. the initial values are h'ff. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
651 (continued from previous page) bit names h'ffb0 mult * ca h'00 h'ffb1 (ca) h'00 h'ffb2 cb h'00 h'ffb3 (cb) h'00 h'ffb4 cc h'00 h'ffb5 (cc) h'00 h'ffb6 xh undeter- mined h'ffb7 (xh) undeter- mined h'ffb8 h undeter- mined h'ffb9 (h) undeter- mined h'ffba l undeter- mined h'ffbb (l) undeter- mined h'ffbc mr h'00 h'ffbd (mr) h'00 h'ffbe mmr h'00 h'ffbf (mmr) h'00 legend mult: multiplier note: * mult is not present in the h8/538. the initial values are h'ff. address module register initial (low) name name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value
appendix d pin function selection d.1 port 3 function selection 652 doe11, 10 (t1oera) p3 0 ddr selected function 00 01 p3 0 input port p3 0 output port 01, 10, 11 don? care t1oc 1 output table d-1 ipu and p3ddr settings and selected functions of p3 0 /t1oc 1 table d-2 ipu and p3ddr settings and selected functions of p3 1 /t1oc 2 doe21, 20 (t1oera) p3 1 ddr selected function 00 01 p3 1 input port p3 1 output port 01, 10, 11 don? care t1oc 2 output table d-3 ipu and p3ddr settings and selected functions of p3 2 /t1oc 3 doe31, 30 (t1oerb) p3 2 ddr selected function 00 01 p3 2 input port p3 2 output port 01, 10, 11 don? care t1oc 3 output table d-4 ipu and p3ddr settings and selected functions of p3 3 /t1oc 4 doe41, 40 (t1oerb) p3 3 ddr selected function 00 01 p3 3 input port p3 3 output port 01, 10, 11 don? care t1oc 4 output table d-5 ipu and p3ddr settings and selected functions of p3 4 /t2oc 1 doe11, 10 (t2oer) p3 4 ddr selected function 00 01 p3 4 input port p3 4 output port 01, 10, 11 don? care t2oc 1 output table d-6 ipu and p3ddr settings and selected functions of p3 5 /t2oc 2 doe21, 20 (t2oer) p3 5 ddr selected function 00 01 p3 5 input port p3 5 output port 01, 10, 11 don? care t2oc 2 output
653 table d-7 ipu and p4ddr settings and selected functions of p4 0 /t4ioc 1 goe11, 10 (t4oer) ieg11, 10 (t4crl) p4 0 ddr selected function 00 00 0 p4 0 input port 1 p4 0 output port don? care 01, 10, 11 01 p4 0 input port p4 0 output port t4ioc 1 input t4ioc 1 output 01, 10, 11 00 01 table d-8 ipu and p4ddr settings and selected functions of p4 1 /t4ioc 2 goe21, 20 (t4oer) ieg21, 20 (t4crl) p4 1 ddr selected function 00 00 0 p4 1 input port 1 p4 1 output port don? care 01, 10, 11 01 p4 1 input port p4 1 output port t4ioc 2 input t4ioc 2 output 01, 10, 11 00 01 table d-9 ipu and p4ddr settings and selected functions of p4 2 /t5ioc 1 goe11, 10 (t5oer) ieg11, 10 (t5crl) p4 2 ddr selected function 00 00 0 p4 2 input port 1 p4 2 output port don? care 01, 10, 11 01 p4 2 input port p4 2 output port t5ioc 1 input t5ioc 1 output 01, 10, 11 00 01 table d-10 ipu and p4ddr settings and selected functions of p4 3 /t5ioc 2 goe21, 20 (t5oer) ieg21, 20 (t5crl) p4 3 ddr selected function 00 00 0 p4 3 input port 1 p4 3 output port don? care 01, 10, 11 01 p4 3 input port p4 3 output port t5ioc 2 input t5ioc 2 output 01, 10, 11 00 01 d.2 port 4 function selection
654 table d-11 ipu and p4ddr settings and selected functions of p4 4 /t6ioc 1 goe11, 10 (t6oer) ieg11, 10 (t6crl) p4 4 ddr selected function 00 00 0 p4 4 input port 1 p4 4 output port don? care 01, 10, 11 01 p4 4 input port p4 4 output port t6ioc 1 input t6ioc 1 output 01, 10, 11 00 01 table d-12 ipu and p4ddr settings and selected functions of p4 5 /t6ioc 2 goe21, 20 (t6oer) ieg21, 20 (t6crl) p4 5 ddr selected function 00 00 0 p4 5 input port 1 p4 5 output port don? care 01, 10, 11 01 p4 5 input port p4 5 output port t6ioc 2 input t6ioc 2 output 01, 10, 11 00 01 table d-13 ipu and p4ddr settings and selected functions of p4 6 /t7ioc 1 goe11, 10 (t7oer) ieg11, 10 (t7crl) p4 6 ddr selected function 00 00 0 p4 6 input port 1 p4 6 output port don? care 01, 10, 11 01 p4 6 input port p4 6 output port t7ioc 1 input t7ioc 1 output 01, 10, 11 00 01 table d-14 ipu and p4ddr settings and selected functions of p4 7 /t7ioc 2 goe21, 20 (t7oer) ieg21, 20 (t7crl) p4 7 ddr selected function 00 00 0 p4 7 input port 1 p4 7 output port don? care 01, 10, 11 01 p4 7 input port p4 7 output port t7ioc 2 input t7ioc 2 output 01, 10, 11 00 01
655 d.3 port 5 function selection table d-15 ipu and p5ddr settings and selected functions of p5 0 /t1ioc 1 goe11, 10 (t1oera) ieg11, 10 (t1cral) p5 0 ddr selected function 00 00 0 p5 0 input port 1 p5 0 output port don? care 01, 10, 11 01 p5 0 input port p5 0 output port t1ioc 1 input t1ioc 1 output 01, 10, 11 00 01 table d-16 ipu and p5ddr settings and selected functions of p5 1 /t1ioc 2 goe21, 20 (t1oera) ieg21, 20 (t1cral) p5 1 ddr selected function 00 00 0 p5 1 input port 1 p5 1 output port don? care 01, 10, 11 01 p5 1 input port p5 1 output port t1ioc 2 input t1ioc 2 output 01, 10, 11 00 01 table d-17 ipu and p5ddr settings and selected functions of p5 2 /t1ioc 3 goe31, 30 (t1oerb) ieg31, 30 (t1crb) p5 2 ddr selected function 00 00 0 p5 2 input port 1 p5 2 output port don? care 01, 10, 11 01 p5 2 input port p5 2 output port t1ioc 3 input t1ioc 3 output 01, 10, 11 00 01 table d-18 ipu and p5ddr settings and selected functions of p5 3 /t1ioc 4 goe41, 40 (t1oera) ieg41, 40 (t1crb) p5 3 ddr selected function 00 00 0 p5 3 input port 1 p5 3 output port don? care 01, 10, 11 01 p5 3 input port p5 3 output port t1ioc 4 input t1ioc 4 output 01, 10, 11 00 01
656 table d-19 ipu and p5ddr settings and selected functions of p5 4 /t2ioc 1 goe11, 10 (t2oer) ieg11, 10 (t2crl) p5 4 ddr selected function 00 00 0 p5 4 input port 1 p5 4 output port don? care 01, 10, 11 01 p5 4 input port p5 4 output port t2ioc 1 input t2ioc 1 output 01, 10, 11 00 01 table d-20 ipu and p5ddr settings and selected functions of p5 5 /t2ioc 2 goe21, 20 (t2oer) ieg21, 20 (t2crl) p5 5 ddr selected function 00 00 0 p5 5 input port 1 p5 5 output port don? care 01, 10, 11 01 p5 5 input port p5 5 output port t2ioc 2 input t2ioc 2 output 01, 10, 11 00 01 table d-21 ipu and p5ddr settings and selected functions of p5 6 /t3ioc 1 goe11, 10 (t3oer) ieg11, 10 (t3crl) p5 6 ddr selected function 00 00 0 p5 6 input port 1 p5 6 output port don? care 01, 10, 11 01 p5 6 input port p5 6 output port t3ioc 1 input t3ioc 1 output 01, 10, 11 00 01 table d-22 ipu and p5ddr settings and selected functions of p5 7 /t3ioc 2 goe21, 20 (t3oer) ieg21, 20 (t3crl) p5 7 ddr selected function 00 00 0 p5 7 input port 1 p5 7 output port don? care 01, 10, 11 01 p5 7 input port p5 7 output port t3ioc 2 input t3ioc 2 output 01, 10, 11 00 01
657 d.4 port 6 function selection table d-24 irqcr and p6ddr settings and selected functions of p6 1 /irq 3 irq3e (irqcr) p6 1 ddr selected function 01 0 p6 1 input port 1 p6 1 output port 0 p6 1 input port 1 p6 1 output port irq 3 input table d-25 ipu and p6ddr settings and selected functions of p6 2 /tclk 1 tpsc3? (tcrh) p6 2 ddr selected function 0000?100, 1110, 1111 1101 0 p6 2 input port 1 p6 2 output port 0 p6 2 input port 1 p6 2 output port tclk 1 input table d-26 ipu and p6ddr settings and selected functions of p6 3 /tclk 2 tpsc3? (tcrh) p6 3 ddr selected function 0000?101, 1111 1110 0 p6 3 input port 1 p6 3 output port 0 p6 3 input port 1 p6 3 output port tclk 2 input table d-23 pw3e (p67cr) oe (tcr: pwm3) irq 2 e (irqcr) p6 1 ddr selected function 0 * 1 01 0101 01 010101010101 p67cr, pwm3, irqcr, and p6ddr settings and selected functions of p6 0 /irq 2 /pw 3 (h8/539) p6 0 input port p6 0 output port irq 2 input p6 0 input port p6 0 output port p6 0 input port p6 0 output port irq 2 input p6 0 input port p6 0 output port pw 3 output pw 3 output and irq 2 input note: settings when pw3e = 0 applies in the h8/538.
658 d.5 port 7 function selection table d-28 irqcr and p7ddr settings and selected functions of p7 0 /irq 0 irq0e (irqcr) p7 0 ddr selected function 01 0 p7 0 input port 1 p7 0 output port 0 p7 0 input port 1 p7 0 output port irq 0 input table d-29 trge (adcr: a/d) irq1e (irqcr) p7 1 ddr selected function 0 0 1 1 0 1 1 0 0 * 1 1 * 2 0 * 1 1 * 2 0 * 1 1 * 2 0 * 1 1 * 2 irq 1 input adtrg input irq 1 and adtrg input p7 1 input port p7 1 output port notes: 1. 2. irqcr, a/d converter, and p7ddr settings and selected functions of p7 1 /irq 1 /adtrg table d-30 sci1 and p7ddr settings and selected functions of p7 2 /txd 1 te (scr: sci1) p7 2 ddr selected function 01 0 p7 2 input port 1 p7 2 output port 01 txd 1 output table d-27 ipu and p6ddr settings and selected functions of p6 4 /tclk 3 tpsc3? (tcrh) p6 4 ddr selected function 0000?110 1111 0 p6 4 input port 1 p6 4 output port 0 p6 4 input port 1 p6 4 output port tclk 3 input
table d-34 p67cr, pwm1, sci1, and p7ddr settings and selected functions of p7 6 /sck 1 /pw 1 (h8/539) pw1e (p67cr) 0 1 oe (tcr: pwm1) * 01 c/a (smr: sci1) 0 1 ** cke1 (smr: sci1) 0 1 0 1 0 1 0 1 cke0 (smr: sci1) 0 1 **** *** p7 6 ddr 0 1 *** * 0101 ** selected function p7 6 p7 6 sck 1 sck 1 sck 1 sck 1 p7 6 p7 6 p7 6 p7 6 pw 1 pw 1 input output output input output input input output input output output output port port port port port port and and and sck 1 sck 1 sck 1 input input input note: settings when pw1e = 0 applies in the h8/538. 659 table d-32 sci2 and p7ddr settings and selected functions of p7 4 /txd 2 te (scr: sci2) p7 4 ddr selected function 01 0 p7 4 input port 1 p7 4 output port 01 txd 2 output table d-33 sci2 and p7ddr settings and selected functions of p7 5 /rxd 2 re (scr: sci2) p7 5 ddr selected function 01 0 p7 5 input port 1 p7 5 output port 01 rxd 2 input table d-31 sci1 and p7ddr settings and selected functions of p7 3 /rxd 1 re (scr: sci1) p7 3 ddr selected function 01 0 p7 3 input port 1 p7 3 output port 01 rxd 1 input
table d-35 p67cr, pwm2, sci2, and p7ddr settings and selected functions of p7 7 /sck 2 /pw 2 (h8/539) pw2e (p67cr) 0 1 oe (tcr: pwm2) * 01 c/a (smr: sci2) 0 1 ** cke1 (smr: sci2) 0 1 0 1 0 1 0 1 cke0 (smr: sci2) 0 1 **** *** p7 7 ddr 0 1 *** * 0101 ** selected function p7 7 p7 7 sck 2 sck 2 sck 2 sck 2 p7 7 p7 7 p7 7 p7 7 pw 2 pw 2 input output output input output input input output input output output output port port port port port port and and and sck 2 sck 2 sck 2 input input input note: settings when pw2e = 0 applies in the h8/538. d.6 port a function selection table d-36 operating mode, pacr, ipu, pwm1, and paddr settings, and selected functions of pa 0 /a 16 /t4oc 1 /pw 1 (h8/539) operating mode modes 1, 2, 6, 7 mode mode 4 3 or 5 pw1e (pacr) 0 1 * 01 oe (tcr: pwm1) * 01 ** 01 doe11, 10 (t4oer) 00 01,10, **** ** 11 pa 0 ddr 0 1 * 01 ** 0101 * selected function pa 0 pa 0 t4oc 1 pa 0 pa 0 pw 1 a 16 pa 0 a 16 pa 0 pa 0 pw 1 input output output input output output address input address input output output port port port port bus port bus port port note: settings when pw1e = 0 applies in the h8/538. 660
661 table d-37 operating mode, pacr, ipu, pwm2, and paddr settings, and selected functions of pa 1 /a 17 /t4oc 2 /pw 2 (h8/539) operating mode modes 1, 2, 6, 7 mode mode 4 3 or 5 pw2e (pacr) 0 1 * 01 oe (tcr: pwm2) * 01 ** 01 doe21, 20 (t4oer) 00 01,10, **** ** 11 pa 1 ddr 0 1 * 01 ** 0101 * selected function pa 1 pa 1 t4oc 2 pa 1 pa 1 pw 2 a 17 pa 1 a 17 pa 1 pa 1 pw 2 input output output input output output address input address input output output port port port port bus port bus port port note: settings when pw2e = 0 applies in the h8/538. table d-38 operating mode, pacr, ipu, pwm3, and paddr settings, and selected functions of pa 2 /a 18 /t5oc 1 /pw 3 (h8/539) operating mode modes 1, 2, 6, 7 mode mode 4 3 or 5 pw3e (pacr) 0 1 * 01 oe (tcr: pwm3) * 01 ** 01 doe11, 10 (t5oer) 00 01,10, **** ** 11 pa 2 ddr 0 1 * 01 ** 0101 * selected function pa 2 pa 2 t5oc 1 pa 2 pa 2 pw 3 a 18 pa 2 a 18 pa 2 pa 2 pw 3 input output output input output output address input address input output output port port port port bus port bus port port note: settings when pw3e = 0 applies in the h8/538.
table d-39 (1) operating mode, pacr, ipu, sci3, and paddr settings, and selected functions of pa 3 /a 19 /t5oc 2 /sck 3 (h8/539) operating mode modes 1, 2, 6, 7 mode 3 or 5 sck3e (pacr) 0 1 * c/a (smr: sci3) * 0 * cke1 (smr: sci3) * 01 * cke0 (smr: sci3) * 0101 * doe11, 10 (t5oer) 00 01, 10, ***** 11 pa 3 ddr 0 1 * 01 ** * * selected function pa 3 pa 3 t5oc 2 pa 3 pa 3 sck 3 sck 3 sck 3 a 19 input output output input output output input input address port port port port bus note: settings when sck3e = 0 applies in the h8/538. table d-39 (2) operating mode, pacr, ipu, sci3, and paddr settings, and selected functions of pa 3 /a 19 /t5oc 2 /sck 3 (h8/539) operating mode mode 4 sck3e (pacr) 0 1 c/a (smr: sci3) * 0 cke1 (smr: sci3) * 01 cke0 (smr: sci3) * 0 101 cke11, 10 (t5oer) ***** pa 3 ddr 0 1 0 1 *** selected function pa 3 input a 19 pa 3 input pa 3 output sck 3 sck 3 sck 3 port address port port output input input bus note: settings when sck3e = 0 applies in the h8/538. 662 table d-40 operating mode wms1 (wcr) pa 4 ddr selected function modes 1 to 6 mode 7 0 1 don? care 0101 01 input port wait input pa 4 input port pa 4 output port operating mode, wcr and paddr settings, and selected functions of pa 4 /wait output port
table d-41 (1) operating mode, pacr, brcr, ipu, sci3, and paddr settings, and selected functions of pa 5 /t3oc 1 / breq /rxd 3 (h8/539) operating mode modes 1 to 6 rxd3e (pacr) 0 1 1 re (scr: sci3) * 01 brle (brcr) 0 1 0 1 0 1 doe11, 10 (t3oer) 00 01, 10, * 00 01, 10, *** 11 11 pa 5 ddr 0 1 ** 01 ** * * selected function pa 5 pa 5 t3oc 1 breq pa 5 pa 5 t3oc 1 breq rxd 3 breq input output output input input output output input input input port port port port and rxd 3 input note: settings when rxd3e = 0 applies in the h8/538. table d-41 (2) operating mode, pacr, brcr, ipu, sci3, and paddr settings, and selected functions of pa 5 /t3oc 1 / breq /rxd 3 (h8/539) operating mode mode 7 rxd3e (pacr) 0 1 1 re (scr: sci3) * 01 brle (brcr) *** doe11, 10 (t3oer) 00 01, 10, 11 00 01, 10, 11 * pa 5 ddr 0 1 * 01 ** selected function pa 5 input pa 5 output t3oc 1 pa 5 input pa 5 output t3oc 1 rxd 3 port port output port port output input note: settings when rxd3e = 0 applies in the h8/538. 663
table d-42 (1) operating mode, pacr, brcr, ipu, sci3, and paddr settings, and selected functions of pa 6 /t3oc 2 / back /txd 3 (h8/539) operating mode modes 1 to 6 txd3e (pacr) 0 1 1 te (scr: sci3) * 01 brle (brcr) 0 1 0 1 0 1 doe21, 20 (t3oer) 00 01, 10, * 00 01, 10, *** 11 11 pa 6 ddr 0 1 ** 01 ** * * selected function pa 6 pa 6 t3oc 2 back pa 6 pa 6 t3oc 2 back txd 3 back input output output output input output output output output output port port port port note: settings when txd3e = 0 applies in the h8/538. table d-42 (2) operating mode, pacr, brcr, ipu, sci3, and paddr settings, and selected functions of pa 6 /t3oc 2 / back /txd 3 (h8/539) operating mode mode 7 txd3e (pacr) 0 1 1 te (scr: sci3) * 01 brle (brcr) *** doe21, 20 (t3oer) 00 01, 10, 11 00 01, 10, 11 * pa 6 ddr 0 1 * 01 ** selected function pa 6 input pa 6 output t3oc 2 pa 6 input pa 6 output t3oc 2 txd 3 port port output port port output output note: settings when txd3e = 0 applies in the h8/538. 664
appendix e i/o port block diagrams figure e-1 port 1 block diagram clr qd p1ndr ck clr qd p1nddr ck p1n (n = 0?) port 1 read/write control output multiplexer input multiplexer modes 1 to 6 write to p1ddr write to p1dr read p1dr read external address write to external address reset internal data bus (pdb8 to pdb15) 665
figure e-2 port 2 block diagram clr qd p2ndr ck clr qd p2nddr ck p2n (n = 0?) port 2 read/write control output multiplexer input multiplexer mode 1, 3, 4, 5, or 6 write to p2ddr write to p2dr read p2dr read external address write to external address reset internal data bus (pdb8 to pdb15) internal data bus (pdb0 to pdb7) 666
figure e-3 port 3 block diagram clr qd p3ndr ck clr qd p3nddr ck p3n (n = 0?) port 3 output multiplexer input multiplexer ipu output enable write to p3ddr write to p3dr read p3dr reset internal data bus (pdb8 to pdb15) ipu compare match output (t1oc 1/2/3/4 , t2oc 1/2 ) port 3 direction control 667
figure e-4 port 4 block diagram clr qd p4ndr ck clr qd p4nddr ck p4n (n = 0?) port 4 output multiplexer input multiplexer ipu output enable write to p4ddr write to p4dr read p4dr reset internal data bus (pdb8 to pdb15) ipu compare match output (t4ioc 1/2 , t5ioc 1/2 , t6ioc 1/2 , t7ioc 1/2 ) port 4 direction control ipu input capture enable ipu input capture (t4ioc 1/2 , t5ioc 1/2 , t6ioc 1/2 , t7ioc 1/2 ) 668
figure e-5 port 5 block diagram clr qd p5ndr ck clr qd p5nddr ck p5n (n = 0?) port 5 output multiplexer input multiplexer ipu output enable write to p5ddr write to p5dr read p5dr reset internal data bus (pdb8 to pdb15) ipu compare match output (t1ioc 1/2/3/4 , t2ioc 1/2 , t3ioc 1/2 ) port 5 direction control ipu input capture enable ipu input capture (t1ioc 1/2/3/4 , t2ioc 1/2 , t3ioc 1/2 ) 669
figure e-6 (a) port 6 block diagram (1) (h8/539) 670 clr qd p6 0 dr ck clr qd p6 0 ddr ck p6 0 h8/539 port 6 output multiplexer input multiplexer read p6dr internal data bus (pdb8 to pdb15) port 6 direction control irq 2 input enable edge detector pw 3 output irq 2 input pw 3 e write p6ddr write p6dr
figure e-6 (b) port 6 block diagram (1) (h8/538) 671 clr qd p6ndr ck clr qd p6nddr ck p6 0 h8/538 port 6 input multiplexer write to p6ddr write to p6dr read p6dr reset internal data bus (pdb8 to pdb15) irq 2 input enable irq 2 input edge detector
figure e-7 port 6 block diagram (2) clr qd p6ndr ck clr qd p6nddr ck p6 1 port 6 input multiplexer write to p6ddr write to p6dr read p6dr reset internal data bus (pdb8 to pdb15) irq input enable (irq 3 ) irq input (irq 3 ) edge detector 672
figure e-8 port 6 block diagram (3) clr qd p6ndr ck clr qd p6nddr ck p6n (n = 2?) port 6 input multiplexer write to p6ddr write to p6dr read p6dr reset internal data bus (pdb8 to pdb15) ipu external clock input enable ipu external clock input (tclk 1/2/3 ) 673
figure e-9 port 7 block diagram (1) clr qd p7 0 dr ck clr qd p7 0 ddr ck p7 0 port 7 input multiplexer write to p7ddr write to p7dr read p7dr reset internal data bus (pdb8 to pdb15) irq 0 input enable irq 0 input 674
figure e-10 port 7 block diagram (2) clr qd ck clr qd p7 1 ddr ck p7 1 port 7 input multiplexer write to p7ddr write to p7dr read p7dr reset internal data bus (pdb8 to pdb15) irq 1 input enable irq 1 input adtrg input enable edge detector adtrg input p7 1 dr 675
figure e-11 port 7 block diagram (3) clr qd p7ndr ck clr qd p7nddr ck p7n (n = 2, 4) port 7 port 7 direction control output multiplexer sci transmit enable write to p7ddr write to p7dr read p7dr reset internal data bus (pdb8 to pdb15) input multiplexer sci transmit data output (txd 1 , txd 2 ) 676
figure e-12 port 7 block diagram (4) clr qd p7ndr ck clr qd p7nddr ck p7n (n = 3, 5) port 7 port 7 direction control sci receive enable write to p7ddr write to p7dr read p7dr reset internal data bus (pdb8 to pdb15) input multiplexer sci receive data input (rxd 1 , rxd 2 ) 677
figure e-13 (a) port 7 block diagram (5) (h8/539) clr qd p7ndr ck clr qd p7nddr ck p7n (n = 6, 7) h8/539 port 7 output multiplexer p7ddr write p7dr write p7dr read reset internal data bus (pdb8 to pdb15) input multiplexer port 7 direction control sci serial clock input enable sci serial clock output enable pwm enable pwm output enable sci serial clock output (sck1, sck2) pwm output (pw 1 , pw 2 ) sci serial clock input (sck 1 , sck 2 ) 678
figure e-13 (b) port 7 block diagram (5) (h8/538) clr qd p7ndr ck clr qd p7nddr ck p7n (n = 6, 7) h8/538 port 7 output multiplexer input multiplexer sci serial clock output enable write to p7ddr write to p7dr read p7dr reset internal data bus (pdb8 to pdb15) sci serial clock output (sck 1 , sck 2 ) port 7 direction control sci serial clock input (sck 1 , sck 2 ) sci serial clock input enable 679
figure e-14 port 8 block diagram figure e-15 port 9 block diagram p8n (n = 0?) port 8 a/d converter analog input (an 8 to an 11 ) a/d converter input sampling read p8dr internal data bus (pdb8 to pdb15) p9n (n = 0?) port 9 a/d converter analog input (an 0 to an 7 ) a/d converter input sampling read p9dr internal data bus (pdb8 to pdb15) 680
figure e-16 (a) port a block diagram (1) (h8/539) clr qd pandr ck clr qd panddr ck pan (n = 0?) h8/539 port a port a direction control output multiplexer input multiplexer mode 1, 2, 6, or 7 mode 4 reset internal data bus (pdb8 to pdb15) internal address bus (pab16 to pab19) padr read padr write paddr write mode 3 or 5 software standby mode bus released ipu output enable (t4oc 1/2 , t5oc 1 ) pwm enable pwm output enable ipu compare match output (t4oc 1/2 , t5oc 1 ) pwm output (pw 1/2/3 ) 681
figure e-16 (b) port a block diagram (1) (h8/539) clr qd pandr ck clr qd panddr ck pa 3 h8/539 port a port a direction control output multiplexer input multiplexer mode 1, 2, 6, or 7 mode 4 reset internal data bus (pdb8 to pdb15) internal address bus (pab16 to pab19) padr read padr write paddr write mode 3 or 5 software standby mode bus released ipu output enable (t4oc 1/2 , t5oc 1 ) pwm enable pwm output enable ipu compare match output (t4oc 1/2 , t5oc 1 ) pwm output (pw 1/2/3 ) 682
figure e-16 (c) port a block diagram (1) (h8/538) clr qd pandr ck clr qd panddr ck pan (n = 0?) h8/538 port a port a direction control output multiplexer input multiplexer mode 1, 2, 6, or 7 mode 3 or 5 software standby mode reset internal data bus (pdb8 to pdb15) internal address bus (pab16 to pab19) mode 4 bus released ipu output enable (t4oc 1/2 , t5oc 1/2 ) read padr write to padr write to paddr ipu compare match output (t4oc 1/2 , t5oc 1/2 ) 683
figure e-17 port a block diagram (2) clr qd pa 4 dr ck pa 4 port a port a direction control write to padr read padr reset input multiplexer wait input write to paddr wait input enable clr qd pa 4 ddr ck internal data bus (pdb8 to pdb15) 684
figure e-18 (a) port a block diagram (3) (h8/539) ipu compare match output (t3oc 1 ) pa 5 h8/539 port a port a direction control output multiplexer input multiplexer reset internal data bus (pdb8 to pdb15) read padr write to padr write to paddr modes 1 to 6 bus release enable clr qd pa 5 dr ck clr qd pa 5 ddr ck breq input ipu output enable (t3oc1) rxd3 enable rxd3 input enable 685
figure e-18 (b) port a block diagram (3) (h8/538) ipu compare match output (t3oc 1 ) pa 5 h8/538 port a port a direction control output multiplexer input multiplexer bus release enable reset internal data bus (pdb8 to pdb15) read padr write to padr write to paddr modes 1 to 6 ipu output enable (t3oc 1 ) clr qd pa 5 dr ck clr qd pa 5 ddr ck breq input 686
figure e-19 (a) port a block diagram (4) (h8/539) pa 6 h8/539 port a port a direction control input multiplexer bus release enable reset internal data bus (pdb8 to pdb15) read padr write to padr write to paddr ipu compare match output (t3oc 2 ) modes 1 to 6 back output clr qd pa 6 dr ck clr qd pa 6 ddr ck output multiplexer ipu output enable (t3oc 2 ) txd3 enable txd3 output enable txd 3 output 687
figure e-19 (b) port a block diagram (4) (h8/538) pa 6 h8/538 port a port a direction control output multiplexer input multiplexer bus release enable reset internal data bus (pdb8 to pdb15) read padr write to padr write to paddr ipu compare match output (t3oc 2 ) modes 1 to 6 ipu output enable (t3oc 2 ) back output clr qd pa 6 dr ck clr qd pa 6 ddr ck output multiplexer 688
figure e-20 port b block diagram pbn port b port b direction control input multiplexer reset internal data bus (pdb8 to pdb15) read pbdr write to pbdr write to pbddr mode 1, 3, 5, or 6 clr qd pbndr ck clr qd pbnddr ck output multiplexer software standby mode mode 2 or 4 bus released mode 7 clr qd pbnpcr ck write to pbpcr input pull-up control internal address bus (a8 to a15) (n = 0?) 689
figure e-21 port c block diagram pcn port c port c direction control input multiplexer reset internal data bus (pdb8 to pdb15) read pcdr write to pcdr write to pcddr mode 1, 3, 5, or 6 clr qd pcndr ck clr qd pcnddr ck output multiplexer software standby mode mode 2 or 4 bus released mode 7 clr qd pcnpcr ck write to pbcpcr input pull-up control internal address bus (a0 to a7) (n = 0?) 690
appendix f memory maps f.1 h8/538 h'0000 h'00ff h'0100 vector table external address space on-chip ram (2 kbytes) on-chip registers (384 bytes) h'f67f h'f680 h'fe7f h'fe80 h'ffff h'0000 h'00ff h'0100 vector table external address space on-chip ram (2 kbytes) on-chip registers (384 bytes) on-chip rom (60 kbytes) h'f67f h'f680 h'fe7f h'fe80 h'ffff modes 1 and 6 mode 2 vector table external address space external address space on-chip ram (2 kbytes) on-chip registers (384 bytes) h'00000 h'001ff h'00200 vector table external address space external address space on-chip ram (2 kbytes) on-chip registers (384 bytes) on-chip rom (60 kbytes) h'0f67f h'0f680 h'0fe7f h'0fe80 h'0dfff h'0e000 h'0ffff h'010000 h'1ffff h'20000 h'fffff page 0 page 1 pages 2 to 15 page 0 page 1 pages 2 to 15 h'ee7f h'ee80 modes 3 and 5 mode 4 vector table on-chip ram (2 kbytes) on-chip registers (384 bytes) on-chip rom (60 kbytes) mode 7 expanded minimum modes expanded maximum modes h'00000 h'001ff h'00200 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'010000 h'1ffff h'20000 h'fffff single-chip mode h'0000 h'00ff h'0100 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'ee7f h'ee80 691
f.2 h8/539 692 h'0000 h'00ff h'0100 vector table external address space on-chip ram (4 kbytes) on-chip registers (384 bytes) h'ee7f h'ee80 h'fe7f h'fe80 h'ffff h'0000 h'00ff h'0100 vector table external address space on-chip ram (4 kbytes) on-chip registers (384 bytes) on-chip rom (16 kbytes) h'ee7f h'ee80 h'fe7f h'fe80 h'ffff modes 1 and 6 mode 2 vector table external address space external address space on-chip ram (4 kbytes) on-chip registers (384 bytes) h'00000 h'001ff h'00200 vector table external address space on-chip rom (64 kbytes) on-chip ram (4 kbytes) on-chip registers (384 bytes) on-chip rom (16 kbytes) h'0ee7f h'0ee80 h'0fe7f h'0fe80 h'03fff h'04000 h'0ffff h'10000 h'1ffff h'20000 h'fffff page 0 page 1 pages 2 to 15 page 0 page 1 pages 2 to 15 h'3fff h'4000 modes 3 and 5 mode 4 vector table on-chip rom (64 kbytes) on-chip rom (64 kbytes) on-chip rom (16 kbytes) mode 7 expanded minimum modes expanded maximum modes h'00000 h'001ff h'00200 h'0ee7f h'0ee80 h'0fe7f h'0fe80 h'0ffff h'10000 h'1ffff h'20000 h'fffff single-chip mode h'00000 h'001ff h'00200 h'03fff h'04000 h'0ffff h'10000 h'1ffff h'20000 h'2ffff h'0ee7f h'0ee80 on-chip registers (384 bytes) on-chip ram (4 kbytes) h'0fe7f h'0fe80 on-chip rom (64 kbytes) external address space h'2ffff h'3ffff
appendix g pin states g.1 states of i/o ports table g-1 states of i/o ports program execution hardware software bus mode standby standby sleep release (normal pin name mode reset mode mode mode mode operation) clock t h clock clock clock output output output output rd, as, 1? h t t h t rd, as, hwr, lwr hwr, lwr 7tt t tt p1 7 ?1 0 1? t t t t t d 15 ? 8 7 keep keep keep i/o port p2 7 ?2 0 1, 3?, 6 t t t t t d 7 ? 0 2, 7 keep keep keep i/o port p3 5 ?3 0 1? t t keep * 1 keep keep i/o port p4 7 ?4 0 p5 7 ?5 0 p6 4 ?6 0 p7 7 ?7 0 p8 4 ?8 0 1? t t t t t input port p9 7 ?9 0 pa 6 ?a 4 1? t t keep * 2 keep * 3 keep * 4 i/o port or control input/output pa 3 ?a 0 3, 5 l t t l t a 19 ? 16 1, 2, 4, 6, 7 t keep * 1 keep keep i/o port 1, 3, 5, 6 l t t l t a 15 ? 0 2, 4, 7 t keep keep keep i/o port legend h: high, l: low, t: high-impedance state keep: input pins are in the high-impedance state; output pins maintain their previous state. notes: 1. the on-chip supporting modules are reset, so these pins become input or output pins according to their ddr and dr bits. 2. if pa5 is set for back output, it goes to the high-impedance state. 3. breq can be received, and back is high. 4. back is low. pb 7 ?b 0 pc 7 ?c 0 693
g.2 pin states at reset (1) modes 1 and 6: figure g-1 is a timing diagram for the case in which res goes low during three-state access in mode 1 or 6. as soon as res goes low, all ports are initialized to the input state. as , rd , lwr , and hwr go high, and d 15 to d 0 go to the high-impedance state. a 15 to a 0 are initialized to the low state 1.5 system clock cycles (1.5? after the low level of res is sampled. figure g-1 reset during three-state access (modes 1 and 6) 3-state external access t 1 t 2 t 3 h'0000 res internal reset signal a 15 ? 0 as, rd lwr, hwr d 15 ? 0 i/o ports res is sampled here high impedance high impedance 1.5 694
(2) mode 2: figure g-2 is a timing diagram for the case in which res goes low during three- state access in mode 2. as soon as res goes low, all ports are initialized to the input state. as , rd , lwr , and hwr go high, and d 15 to d 8 go to the high-impedance state. a 15 to a 0 are initialized as soon as res goes low, and become input ports. figure g-2 reset during three-state access (mode 2) 3-state external access res internal reset signal hwr i/o ports high impedance high impedance high impedance t 1 t 2 t 3 a 15 ? 0 as, rd d 15 ? 8 res is sampled here 695
(3) modes 3 and 5: figure g-3 is a timing diagram for the case in which res goes low during three-state access in mode 3 or 5. as soon as res goes low, all ports are initialized to the input state. as , rd , lwr , and hwr go high, and d 15 to d 0 go to the high-impedance state. a 19 to a 0 are initialized to the low state 1.5 system clock cycles (1.5? after the low level of res is sampled. figure g-3 reset during three-state access (modes 3 and 5) 3-state external access t 1 t 2 t 3 h'0000 res internal reset signal a 19 ? 0 as, rd lwr, hwr d 15 ? 0 i/o ports res is sampled here high impedance high impedance 1.5 696
(4) mode 4: figure g-4 is a timing diagram for the case in which res goes low during three- state access in mode 4. as soon as res goes low, all ports are initialized to the input state. as , rd , lwr , and hwr go high, and d 15 to d 0 go to the high-impedance state. a 19 to a 0 are initialized as soon as res goes low, and become input ports. figure g-4 reset during three-state access (mode 4) 3-state external access res internal reset signal lwr, hwr i/o ports high impedance high impedance high impedance t 1 t 2 t 3 a 19 ? 0 as, rd d 15 ? 0 res is sampled here 697
(5) mode 7: figure g-5 is a timing diagram for the case in which res goes low in mode 7. as soon as res goes low, all ports are initialized to the input state. figure g-5 resetting of i/o ports (mode 7) internal reset signal i/o ports res is sampled here high impedance res 698
appendix h package dimensions figure h-1 shows the fp-112 package dimensions of the h8/538 and h8/539. unit: mm figure h-1 package dimensions (fp-112) 699

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