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500 mhz, 32 x 32 buffered video crosspoint switch preliminary technical data AD8117/ad8118 rev. pr a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog dev ices for its use, nor for any infringements of patents or other rights of third p arties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of a nalog devices. trademarks and registered trademarks are the property of their res pective owners. one technology way, p.o. box 9106, norwood, ma 0206 2-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. features large, 32 x 32 high speed, nonblocking switch array g = 1 (AD8117) or g = 2 (ad8118) operation differential or single-ended operation single +5 v supply, or dual 2.5 v supply serial or parallel programming of switch array high impedance output disable allows connection of multiple devices with minimal output bus load excellent video performance 100 mhz 0.1 db gain flatness 0.1% differential gain error (r l = 150 ) 0.1 differential phase error (r l = 150 ) excellent ac performance bandwidth: >500 mhz slew rate: 1,800 v/s low power of 2.5 w low all hostile crosstalk: -75 db @ 5 mhz -40 db @ 500 mhz reset pin allows disabling of all outputs (connected through a capacitor to ground provides power-on reset capability) 304 ball sbga package (31 mm 31 mm) applications routing of high speed signals including: rgb and component video routing compressed video (mpeg, wavelet) data communications functional block diagram output buffer g = +1 192 192 1024 192-bit shift register with 6-bit parallel loading parallel latch decode 32 6:32 decoders 32 clk data in update we reset 32 input pairs a0 data out 32 output pairs a1 a2 ser/par d0 d1 d2 d3 d4 a3 switch matrix input receiver g = +1 AD8117 (ad8118) d5 a4 vocm vneg vpos dgnd vdd 1 0 x 2 2 (g = +2) figure 1. AD8117 g = +1 product description the AD8117/ad8118 is a high speed 32 32 video cro sspoint switch matrix. it offers a 500 mhz bandwidth and sl ew rate of 1800 v/s for high resolution computer graphics (rg b) signal switching. with ?75 db of crosstalk and ?100 db is olation (@ 5 mhz), the AD8117 is useful in many high-speed app lications. the 0.1 db flatness out to 100 mhz makes the AD8117 ideal for composite video switching. the AD8117's 32 independent output buffers can be p laced into a high impedance state for paralleling crosspoint o utputs so that off-channels present minimal loading to an output b us. the AD8117 is available in gain of 1 or 2 (ad8118) for ease of use in back-terminated load applications. it operates as a fully differential device or can be configured for single -ended operation. either a single +5 v supply, or dual 2 .5 v supplies can be used while consuming only 500 ma of idle cur rent with all outputs enabled. the channel switching is perfo rmed via a double-buffered, serial digital control (which can accommodate daisy chaining of several devices) or via a paralle l control allowing updating of an individual output without reprogramming the entire array. the AD8117/ad8118 is packaged in a 304 ball bga pac kage and is available over the extended industrial tempe rature range of ?40c to +85c.
AD8117/ad8118 preliminary technical data rev. pra | page 2 of 32 table of contents AD8117 specifications.............................. ....................................... 3 timing characteristics (serial mode) ............... ............................ 5 timing characteristics (parallel mode) ............. ........................... 6 absolute maximum ratings........................... ................................. 7 thermal resistance ................................. ..................................... 7 power dissipation.................................. ....................................... 7 esd caution........................................ .......................................... 7 pin configurations and function descriptions ....... .................... 8 typical performance characteristics ................ ........................... 15 theory of operation ................................ ...................................... 18 applications....................................... .............................................. 19 programming........................................ ...................................... 19 operating modes.................................... .................................... 20 outline dimensions ................................. ...................................... 31 ordering guide ..................................... ..................................... 31 revision history revision pra: preliminary datasheet
preliminary technical data AD8117/ad8118 rev. pra | page 3 of 32 AD8117 specifications v s = 2.5 v at t a = 25c, g = +1, r l = 100 , differential i/o mode, unless otherwise n oted. table 1. AD8117abpz parameter conditions min typ max unit dynamic performance ?3 db bandwidth 200 mv p-p, r l = 100 >500 mhz 2 v p-p, r l = 100 >420 mhz gain flatness 0.1 db, 200 mv p-p, r l = 100 100 mhz 0.1 db, 2 v p-p, r l = 100 70 mhz propagation delay 2 v p-p, r l =100 1.3 ns settling time 1% , 2 v step, r l = 100 2.5 ns slew rate 2 v step, r l = 100 , peak 1,800 v/s 2 v step, r l = 100 , 10-90% 1,500 v/s noise/distortion performance differential gain error ntsc or pal, r l = 150 or r l = 1k 0.1 % differential phase error ntsc or pal, r l = 150 or r l = 1k 0.1 degrees crosstalk, all hostile ? = 5 mhz C75 db ? = 10 mhz C70 db ? = 100 mhz C50 db ? = 500 mhz C40 db off isolation, input-output ? = 10 mhz, r l = 100 , one channel ?100 db input voltage noise 0.01 mhz to 50 mhz 45 nv/ hz dc performance gain error r l = 100 or 150 1 2 % gain matching no load, channel-channel 0.5 1 % r l = 100 , channel-channel 0.5 1 % output characteristics output impedance dc, enabled 0.1 disabled, differential 30 k output disable capacitance disabled 2 pf output leakage current disabled 1 a output voltage range no load 2 v p-p input characteristics input offset voltage differential 10 mv input voltage range - common mode 4 v p-p input voltage range - differential mode 2 v p-p common-mode rejection ratio ? = 10 mhz C48 db input capacitance any switch configuration 2 pf input resistance differential 5 k input bias current 3 a switching characteristics enable on time 50% update to 1% settling 200 ns switching time, 2 v step 50% settling 20 ns switching transient (glitch) differential 40 mv p-p
AD8117/ad8118 preliminary technical data rev. pra | page 4 of 32 power supplies supply current v pos , outputs enabled, no load 500 ma outputs disabled 210 ma v neg , outputs enabled, no load 500 ma outputs disabled 220 ma d vdd , outputs enabled, no load 1 ma supply voltage range 4.5 to 5.5 v psrr v neg , v pos , ? = 1 mhz C85 db v ocm , ? = 1 mhz C75 db operating temperature range temperature range operating (still air) ? 40 to +85 c ja operating (still air) 15 c/w
preliminary technical data AD8117/ad8118 rev. pra | page 5 of 32 timing characteristics (serial mode) limit parameter symbol min typ max unit serial data setup time t 1 ns clk pulsewidth t 2 ns serial data hold time t 3 ns clk pulse separation t 4 ns clk to update delay t 5 ns update pulsewidth t 6 ns clk to data out valid t 7 ns propagation delay, update to switch on or off n s data load time, clk = 5 mhz, serial mode s clk, update rise and fall times ns reset time ns specifications subject to change without notice. 10 1 0 1 = latched 0 = transparent data out clk data in out7 (d4) out7 (d3) out00 (d0) load data into serial register on falling edge transfer data from serial register to parallel latches during low level t 2 t 4 t 1 t 3 t 7 t 5 t 6 update figure 2. timing diagram, serial mode table 2. logic levels v ih v il v oh v ol i ih i il i oh i ol reset, serpar, clk, data in, update reset, serpar, clk, data in, update data out data out reset, serpar, clk, data in, update reset, serpar, clk, data in, update data out data out 2.0 v min 0.8 v max 2.7 v min 0.5 v max 20 a max C400 a max C400 a max 1 ma min
AD8117/ad8118 preliminary technical data rev. pra | page 6 of 32 timing characteristics (parallel mode) limit parameter symbol min typ max unit parallel data setup time t 1 ns we pulsewidth t 2 ns parallel data hold time t 3 ns we pulse separation t 4 ns we to update delay t 5 ns update pulsewidth t 6 ns propagation delay, update to switch on or off n s we, update rise and fall times ns reset time ns specifications subject to change without notice. t 5 t 6 t 4 t 2 t 1 t 3 10 1 0 1 = latched we d0Cd5 a0Ca4 0 = transparent update figure 3. timing diagram, parallel mode table 3. logic levels v ih v il v oh v ol i ih i il i oh i ol reset, serpar, we, d0, d1, d2, d3, d4, d5, a0, a1, a2, a3, a4, update reset, serpar, we, d0, d1, d2, d3, d4, d5, a0, a1, a2, a3, a4, update data out data out reset, serpar, we, d0, d1, d2, d3, d4, d5, a0, a1, a2, a3, a4, update reset, serpar, we, d0, d1, d2, d3, d4, d5, a0, a1, a2, a3, a4, update data out data out 2.0 v min 0.8 v max disabled disabled 20 a max C400 a max disabled disabled
preliminary technical data AD8117/ad8118 rev. pra | page 7 of 32 absolute maximum ratings table 4. parameter rating analog supply voltage (v pos C v neg ) +6 v digital supply voltage (v dd C d gnd ) +6 v ground potential difference (v neg C d gnd ) +0.5 v to C2.5 v maximum potential difference (v dd C v neg ) +6 v common-mode analog input voltage (v neg C 0.5 v) to (v pos + 0.5 v) differential analog input voltage 2 v digital input voltage vdd output voltage (disabled analog output) (v pos C 1 v) to (v neg + 1 v) output short-circuit duration momentary storage temperature ?65c to +125c operating temperature range ?40c to +85c lead temperature range (soldering 10 sec) 300c junction temperature 150c note stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the o perational section of this specification is not implied. expos ure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance q ja is specified for the worst-case conditions, that i s, a device soldered in a circuit board for surface-mount packa ges. table 5. thermal resistance package type q qq q ja q qq q jc unit bga 15 c/w power dissipation the AD8117/ad8118 are operated with 2.5 v or +5 v supplies and can drive loads down to 100 , resulting in a large range of possible power dissipations. for this rea son, extra care must be taken derating the operating condition s based on ambient temperature. packaged in a 308-lead bga, the AD8117/ad8118 junct ion- to-ambient thermal impedance ( q ja ) is 15 c/w. for long-term reliability, the maximum allowed junction temperatu re of the die should not exceed 150c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. exceed ing a junction temperature of 175c for an extended period can res ult in device failure. the following curve shows the rang e of allowed internal die power dissipations that meet these con ditions over the ?40c to +85c ambient temperature range. when using the table, do not include external load power in th e maximum power calculation, but do include load current drop ped on the die output transistors. 8.0 m a x i m u m p o w e r C w a t t s 7.0 4.0 6.0 5.0 85 75 ambient temperature C c t j = 150 c 65 55 45 35 25 15 figure 4. maximum die power dissipation vs. ambient temperature esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wit hout detection. although this product features proprietary esd protection circuitry, permanent damage m ay occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD8117/ad8118 preliminary technical data rev. pra | page 8 of 32 pin configurations and function descriptions 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a vpos vpos vpos vpos op17 on17 op19 on19 op21 on21 op23 on23 op2 5 on25 op27 on27 op29 on29 op31 on31 vpos vpos vpos a b vpos vpos vpos op16 on16 op18 on18 op20 on20 op22 on22 op24 on2 4 op26 on26 op28 on28 op30 on30 vpos vpos vpos vpos b c vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpo s vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos c d in16 vpos vpos vneg vocm vneg vneg vneg vneg vneg vpos vpos vpo s vneg vneg vneg vneg vneg vocm vneg vpos ip0 vpos d e ip16 in17 vneg vocm vocm vneg in0 ip1 e f in18 ip17 vneg vdd vdd vneg ip2 in1 f g ip18 in19 vneg dgnd dgnd vneg in2 ip3 g h in20 ip19 vneg resetb data_out vneg ip4 in3 h j ip20 in21 vneg updateb clk vneg in4 ip5 j k in22 ip21 vneg web data_in vneg ip6 in5 k l ip22 in23 vpos d5 serbpar vpos in6 ip7 l m in24 ip23 vpos d4 a4 vpos ip8 in7 m n ip24 in25 vpos d3 a3 vpos in8 ip9 n p in26 ip25 vneg d2 a2 vneg ip10 in9 p r ip26 in27 vneg d1 a1 vneg in10 ip11 r t in28 ip27 vneg d0 a0 vneg ip12 in11 t u ip28 in29 vneg vdd vdd vneg in12 ip13 u v in30 ip29 vneg dgnd dgnd vneg ip14 in13 v w ip30 in31 vneg vocm vocm vneg in14 ip15 w y vpos ip31 vpos vneg vocm vneg vneg vneg vneg vneg vpos vpos vpo s vneg vneg vneg vneg vneg vocm vneg vpos vpos in15 y aa vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpo s vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos aa ab vpos vpos vpos vpos on14 op14 on12 op12 on10 op10 on8 op8 on6 op 6 on4 op4 on2 op2 on0 op0 vpos vpos vpos ab ac vpos vpos vpos on15 op15 on13 op13 on11 op11 on9 op9 on7 op7 on5 op5 on3 op3 on1 op1 vpos vpos vpos vpos ac 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p r e l i m i n a r y bottom view p r e l i m i n a r y figure 5. bga bottom view pinout
preliminary technical data AD8117/ad8118 rev. pra | page 9 of 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 a vpos vpos vpos on31 op31 on29 op29 on27 op27 on25 op25 on23 op2 3 on21 op21 on19 op19 on17 op17 vpos vpos vpos vpos a b vpos vpos vpos vpos on30 op30 on28 op28 on26 op26 on24 op24 on2 2 op22 on20 op20 on18 op18 on16 op16 vpos vpos vpos b c vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpo s vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos c d vpos ip0 vpos vneg vocm vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg vneg vneg vocm vneg vpos vpos in16 d e ip1 in0 vneg vocm vocm vneg in17 ip16 e f in1 ip2 vneg vdd vdd vneg ip17 in18 f g ip3 in2 vneg dgnd dgnd vneg in19 ip18 g h in3 ip4 vneg data_out resetb vneg ip19 in20 h j ip5 in4 vneg clk updateb vneg in21 ip20 j k in5 ip6 vneg data_in web vneg ip21 in22 k l ip7 in6 vpos serbpar d5 vpos in23 ip22 l m in7 ip8 vpos a4 d4 vpos ip23 in24 m n ip9 in8 vpos a3 d3 vpos in25 ip24 n p in9 ip10 vneg a2 d2 vneg ip25 in26 p r ip11 in10 vneg a1 d1 vneg in27 ip26 r t in11 ip12 vneg a0 d0 vneg ip27 in28 t u ip13 in12 vneg vdd vdd vneg in29 ip28 u v in13 ip14 vneg dgnd dgnd vneg ip29 in30 v w ip15 in14 vneg vocm vocm vneg in31 ip30 w y in15 vpos vpos vneg vocm vneg vneg vneg vneg vneg vpos vpos vpo s vneg vneg vneg vneg vneg vocm vneg vpos ip31 vpos y aa vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vpos vpos vpo s vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos aa ab vpos vpos vpos op0 on0 op2 on2 op4 on4 op6 on6 op8 on8 op10 on10 o p12 on12 op14 on14 vpos vpos vpos vpos ab ac vpos vpos vpos vpos op1 on1 op3 on3 op5 on5 op7 on7 op9 on9 op11 o n11 op13 on13 op15 on15 vpos vpos vpos ac 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 p r e l i m i n a r y p r e l i m i n a r y top view figure 6. bga top view pinout table 6. ball grid description ball mnemonic description a1 vpos analog positive power supply. a2 vpos analog positive power supply. a3 vpos analog positive power supply. a4 on31 output number 31, negative phase. a5 op31 output number 31, positive phase. a6 on29 output number 29, negative phase. a7 op29 output number 29, positive phase. a8 on27 output number 27, negative phase. a9 op27 output number 27, positive phase. a10 on25 output number 25, negative phase. a11 op25 output number 25, positive phase. a12 on23 output number 23, negative phase. ball mnemonic description a13 op23 output number 23, positive phase. a14 on21 output number 21, negative phase. a15 op21 output number 21, positive phase. a16 on19 output number 19, negative phase. a17 op19 output number 19, positive phase. a18 on17 output number 17, negative phase. a19 op17 output number 17, positive phase. a20 vpos analog positive power supply. a21 vpos analog positive power supply. a22 vpos analog positive power supply. a23 vpos analog positive power supply. b1 vpos analog positive power supply.
AD8117/ad8118 preliminary technical data rev. pra | page 10 of 32 ball mnemonic description b2 vpos analog positive power supply. b3 vpos analog positive power supply. b4 vpos analog positive power supply. b5 on30 output number 30, negative phase. b6 op30 output number 30, positive phase. b7 on28 output number 28, negative phase. b8 op28 output number 28, positive phase. b9 on26 output number 26, negative phase. b10 op26 output number 26, positive phase. b11 on24 output number 24, negative phase. b12 op24 output number 24, positive phase. b13 on22 output number 22, negative phase. b14 op22 output number 22, positive phase. b15 on20 output number 20, negative phase. b16 op20 output number 20, positive phase. b17 on18 output number 18, negative phase. b18 op18 output number 18, positive phase. b19 on16 output number 16, negative phase. b20 op16 output number 16, positive phase. b21 vpos analog positive power supply. b22 vpos analog positive power supply. b23 vpos analog positive power supply. c1 vpos analog positive power supply. c2 vpos analog positive power supply. c3 vpos analog positive power supply. c4 vpos analog positive power supply. c5 vneg analog negative power supply. c6 vneg analog negative power supply. c7 vneg analog negative power supply. c8 vneg analog negative power supply. c9 vneg analog negative power supply. c10 vneg analog negative power supply. c11 vpos analog positive power supply. c12 vpos analog positive power supply. c13 vpos analog positive power supply. c14 vneg analog negative power supply. c15 vneg analog negative power supply. c16 vneg analog negative power supply. c17 vneg analog negative power supply. c18 vneg analog negative power supply. c19 vneg analog negative power supply. c20 vpos analog positive power supply. c21 vpos analog positive power supply. c22 vpos analog positive power supply. c23 vpos analog positive power supply. d1 vpos analog positive power supply. d2 ip0 input number 0, positive phase. d3 vpos analog positive power supply. d4 vneg analog negative power supply. d5 vocm output common-mode reference supply. ball mnemonic description d6 vneg analog negative power supply. d7 vneg analog negative power supply. d8 vneg analog negative power supply. d9 vneg analog negative power supply. d10 vneg analog negative power supply. d11 vpos analog positive power supply. d12 vpos analog positive power supply. d13 vpos analog positive power supply. d14 vneg analog negative power supply. d15 vneg analog negative power supply. d16 vneg analog negative power supply. d17 vneg analog negative power supply. d18 vneg analog negative power supply. d19 vocm output common-mode reference supply. d20 vneg analog negative power supply. d21 vpos analog positive power supply. d22 vpos analog positive power supply. d23 in16 input number 16, negative phase. e1 ip1 input number 1, positive phase. e2 in0 input number 0, negative phase. e3 vneg analog negative power supply. e4 vocm output common-mode reference supply. e20 vocm output common-mode reference supply. e21 vneg analog negative power supply. e22 in17 input number 17, negative phase. e23 ip16 input number 16, positive phase. f1 in1 input number 1, negative phase. f2 ip2 input number 2, positive phase. f3 vneg analog negative power supply. f4 vdd logic positive power supply. f20 vdd logic positive power supply. f21 vneg analog negative power supply. f22 ip17 input number 17, positive phase. f23 in18 input number 18, negative phase. g1 ip3 input number 3, positive phase. g2 in2 input number 2, negative phase. g3 vneg analog negative power supply. g4 dgnd logic negative power supply. g20 dgnd logic negative power supply. g21 vneg analog negative power supply. g22 in19 input number 19, negative phase. g23 ip18 input number 18, positive phase. h1 in3 input number 3, negative phase. h2 ip4 input number 4, positive phase. h3 vneg analog negative power supply. h4 data_out control pin: serial data out. h20 resetb control pin: second rank data reset. h21 vneg analog negative power supply. h22 ip19 input number 19, positive phase. h23 in20 input number 20, negative phase.
preliminary technical data AD8117/ad8118 rev. pra | page 11 of 32 ball mnemonic description j1 ip5 input number 5, positive phase. j2 in4 input number 4, negative phase. j3 vneg analog negative power supply. j4 clk control pin: serial data clock. j20 updateb control pin: second rank write strobe. j21 vneg analog negative power supply. j22 in21 input number 21, negative phase. j23 ip20 input number 20, positive phase. k1 in5 input number 5, negative phase. k2 ip6 input number 6, positive phase. k3 vneg analog negative power supply. k4 data_in control pin: serial data in. k20 web control pin: first rank write strobe. k21 vneg analog negative power supply. k22 ip21 input number 21, positive phase. k23 in22 input number 22, negative phase. l1 ip7 input number 7, positive phase. l2 in6 input number 6, negative phase. l3 vpos analog positive power supply. l4 serbpar control pin: serial/parallel mode select. l20 d5 control pin: input address bit 5. l21 vpos analog positive power supply. l22 in23 input number 23, negative phase. l23 ip22 input number 22, positive phase. m1 in7 input number 7, negative phase. m2 ip8 input number 8, positive phase. m3 vpos analog positive power supply. m4 a4 control pin: output address bit 4. m20 d4 control pin: input address bit 4. m21 vpos analog positive power supply. m22 ip23 input number 23, positive phase. m23 in24 input number 24, negative phase. n1 ip9 input number 9, positive phase. n2 in8 input number 8, negative phase. n3 vpos analog positive power supply. n4 a3 control pin: output address bit 3. n20 d3 control pin: input address bit 3. n21 vpos analog positive power supply. n22 in25 input number 25, negative phase. n23 ip24 input number 24, positive phase. p1 in9 input number 9, negative phase. p2 ip10 input number 10, positive phase. p3 vneg analog negative power supply. p4 a2 control pin: output address bit 2. p20 d2 control pin: input address bit 2. p21 vneg analog negative power supply. p22 ip25 input number 25, positive phase. p23 in26 input number 26, negative phase. r1 ip11 input number 11, positive phase. r2 in10 input number 10, negative phase. ball mnemonic description r3 vneg analog negative power supply. r4 a1 control pin: output address bit 1. r20 d1 control pin: input address bit 1. r21 vneg analog negative power supply. r22 in27 input number 27, negative phase. r23 ip26 input number 26, positive phase. t1 in11 input number 11, negative phase. t2 ip12 input number 12, positive phase. t3 vneg analog negative power supply. t4 a0 control pin: output address bit 0. t20 d0 control pin: input address bit 0. t21 vneg analog negative power supply. t22 ip27 input number 27, positive phase. t23 in28 input number 28, negative phase. u1 ip13 input number 13, positive phase. u2 in12 input number 12, negative phase. u3 vneg analog negative power supply. u4 vdd logic positive power supply. u20 vdd logic positive power supply. u21 vneg analog negative power supply. u22 in29 input number 29, negative phase. u23 ip28 input number 28, positive phase. v1 in13 input number 13, negative phase. v2 ip14 input number 14, positive phase. v3 vneg analog negative power supply. v4 dgnd logic negative power supply. v20 dgnd logic negative power supply. v21 vneg analog negative power supply. v22 ip29 input number 29, positive phase. v23 in30 input number 30, negative phase. w1 ip15 input number 15, positive phase. w2 in14 input number 14, negative phase. w3 vneg analog negative power supply. w4 vocm output common-mode reference supply. w20 vocm output common-mode reference supply. w21 vneg analog negative power supply. w22 in31 input number 31, negative phase. w23 ip30 input number 30, positive phase. y1 in15 input number 15, negative phase. y2 vpos analog positive power supply. y3 vpos analog positive power supply. y4 vneg analog negative power supply. y5 vocm output common-mode reference supply. y6 vneg analog negative power supply. y7 vneg analog negative power supply. y8 vneg analog negative power supply. y9 vneg analog negative power supply. y10 vneg analog negative power supply. y11 vpos analog positive power supply. y12 vpos analog positive power supply.
AD8117/ad8118 preliminary technical data rev. pra | page 12 of 32 ball mnemonic description y13 vpos analog positive power supply. y14 vneg analog negative power supply. y15 vneg analog negative power supply. y16 vneg analog negative power supply. y17 vneg analog negative power supply. y18 vneg analog negative power supply. y19 vocm output common-mode reference supply. y20 vneg analog negative power supply. y21 vpos analog positive power supply. y22 ip31 input number 31, positive phase. y23 vpos analog positive power supply. aa1 vpos analog positive power supply. aa2 vpos analog positive power supply. aa3 vpos analog positive power supply. aa4 vpos analog positive power supply. aa5 vneg analog negative power supply. aa6 vneg analog negative power supply. aa7 vneg analog negative power supply. aa8 vneg analog negative power supply. aa9 vneg analog negative power supply. aa10 vneg analog negative power supply. aa11 vpos analog positive power supply. aa12 vpos analog positive power supply. aa13 vpos analog positive power supply. aa14 vneg analog negative power supply. aa15 vneg analog negative power supply. aa16 vneg analog negative power supply. aa17 vneg analog negative power supply. aa18 vneg analog negative power supply. aa19 vneg analog negative power supply. aa20 vpos analog positive power supply. aa21 vpos analog positive power supply. aa22 vpos analog positive power supply. aa23 vpos analog positive power supply. ab1 vpos analog positive power supply. ab2 vpos analog positive power supply. ab3 vpos analog positive power supply. ab4 op0 output number 0, positive phase. ab5 on0 output number 0, negative phase. ab6 op2 output number 2, positive phase. ball mnemonic description ab7 on2 output number 2, negative phase. ab8 op4 output number 4, positive phase. ab9 on4 output number 4, negative phase. ab10 op6 output number 6, positive phase. ab11 on6 output number 6, negative phase. ab12 op8 output number 8, positive phase. ab13 on8 output number 8, negative phase. ab14 op10 output number 10, positive phase. ab15 on10 output number 10, negative phase. ab16 op12 output number 12, positive phase. ab17 on12 output number 12, negative phase. ab18 op14 output number 14, positive phase. ab19 on14 output number 14, negative phase. ab20 vpos analog positive power supply. ab21 vpos analog positive power supply. ab22 vpos analog positive power supply. ab23 vpos analog positive power supply. ac1 vpos analog positive power supply. ac2 vpos analog positive power supply. ac3 vpos analog positive power supply. ac4 vpos analog positive power supply. ac5 op1 output number 1, positive phase. ac6 on1 output number 1, negative phase. ac7 op3 output number 3, positive phase. ac8 on3 output number 3, negative phase. ac9 op5 output number 5, positive phase. ac10 on5 output number 5, negative phase. ac11 op7 output number 7, positive phase. ac12 on7 output number 7, negative phase. ac13 op9 output number 9, positive phase. ac14 on9 output number 9, negative phase. ac15 op11 output number 11, positive phase. ac16 on11 output number 11, negative phase. ac17 op13 output number 13, positive phase. ac18 on13 output number 13, negative phase. ac19 op15 output number 15, positive phase. ac20 on15 output number 15, negative phase. ac21 vpos analog positive power supply. ac22 vpos analog positive power supply. ac23 vpos analog positive power supply.
preliminary technical data AD8117/ad8118 rev. pra | page 13 of 32 table 7. operation truth table update clk data in data out we reset ser/par operation/comment x x x x x 0 x asynchronous reset. all outputs are disabled. x x x x x 1 x tbd x x x x x 1 x tbd x x x x x 1 x tbd x x x x x 1 x tbd x x x x x 1 x tbd figure 7. logic diagram
AD8117/ad8118 preliminary technical data rev. pra | page 14 of 32 opn,onn opn onn 0.4pf 30k 3.4pf 3.4pf inn 2500 w ww w 2538 w ww w 2538 w ww w ipn 2500 w ww w 2500 w ww w 0.3pf 1.3pf 1.3pf a. AD8117/ad8118 enabled output (see also esd protection map) b. AD8117/ad8118 disabled output (see also esd protection map) c. AD8117 receiver (see also esd protection map) inn 2500 w ww w 5075 w ww w 5075 w ww w ipn 2500 w ww w 2500 w ww w 0.3pf 1.3pf 1.3pf inn 2500 w ww w i p n 2500 w ww w 0.3pf 1.3pf 1.3pf inn 1.6pf i p n 3.33k w ww w AD8117 g=+1 3.76k w ww w ad8118 g=+2 d. ad8118 receiver (see also esd protection map) e. AD8117/ad8118 receiver simplified equivalent circuit when driving differentially f. AD8117/ad8118 receiver simplified equivalent circuit when driving single-ended vocm vneg reset dgnd 25k w ww w 1k w ww w v d d dgnd 1k w ww w clk, ser/par, we, update, data in, a[4:0], d[4:0] g. vocm input (see also esd protection map) h. rese t input (see also esd protection map) i. logic inpu t (see also esd protection map) dgnd data out v d d vneg v p o s dgnd v d d ipn, inn, opn, onn, vocm clk, reset, ser/par, we, update, data in, data out, a[4:0], d[5:0] j. logic output (see also esd protection map) k. es d protection map figure 8. i/o schematics
preliminary technical data AD8117/ad8118 rev. pra | page 15 of 32 typical performance characteristics frequency (hz) g a i n ( d b ) 1 m 300 k 10 m 100 m 1 g 8 g 0 -2 -4 2 4 -10 -12 -14 -8 -6 -16 v out = 1 v pp single-ended figure 9. AD8117 large signal frequency response differential in/out frequency (hz) c m r r ( d b ) 1 m 300 k 10 m 100 m 1 g 2 g -20 -30 -10 0 -50 -60 -40 -70 figure 10. AD8117 common-mode rejection frequency (hz) n o i s e s p e c t r a l d e n s i t y ( n v / r t h z ) 10 k 1 k 100 k 1 m 140 100 120 80 0 60 40 20 differential out figure 11. AD8117 noise spectral density, differen tial mode frequency (hz) c r o s s t a l k ( d b ) 1 m 300 k 10 m 100 m 1 g 2 g -20 0 -60 -40 -80 -100 differential in/out figure 12. AD8117 crosstalk, one adjacent channel, differential mode frequency (hz) c r o s s t a l k ( d b ) 1 m 300 k 10 m 100 m 1 g 2 g -20 0 -60 -40 -80 -100 single-ended in/out figure 13. AD8117 crosstalk, one adjacent channel, single-ended mode frequency (hz) c r o s s t a l k ( d b ) 1 m 300 k 10 m 100 m 1 g 2 g -20 0 -60 -40 -80 -100 differential in/out figure 14. AD8117 crosstalk, all-hostile, differen tial mode
AD8117/ad8118 preliminary technical data rev. pra | page 16 of 32 frequency (hz) c r o s s t a l k ( d b ) 1 m 300 k 10 m 100 m 1 g 2 g -20 0 -60 -40 -80 -100 single-ended in/out figure 15. AD8117 crosstalk, all-hostile, single-e nded mode frequency (hz) c r o s s t a l k ( d b ) 1 m 300 k 10 m 100 m 1 g 2 g -20 0 -60 -40 -80 -100 differential in/out figure 16. AD8117 crosstalk, off-isolation, differ ential mode frequency (hz) c r o s s t a l k ( d b ) 1 m 300 k 10 m 100 m 1 g 2 g -20 0 -60 -40 -80 -100 single-ended in/out figure 17. AD8117 crosstalk, off-isolation, single -ended mode frequency (hz) i n p u t i m p e d a n c e ( o h m s ) 1 m 300 k 10 m 100 m 1 g 5k 3k 4k 2k 0 1k differential in figure 18. AD8117 input impedance, differential mo de frequency (hz) i n p u t i m p e d a n c e ( o h m s ) 1 m 300 k 10 m 100 m 1 g 3.5k 2.5k 3.0k 2.0k 0 1.5k 1.0k 0.5k single-ended in figure 19. AD8117 input impedance, single-ended mo de frequency (hz) o u t p u t i m p e d a n c e ( o h m s ) 1 m 100 k 10 m 100 m 1 g 25k 3 0 k 15k 20k 10k 0 5k differential out figure 20. AD8117 output impedance, disabled, diff erential mode
preliminary technical data AD8117/ad8118 rev. pra | page 17 of 32 frequency (hz) o u t p u t i m p e d a n c e ( o h m s ) 1 m 300 k 10 m 100 m 1 g 25k 15k 20k 10k 0 5k single-ended out figure 21. AD8117 output impedance, disabled, sing le-ended mode
AD8117/ad8118 preliminary technical data rev. pra | page 18 of 32 theory of operation the AD8117 is a fully-differential crosspoint array with 32 outputs, each of which can be connected to any one of 32 inputs. organized by output row, 32 switchable inp ut transconductance stages are connected to each outpu t buffer to form 32-to-1 multiplexers. there are 32 of these m ultiplexers, each with its inputs wired in parallel, for a total array of 1,024 transconductance stages forming a multicast-capable crosspoint switch. decoding logic for each output selects one (or none ) of the transconductance stages to drive the output stage. the enabled transconductance stage drives the output stage, and feedback forms a closed-loop amplifier with a differential g ain of one (the difference between the output voltages is equal to the difference between the input voltages). a second feedback loo p controls the common-mode output level, forcing the average o f the differential output voltages to match the voltage o n the vocm reference pin. although each output has an indepen dent common-mode control loop, the vocm reference is com mon for the entire chip, and as such needs to be driven with a low impedance to avoid crosstalk. each differential input to the AD8117 is buffered b y a receiver. the purpose of this receiver is to provide an exten ded input common-mode range, and to remove this common-mode f rom the signal chain. like the output multiplexers, t he input receiver has both a differential loop and a common- mode control loop. a mask-programmable feedback network sets the closed-loop differential gain. for the AD8117, thi s differential gain is one, and for the ad8118, this is a differen tial gain of two. the receiver has an input stage that does not respond to the common-mode of the signal. this architecture, along with the attenuating feedback network, allows the user t o apply input voltages that extend from rail-to-rail. excess dif ferential loop gain-bandwidth product reduces the effect of the cl osed-loop gain on the bandwidth of the device. the output stage of the AD8117 is designed for low differential gain and phase error when driving composite video s ignals. it also provides slew current for fast pulse response when driving component video signals. unlike many multiplexer d esigns, these requirements are balanced such that large sig nal bandwidth is very similar to small signal bandwidth . the design load is 150 l, but provisions are made to dr ive loads as low as 75 l so long as on-chip power dissipation li mits are not exceeded. the outputs of the AD8117 can be disabled to minimi ze on- chip power dissipation. when disabled, there is on ly a common-mode feedback network of 30kl between the differential outputs. this high impedance allows m ultiple ics to be bussed together without additional buffering. care must be taken to reduce output capacitance, which will r esult in more overshoot and frequency-domain peaking. a series o f internal amplifiers drive internal nodes such that a wide-ba nd high- impedance is presented at the disabled output, even while the output bus is under large signal swings. when the outputs are disabled and driven externally, the voltage applied to them should not exceed the valid output swing range for the AD8117 in order to keep these internal amplifiers in their linear range of operation. applying excess differential voltages t o the disabled outputs can cause damage to the AD8117 and should b e avoided (see the absolute maximum ratings section o f this datasheet for guidelines). the connection of the AD8117 is controlled by a fle xible ttl compatible logic interface. either parallel or ser ial loading into a first rank of latches preprograms each output. a global update signal moves the programming data into the s econd rank of latches, simultaneously updating all output s. in serial mode, a serial-out pin allows devices to be daisy c hained together for single-pin programming of multiple ics . a power- on reset pin is available to avoid bus conflicts by disabling all outputs. this power-on reset clears the second ran k of latches, but does not clear the first rank of latches. in p arallel mode, to quickly clear the first rank, a broadcast parallel programming feature is available. in serial-mode, pre-programm ing individual inputs is not possible and the entire sh ift register needs to be flushed. the AD8117 can operate on a single +5 v supply, pow ering both the signal path (with the vpos/vneg supply pin s), and the control logic interface (with the vdd/dgnd supp ly pins). but in order to easily interface to ground-referenc ed video signals, split supply operation is possible with 2.5 v supplies. in this case, a flexible logic interface allows the control logic supplies (vdd/dgnd) to be run off +2 v/0 v to +3.3 v/0 v while the core remains on split supplies. addition al flexibility in the analog output common-mode level facilitates unequal split supplies. if +3 v/C2 v supplies to +2 v/C3 v s upplies are desired, the vocm pin can still be set to 0 v for g round- referenced video signals.
preliminary technical data AD8117/ad8118 rev. pra | page 19 of 32 applications programming the AD8117/ad8118 have two options for changing the programming of the crosspoint matrix. in the first option a serial word of 192 bits can be provided that will u pdate the entire matrix each time. the second option allows f or changing a single outputs programming via a parallel interf ace. the serial option requires fewer signals, but more time (clock cycles) for changing the programming, while the par allel programming technique requires more signals, but ca n change a single output at a time and requires fewer clock cycles to complete programming. serial programming description the serial programming mode uses the device pins cl k, data in, update and ser/par. the first step is to a ssert a low on ser/par in order to enable the serial progra mming mode. the parallel clock, we should be held high d uring the entire serial programming operation. the update signal should be high during the time that data is shifted into the devices serial port. although the data will still shift in when update is low, the transparent, asynchronous latches will allow the shifting data to reach the m atrix. this will cause the matrix to try to update to every intermed iate state as defined by the shifting data. the data at data in is clocked in at every falling edge of clk. a total of 192 bits must be shifted in to complete the programming. for each of the 32 outputs, there are five bits (d0Cd4) that determine the source of its input follo wed by one bit (d5) that determines the enabled state of the o utput. if d5 is low (output disabled), the four associated bits (d0 Cd4) do not matter, because no input will be switched to th at output. the most-significant-output-address data is shifted in first, then following in sequence until the least-signific ant-output- address data is shifted in. at this point update can be taken low, which will cause the programming of the device according to the data that was just shifted in. the update latches are asynchronous and when update is low they are transparent. if more than one AD8117 device is to be serially pr ogrammed in a system, the data out signal from one device ca n be connected to the data in of the next device to form a serial chain. all of the clk, update, and ser/par pins sho uld be connected in parallel and operated as described abo ve. the serial data is input to the data in pin of the firs t device of the chain, and it will ripple through to the last. ther efore, the data for the last device in the chain should come at the beginning of the programming sequence. the length of the program ming sequence will be 192 bits times the number of devic es in the chain. parallel programming description when using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. in fact, parallel programming allows the mo dification of a single output at a time. since this takes only one we/update cycle, significant time savings can be re alized by using parallel programming. one important consideration in using parallel progr amming is that the reset signal does not reset all registers in the AD8117. when taken low, the reset signal will only set each output to the disabled state. this is helpful during power- up to ensure that two parallel outputs will not be active at the same time. after initial power-up, the internal registers in t he device will generally have random data, even though the reset signal has been asserted. if parallel programming is used to p rogram one output, then that output will be properly programme d, but the rest of the device will have a random program state depending on the internal register content at power-up. there fore, when using parallel programming, it is essential that al l outputs be programmed to a desired state after power-up. this will ensure that the programming matrix is always in a known st ate. from then on, parallel programming can be used to modify a single output or more at a time. in similar fashion, if update is taken low after in itial power-up, the random power-up data in the shift reg ister will be programmed into the matrix. therefore, in order to prevent the crosspoint from being programmed into an unknow n state, do not apply a low logic level to update after powe r is initially applied. programming the full shift regis ter one time to a desired state, by either serial or parallel progr amming after initial power-up, will eliminate the possibility of programming the matrix to an unknown state. to change an outputs programming via parallel prog ramming, ser/par and update should be taken high. the serial programming clock, clk, should be left high during parallel programming. the parallel clock, we, should start in the high state. the 5-bit address of the output to be p rogrammed should be put on a0Ca4. the first five data bits (d 0Cd4) should contain the information that identifies the input that gets programmed to the output that is addressed. th e sixth data bit (d5) will determine the enabled state of the ou tput. if d5 is low (output disabled), then the data on d0Cd4 does not matter.
AD8117/ad8118 preliminary technical data rev. pra | page 20 of 32 after the desired address and data signals have bee n established, they can be latched into the shift reg ister by a high to low transition of the we signal. the matrix will not be programmed, however, until the update signal is tak en low. it is thus possible to latch in new data for severa l or all of the outputs first via successive negative transitions o f we while update is held high, and then have all the new data take effect when update goes low. this is the technique that should be used when programming the device for the first time after power-up when using parallel programming. reset when powering up the AD8117, it is usually desirabl e to have the outputs come up in the disabled state. the rese t pin, when taken low, will cause all outputs to be in the disabled state. however, the reset signal does not reset all registers in the AD8117. this is important when operating in the parallel programming mode. please refer to that section for information about programming internal registers af ter power- up. serial programming will program the entire matr ix each time, so no special considerations apply. since the data in the shift register is random afte r power-up, it should not be used to program the matrix, or the ma trix can enter unknown states. to prevent this, do not apply a logic low signal to update initially after power-up. the shift register should first be loaded with the desired data, and t hen update can be taken low to program the device. the reset pin has a 20 kl pull-up resistor to vdd t hat can be used to create a simple power-up reset circuit. a c apacitor from reset to ground will hold reset low for some time while the rest of the device stabilizes. the low condition wi ll cause all the outputs to be disabled. the capacitor will then cha rge through the pull-up resistor to the high state, thus allowi ng full programming capability of the device. broadcast the AD8117 logic interface has a broadcast mode, in which all first rank latches can be simultaneously parallel-p rogrammed to the same data in one write-cycle. this is especial ly useful in clearing random first rank data after power-up. to access the broadcast mode, the part is parallel-programmed usi ng the device pins we, a0Ca4, d0Ca5 and update. the only difference is that the ser/par pin is held low, as if serial programming. by holding clk high, no serial clocki ng will occur, and instead the we can be used to clock all first rank latches in the chip at once. operating modes the AD8117/ad8118 has fully-differential inputs and outputs. the inputs and outputs can also be operated in a si ngle-ended fashion. this presents several options for circuit configurations that will require different gains and treatment of terminations, if they are used. differential input the AD8117/ad8118 has differential input receivers. these receivers allow the user to drive the inputs with a differential signal with an uncertain common-mode voltage, such as from a remote source over twisted pair. the receivers wil l respond only to the difference in input voltages, and will restore a common-mode voltage suitable for the internal signa l path. noise or crosstalk that is present in both inputs w ill be rejected by the input stage, as specified by its common-mode rejection ratio (cmrr). differential operation offers a grea t noise benefit for signals that are propagated over distan ce in a noisy environment. rcvr r g out- out+ in+ vocm in- r g r f r f to switch matrix figure 22. input receiver equivalent circuit the circuit configuration used by the differential input receivers is similar to that of several analog devices genera l-purpose differential amplifiers, such as the ad8131. it is a voltage- feedback amplifier with internal gain setting resis tors. the arrangement of feedback makes the differential inpu t impedance appear to be 5 kl across the inputs. this impedance will create a small differential ter mination error if the user does not account for the 5 kl par allel element, although this error will be less than 1% in most ca ses. additionally, the source impedance driving the ad81 17 appears in parallel with the internal gain-setting resistors, such that there may be a gain error for some values of s ource resistance. the AD8117/ad8118 are adjusted such th at their gains will be correct when driven by a back-termina ted 75 l source impedance at each input phase (37.5 l effect ive impedance to ground at each input pin, or 75 l diff erential source impedance across pairs of input pins). if a different source impedance is presented, the differential gai n of the AD8117/ad8118 can be calculated by r in, dm = 2 r g = 5 kl g dm = r f r g + r s v out, dm v in, dm =
preliminary technical data AD8117/ad8118 rev. pra | page 21 of 32 where r g is 2.5 kl, r s is the user single-ended source resistance (such as 37.5 l for a back-terminated 75 l source), and r f is 2.538 kl for the AD8117 and 5.075 kl for the ad8118 . in the case of the AD8117, this is in the case of the ad8118, this is when operating with a differential input, care must be taken to keep the common-mode, or average, of the input volt ages within the linear operating range of the AD8117/ad8 118 receiver. this common-mode range can extend rail-t o-rail, provided the differential signal swing is small eno ugh to avoid forward biasing the esd diodes (it is safest to kee p the common-mode plus differential signal excursions wit hin the supply voltages of the part). the differential output of the AD8117/ad8118 receiv er is linear for a peak of 1.4v of output voltage differe nce (1.4 v peak input difference for the AD8117, and 0.7 v pea k input difference for the ad8118). taking the output diff erentially, using the two output phases, this allows 2.8 v pp of linear output signal swing. beyond this level, the signal path w ill saturate and limit the signal swing. this is not a desired oper ation, as the supply current will increase and the signal path wi ll be slow to recover from clipping. the absolute maximum allowe d differential input signal is limited by long-term r eliability of the input stage. the limits in the absolute maximum ra tings section of the datasheet should be observed in orde r to avoid degrading device performance permanently. 50 w ww w 50 w ww w opn AD8117 onn rcvr ipn inn figure 23. example of input driven differentially ac-coupling it is possible to ac-couple the inputs of the ad811 7/ad8118 receiver. this is simplified in that bias current does not need to be supplied externally. a capacitor in series with the inputs to the AD8117/ad8118 will create a high-pass filter wi th the input impedance of the device. this capacitor will need to be sized such that the corner frequency is low enough for fr equencies of interest. single-ended input the AD8117/ad8118 input receiver can also be driven single- ended (unbalanced). from the standpoint of the rec eiver, there is very little difference between signals applied p ositive and negative in two phases to the input pair, versus a signal applied to one input only with the other input held at a co nstant potential. one small difference is that the common -mode between the input pins will be changing if only one input is moving, and there is a very small common-mode to di fferential conversion gain in the receiver that will add an ad ditional gain error to the output (see the common-mode rejection ratio specifications for the input stage). for low frequ encies, this gain error is negligible. the common-mode rejectio n ratio degrades with increasing frequency. when operating the AD8117/ad8118 receiver single-en dedly, the observed input resistance at each input pin is higher than in the differential input case, due to a fraction of t he receiver internal output voltage appearing as a common-mode signal on its input terminals, bootstrapping the voltage on t he input resistance. this single-ended input resistance can be calculated by the formula where r g is 2.5 kl, r s is the user single-ended source resistance (such as 37.5 l for a back-terminated 75 l source), and r f is 2.538 kl for the AD8117 and 5.075 kl for the ad8118 . in most cases, a single-ended input signal will be referred to mid-supply, typically ground. in this case, the un driven differential input could be connected to ground. f or best dynamic performance and lowest offset voltage, this unused input should be terminated with an impedance matchi ng the driven input, instead of being directly shorted to ground. due to the differential feedback of the receiver, there is high- frequency signal current in the undriven input and it should be treated as a signal line in the board design. r in = r g + r s 1 C r f 2 ( r g + r s + r f ) + rf g dm = 5.075 kl 2.5 kl + r s g dm = 2.538 kl 2.5 kl + r s
AD8117/ad8118 preliminary technical data rev. pra | page 22 of 32 75 w ww w 75 w ww w ( (( ( or 37.5 w ww w) )) ) opn AD8117 onn rcvr ipn inn figure 24. example of input driven single-ended differential output benefits of differential operation the AD8117/ad8118 has a fully-differential switch c ore, with differential outputs. the two output voltages move in opposite directions, with a differential feedback loop maint aining a fixed output stage differential gain of +1 (the different overall signal path gains between the AD8117 and ad8118 are set in the input stage for best signal-to-noise ratio). this differential output stage provides a benefit of crosstalk-cancel ing due to parasitic coupling from one output to another being equal and out of phase. additionally, if the output of the d evice is utilized in a differential design, noise, crosstalk and offs et voltages generated on-chip that are coupled equally into bot h outputs will be cancelled by the common-mode rejection rati o of the next device in the signal chain. by utilizing the AD8117/ad8118 outputs in a differential application , the best possible noise and offset specifications can be rea lized. differential gain the specified signal path gain of the AD8117/ad8118 refers to its differential gain. for the AD8117, the gain of +1 means that the difference in voltage between the two output te rminals is equal to the difference applied between the two inp ut terminals. for the ad8118, the ratio of output difference volt age to applied input difference voltage is +2. the common-mode, or average voltage of the pair of output signals is set by the voltage on the vocm pin. thi s voltage is typically set to mid-supply (often ground), but may be moved approximately 0.5 v in order to accommodate cases where the desired output common-mode voltage may not be m id- supply (as in the case of unequal split supplies). adjusting vocm beyond 0.5 v can limit differential swing in ternally below the specifications on the datasheet. regardless of the differential gain of the device, the common- mode gain for the AD8117 and ad8118 is +1 to the ou tput. this means that the common-mode of the output volta ges will directly follow the reference voltage applied to th e vocm input. the vocm reference is a high-speed signal input, co mmon to all output stages on the device. it requires only small amounts of bias current, but noise appearing on this pin wi ll be buffered to the outputs of all the output stages. as such, the vocm node should be connected to a low-noise, low-impeda nce voltage to avoid being a source of noise, offset an d crosstalk in the signal path. termination the AD8117/ad8118 is designed to drive 150 l on eac h output (or an effective 300 l differential) while m eeting datasheet specifications, but the output stage is c apable of supplying the current to drive 100 l loads (200 l d ifferential) over the specified operating temperature range. if care is taken to observe the maximum power derating curves, the o utput stage can drive 75 l loads with slightly reduced sl ew rate and bandwidth (an effective 150 l differential load). termination at the load end is recommended for best signal integrity. this load termination is often a resist or to a ground reference on each individual output. by terminatin g to the same voltage level that drives the vocm reference, the power dissipation due to dc termination current will be r educed. in differential signal paths, it is often desirable to terminate differentially, with a single resistor across the d ifferential outputs at the load end. this is acceptable for th e AD8117/ad8118, but when the device outputs are plac ed in a disabled state, a small amount of dc bias current i s required if the output is to present as a high-impedance over a n excursion of output bus voltages. if the AD8117/ad8118 disab led outputs are floated (or simply tied together by a resistor) , internal nodes will saturate and an increase in disabled output cu rrent may be observed. for best pulse response, it is often desirable to p lace a series resistor in each output to match the characteristic impedance and termination of the output trace or cable. this is known as back-termination, and helps shorten settling time b y terminating reflected signals when driving a load t hat is not accurately terminated at the load end. a side-effe ct of back- termination is an attenuation of the output signal by a factor of two. in this case, a gain of two is usually necess ary somewhere in the signal path to restore the signal. 50 w ww w 50 w ww w 100 w ww w opn AD8117 onn
preliminary technical data AD8117/ad8118 rev. pra | page 23 of 32 figure 25. example of back-terminated differential load single-ended output usage the AD8117/ad8118 output pairs can be used single-e ndedly, taking only one output and not using the second. t his is often desired to reduce the routing complexity in the des ign, or because a single-ended load is being driven directl y. this mode of operation will produce good results, but has som e shortcomings when compared to taking the output differentially. when observing the single-ended ou tput, noise that is common to both outputs appears in the outpu t signal. this includes thermal noise in the chip biasing, as well as crosstalk that coupled into the signal path. this component noise and crosstalk is equal in both outputs, and a s such can be ignored by a differential receiver with high common -mode rejection ratio. but when taking the output single -ended, this noise is present with respect to the ground (or voc m) reference and is not rejected. when observing the output single-ended, the distrib ution of offset voltages will appear greater. in the differ ential case, the difference between the outputs when the difference between the inputs is zero will be a small differential offset. this offset of created from mismatches in components of the signal path which must be corrected by the finite differential loop gain of the device. in the single-ended case, this differe ntial offset is still observed, but an additional offset component is also relevant. this additional component is the common- mode offset, which is a difference between the average o f the outputs and the vocm reference. this offset is created by mismatches that affect the signal path in a common-mode manner , and is corrected by the finite common-mode loop gain of th e device. a differential receiver would reject this common-mo de offset voltage, but in the single ended case this offset i s observed with respect to the signal ground. the single-ended out put sums half the differential offset voltage and all of the common-mode offset voltage for a net gain in observed random of fset. single-ended gain the AD8117/ad8118 operates as a closed-loop differe ntial amplifier. the primary control loop forces the dif ference between the output terminals to be a ratio of the d ifference between the input terminals. one output will incre ase in voltage, while the other decreases an equal amount to make the total difference correct. the average of these out put voltages is forced to the voltage on the vocm terminal by a sec ond control loop. if only one output terminal is obser ved with respect to the vocm terminal, only half of the diff erence voltage will be observed. this implies that when u sing only one output of the device, half of the differential gain will be observed. an AD8117 taken with single-ended output will appear to have a gain of +0.5. an ad8118 will be a single- ended gain of +1. this factor of one-half in the gain increases the n oise of the device when referred to the input, contributing to higher noise specifications for single-ended output designs. termination when operating the AD8117/ad8118 with a single-ende d output, the preferred output termination scheme is a resistor at the load end to the vocm voltage. a back-terminati on may be used, at an additional cost of one half the signal gain. in single-ended output operation, the second phase of the output is not used, and may or may not be terminate d locally. termination of the unused output is not necessary f or proper device operation, so total design power dissipation can be reduced by floating this output. however, there ar e several reasons for terminating the unused output with a lo ad resistance equal to the signal output. one component of crosstalk is magnetic, coupling by mutual inductance between output package traces and bond w ires that carry load current. in a differential design, ther e is coupling from one pair of outputs to other adjacent pairs of outputs. the differential nature of the output signal simultaneo usly drives the coupling field in one direction for one phase of th e output, and in an opposite direction for the other phase of the output. these magnetic fields do not couple exactly equal i nto adjacent output pairs due to different proximities, but they do destructively cancel the crosstalk to some extent. if the load current in each output is equal, this cancellation will be greater and less adjacent crosstalk will be observed (regar dless if the second output is actually being used). a second benefit of balancing the output loads in a differential pair is to reduce fluctuations in current requireme nts from the power supply. in single-ended loads, the load curr ents alternate from the positive supply to the negative supply. t his creates a parasitic signal voltage in the supply pins due to the finite resistance and inductance of the supplies. this su pply fluctuation appears as crosstalk in all outputs, at tenuated by the power supply rejection ratio (psrr) of the device. at low frequencies, this is a negligible component of cros stalk, but psrr falls off as frequency increases. with differ ential, balanced loads, as one output draws current from th e positive supply, the other output draws current from the neg ative supply. when the phase alternates, the first output draws c urrent from the negative supply and the second from the positiv e supply. the effect is that a more constant current is drawn from each supply, such that the crosstalk-inducing supply flu ctuation is minimized.
AD8117/ad8118 preliminary technical data rev. pra | page 24 of 32 a third benefit of driving balanced loads can be se en if one considers that the output pulse response will chang e as load changes. the differential signal control loop in t he AD8117/ad8118 forces the difference of the outputs to be a fixed ratio to the difference of the inputs. if th e two output responses are different due to loading, this create s a difference that the control loop will see as signal response e rror, and it will attempt to correct this error. this will distort t he output signal from the ideal response if the two outputs were bal anced. 75 w ww w 150 w ww w 75 w ww w opn AD8117 onn figure 26. example of back-terminated single-ended load decoupling the signal path of the AD8117/ad8118 is based on hi gh open loop gain amplifiers with negative feedback. domin ant-pole compensation is used on-chip to stabilize these amp lifiers over the range of expected applied swing and load condit ions. to guarantee this designed stability, proper supply de coupling is necessary with respect to both the differential con trol loops and the common-mode control loops of the signal path. signal- generated currents must return to their sources thr ough low- impedance paths at all frequencies in which there i s still loop gain (up to 700 mhz at a minimum). refer to the ex ample evaluation board schematic as an example of wideban d parallel capacitor arrangements that can properly decouple t he AD8117/ad8118. the signal path compensation capacitors in the AD8117/ad8118 are connected to the vneg supply. at high frequencies, this limits the power supply rejection ratio (psrr) from the vneg supply to a lower value than that fro m the vpos supply. if given a choice, an application boa rd should be designed such that the vneg power is supplied from a low- inductance plane, subject to a least amount of nois e. the vocm should be considered a reference pin and n ot a power supply. it is an input to the high-speed, hi gh-gain common-mode control loop of all receivers and outpu t drivers. in the single-ended output sense, there is no rejec tion from noise on the vocm net to the output. for this reas on, care must be taken to produce a low-noise vocm source ov er the entire range of frequencies of interest. this is n ot only important to single-ended operation, but to differe ntial operation as there is a common-mode to differential gain conversion that becomes greater at higher frequenci es. during operation of the AD8117/ad8118, transient cu rrents will flow into the vocm net from the amplifier cont rol loops. although the magnitude of these currents are small (10 C 20 a per output), they can contribute to crosstalk if th ey flow through significant impedances. driving vocm with a low- impedance, low-noise source is desirable. power dissipation calculation of power dissipation 8.0 m a x i m u m p o w e r C w a t t s 7.0 4.0 6.0 5.0 85 75 ambient temperature C c t j = 150 c 65 55 45 35 25 15 figure 27. maximum die power dissipation vs. ambien t temperature the above curve was calculated from as an example, if the AD8117/ad8118 is enclosed in an environment at 45 c (t a ), the total on-chip dissipation under all load and supply conditions must not be allowed to exceed 7.0 w. when calculating on-chip power dissipation, it is n ecessary to include the rms current being delivered to the load , multiplied by the rms voltage drop on the AD8117/ad8118 output devices. for a sinusoidal output, the on-chip power dissipation due the load can be approximated by for nonsinusoidal output, the power dissipation sho uld be calculated by integrating the on-chip voltage drop multiplied by the load current over one period. the user may subtract the quiescent current for the class ab output stage when calculating the loaded power diss ipation. for p d, out = ( v pos C v output, rms ) i output, rms p d, max = ( t junction, max C t ambient ) ja
preliminary technical data AD8117/ad8118 rev. pra | page 25 of 32 each output stage driving a load, subtract a quiesc ent power according to for the AD8117/ad8118, i output, quiescent = 1.65 ma for each single-ended output pin. for each disabled output, the quiescent power suppl y current in vpos and vneg drops by approximately 9 ma. i o,quiescent qpnp qnpn v pos i o,quiescent v neg v output i output figure 28. simplified output stage an example: AD8117, in an ambient temperature of 85c, with all 32 outputs driving 1 v rms into 100 l load s. power supplies are 2.5 v. step 1. calculate power dissipation of AD8117 using data sheet quiescent currents. we are neglecting v dd current as it is insignificant. p d, quiescent = ( v pos i vpos ) + ( v neg i vneg ) step 2. calculate power dissipation from loads. for a differential output and ground-referenced load, the output power is symmetrical in each output phase. there are 32 output pairs, or 64 output currents. step 3. subtract quiescent output stage current for num ber of loads (64 in this example). the output stage is either standing, or driving a load but the current only needs to be counted once (valid for output voltages > 0.5 v). there are 32 output pairs, or 64 output currents. np d, output = 64 8.25 mw = 0.53 w step 4. verify that the power dissipation does not ex ceed maximum allowed value. from the figure or the equation, this power dissipat ion is below the maximum allowed dissipation for all ambie nt temperatures up to and including 85c. short circuit output conditions although there is short-circuit current protection on the AD8117 outputs, the output current can reach values of 80 ma into a grounded output. any sustained operation wit h too many shorted outputs can exceed the maximum die temperature and can result in device failure (see a bsolute maximum ratings). crosstalk many systems, such as broadcast video and kvm switc hes, that handle numerous analog signal channels, have strict requirements for keeping the various signals from i nfluencing any of the others in the system. crosstalk is the t erm used to describe the coupling of the signals of other nearb y channels to a given channel. when there are many signals in close proximity in a system, as will undoubtedly be the case in a system that uses the AD8117/ad8118, the crosstalk issues can be quite co mplex. a good understanding of the nature of crosstalk and s ome definition of terms is required in order to specify a system that uses one or more crosspoint devices. types of crosstalk crosstalk can be propagated by means of any of thre e methods. these fall into the categories of electric field, m agnetic field, and sharing of common impedances. this section will explain these effects. every conductor can be both a radiator of electric fields and a receiver of electric fields. the electric field cro sstalk mechanism occurs when the electric field created by the trans mitter propagates across a stray capacitance (e.g., free s pace) and couples with the receiver and induces a voltage. th is voltage is an unwanted crosstalk signal in any channel that re ceives it. p d, on-chip = p d, quiescent + np d, output + np dq, output p d, on - chip = 2.5 w + 0. 96 w C 0.53 w = 2. 9 w p dq, output = ( v pos C v neg ) i o , quiescent p dq, output = ( 2.5 v C ( C 2.5v)) (1.65 ma) = 8.25 mw np d, output = 64 15 mw = 0.96 w p d, output = ( v pos C v output, rms ) i output, rms p d, output = ( 2.5 v C 1 v ) ( 1 v/150 l ) = 10 mw p d, quiescent = (2.5 v 500 ma) + (2.5 v 500 ma) = 2.5 w p d, out, q = ( v pos C v neg ) i output, quiescent p d, output = ( v pos C v output, rms ) i output, rms p d, output = ( 2.5 v C 1 v ) ( 1 v/1 0 0 l ) = 1 5 mw
AD8117/ad8118 preliminary technical data rev. pra | page 26 of 32 currents flowing in conductors create magnetic fiel ds that circulate around the currents. these magnetic field s then generate voltages in any other conductors whose pat hs they link. the undesired induced voltages in these other channels are crosstalk signals. the channels that crosstalk can be said to have a mutual inductance that couples signals from one c hannel to another . the power supplies, grounds, and other signal retur n paths of a multichannel system are generally shared by the var ious channels. when a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an input crosstalk signal for other channel s that share the common impedance . all these sources of crosstalk are vector quantitie s, so the magnitudes cannot simply be added together to obtai n the total crosstalk. in fact, there are conditions where driv ing additional circuits in parallel in a given configuration can a ctually reduce the crosstalk. the fact that the AD8117/ad8118 is a fully- differential design means that many sources of cros stalk either destructively cancel, or are common-mode to the sig nal and can be rejected by a differential receiver. areas of crosstalk a practical AD8117/ad8118 circuit must be mounted t o some sort of circuit board in order to connect it to pow er supplies and measurement equipment. great care has been take n to create a characterization board (also available as an evaluation board) that adds minimum crosstalk to the intrinsic device. this, however, raises the issue that a systems cro sstalk is a combination of the intrinsic crosstalk of the devic es in addition to the circuit board to which they are mounted. it is important to try to separate these two areas when attempting to minimize the effect of crosstalk. in addition, crosstalk can occur among the inputs t o a crosspoint and among the outputs. it can also occur from input to output. techniques will be discussed for diagnos ing which part of a system is contributing to crosstalk. measuring crosstalk crosstalk is measured by applying a signal to one o r more channels and measuring the relative strength of tha t signal on a desired selected channel. the measurement is usuall y expressed as db down from the magnitude of the test signal. t he crosstalk is expressed by |xt| = 20 log 10 ( a sel ( s ) / a test ( s )) where s = j is the laplace transform variable, a sel ( s ) is the amplitude of the crosstalk induced signal in the se lected channel, and a test ( s ) is the amplitude of the test signal. it can be seen that crosstalk is a function of frequency, but not a function of the magnitude of the test signal (to first order ). in addition, the crosstalk signal will have a phase relative to the test signal associated with it. a network analyzer is most commonly used to measure crosstalk over a frequency range of interest. it ca n provide both magnitude and phase information about the crosstalk signal. as a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. for example, in the case of the 32 32 matrix of the AD8117, we can look at the number of crosstalk terms that can be considered for a single channel, say the in00 input. in00 is programmed to connect to one of the AD8117 outputs where the measurement can be made. first, the crosstalk terms associated with driving a test signal into each of the other 31 inputs can be measured on e at a time, while applying no signal to in00. then the crosstal k terms associated with driving a parallel test signal into all 31 other inputs can be measured two at a time in all possibl e combinations, then three at a time, and so on, unti l, finally, there is only one way to drive a test signal into a ll 31 other inputs in parallel. each of these cases is legitimately different from the others and might yield a unique value, depending on the resolu tion of the measurement system, but it is hardly practical to m easure all these terms and then specify them. in addition, thi s describes the crosstalk matrix for just one input channel. a similar crosstalk matrix can be proposed for every other in put. in addition, if the possible combinations and permutat ions for connecting inputs to the other outputs (not used fo r measurement) are taken into consideration, the numb ers rather quickly grow to astronomical proportions. if a larg er crosspoint array of multiple AD8117s is constructed, the numbe rs grow larger still. obviously, some subset of all these cases must be s elected to be used as a guide for a practical measure of crosstal k. one common method is to measure all hostile crosstalk; this means that the crosstalk to the selected channel is measu red while all other system channels are driven in parallel. in ge neral, this will yield the worst crosstalk number, but this is not a lways the case, due to the vector nature of the crosstalk signal. other useful crosstalk measurements are those creat ed by one nearest neighbor or by the two nearest neighbors on either side. these crosstalk measurements will generally be high er than those of more distant channels, so they can serve a s a worst- case measure for any other one-channel or two-chann el crosstalk measurements.
preliminary technical data AD8117/ad8118 rev. pra | page 27 of 32 input and output crosstalk capacitive coupling is voltage-driven (dv/dt), but is generally a constant ratio. capacitive crosstalk is proportion al to input or output voltage, but this ratio is not reduced by si mply reducing signal swings. attenuation factors must be changed by changing impedances (lowering mutual capacitance), or destructive canceling must be utilized by summing e qual and out of phase components. for high-input impedance devices such as the AD8117/ad8118, capacitances generally d ominate input-generated crosstalk. inductive coupling is proportional to current (di/d t), and will often scale as a constant ratio with signal voltage , but will also show a dependence on impedances (load current). in ductive coupling can also be reduced by constructive cancel ing of equal and out of phase fields. in the case of driving lo w-impedance video loads, output inductances contribute highly t o output crosstalk. the flexible programming capability of the AD8117/a d8118 can be used to diagnose whether crosstalk is occurr ing more on the input side or the output side. some examples ar e illustrative. a given input pair (in07 in the middl e for this example) can be programmed to drive out07 (also in the middle). the inputs to in07 are just terminated to ground (via 50 l or 75 l) and no signal is applied. all the other inputs are driven in parallel with th e same test signal (practically provided by a distribution ampl ifier), with all other outputs except out07 disabled. since grounded in07 is programmed to drive out07, no signal should be pres ent. any signal that is present can be attributed to the oth er 15 hostile input signals, because no other outputs are driven (they are all disabled). thus, this method measures the all-hosti le input contribution to crosstalk into in07. of course, the method can be used for other input channels and combinations o f hostile inputs. for output crosstalk measurement, a single input ch annel is driven (in00, for example) and all outputs other th an a given output (in07 in the middle) are programmed to conne ct to in00. out07 is programmed to connect to in15 (far a way from in00), which is terminated to ground. thus out 07 should not have a signal present since it is listen ing to a quiet input. any signal measured at the out07 can be attr ibuted to the output crosstalk of the other 16 hostile output s. again, this method can be modified to measure other channels an d other crosspoint matrix combinations. effect of impedances on crosstalk the input side crosstalk can be influenced by the o utput impedance of the sources that drive the inputs. the lower the impedance of the drive source, the lower the magnit ude of the crosstalk. the dominant crosstalk mechanism on the input side is capacitive coupling. the high impedance inputs d o not have significant current flow to create magnetically ind uced crosstalk. however, significant current can flow th rough the input termination resistors and the loops that driv e them. thus, the pc board on the input side can contribute to ma gnetically coupled crosstalk. from a circuit standpoint, the input crosstalk mech anism looks like a capacitor coupling to a resistive load. for low frequencies the magnitude of the crosstalk will be given by where r s is the source resistance, c m is the mutual capacitance between the test signal circuit and the selected ci rcuit, and s is the laplace transform variable. from the equation it can be observed that this cros stalk mechanism has a high-pass nature; it can also be mi nimized by reducing the coupling capacitance of the input circ uits and lowering the output impedance of the drivers. if th e input is driven from a 75 l terminated cable, the input cros stalk can be reduced by buffering this signal with a low output impedance buffer. on the output side, the crosstalk can be reduced by driving a lighter load. although the AD8117 is specified with excellent differential gain and phase when driving a standard 150 l video load, the crosstalk will be higher than the m inimum obtainable due to the high output currents. these c urrents will induce crosstalk via the mutual inductance of the o utput pins and bond wires of the AD8117. from a circuit standpoint, this output crosstalk me chanism looks like a transformer with a mutual inductance b etween the windings that drives a load resistor. for low frequ encies, the magnitude of the crosstalk is given by where m xy is the mutual inductance of output x to output y and r l is the load resistance on the measured output. thi s crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing r l . the mutual inductance can be kept low by increasing the spacing of the conduc tors and minimizing their parallel length. pcb layout extreme care must be exercised to minimize addition al crosstalk generated by the system circuit board(s). the areas |xt| = 20 log 10 [( r s c m ) s ] |xt| = 20 log 10 ( m xy s / r l )
AD8117/ad8118 preliminary technical data rev. pra | page 28 of 32 that must be carefully detailed are grounding, shie lding, signal routing, and supply bypassing. the packaging of the AD8117/ad8118 is designed to h elp keep the crosstalk to a minimum. on the bga substrate, e ach pair is carefully routed to predominately couple to each ot her, with shielding traces separating adjacent signal pairs. the ball grid array is arranged such that similar board routing c an be achieved. only the outer two rows are used for sig nals, such that vias can be used to take the input rows to a l ower signal plane if desired. the input and output signals will have minimum cros stalk if they are located between ground planes on layers ab ove and below, and separated by ground in between. vias sho uld be located as close to the ic as possible to carry the inputs and outputs to the inner layer. the input and output si gnals surface at the input termination resistors and the output s eries back- termination resistors. to the extent possible, thes e signals should also be separated as soon as they emerge fro m the ic package. pcb termination layout as frequencies of operation increase, the importanc e of proper transmission line signal routing becomes more impor tant. the bandwidth of the AD8117/ad8118 is large enough that using high impedance routing will not provide a flat in-b and frequency response for practical signal trace lengt hs. it is necessary for the user to choose a characteristic i mpedance suitable for the application and properly terminate the input and output signals of the AD8117/ad8118. tradition ally, video applications have used 75 l single-ended envi roments. rf applications are generally 50 l single-ended (an d board manufacturers have the most experience with this ap plication). cat-5 cabling is usually driven as differential pai rs of 100 l differential impedance. for flexibility, the AD8117/ad8118 does not contain on-chip termination resistors. this flexibility in applica tion comes with some board layout challenges. the distance between the termination of the input transmission line and the AD8117/ad8118 die is a high-impedance stub, and wil l cause reflections of the input signal. with some simplif ication, it can be shown that these reflections will cause peaking of the input at regular intervals in frequency, dependent on the propagation speed ( v p ) of the signal in the choosen board material and t he distance ( d ) between the termination resistor and the AD8117/ad8118. if the distance is great enough, th ese peaks can occur in-band. in fact, practical experience s hows that these peaks are not high- q , and should be pushed out to three or four times the desired bandwidth in order to not have an effect on the signal. for a board designer using f r4 ( v p = 144 10 6 m/s), this means the AD8117/ad8118 should be no mo re than 1.5 cm after the termination resistors, and pr eferably should be placed even closer. the bga substrate ro uting inside the AD8117/ad8118 is approximately 1 cm in length a nd adds to the stub length, so 1.5 cm pcb routing equates t o d = 2.5 10 C2 m in the calculations. in some cases, it is difficult to place the termina tion close to the AD8117/ad8118 due to space constraints, differentia l routing, and large resistor footprints. a preferable soluti on in this case is to maintain a controlled transmission line past the AD8117/ad8118 inputs and terminate the end of the l ine. this is known as fly-by termination. the input imp edance of the AD8117/ad8118 is large enough and stub length i nside the package is small enough that this works well in pra ctice. implementation of fly-by input termination often in cludes bringing the signal in on one routing layer, then p assing through a filled-via under the AD8117/ad8118 input ball, then back out to termination on another signal layer. i n this case, care must be taken to tie the reference ground plan es together near the signal via if the signal layers are refere nced to different ground planes. opn AD8117 onn ipn inn 75 w ww w figure 29. fly-by input termination. grounds for t he two transmission lines shown must be tied together close to the inn pin. if multiple AD8117/ad8118 are to be driven in paral lel, a fly- by input termination scheme is very useful, but the distance from each AD8117/ad8118 input to the driven input transmission line is a stub that should be minimize d in length and parasitics using the discussed guidelines. when driving the AD8117/ad8118 single-endedly, the undriven input is often terminated with a resistanc e in order to balance the input stage. it can be seen that by te rminating the undriven input with a resistor of one-half the char acteristic impedance, the input stage will be perfectly balanc ed (37.5 l, for example, to balance the two parallel 75 l termi nations on the driven input). however, due to the feedback in the input receiver, there is high-speed signal current leavin g the undriven input. in order to terminate this high-speed signa l, proper transmission-line techniques should be used. one s olution is f peak = (2n + 1)v p 4d , n = {0, 1, 2, 3, }
preliminary technical data AD8117/ad8118 rev. pra | page 29 of 32 to adjust the trace width to create a transmission line of half the characteristic impedance and terminate the far end with this resistance (37.5 l in a 75 l system). this is not often practical as trace widths become large. in most cases, the b est practical solution is to place the half-characteristic impeda nce resistor as close as possible (preferably less than 1.5 cm away ) and to reduce the parasitics of the stub (by removing the ground plane under the stub, for example). in either case, the designer must decide if the layout complexity created by a balanc ed, terminated solution is preferable to simply groundi ng the undriven input at the ball with no trace. while the examples discussed so far are for input t ermination, the theory is similar for output back-termination. taking the AD8117/ad8118 as an ideal voltage source, any dista nce of routing between the AD8117/ad8118 and a back-termin ation resistor will be a stub that will create reflection s. for this reason, back-termination resistors should also be p laced close to the AD8117/ad8118. in practice, because back-te rmination resistors are series elements, their footprint in t he routing is narrower and it is easier to place them close in bo ard layout.
AD8117/ad8118 preliminary technical data rev. pra | page 30 of 32 figure 30. evaluation board simplified schematic
preliminary technical data AD8117/ad8118 rev. pra | page 31 of 32 outline dimensions * compliant to jedec standards mo-192-ban-2 with the exception to package height. detail a a b c d ef g h j k lm n p r t u v wy aa ab ac 1 3 5 7 9 11 15 17 19 21 23 13 4 6 8 10 12 2 16 18 20 22 14 27.94 bsc sq bottom view a1 corner index area 1.27 bsc top view 31.00 bsc sq ball a1 indicator 0.10 min 0.70 0.63 0.56 1.07 0.99 0.92 coplanarity 0.20 0.90 0.75 0.60 seating plane ball diameter 0.25 min (4 ) detail a * 1.765 max figure 31. 304-lead ball grid array, thermally enha nced [bga_ed] dimensions shown in millimeters ordering guide model temperature range package description package option AD8117abpz ?40c to +85c 304-lead ball grid array p ackage [bga_ed] (31 31 mm) sbga-304 ad8118abpz ?40c to +85c 304-lead ball grid array p ackage [bga_ed] (31 31 mm) sbga-304 AD8117-eval AD8117 evaluation kit note: z suffix denotes lead-free package.
AD8117/ad8118 preliminary technical data rev. pra | page 32 of 32 notes ? 2006 analog devices, inc. all rights reserved. tr ademarks and registered trademarks are the property of their res pective owners. pr06365-0-8/06(pra)

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