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ucb1400 audio codec with touch screen controller and power management monitor rev. 02 21 june 2002 product data 1. general description the ucb1400 is a stereo audio codec equipped with touch screen and power management interfaces. it integrates an ac 97 rev. 2.1 interface for communication to an ac link host controller such as the intel xscale? processor. the stereo audio codec inputs connect directly to a microphone or line level sources such as a cd player. the stereo audio codec outputs at line level and can drive a headphone directly. the touch screen interface connects directly to a 4-wire resistive touch screen. a built-in 10-bit analog-to-digital converter provides readout of touch screen and power management parameters. ten general-purpose i/o pins provide programmable inputs and/or outputs to the system. 2. features n 48-pin lqfp surface mount package and low external component count for minimal pcb space requirement n integrated ac 97 rev. 2.1 interface n 20-bit stereo audio codec supporting programmable sample rates, and input/output gain control u stereo line input and mono microphone input u stereo line/headphone output with bass/treble control u headphone driver with short circuit protection and virtual ground for dc coupling n 4-wire resistive touch screen interface circuit supporting position, pressure and plate resistance measurements n 10-bit successive approximation adc with internal track-and-hold circuit and analog multiplexer for touch screen readout and monitoring of four external high voltage (7.5 v) sources n ten general purpose input/output pins n 3.3 v supply voltage and built-in power saving modes for portable and battery powered applications. 3. applications n smart mobile phones n handheld pcs n palm-top pcs n personal intelligent communicators (pic) n personal digital assistants (pda).
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 2 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 4. ordering information 5. block diagram table 1: ordering information type number package name description version UCB1400BE lqfp48 plastic low pro?le quad ?at package, 48 leads; body 7 7 1.4 mm sot313-2 fig 1. block diagram. tspx tsmx tspy tsmy sn00236 touch i/f mux ad[3:0] 10-bit adc ac link i/o and control adcsync sdata_in sdata_out bit_clk reset sync irqout 2-channel 20-bit audio dac line_out_l, line_out_r 2-channel 20-bit audio adc line_in_l, line_in_r, micp micgnd osc xtl_in xtl_out digital i/o io[9:0] voltage reference
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 3 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration (lqfp48). io2 1 2 3 4 5 6 7 dvdd1 xtl_in xtl_out dvss1 sdata_out dvss2 bit_clk 8 9 10 11 sdata_in dvdd2 reset sync 12 adcsync ad3 ad2 ad1 ad0 tspx tsmx tsmy tspy micp micgnd line_in_l line_in_r 36 35 34 33 32 31 30 line_out_r line_out_l vrefdrv avss2 avdd2 vrefbyp vadcn 29 28 27 26 irqout vadcp avss1 vref 25 avdd1 io9 io8 io7 io6 io5 io4 avss3 io3 io1 avdd3 io0 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 ucb1400 sn00219 table 2: pin description total pin count = 48 symbol pin type default state description ac-link, crystal and interrupt interface (pin count = 8) xtl_in 2 i - 24.576 mhz crystal / master clock input xtl_out 3 o - 24.576 mhz crystal reset 11 i - ac-link master reset sync 10 i - ac-link sample sync bit_clk 6 o 0 ac-link 12.288 mhz serial data clock sdata_out 5 i - ac-link serial data output. ucb1400 input stream sdata_in 8 o 0 ac-link serial data input. ucb1400 output stream irqout 29 o 0 interrupt output
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 4 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. audio interface (pin count = 6) micp 21 i - microphone input micgnd 22 i closed microphone ground switch input line_in_l 23 i - line in left channel line_in_r 24 i - line in right channel line_out_l 35 o driver off line out left channel line_out_r 36 o driver off line out right channel adc and touch screen interface (pin count = 9) ad[3:0] 13, 14, 15, 16 i - analog voltage input tspx 17 i/o hi-z touch screen positive x-plate tsmx 18 i/o hi-z touch screen negative x-plate tsmy 19 i/o hi-z touch screen negative y-plate tspy 20 i/o hi-z touch screen positive y-plate adcsync 12 i - adc synchronization pulse gpio interface (pin count = 10) io[9:0] 48, 47, 46, 45, 44, 43, 41, 40, 39, 37 i/o input general purpose input/output power and miscellaneous (pin count = 15) dvdd2, dvdd1 9, 1 s - digital supply dvss2, dvss1 7, 4 s - digital ground avdd3, avdd2, avdd1 38, 32, 25 s - analog supply avss3, avss2, avss1 42, 33, 26 s - analog ground vrefdrv 34 o - reference voltage for headphone drivers vref 27 o - reference voltage vadcp 28 s - audio adc positive reference voltage vadcn 31 s - audio adc negative reference voltage vrefbyp 30 i/o hi-z reference bypass output/ external reference voltage input table 2: pin description continued total pin count = 48 symbol pin type default state description
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 5 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 7. functional description 7.1 functional block diagram fig 3. functional block diagram. sn00243 master vol. 0C94.5 db (0x02) master vol. 0C94.5 db (0x02) record gain 0C22.5 db (0x1c) record gain 0C22.5 db (0x1c) mux (0x1a) 0C22.5 db (0x0e) micp line_in_l line_out_r line_out_l line_in_r dac_l variable rate (0x2a, 0x2c) dac_r variable rate (0x2a, 0x2c) adc_l variable rate (0x2a, 0x32) adc_r variable rate (0x2a, 0x32) interpolation filter & noise shaper dsp (0x6a) decimation filter loop back (0x20) digital interface sdata_out sdata_in bit_clk sync reset irqout ovfl ground switch (0x1a) oscillator / pll adc / touch power up/down (0x64, 0x66) ac97 / audio power up/down (0x26, 0x6c) io block data (0x5a) direction (0x5c) io data micgnd xtl_in xtl_out io[9:0] touch screen biasing matrix (0x64) interrupt generation positive (0x5e) negative (0x60) status/clear (0x62) mux (0x64, 0x66) bias current adc control (0x66) data (0x68) adc ready tspx tsmx tspy tsmy ad[3:0] adcsync adc data interrupt
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 6 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8. ac 97 interface the ucb1400 implements an ac 97 revision 2.1 interface. refer to the audio codec 97 component speci?cation revision 2.1 from intel. 8.1 clocking the ucb1400 functions only as a primary codec. as such, it derives its clock internally from an externally attached 24.576 mhz crystal or clock oscillator, and drives a buffered and divided down ( 1 2 ) clock to its digital companion controller over ac-link under the signal name bit_clk. the beginning of all audio sample packets, or audio frames, transferred over ac-link is synchronized to the rising edge of the sync signal. sync is driven by the ac 97 controller. the ac 97 controller takes bit_clk as an input and generates sync by dividing bit_clk by 256 and applying some conditioning to tailor its duty cycle. this yields a 48 khz sync signal whose period de?nes an audio frame. data is transitioned on ac-link on every rising edge of bit_clk, and subsequently sampled on the receiving side of ac-link on each immediately following falling edge of bit_clk. 8.2 resetting ucb1400 the ucb1400 recognizes the following types of reset: ? cold reset: where all ucb1400 logic (registers included) is initialized to its default state. initiated by bringing reset low for at least 1 m s. ? warm reset: where the contents of the ucb1400 register set are left unaltered. initiated by bringing sync high for at least 1 m s without bit_clk. ? register reset: which only initializes the ucb1400 registers to their default states. initiated by a write to register 0x00. after signaling a reset to ucb1400, the ac 97 controller should not attempt to play or capture audio data until it has sampled a codec ready indication from ucb1400. fig 4. ucb1400 and ac 97 controller connection diagram. sn00237 ucb1400 sync bit_clk sdata_out sdata_in reset irqout ac97 controller
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 7 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8.3 digital interface 8.3.1 ac-link digital serial interface protocol the ucb1400 incorporates a 5-pin digital serial interface that links it to the ac 97 controller. ac-link is a bi-directional, ?xed rate, serial pcm digital stream. it handles multiple input, and output audio and modem streams, as well as control register accesses employing a time division multiplexed (tdm) scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. the control and data slots de?ned by ucb1400 include: ? sdata_out tag (output slot 0) ? sdata_in tag (input slot 0) ? control (cmd addr & data) write port (output slots 1, 2) ? status (status addr & data) read port (input slots 1, 2) ? pcm l & r dac playback (output slots 3, 4) ? pcm l & r adc record (input slots 3, 4) ? gpio interrupt status (input slot 12) the ac-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is de?ned as the tag phase. the remainder of the audio frame where sync is low is de?ned as the data phase. additionally, for power savings, all clock, sync, and data signals can be halted. ucb1400 is implemented as a static design to allow its register contents to remain intact when entering a power savings mode. fig 5. standard bi-directional audio frame. tag cmd addr cmd data pcm l pcm r line 1 dac pcm center pcm l surr pcm r surr pcm lfe line 2 dac hset dac io ctrl tag status addr status data pcm l pcm r line 1 adc mic adc rsrvd line 2 adc hset adc io status rsrvd rsrvd 123456789101112 0 slot # sync sdata_out sdata_in codec id pcm c (n+1) pcm r (n+1) slotreq 3C12 pcm l (n+1) sn00220
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 8 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8.3.2 ac-link audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting ucb1400s dac inputs, and control registers. each audio output frame supports up to 12 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16 bits which are used for ac-link protocol infrastructure. slot 0: tag: within slot 0, the ?rst bit is a global bit (sdata_out slot 0, bit 15) which ?ags the validity for the entire audio frame. if the valid frame bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. the next 12 bit positions sampled by ucb1400 indicate which of the corresponding 12 time slots contain valid data. in this way, data streams of differing sample rates can be transmitted across ac-link at its ?xed 48 khz audio frame rate. figure 6 illustrates the time slot based ac-link protocol. (note that bits 1 and 0 of slot 0 tag phase are used for primary/secondary codec addressing as described in section 8.4 . a new audio output frame begins with a low-to-high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the ucb1400 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the ac 97 controller transitions sdata_out into the ?rst bit position of slot 0 (valid frame bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by ucb1400 on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned. * see ta b l e 4 . fig 6. ac link audio output frame. 20.8 m s (48 khz) tag phase data phase 81.4 ns (12.288 mhz) valid frame sync bit_clk sdata_out end of previous audio frame slot(1) slot(2) slot(12) 0 ** 19 019 019 0 19 0 time slot valid bits (1 = time slot contains valid pcm data) slot 1 slot 2 slot 3 slot 12 sn00221
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 9 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. sdat_outs composite stream is msb justi?ed (msb ?rst) with all non-valid slots bit positions stuffed with 0s by the ac 97 controller. if there are less than 20 valid bits within an assigned and valid time slot, the ac 97 controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s. slot 1: command address port: the command port is used to control features, and monitor status (see section 8.3.3 ac-link audio input frame (sdata_in) , slots 1 and 2) for ac 97 functions including, but not limited to, sample rate, codec con?guration, and power management. the control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries, and reserves support for 64 odd addresses, as described in ac 97 2.1 component speci?cation appendix d . only the even registers (00h, 02h, etc.) are currently de?ned, odd register (01h, 03h, etc.) accesses are reserved. note that shadowing of the control register ?le on the ac 97 controller is an option left open to the implementation of the ac 97 controller. ucb1400s control register ?le is readable as well as writable to provide more robust testability. audio output frame slot 1 communicates control register address, and write/read command information to the ucb1400. command address port bit assignments are: ? bit(19) read/write command (1 = read, 0 = write). ? bit(18:12) control register index (64 16-bit locations, addressed on even byte boundaries) ? bit(11:0) reserved (stuffed with 0s) the ?rst bit (msb) sampled by ucb1400 indicates whether the current control transaction is a read or a write operation. the following 7 bit positions communicate with the targeted control register address. the trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the ac 97 controller. fig 7. start of an audio output frame. sync bit_clk sdata_out end of previous audio frame slot(1) slot(2) sn00222 valid frame ac 97 samples sync assertion here ac 97 samples first sdata_out bit of frame here
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 10 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. slot 2: command data port: the command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle (as indicated by slot 1, bit 19). ? bit(19:4) control register write data (stuffed with 0s if current operation is a read). ? bit(3:0) reserved (stuffed with 0s) if the current command port operation is a read, then the entire slot time must be stuffed with 0s by the ac 97 controller. slot 3: pcm playback left channel: audio output frame slot 3 is the composite digital audio left playback stream. typically, this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac 97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20 bits is transferred, the ac 97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. slot 4: pcm playback right channel: audio output frame slot 4 is the composite digital audio right playback stream. typically, this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac 97 controller or host processor) with music synthesis output samples. if a sample stream of resolution less than 20 bits is transferred, the ac 97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. slots 5 through 12: all other audio output frame slots are ignored by the ucb1400. 8.3.3 ac-link audio input frame (sdata_in) the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac 97 controller. as is the case for audio output frame, each ac-link audio input frame consists of 12, 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits, which are used for ac-link protocol infrastructure. slot 0: tag: within slot 0, the ?rst bit is a global bit (sdata_in slot 0, bit 15) which ?ags whether ucb1400 is in the codec ready state or not. if the codec ready bit is a 0, this indicates that ucb1400 is not ready for normal operation. this condition is normal following the deassertion of power-on reset, for example, while ucb1400s voltage references settle. when the ac-link codec ready indicator bit is a logic 1, it indicates that the ac-link and ucb1400 control and status registers are in a fully operational state. the ac 97 controller must further probe the power-down control/status register (0x26) to determine exactly which subsections, if any, are ready. prior to any attempts at putting ucb1400 into operation, the ac 97 controller should poll the ?rst bit in the audio input frame (sdata_in slot 0, bit 15) for an indication that the ucb1400 has gone codec ready. once the ucb1400 is sampled codec ready then the next 12 bit positions sampled by the ac 97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. figure 8 illustrates the time slot based ac-link protocol.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 11 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. a new audio input frame begins with a low-to-high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, ucb1400 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bit_clk, ucb1400 transitions sdata_in into the ?rst bit position of slot 0 (codec ready bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the ac 97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. sdata_ins composite stream is msb justi?ed (msb ?rst) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by the ucb1400. sdata_in data is sampled on the falling edges of bit_clk. fig 8. ac-link audio input frame. 20.8 m s (48 khz) tag phase data phase 81.4 ns (12.288 mhz) codec ready sync bit_clk sdata_in end of previous audio frame slot(1) slot(2) slot(12) 0 0 0 19 019 019 0 19 0 time slot valid bits (1 = time slot contains valid pcm data) slot 1 slot 2 slot 3 slot 12 sn00223 fig 9. start of an audio input frame. sync bit_clk sdata_in end of previous audio frame slot(1) slot(2) sn00224 codec ready ac 97 samples sync assertion here ac 97 controller samples first sdata_in bit of frame here
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 12 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. slot 1: status address port: the status port is used to monitor status for ucb1400 functions including, but not limited to, codec settings and power management. audio input frame slot 1s stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged valid by ucb1400 during slot 0.) status address port bit assignments are: ? bit(19) reserved (stuffed with 0s) ? bit(18:12) control register index (echo of register index for which data is being returned) ? bit(11:2) slotreq bits: only bits 11 and 10 (pcm l & r) shall be used by ucb1400. all unused bits shall be stuffed with 0s. ? bit(1, 0) reserved (stuffed with 0s) the ?rst bit (msb) generated by ucb1400 is always stuffed with a 0. the following 7 bit positions communicate the associated control register address, the next 10 bits are the slotreq bits, two of which (bits 11 and 10) are used by ucb1400 to request data using the variable sample rate signaling protocol as de?ned in the ac 97 component speci?cation . the trailing 2 bit positions are stuffed with 0s by ucb1400. slot 2: status data port: the status data port delivers 16-bit control register read data. ? bit(19:4) control register read data (stuffed with 0s if tagged invalid by ucb1400) ? bit(3:0) reserved (stuffed with 0s) if slot 2 is tagged invalid by ucb1400, then the entire slot will be stuffed with 0s by ucb1400. slot 3: pcm record left channel: audio input frame slot 3 is the left channel output of ucb1400s input mux, post-adc. the ucb1400s adcs are implemented to support 20-bit resolution. ucb1400 ships out its adc output data (msb ?rst) to ?ll out its 20-bit time slot. slot 4: pcm record right channel: audio input frame slot 4 is the right channel output of ucb1400s input mux, post-adc. the ucb1400s adcs are implemented to support 20-bit resolution. ucb1400 ships out its adc output data (msb ?rst) to ?ll out its 20-bit time slot. slot 12: gpio status: audio output frame slot 12 is used to carry modem gpio input data. ta b l e 3 shows the de?nition by ac 97 component speci?cation . the ucb1400 does not make use of slot 12 to report its io pin status. it only uses the gpio_int as an optional means (when the gien bit is set in the feature csr1 register) to signify an interrupt event (in addition to pin irqout).
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 13 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. slots 5 through 11: all other audio input frame slots shall be stuffed with 0s by the ucb1400. 8.3.4 ac-link low power mode the ac-link signals can be placed in a low power mode. when the ucb1400s pr4 bit is set to 1 in the power-down status and control register (0x26), both bit_clk and sdata_in will be brought to, and held at, a logic low voltage level. bit_clk and sdata_in are transitioned low immediately following the decode of the write to register 0x26 with pr4. when the ac 97 controller driver is at the point where it is ready to program the ac-link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame. the ac 97 controller should also drive sync and sdata_out low after programming ucb1400 ac 97 to this low power, halted mode. the ac 97 controller is required to drive and keep sync and sdata_out low in this low power, halted mode. once the ucb1400 has been instructed to halt bit_clk, a special wake-up protocol must be used to bring the ac-link to the active mode since normal audio output and input frames cannot be communicated in the absence of bit_clk. table 3: slot 12 de?nition bit gpio name sense description 19-4 gpio[15:0] in/out modem gpio as de?ned by the intel ac 97 component speci?cation . 3-1 vendor rsrvd vendor optional. 0 gpio_int in gpio_int (uses same logic as wake-up event) fig 10. ac-link power-down timing. sync sdata_in tag sn00244 slot 12 prev. frame sdata_out tag slot 12 prev. frame write to 0x26 data pr4 bit_clk
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 14 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. waking up the ac-link: there are two methods for bringing the ac-link out of a low power, halted mode. regardless of the method, it is the ac 97 controller that performs the wake-up task. ac-link protocol provides for a cold ac 97 reset, and a warm ac 97 reset. the current power-down state would ultimately dictate which form of ac 97 reset is appropriate. unless a cold or register reset (a write to the reset register) is performed, wherein the ucb1400 registers are initialized to their default values, registers are required to keep state during all power-down modes. once powered down, re-activation of the ac-link via re-assertion of the sync signal must not occur for a minimum of four audio frame times following the frame in which the power-down was triggered. when ac-link powers-up, it indicates readiness via the codec ready bit (input slot 0, bit 15). cold ac 97 reset: a cold reset is achieved by asserting reset for the minimum speci?ed time. by driving reset low, all ucb1400 control registers will be initialized to their default power-on reset values. bit_clk and sdata_out will be activated, or re-activated as the case may be. reset is an asynchronous input to the ucb1400. warm ac 97 reset: a warm ac 97 reset will re-activate the ac-link without altering the current ac 97 register values. a warm reset is signaled, in the absence of bit_clk, by driving sync high for a minimum of 1 m s. within normal audio frames, sync is a synchronous input to the ucb1400. however, in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to the ucb1400. the ucb1400 must not respond with the activation of bit_clk until sync has been sampled low again by the ucb1400. this will preclude the false detection of a new audio frame. 8.4 accessing the ucb1400 the ucb1400 supports only primary codec con?guration. typically, the ucb1400 expects a 24.576 mhz crystal across the xtl_in and xtl_out pins. alternatively, an external 24.576 mhz clock can be applied to xtl_in. table 4: ac-link audio output frame slot 0 bit allocation bit description 15 frame valid 14 slot 1 valid command address bit (primary codec only) 13 slot 2 valid command data bit (primary codec only) 12-3 slot 3-12 valid bits as de?ned by ac 97 component speci?cation 2 reserved (set to 0) 1-0 2-bit codec id ?eld 00 reserved for primary 01, 10, 11 indicate secondary
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 15 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. in order for the ac 97 digital controller to access the ucb1400, the 2-bit codec id ?eld (chip select) (lsbs of output slot 0) must be set to 0 (see ta b l e 4 ). the ucb1400 shall monitor the frame valid, slot 1 valid command address, slot 2 valid command data and codec id bits, and respond only if properly accessed by the ac 97 digital controller, as illustrated in ta b l e 5 . note that although slotreq bits reside in slot 1, they have validity independent of the tag bit for valid slot 1 address. the ucb1400 shall only set sdata_in tag bits for slot 1 (address) and slot 2 (data) to 1 when returning valid data from a previous register read, regardless of the validity of slotreq bits (see also section 8.5 ). table 5: ucb1400 response to ac 97 digital controller access function slot 0, bit 15 (valid frame) slot 0, bit 14 (valid slot 1 address) slot 0, bit 13 (valid slot 2 data) slot 0, bits 1-0 (codec id) action ac 97 digital controller primary read frame n, sdata_out 11000ac 97 controller reads ucb1400 register ucb1400 status frame n+1, in response to ac 97 digital controller primary read frame n, sdata_in 11100 ucb1400 returns register status ac 97 digital controller primary write frame n, sdata_out 11100ac 97 controller writes ucb1400 register ucb1400 status frame n+1, in response to ac 97 digital controller primary write frame n, sdata_in 10000 ucb1400 writes register internally and returns nothing ac 97 digital controller secondary read or write frame n, sdata_out 1 0 0 01, 10 or 11 ac 97 controller reads or writes secondary codec ucb1400 status frame n+1, in response to ac 97 digital controller secondary read or write frame n, sdata_in 10000 ucb1400 ignores commands and returns nothing
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 16 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8.5 variable sample rate signaling protocol the ac-link is de?ned for a ?xed transfer rate of 48 khz. to support the diverse sample rates, ucb1400 implements the variable sample rate signaling protocol of the ac 97 component speci?cation : ? to control the ac 97 controller to input a rate other than 48 khz, the ucb1400 uses the tag bit for slot 3 and 4 (pcm l & r) to indicate whether valid data is present or not. ? to control the ac 97 controller to output a rate other than 48 khz, the ucb1400 uses the active-low slotreq bit for slot 3 and slot 4 (pcm l & r) to indicate whether it needs data from the ac 97 controller. 8.5.1 slotreq protocol to control the ac 97 controller to output a rate other than 48 khz, the ucb1400 examines its sample rate control registers, the state of its fifos, and the incoming sdata_out tag bits at the beginning of each audio output frame to determine which slotreq bits to set active (low). slotreq bits asserted during the current audio input frame signal which active output slots require data from the ac 97 digital controller in the next audio output frame. an active output slot is de?ned as any slot supported by ucb1400 that is not in a power-down state. in case of ucb1400, the only slotreq bits used are that for slot 3 and slot 4 request (bits 11 and 10 of input slot 1). slotreq bits for all other slots shall be stuffed with 0s by ucb1400. note that although slotreq bits reside in slot 1, their validity does not depend on the tag bit for valid slot 1 address (see also section 8.4 ). 8.6 wake-up support pressing the touch screen is an example of events that might need to wake-up the host cpu that has suspended into a low power state. figure 11 shows the ac link power-down/power-up sequence. the ucb1400 powers down the ac link subsequent to its pr4 bit being programmed to 1. when enabled to wake on, e.g., a touch screen event, a wake event causes the ucb1400 to transition irqout from low to high. the system controller can use this information as a signal to wake up. subsequently, the ?rst thing that the device driver must do to reestablish communications with the ucb1400 is to command the ac 97 digital controller to execute a warm reset to the ac link. alternatively, if the gien bit in the feature csr1 register (0x6a) is set, a wake event will cause the ucb1400 to transition its sdata_in from low to high. the ucb1400 shall keep sdata_in high until it has sampled sync having gone high, and then low.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 17 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. before enabling wake-up via irqout or gien bit, the ucb1400 must be enabled for interrupt by setting the appropriate bits in the positive int enable register (0x5e) and negative int enable register (0x60). the int clear/status register (0x62) should then be cleared of any previous interrupts before going to low-power mode. 8.7 test modes ac 97 component speci?cation de?nes two test modes. one is for ate in-circuit test, and the other if for vendor-speci?c tests. the ucb1400 enters the ate in-circuit test mode if sdata_out is sampled high at the trailing edge of reset. the ucb1400 enters the vendor-speci?c test mode when coming out of reset if sync is high. these cases will never occur during standard operating conditions. regardless of the test mode, the ac 97 controller must issue a cold reset to resume normal operation of the ucb1400. 8.7.1 ate in-circuit test mode when the ucb1400 is placed in the ate test mode, its digital ac-link outputs (i.e., bit_clk and sdata_in) shall be driven to a high impedance state. this allows ate in-circuit testing of the ac 97 controller. 8.7.2 vendor-speci?c test mode when the ucb1400 is placed in the vendor-speci?c test mode, the test control register (index 0x6e) determines the kind of tests to be performed. refer to section 12 register de?nition for details. fig 11. ac link power-down/power-up sequence. sync sdata_in tag sn00251 slot 12 prev. frame sdata_out tag slot 12 prev. frame write to 0x26 data pr4 bit_clk irqout power-down frame sleep state wake event new audio frame slot 2 slot 2 tag tag slot 1 slot 1
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 18 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 8.8 general purpose ios the ucb1400 has 10 programmable digital input/output (i/o) pins. these pins can be independently programmed as input or output using the iod[9:0] bits in the io direction register (0x5c). the output data is determined by the content of the io[9:0] bits in the io data register (0x5a), while the actual status of these pins can be read from the same register bits. the data on the io[9:0] pins are fed into the interrupt control block, where they can generate an interrupt on the rising and/or falling edge of these signals. 8.9 interrupt generation the ucb1400 contains a programmable interrupt control block, which can generate an interrupt for a 0-to-1 and/or 1-to-0 transition on one or more of the io[9:0] pins, the audio overload detection, the adc ready signal, and the tspx and tsmx signals. fig 12. block diagram of io pin circuitry. iod[x] io data[x] (write) io data[x] (read) to interrupt module io[x] sn00225 fig 13. block diagram of the interrupt controller. d r d r 1 xxxs write 1 reset interrupt source xxx xxxn xxxp or tree xxxs read irqout gien to ac97 gpio_int and wake-up block sn00239
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 19 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. the interrupt generation mode is set by the positive int enable register (0x5e) and negative int enable register (0x60). the actual interrupt status of each signal can be read from the int clear/status register (0x62). the interrupt status is cleared whenever a 1 is written in the int clear/status register (0x62) for the corresponding bit. the interrupt controller is implemented asynchronously. this provides the possibility to generate interrupts when the bit_clk is stopped, e.g., an interrupt can be generated in power-down mode when the touch screen is pressed or when the state of one of the io pins changes. the irqout pin presents the or function of all interrupt status bits and can be used to give an interrupt to the system controller. when the gien bit of the feature control/status register 1 (0x6a) is set, the irqout signal is communicated to the ac link by means of: ? gpio_int bit of input slot 12 when bit_clk is on. ? rising sdata_in when bit_clk is off.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 20 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 9. audio codec 9.1 adc analog front-end the analog front-end of the ucb1400 consists of one stereo adc with a selector in front of it. using this selector, one can either select the microphone input with a dedicated low noise ampli?er (lna), or the line input with a programmable gain ampli?er (pga). via appropriate ac 97 register settings, the following modes can be supported: ? standby mode: all pgas, lna and adcs are powered down. ? stereo line in mode: the pgas are used, and the lna is powered down. ? microphone mode: the pgas and right channel adc are powered down, and micgnd switch is on. the mono microphone signal can be sent to both left and right input of the decimation ?lter via a mux in front of the decimation input. ? one line-in and one microphone mode: the left pga is powered down. fig 14. audio codec block diagram. headphone driver noise shaper interpolation filter dsp features fsdac fsdac bb, tr, de, ml, mr, mm 0 1 clock module dr, ar pll 24.576 mhz line_out_l vrefdrv line_out_r dac clocks adc clocks 1 0 left, right from ac link decimation filter to ac link left, right dc, hips, gl, gr, rm overload detection ovfl lpbk sr = line_in_r adc adc 0 1 sr = line_in_l lna pga pga gr gl 0/20 db line_in_r line_in_l micp micgnd (sl = mic) & not powered down sn00245
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 21 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 9.1.1 line inputs the analog front-end of the ucb1400 consists of two stereo adcs with a programmable gain stage. the full scale input voltage of the line input path is programmable in 1.5 db steps independently for the left and right channels by setting the gl[3:0] and gr[3:0] bits in the record gain register (0x1c). 9.1.2 microphone input the ucb1400 audio codec input path accepts microphone signals via a dc blocking capacitor. the ground side of the microphone is either connected to the analog ground (av ss ) or to the micgnd pin of the ucb1400. the latter will decrease the current consumption of active microphones, since the micgnd pin is made hi-z when the microphone input is not selected (sl = line_in_l in record select register (0x1a)). the lna gain can be set to 0 or 20 db via the 20 db bit in the mic volume register (0x0e). additional gain in 1.5 db steps is possible via the gl[3:0] in the record gain register (0x1c). 9.1.3 decimation ?lter the decimation from 128 fs is performed in two stages. the ?rst stage realizes sin(x)/x characteristics with decimation factor of 16. the second stage consists of 3 half-band ?lters, each decimating by a factor of 2. the ?lter characteristics are shown in ta b l e 6 . a. passive microphone. b. active microphone. fig 15. possible microphone connections. ucb1400 av dd micp micgnd av ss sn00226 ucb1400 av dd micp micgnd av ss sn00227 table 6: decimation ?lter characteristics item condition value (db) pass-band ripple 0 to 0.45 fs 0.015 stop band > 0.55 fs - 60 dynamic range 0 to 0.45 fs > 135
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 22 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. two bits in the feature control/status register 1 (0x6a) provide control over dc ?ltering: ? dc bit: controls the dc ?lter before the decimator used to compensate the dc offset is added in the adc to remove idle tones from the audio band. ? hips bit: controls the dc ?lter at the output of the decimation ?lter. 9.1.4 overload detection an overload detection circuit will inform the user whenever the input voltage exceeds the maximum input voltage, which will lead to a high distortion. in that case, the ovfl bit in the feature control/status register 1 (0x6a) is set. in addition, an interrupt is generated on the irqout pin of the ucb1400 whenever the ovlp bit or the ovln bit is set in the positive and/or negative int enable registers. 9.2 interpolation ?lter (dac) the digital interpolation ?lter interpolates from 1 fs to 128 fs by means of a cascade of fir ?lters. the ?lter characteristics are shown in ta b l e 7 . 9.2.1 dsp features the ucb1400 supports the following dsp (digital sound processing) features through the feature control/status register 1 (0x6a): ? tone control: bass boost (bb[3:0]) and treble boost (tr[1:0]) ? flat/minimum/maximum setting for bass and treble boost (m[1:0]) ? de-emphasis control (de bit) in addition, the ucb1400 supports volume control and soft muting via the master volume register (0x02): ? master volume control: the output level can be attenuated in 1.5 db steps down to - 94.5 db independently for the left and right channels via the master volume register (0x02). ? mute: the output is muted when the mm bit in the master volume register is set. muting the dac will result in a cosine roll-off soft mute, using 128 samples in the normal mode: this results in 3 ms at fs = 44.1 khz. 9.2.2 noise shaper the 3rd-order noise shaper operates at 128 fs. it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter (fsdac). table 7: interpolation ?lter characteristics item condition value (db) pass-band ripple 0 to 0.45 fs 0.025 stop band > 0.55 fs - 65 dynamic range 0 to 0.45 fs > 135
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 23 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 9.2.3 filter stream dac the fsdac is a semi-digital reconstruction ?lter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the ?lter coef?cients are implemented as current sources and are summed at virtual ground of the output operational ampli?er. in this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post-?lter is not needed due to the inherent ?lter function of the dac. on-board ampli?ers convert the fsdac output current to an output voltage signal capable of driving a line output. the output voltage of the fsdac scales proportionally with the power supply voltage. 9.2.4 headphone driver the headphone driver a reference output that acts as the virtual ground. this allows direct connection to a stereo headphone without the use of external dc blocking capacitors. the headphone driver is enabled when hpen is set to 1 in the feature control/status register 1 (0x6a). the headphone driver is equipped with a short circuit protection on each of the line_out_l, line_out_r and vrefdrv output. when hpen = 1, the short circuit protection circuit will inform the user in case the limiter is activated, e.g., in case of short circuit, by setting the corresponding bit (clpl, clpr or clpg) in the extra interrupt register (0x70). in addition, an interrupt is generated on the irqout pin of ucb1400 whenever the clpp or clpn bit is set in the positive and/or negative int enable registers. in that case, the cpls bit will be set in the int clear/status register (index 0x62). the user can subsequently examine the extra interrupt register (0x70) to determine the source of the short circuit. fig 16. headphone connections. ucb1400 line_out_l vrefdrv line_out_r sn00228
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 24 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 9.3 loopback mode the audio codec incorporates a loopback mode, in which codec input path and output path are connected in series. it is activated when the lpbk bit in the general purpose register (0x20) set. the loopback internally connects the digital output from the decimator of the adc to the digital input of the interpolator of the dac, allowing for codec testing without the use of the ac link. 9.4 pll and sample rates the audio sample rate is derived from the 24.576 mhz crystal clock for 8, 12, 16, 24, 32, and 48 khz sample rates, and from the built-in pll for 11.025, 22.05 and 44.1 khz sample rates. the adc and dac can run at independent sample rates and are controlled by the adc and dac sample rate registers (0x32 and 0x2c). 9.5 power-down modes the audio input and output paths can be powered down independently; the input path is powered down when the pr0 bit in the power-down control/status register (0x26) is set. the output path is disabled when the pr1 bit of the same register is set. this provides the user the means to reduce the current consumption of ucb1400 if one part of the audio codec is not used in the application. when both the input and output paths are disabled, the pr3 bit of the same register can also be set to turn off the audio reference to further reduce power consumption. if the smart low power bits (slp0 and slp1) are set in the feature control/status register 2 (0x6c), the ucb1400 will power down unused blocks in the audio adc analog front end and the pll in a smart way, ensuring the lowest power consumption in each audio operating mode.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 25 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 10. touch screen interface 10.1 universal touch screen matrix the ucb1400 contains a universal touch screen interface for 4-wire resistive touch screen, capable of performing position, pressure and plate resistance measurements. in addition, the touch screen can be programmed to generate interrupts when the touch screen is pressed. the last mode is also active when the ucb1400 is set in the stand-by mode. the touch screen interface connects to the touch screen by four wires: tspx, tsmx, tspy and tsmy. each of these pins can be programmed to be ?oating, powered or grounded in the touch screen switch matrix. the setting of each touch screen pin is programmable by the pxp, mxp, pyp, myp and pxg, myg, pyg, myg bits in the touch screen control register. possible con?icting settings (grounding and powering of a touch screen pin at the same time) are detected by the ucb1400. in that case, the ucb1400 will ground the touch screen pin. each of the four touch screen signals can be selected as input for the built-in 10-bit adc, which is used to determine the voltage on the selected touch screen pin in position measurement mode. in addition, the ucb1400 can monitor touch screen current via an internal 1 k w resistor that can act as the input to the 10-bit adc in pressure or plate resistance measurement mode. the ?exible switch matrix and the multi-functional touch screen bias circuit enable the user of the ucb1400 to set each desired touch screen con?guration. fig 17. block diagram of the touch screen interface. sn00246 tspx tsmx tspy tsmy ad[3:0] av ss 1 k w 7:4 0 1 2 3 analog mux 01 analog mux touch screen current monitor av dd tm[1:0]=00 touch screen bias voltage av ss bias tm[1:0] = 01 to adc input ai[2:0] tm[1:0] = 00 or 1x pxp, mxp, pyp, myp pxg, mxg, pyg, myg
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 26 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. the ucb1400s internal voltage reference (v ref ) acts as the reference voltage for the touch screen bias circuitry. this makes the touch screen biasing independent of supply voltage and temperature variations. four low pass ?lters, one on each touch screen terminal, are built in to minimize the noise coupled from the lcd into the touch screen signals. an lcd typically generates large noise glitches on the touch screen, since they are closely coupled. the setting of the touch screen bias circuitry and the adc multiplexer is determined by the setting of tm[1:0] in the touch screen control register according to ta b l e 8 . 10.2 operational modes the ucb1400 supports three modes of touch screen measurements: position, pressure, and plate resistances. additionally, an interrupt mode is provided for detection of touch events. 10.2.1 position measurement two position (x, y) measurements are needed to determine the location of the pressed spot. the x plate is biased during the x position measurement and the voltage on one or both y terminals (tspy, tsmy) is measured. the circuit can be represented by a potentiometer, with the tspy and/or tsmy electrode being the wiper. the measured voltage on the tspy/tsmy terminal is proportional to the x position of the pressed spot of the touch screen. in the y position mode, the x plate and y plate terminals are interchanged, thus the y plate is biased and the voltage on the tspx and/or tsmx terminal is measured. table 8: touch screen mode selection tm[1:0] selected mode touch screen bias source adc multiplexer setting 00 interrupt resistor to av dd de?ned by ai[2:0] 01 pressure touch screen bias circuit touch screen current monitor 10 position touch screen bias circuit de?ned by ai[2:0] 11 position touch screen bias circuit de?ned by ai[2:0] fig 18. touch screen setup for x position measurement. tspy tsmx tspx vbias to adc tsmy to adc tspy tspx vbias tsmy tsmx touch r y1 r y2 r t r x1 r x2 sn00247
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 27 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 10.2.2 pressure measurement the pressure applied to the touch screen can be determined. in fact, the contact resistance between the x and y plates is measured, which is a good indication of the size of the pressed spot and the applied pressure. a soft stylus, e.g., a ?nger, leads to a rather large contact area between the two plates when a large pressure is applied. a hard stylus, e.g., a pen, leads to less variation in measured contact resistance since the contact area is rather small. one plate is biased at one or both terminals during this pressure measurement, whereas the other plate is grounded, again on one or both terminals. the current ?owing through the touch screen is a direct indication for the resistance between both plates. a compensation for the series resistance, formed by the touch screen plates and the internal 1 k w resistance of the ucb1400 will improve the accuracy of this measurement. fig 19. touch screen setup for pressure-1 measurement (see table 9 ). tspy tsmx tspx vbias to adc tsmy to adc tspy tspx vbias tsmy tsmx touch r y1 r y2 r t r x1 r x2 sn00248 vbias 1 k w 1 k w vbias
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 28 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 10.2.3 plate resistance measurement the plate resistance of a touch screen varies a lot due to processing spreads. knowing the actual plate resistance makes it possible to compensate for the plate resistance effects in the pressure resistance measurements. secondly, the plate resistance decreases when two or more spots on the touch screen are pressed. in that case, a part of one plate, e.g., the x plate, is shorted by the other plate, which decreases the actual plate resistance. the plate resistance measurement is executed in the same way as the pressure resistance measurement. in this case, only one of the two plates is biased, and the other plate is kept ?oating. the current through the connected plate is again a direct indication of the connected resistance. 10.2.4 interrupt mode fig 20. touch screen setup for x plate resistance measurement. tspy tsmx tspx vbias to adc tsmy tspy tspx vbias tsmy to adc r y1 r y2 r t r x1 r x2 sn00249 1 k w 1 k w tsmx fig 21. touch screen setup for interrupt detection. tspy tsmx tspx tsmy tspy tspx tsmy r y1 r y2 r t r x1 r x2 sn00250 tsmx touch r int schmitt trigger schmitt trigger av dd av dd r int
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 29 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. in addition to the measurements made above, the touch screen can also act as an interrupt source. in this mode, the x plate of the touch screen has to be powered, and the y plate has to be grounded. in this case, the touch screen is not biased by the active touch screen bias circuit, but by a resistor to av dd . this con?guration simply biases the touch screen and the ucb1400 does not consume power unless the touch screen is touched. the voltage on the x plate terminals drops if the screen is pressed. this voltage drop is detected by schmitt trigger circuits, of which the outputs are connected to the interrupt control block. a touch screen interrupt is generated either when the touch screen is pressed (falling edge enabled) or when the touch screen is released (rising edge enabled), which can be used to activate the system around the ucb1400 to start a touch screen readout sequence. the internal schmitt trigger circuits are connected to the tspx and tsmx signals after the built-in low-pass ?lters. this reduces the number of spurious interrupts, due to the coupling between the lcd screen and the touch screen sensors. 10.2.5 mode summary [1] for x and y position measurements, (pxp, pxg, pyp, pyg) can be swapped with (mxp, mxg, myp, myg) to get readings reversed in direction. [2] for pressure measurements, (pxp, pxg, pyp, pyg) can be swapped with (mxp, mxg, myp, myg) to get the same readings with current ?owing in the opposite direction. table 9: measurement mode summary touch screen measurement pxp pxg mxp mxg pyp pyg myp myg bias tm ai x position [1] 10010000122 or 3 y position [1] 00001001120 or 1 pressure - 1 [2] 1010010111any pressure - 2 [2] 1000010011any pressure - 3 [2] 0001100011any pressure - 4 [2] 0010000111any pressure - 5 [2] 0100001011any x plate resistance 1001000011any y plate resistance 0000100111any interrupt 1010010100any
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 30 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 11. 10-bit adc the ucb1400 includes a 10-bit successive approximation analog-to-digital converter (adc) with built-in track-and-hold circuitry, and an analog multiplexer to select one of the four analog inputs (ad0-3), the four touch screen inputs (tspx, tsmx, tspy, tsmy) or the current of the touch screen bias circuit. the analog multiplexer contains four resistive dividers to attenuate the high voltages on the ad0-3 inputs to the adc input range. the adc is controlled through the ac 97 interface, but the ucb1400 contains internal logic to ease the control of the adc and to minimize the number of ac 97 frame read/write actions. the adc is activated by the ae bit in the adc control register (0x66). the adc circuitry, including the track and hold circuitry does not consume any power as long as this bit is reset. the analog input multiplexer is controlled by the ai[2:0] bits and the adc is actually started with the as bit in the adc control register (0x66). a complete adc control sequence consists of several phases. first the adc has to be enabled; secondly, the input selector must be set to the proper input; thirdly, the adc conversion has to be started; and ?nally, the adc result has to be read from the adc data register (0x68). the ucb1400 has two different modes to start the adc conversion, which are selected by the ase bit in the adc control register (0x66). when ase is 0, the adc conversion is started directly by writing a 1 in the as bit. if the ave bit in the feature/control status register 2 (0x6c) is set to 1, additional ?ltering is applied to the adc data, making it more immune to high frequency ?uctuations in a noisy environment. fig 22. block diagram of the 10-bit adc circuit. input mux ad0 ad1 ad2 ad3 tspx tsmx tspy tsmy bias current internal reference track and hold ae 10-bit adc adc start/stop logic clock adcsync as ai[2:0] tm[1:0] ad[9:0] sn00240
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 31 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. when ase is 1, the adc is started at a rising edge of the signal applied to the adcsync pin. in this mode, writing 1 to the as bit will arm the adc, such that it will start in the ?rst detected rising edge of the adcsync signal. a rising edge of the signal connected to the adcsync pin occurring during the tracking time is ignored; the adc conversion is started on the ?rst rising edge detected after this delay time. this mode is particularly useful when the internal adc has to be synchronized to the external system. note that the ave bit should not be set to 1 when ase is 1. the result of the conversion is stored in the adc data register (0x68), after the completion of the conversion. an interrupt may be generated whenever a conversion is completed (adcp and/or adcn bits in the positive and negative int enable registers) to ease the synchronization between the ucb1400 and the system controller. the adv bit in the adc data register 0x68 indicates the status of the adc data; it equals 0 when an adc sequence is started, which implies that the adc result is not valid, and it equals 1 when the adc conversion is completed and the result is stored in the adc data register (0x68). the applied voltage on the four analog inputs of the ucb1400 (ad0-ad3) is attenuated before it is applied to the adc input multiplexer using on-chip resistive dividers. these high voltage inputs are optimized to handle voltages larger than the used supply voltage. the built-in resistive voltage dividers are only activated if the corresponding analog input is selected. the resistive dividers are made ?oating when the input is not selected by the adc input multiplexer, such that the input leakage of these high voltage analog pins is minimized. this makes these analog inputs very suitable to monitor battery voltages. 11.1 on-chip reference circuit the ucb1400 contains an on-chip reference voltage source, which generates the reference voltage for the 10-bit adc and touch screen bias. the internal bandgap circuit is activated if the 10-bit adc or touch screen function is activated. this reduces the current consumption of the ucb1400 in standby mode. the internal reference voltage is connected to the vrefbyp pin, where an external capacitor can be connected to ?lter this reference voltage, if the vrefb bit (register 0x66) is set to 1. fig 23. ad0-ad3 resistive dividers block diagram. ad[n] adc input mux ai[2:0] sn00241
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 32 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12. register de?nition the following tables describe the register de?nition for the ucb1400. the ucb1400 shall follow the ac 97 2.1 interoperability requirements and recommendations as follows: ? non-implemented or reserved register bits: all reserved or non-implemented register bits (marked x in the tables) are required to return 0 when read. ? non-implemented addresses: read access to non-implemented registers are required to echo a valid 7-bit register address in input slot 1 and return valid 0x0000 data in input slot 2 on the next ac-link frame. ? odd register addresses: read (and write) access to odd register addresses are required to be treated the same as non-implemented addresses, instead of aliasing them to the next lower even-numbered register. ? codec register read data need to be returned in the next ac-link frame following the frame in which the read request occurs. ? codec-ready and audio dac/adc status bits shall only change from ready to not ready in response to a pr state change issued by the controller to the power-down control/status registers 0x26. this guarantees that once data is actively ?owing on a slot, the controller does not have to continuously read the power-down control/status register to detect any unexpected codec pr status change.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. product data rev. 02 21 june 2002 33 of 63 table 10: register de?nitions shaded registers are read-only. reg (hex) name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default (hex) 00 reset x x x x x x id9 x id7 x id5 x x x x x 02a0 02 master volume mm x ml5 ml4 ml3 ml2 ml1 ml0 x x mr5 mr4 mr3 mr2 mr1 mr0 8000 04-0c reserved x x x x x x x x x x x x x x x x x 0e mic volume x x x x x x x x x 20db x x x x x x 0000 10-18 reserved x x x x x x x x x x x x x x x x x 1a record select x x x x x sl2 sl1 sl0 x x x x x sr2 sr1 sr0 0000 1c record gain rm x x x gl3 gl2 gl1 gl0 x x x x gr3 gr2 gr1 gr0 8000 1e reserved x x x x x x x x x x x x x x x x x 20 general purpose x x x x x x x x lpbk x x x x x x x 0000 1e-24 reserved x x x x x x x x x x x x x x x x x 26 power-down control/status x x pr5 pr4 pr3 x pr1 pr0 x x x x ref x dac adc 000x 28 extd audio id id1 id0 x x x x x x x x x x x x x vra 0001 2a extd audio status/control x x x x x x x x x x x x x x x vra 0000 2c audio dac rate dr15 dr14 dr13 dr12 dr11 dr10 dr9 dr8 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 bb80 2e-30 reserved x x x x x x x x x x x x x x x x x 32 audio adc rate ar15 ar14 ar13 ar12 ar11 ar10 ar9 ar8 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 bb80 34-58 reserved x x x x x x x x x x x x x x x x x 5a io data x x x x x x io9 io8 io7 io6 io5 io4 io3 io2 io1 io0 0000 5c io direction x x x x x x iod9 iod8 iod7 iod6 iod5 iod4 iod3 iod2 iod1 iod0 0000 5e positive int enable ovlp clpp tmxp tpxp adcp x iop9 iop8 iop7 iop6 iop5 iop4 iop3 iop2 iop1 iop0 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. product data rev. 02 21 june 2002 34 of 63 60 negative int enable ovln clpn tmxn tpxn adcn x ion9 ion8 ion7 ion6 ion5 ion4 ion3 ion2 ion1 ion0 0000 62 int clear/status ovls clps tmxs tpxs adcs x ios9 ios8 ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 0000 64 touch screen control x x mx px bias hysd tm1 tm0 pyg myg pxg mxg pyp myp pxp mxp 0000 66 adc control ae x x x x x x x as x exven ai2 ai1 ai0 vrefb ase 0000 68 adc data adv x x x x x ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 0000 6a feature csr1 x bb3 bb2 bb1 bb0 tr1 tr0 m1 m0 hpen de dc hips gien x ovfl 0000 6c feature csr2 smt suev 1 suev 0 ave aven 1 aven 0 x x x x slp1 slp0 x ev2 ev1 ev0 0000 6e test control x x x x x x x x x tm6 tm5 tm4 tm3 tm2 tm1 tm0 xxxx 70 extra interrupt clpl clpr clpg x x x x x x x x x x x x x 0000 7a reserved x x x x x x x x x x x x x x x x x 7c vendor id1 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 5053 7e vendor id2 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 4304 table 10: register de?nitions continued shaded registers are read-only. reg (hex) name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default (hex)
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 35 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.1 reset register (index 0x00) writing any value to this register performs a register reset, which causes all registers to revert to their default values. 12.2 master volume register (index 0x02) table 11: reset register register address: 0x00; default: 02a0 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol x x x x x x id9 x bit d7 d6 d5 d4 d3 d2 d1 d0 symbol id7 x id5 x x x x x table 12: description of reset register bits bit symbol type description d15 - d10 x r reserved. d9 id9 r always 1 (20-bit adc resolution supported). d8 x r reserved. d7 id7 r always 1 (20-bit dac resolution supported). d6 x r reserved. d5 id5 r always 1 (loudness (bass boost) supported). d4 - d0 x r reserved. table 13: master volume register register address: 0x02; default: 8000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol mm x ml5 ml4 ml3 ml2 ml1 ml0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol x x mr5 mr4 mr3 mr2 mr1 mr0 table 14: description of master volume register bits bit symbol type description d15 mm rw master mute. d14 x r reserved. d13 - d8 ml5 - ml0 rw left channel attenuation in 1.5 db step (000000 = 0 db; 111111 = - 94.5 db). d7 - d6 x r reserved. d5 - d0 mr5 - mr0 rw right channel attenuation in 1.5 db step (000000 = 0 db; 111111 = - 94.5 db).
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 36 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.3 mic volume register (index 0x0e) 12.4 record select register (index 0x1a) table 15: mic volume register register address: 0x0e; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol xxxxxxxx bit d7 d6 d5 d4 d3 d2 d1 d0 symbol x 20db x x x x x x table 16: description of mic volume register bits bit symbol type description d15 - d7 x r reserved. d6 20db rw 20 db boost. d5 - d0 x r reserved. table 17: record select register register address: 0x1a; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol x x x x x sl2 sl1 sl0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol x x x x x sr2 sr1 sr0 table 18: description of record select register bits bit symbol type description d15 - d11 x r reserved. d10 - d8 sl2 - sl0 rw left record source (000 = mic; 100 = line in l; other values reserved). d7 - d3 x r reserved. d2 - d0 sr2 - sr0 rw right record source (000 = copy left; 100 = line in r; other values reserved). when sr = 000, the right record channel copies data from left record channel to create mono data and gain and sample rate control can only be made via the left channel. this mode is primarily intended when the mono mic input is selected at the left channel (sl = 000).
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 37 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.5 record gain register (index 0x1c) 12.6 general purpose register (index 0x20) the lpbk bit enables loopback of the adc output to the dac input without involving the ac-link, allowing for full system performance measurements. table 19: record gain register register address: 0x1c; default: 8000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol rm x x x gl3 gl2 gl1 gl0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol x x x x gr3 gr2 gr1 gr0 table 20: description of master volume register bits bit symbol type description d15 rm rw master record mute. d14 - d12 x r reserved. d11 - d8 gl3 - gl0 rw left channel record gain in steps of 1.5 db (0000 = 0 db; 1111 = 22.5 db). d7 - d4 x r reserved. d3 - d0 gr3 - gr0 rw right channel record gain in steps of 1.5 db (0000 = 0 db; 1111 = 22.5 db). table 21: general purpose register register address: 0x20; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol xxxxxxxx bit d7 d6 d5 d4 d3 d2 d1 d0 symbol lpbk x x x x x x x table 22: description of general purpose register bits bit symbol type description d15 - d8 x r reserved. d7 lpbk rw adc/dac loopback mode (adc output to dac input). d6 - d0 x r reserved.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 38 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.7 power-down control/status register (index 0x26) this read/write register is used to program power-down states and monitor subsystem readiness. the lower half of this register is read only status, a 1 indicating that the subsection is ready. ready is de?ned as the subsection able to perform in its nominal state. when this register is written, the bit values that come in on ac-link will have no effect on read-only bits 0 - 7. when the codec ready indicator bit (sdata_in slot 0, bit 15) is a 1, it indicates that the ucb1400 control and status registers are in a fully operational state. the ac 97 controller must further probe this power-down control/status register to determine exactly which subsections, if any, are ready. table 23: power-down control/status register register address: 0x26; default: 000x bit d15 d14 d13 d12 d11 d10 d9 d8 symbol x x pr5 pr4 pr3 x pr1 pr0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol x x x x ref x dac adc table 24: description of power-down control/status register bits bit symbol type description d15 - d14 x r reserved. d13 pr5 rw internal clock disable. d12 pr4 rw digital interface (ac-link) power-down (external clock off). d11 pr3 rw audio v ref power-down. d10 x r reserved. d9 pr1 rw audio dac and output path power-down. d8 pr0 rw audio adc and input path power-down. d7 - d4 x r reserved. d3 ref r audio v ref up to nominal level. d2 x r reserved. d1 dac r audio dac section ready to accept data. d0 adc r audio adc section ready to transmit data.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 39 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.8 extended audio id register (index 0x28) the extended audio id is a read-only register that identi?es which extended audio features are supported (in addition to the original ac 97 features identi?ed by reading the reset register at index 0x00). 12.9 extended audio status and control register (index 0x2a) table 25: extended audio id register register address: 0x28; default: 0001 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol id1 id0 x x x x x x bit d7 d6 d5 d4 d3 d2 d1 d0 symbol x x x x x x x vra table 26: description of extended audio id register bits bit symbol type description d15 - d14 id1 - id0 r always 0 (ucb1400 is a primary codec). d13 - d1 x r reserved. d0 vra r always 1 (variable rate pcm audio supported). table 27: extended audio status and control register register address: 0x2a; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol xxxxxxxx bit d7 d6 d5 d4 d3 d2 d1 d0 symbol xxxxxxxvra table 28: description of extended audio status and control register bits bit symbol type description d15 - d1 x r reserved. d0 vra rw 1 enables variable rate audio mode (sample rate control registers and slotreq signalling).
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 40 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.10 audio sample rate control register (index 0x2c and 0x32) the sample rate control registers contain 16-bit unsigned values between 0 and 65535, representing the rate of operation in hz. ta b l e 3 1 shows the sample rates supported by ucb1400. in vra mode (vra = 1 in register 0x2a), if the value written to the register is supported, that value will be echoed back when read, otherwise the closest (higher in case of a tie) sample rate supported is returned. the ucb1400s dac and adc are capable of operating at independent rates. in non-vra mode (vra = 0 in register 0x2a), the only supported sample rate is 48 khz. table 29: audio dac sample rate control register register address: 0x2c; default: bb80 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol dr15 dr14 dr13 dr12 dr11 dr10 dr9 dr8 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 table 30: audio adc sample rate control register register address: 0x32; default: bb80 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol ar15 ar14 ar13 ar12 ar11 ar10 ar9 ar8 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 table 31: supported sample rates sample rate (mhz) d15 - d0 8000 1f40 11025 2b11 12000 2ee0 16000 3e80 22050 5622 24000 5dc0 32000 7d00 44100 ac44 48000 bb80
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 41 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.11 io data register (index 0x5a) 12.12 io direction register (index 0x5c) table 32: io data register register address: 0x5a; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol x x x x x x io9 io8 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol io7 io6 io5 io4 io3 io2 io1 io0 table 33: description of io data register bits bit symbol type description d15 - d10 x r reserved. d9 - d0 io9 - io0 rw when read, this register returns the actual state of all io pins. when written, each register bit will be transferred to the corresponding io pin programmed as output. table 34: io direction register register address: 0x5c; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol x x x x x x iod9 iod8 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol iod7 iod6 iod5 iod4 iod3 iod2 iod1 iod0 table 35: description of io direction register bits bit symbol type description d15 - d10 x r reserved. d9 - d0 iod9 - iod0 rw if a bit is 1, the associated io pin is de?ned as output. if a bit is 0, the associated io pin is de?ned as input.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 42 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.13 positive int enable register (index 0x5e) 12.14 negative int enable register (index 0x60) table 36: positive int enable register register address: 0x5e; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol ovlp clpp tmxp tpxp adcp x iop9 iop8 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol iop7 iop6 iop5 iop4 iop3 iop2 iop1 iop0 table 37: description of positive int enable register bits bit symbol type description d15 ovlp rw if 1, the rising edge interrupt of the ovfl signal is enabled. d14 clpp rw if 1, the rising edge interrupt of the clip signal is enabled. d13 tmxp rw if 1, the rising edge interrupt of the tsmx signal is enabled. d12 tpxp rw if 1, the rising edge interrupt of the tspx signal is enabled. d11 adcp rw if 1, the rising edge interrupt of adc ready is enabled. d10 x r reserved. d9 - d0 iop9 - iop0 rw if a bit is 1, the rising edge interrupt of the associated io pin is enabled. table 38: negative int enable register register address: 0x60; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol ovln clpn tmxn tpxn adcn x ion9 ion8 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol ion7 ion6 ion5 ion4 ion3 ion2 ion1 ion0 table 39: description of negative int enable register bits bit symbol type description d15 ovln rw if 1, the falling edge interrupt of the ovfl signal is enabled. d14 clpn rw if 1, the falling edge interrupt of the clip signal is enabled. d13 tmxn rw if 1, the falling edge interrupt of the tsmx signal is enabled. d12 tpxn rw if 1, the falling edge interrupt of the tspx signal is enabled. d11 adcn rw if 1, the falling edge interrupt of adc ready is enabled. d10 x r reserved. d9 - d0 ion9 - ion0 rw if a bit is 1, the falling edge interrupt of the associated io pin is enabled.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 43 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.15 int clear/status register (index 0x62) 12.16 touch screen control register (index 0x64) table 40: int clear/status register register address: 0x62; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol ovls clps tmxs tpxs adcs x ios9 ios8 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 table 41: description of int clear/status register bits bit symbol type description d15 ovls rw when read, returns the ovfl interrupt status. cleared by writing 1 to this bit. d14 clps rw when read, returns the clip interrupt status. cleared by writing 1 to this bit. d13 tmxs rw when read, returns the tsmx interrupt status. cleared by writing 1 to this bit. d12 tpxs rw when read, returns the tspx interrupt status. cleared by writing 1 to this bit. d11 adcs rw when read, returns the adc ready interrupt status. cleared by writing 1 to this bit. d10 x r reserved. d9 - d0 ios9 - ios0 rw when read, returns all io pin interrupt status. the interrupt status of a pin is cleared by writing 1 to the corresponding bit. table 42: touch screen control register register address: 0x64; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol x x mx px bias hysd tm1 tm0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol pyg myg pxg mxg pyp myp pxp mxp table 43: description of touch screen control register bits bit symbol type description d15 - d14 x r reserved. d13 mx r state of the tsmx pin. 0 = low voltage (pen down) 1 = high voltage (pen up) d12 px r state of the tspx pin. 0 = low voltage (pen down) 1 = high voltage (pen up) d11 bias rw if 1, the touch screen bias circuitry is activated. if 0, the touch screen bias is disabled to minimize power consumption.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 44 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.17 adc control register (index 0x66) d10 hysd rw if 1, hysteresis is deactivated on the schmitt triggers. d9 - d8 tm1 - tm0 rw touch screen operation mode 00 = interrupt mode 01 = pressure measurement mode 1x = position measurement mode d7 pyg rw if 1, the tspy pin is grounded. d6 myg rw if 1, the tsmy pin is grounded. d5 pxg rw if 1, the tspx pin is grounded. d4 mxg rw if 1, the tsmx pin is grounded. d3 pyp rw if 1, the tspy pin is powered. d2 myp rw if 1, the tsmy pin is powered. d1 pxp rw if 1, the tspx pin is powered. d0 mxp rw if 1, the tsmx pin is powered. table 43: description of touch screen control register bits continued bit symbol type description table 44: adc control register register address: 0x66; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol aexxxxxxx bit d7 d6 d5 d4 d3 d2 d1 d0 symbol as x exven ai2 ai1 ai0 vrefb ase table 45: description of adc control register bits bit symbol type description d15 ae rw if 1, adc is activated. if 0, adc is powered-down. d14 - d8 x r reserved. d7 as rw writing 1 starts the adc conversion sequence. this bit self-clears. d6 x r reserved. d5 exven r/w must be set to 0 (other values reserved for testing purposes only). d4 - d2 ai2 - ai0 rw adc input selection: 000 = tspx 001 = tsmx 010 = tspy 011 = tsmy 100 = ad0 101 = ad1 110 = ad2 111 = ad3
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 45 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.18 adc data register (index 0x68) d1 vrefb r/w vref bypass. if 1, the internal reference voltage is connected to vrefbyp pin. d0 ase rw if 1, adc is armed by the as bit and started by a rising edge on the adcsync pin. if 0, adc is started by the as bit. table 45: description of adc control register bits continued bit symbol type description table 46: adc data register register address: 0x68; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol adv x x x x x ad9 ad8 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 table 47: description of adc data register bits bit symbol type description d15 adv r 0 if adc conversion is in progress. 1 if the adc conversion is completed and the adc data is stored in ad9 - ad0. d14 - d10 x r reserved. d9 - d0 ad9 - ad0 r adc data.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 46 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.19 feature control/status register 1 (index 0x6a) table 48: feature control/status register 1 register address: 0x6a; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol x bb3 bb2 bb1 bb0 tr1 tr0 m1 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol m0 x de dc hips gien x ovfl table 49: description of feature control/status register 1 bits bit symbol type description d15 x r reserved. d14 - d11 bb3 - bb0 rw bass boost bb m = flat (db) m = min. (db) m = max. (db) 0-9 0 2*bb 2*bb 10-12 0 18 2*bb 13-15 0 18 24 d10 - d9 tr1 - tr0 rw treble boost tr m = flat (db) m = min. (db) m = max. (db) 0-3 0 2*tr 2*tr d8 - d7 m1 - m0 rw mode 00 = ?at 01 = minimum 10 = minimum 11 = maximum d6 hpen rw if 1, headphone driver is enabled. d5 de rw if 1, de-emphasis is enabled when the sample rate is 48, 44.1 or 32 khz. d4 dc rw if 1, dc ?lter is enabled. d3 hips r if 1, activate high-pass ?lter in the decimator. d2 gien rw if 1, the following interrupt/wake-up signalling is enabled: ? interrupt signalling via gpio_int (input slot 12) when bit_clk is on. ? wake-up signalling via sdata_in when bit_clk is off. d1 x r reserved. d0 ovfl rw when read, returns adc over?ow status (set status is sticky until cleared). when written, clears adc over?ow status.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 47 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.20 feature control/status register 2 (index 0x6c) table 50: feature control/status register 2 register address: 0x6c; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol smt suev1 suev0 ave aven1 aven0 x x bit d7 d6 d5 d4 d3 d2 d1 d0 symbol x x slp1 slp0 x ev2 ev1 ev0 table 51: description of feature control/status register 2 bits bit symbol type description d15 smt rw must be set to 0 (other values reserved for testing purposes only). d14 - d13 suev1 - suev0 rw must be set to 0 (other values reserved for testing purposes only). d12 ave rw if 1, adc filter is enabled. d11 - d10 aven1 - aven0 rw must be set to 0 (other values reserved for testing purposes only). d5 - d4 slp1 - slp0 rw ? 0: no smart low power mode. on normal mode operation, all codec input blocks and pll are on. ? 1: smart low power mode on the codec only . on normal mode operation, only used input stage(s) is/are on. pll remains on all the time. ? 2: smart low power mode on the pll only . on normal mode operation, pll is on only when a sample rate equal to 11.025, 22.05, or 44.1 khz is selected and the corresponding audio adc or dac is not in power-down mode. codec input blocks are always on. ? 3: smart low power mode on both codec and pll. d2 - d0 ev2 - ev0 rw must be set to 0 (other values reserved for testing purposes only).
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 48 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.21 test control register (index 0x6e) this register cannot be reset and is not scan testable. it has no effect until the ucb1400 is put in vendor-speci?c test mode (refer to section 8.7.2 ). 12.22 extra interrupt register (index 0x70) table 52: test control register register address: 0x6e; default: xxxx bit d15 d14 d13 d12 d11 d10 d9 d8 symbol xxxxxxxx bit d7 d6 d5 d4 d3 d2 d1 d0 symbol x tm6 tm5 tm4 tm3 tm2 tm1 tm0 table 53: description of test control register bits bit symbol type description d15 - d7 x r reserved. d6 - d0 tm6 - tm0 rw test mode. reserved for testing purposes only. table 54: extra interrupt register register address: 0x70; default: 0000 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol clpl clpr clpg x x x x x bit d7 d6 d5 d4 d3 d2 d1 d0 symbol xxxxxxxx table 55: description of adc data register bits bit symbol type description d15 clpl rw status of the clipl (line_out_l short circuit) signal; write 1 to clear. d14 clpr rw status of the clipr (line_out_r short circuit) signal; write 1 to clear. d13 clpg rw status of the clipgnd (vrefdrv short circuit) signal; write 1 to clear. d12 - d0 x r reserved.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 49 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 12.23 vendor id1 and id2 registers (index 0x7c and 0x7e) table 56: vendor id1 register register address: 0x7c; default: 5053 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol 0 1 0 1 0 0 0 0 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol 0 1 0 1 0 0 1 1 table 57: vendor id2 register register address: 0x7e; default: 4304 bit d15 d14 d13 d12 d11 d10 d9 d8 symbol 0 1 0 0 0 0 1 1 bit d7 d6 d5 d4 d3 d2 d1 d0 symbol 0 0 0 0 0 1 0 0
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 50 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 13. limiting values 14. static characteristics table 58: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 4 v t stg storage temperature - 65 +125 c t amb operating ambient temperature - 40 +85 c v es electrostatic handling voltage equivalent to discharging a 100 pf capacitor via 1.5 k w series resistor - 1500 +1500 v table 59: static characteristics dv dd =av dd =v adcp = 3.3 v; t amb =25 c; all voltage measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply av dd analog supply voltage 3.0 3.3 3.6 v dv dd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current full audio, line-in selected - 18 - ma audio adc only, line-in selected - 12 - ma audio dac and headphone driver only - 13 - ma ac-link only - 7 - ma standby - 1 -m a i dda analog supply current full audio, line-in selected - 12 - ma audio adc only, line-in selected - 8 - ma audio dac and headphone driver only - 4.5 - ma touch screen bias only - 0.9 - ma 10-bit adc only - 1.8 - ma standby - 3 -m a digital input pins (5 v tolerant, ttl compatible) v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage - 0.5 - 0.8 v | i il | input leakage current -- 1 m a c i input capacitance -- 10 pf digital output pins v oh high-level output voltage i oh = - 2 ma 0.85 dv dd -- v v ol low-level output voltage i ol =2ma -- 0.4 v
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 51 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 15. dynamic characteristics table 60: dynamic characteristics dv dd =av dd =v adcp = 3.3 v; t amb =25 c; all voltage measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min typ max unit audio adc v adcp positive reference voltage - av dd - v v adcn negative reference voltage - 0.0 - v r il line input resistance - 10 - k w c il line input capacitance - 24 - pf r im mic input resistance - 10 - k w c im mic input capacitance - 24 - pf z micgnd impedance micgnd - v ssa -- 200 w v i(rms) fs input voltage (rms value) record gain = 0 db line inputs - 1.0 - v mic input 20 db = 0 - 1.0 - v 20 db = 1 - 0.1 - v d v i unbalance between channels - 0.1 - db total harmonic distortion plus noise-to-signal ratio; f s = 48 khz, line-in selected at - 3 db input -- 87 - db at - 60 db input; a-weighted -- 37 - db s/n signal-to-noise ratio; f s = 48 khz, line-in selected at zero input; a-weighted - 97 - db a cs channel separation; f s = 48 khz, line-in selected at 0 db input - 95 - db psrr power supply rejection ratio f ripple = 1 khz; v ripple =30mv (p-p) - 30 - db audio dac + headphone driver r l load resistance 16 32 - w c l load capacitance -- 30 pf v vrefdrv vrefdrv voltage - av dd /2 - v v o(rms) output voltage (rms value) at 0 db (fs) digital input r l =10k w - 1.0 - v p o output power at 0 db (fs) digital input r l =32 w - 25 - mw d v o unbalance between channels at 0 db (fs) digital input r l =10k w - <0.1 - db total harmonic distortion plus noise-to-signal ratio; f s =48khz at 0 db digital input, r l =32 w- - 40 - db at 0 db digital input, r l =10k w -- 80 - db at - 60 db digital input; a-weighted -- 32 - db s/n signal-to-noise ratio code = 0; a-weighted - 91 - db a cs channel separation r l =32 w- 54 - db psrr power supply rejection ratio r l =10k w ; f ripple = 1 khz; v ripple =30mv (p-p) - 58 - db thd ( n ) + s ---------------------------- - thd ( n ) + s ---------------------------- -
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 52 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. touch screen v i(bias) bias voltage position mode selected; no loading - 1.89 - v i max. touch screen current position mode selected 10 -- ma r i max. touch screen resistance to generate an interrupt interrupt mode selected -- 2500 w r gs ground switch on resistance -- 50 w r ps power switch on resistance -- 50 w voltage monitor adc res resolution - 10 - bits v i(ad0-ad3) full scale ad0-ad3 inputs - 7.5 - v z i input impedance - 77 - k w i li input leakage current v ad0 =v ad1 =v ad2 = v ad3 = 7.5 v -- 10 m a le d differential linearity error - 1 - lsb le i integral linearity error - 2 - lsb t en adc enable time t d(s) sampling delay non-synchronization mode (as = 0, ave = 0) 21 t clk_period -- synchronization mode; rising edge adcsync to sample moment (as = 1, ave = 0) 1 t clk_period - 3 t clk_period t conv total conversion time as = ave = 0 - 10 -m s t track tracking time - 2 -m s t adcsync high time adsync signal 81.4 ns oscillator f osc oscillator frequency - 24.576 - mhz table 60: dynamic characteristics continued dv dd =av dd =v adcp = 3.3 v; t amb =25 c; all voltage measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min typ max unit
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 53 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 16. ac link characteristics table 61: characteristics dv dd =av dd =v adcp = 3.3 v; t amb =25 c; all voltage measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min typ max unit cold/warm reset t rst_low reset active-low pulse width (ac link controller) 1.0 - - m s t rst2clk reset inactive to bit_clk start-up delay 162.8 ns t sync_high sync active-high pulse width (ac link controller) 1.0 - - m s t sync2clk sync inactive to bit_clk start-up delay 162.8 - - ns ac-link clocks bit_clk frequency - 12.288 - mhz t clk_period bit_clk period - 81.4 - ns bit_clk output jitter - - 750 ps t clk_high bit_clk high pulse width 36 40.7 45 ns t clk_low bit_clk low pulse width 36 40.7 45 ns sync frequency - 48.0 - khz t sync_period sync period - 20.8 - m s t sync_high sync high pulse width - 1.3 - m s t sync_low sync low pulse width - 19.5 - m s data setup and hold t co output delay from rising edge of bit_clk - - 15 ns t setup input setup to falling edge of bit_clk 10 - - ns t hold input hold from falling edge of bit_clk 10 - - ns trise clk bit_clk rise time - - 10 ns tfall clk bit_clk fall time - - 10 ns trise sync sync rise time - - 6 ns tfall sync sync fall time - - 6 ns trise din sdata_in rise time - - 10 ns tfall din sdata_in fall time - - 10 ns trise dout sdata_out rise time - - 6 ns tfall dout sdata_out fall time - - 6 ns ac-link low power mode t s2_pdown end of slot 2 to bit_clk, sdata_in low - 0.65 - m s ate test mode t setup2rst setup to trailing edge of reset (ac link controller) 15 - - ns t off rising edge of reset to hi-z delay - - 25 ns
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 54 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 17. timing diagrams fig 24. cold reset timing. fig 25. warm reset timing. fig 26. bit_clk and sync timing. t rst_low reset bit_clk sn00229 t rst2clk t sync_high sync bit_clk sn00230 t sync2clk t sync_high sync sn00231 t sync_low t sync_period t clk_high bit_clk t clk_low t clk_period
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 55 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 27. data output and input timing. fig 28. data rise and fall timing. bit_clk not to scale. fig 29. ac link low power timing. sn00232 t co bit_clk v ih v il v oh v ol sdata_out sdata_in sync t setup t hold bit_clk trise clk tfall clk sync trise sync tfall sync sdata_in trise din tfall din sdata_out trise dout tfall dout sn00233 sn00234 t s2_pdown sync bit_clk sdata_out sdata_in slot 1 slot 2 write to 0x26 data pr4
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 56 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 18. application information fig 30. ate test mode timing. sn00235 t setup2rst t off reset sdata_out sdata_in, bit_clk hi-z fig 31. typical application circuit. 37 39 40 41 43 44 45 46 47 48 4 7 26 33 42 16 15 14 13 gpio(0) gpio(1) gpio(2) gpio(3) gpio(4) gpio(5) gpio(6) gpio(7) gpio(8) gpio(9) dvss1 dvss2 avss1 avss2 avss3 ad(0) ad(1) ad(2) ad(3) 19 17 20 18 tsmy tspx tspy tsmx 2 xtl_in 3 xtl_out y1 12 adcsync 27 28 31 vref vadcp vadcn 21 22 23 24 micp micgnd line_in_l line_in_r 8 5 11 29 sdata_in sdata_out irqout 6 10 bit_clk sync 1 9 25 32 38 dvdd1 dvdd2 avdd1 avdd2 avdd3 35 36 34 line_out_l line_out_r vrefdrv ucb1400 24.576 mhz c16 33 pf c17 22 pf ad0 ad1 ad2 ad3 c15 0.1 uf c12 47 uf c11 47 uf c10 4.7 uf micp micgnd line_in_r line_in_l sdata_in sdata_out reset bit_clk sync c9 0.1 uf c8 0.1 uf c7 0.1 uf line_out_l line_out_r vrefdrv gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpio8 gpio9 sn00252 reset tsmy tspx tspy tsmx c14 47 uf adcsync irqout r2 0 w 30 vrefbyp c13 0.1 uf c4 0.1 uf c3 22 uf r1 10 w c2 22 uf +3.3 v dvdd c6 0.1 uf c5 0.1 uf +3.3 v avdd c1 22 uf
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 57 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. fig 32. application block diagram. sn00238 touch i/f mux 10-bit adc ac link i/o and control adcsync 2-channel 20-bit audio dac 2-channel 20-bit audio adc osc 24.576 mhz digital i/o general purpose i/o parts 3.3v headphones powered speakers cd player mic spare processor sdata_in sdata_out bit_clk reset sync irqout touch screen (resistive) power supply backup (lithium) main battery thermistor voltage reference
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 58 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 19. package outline fig 33. lqfp48 (sot313-2). unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 99-12-27 00-01-19 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 59 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 20. soldering 20.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 20.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c small/thin packages. 20.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners.
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 60 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 20.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 20.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [4] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [5] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [6] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. table 62: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable [3] suitable plcc [4] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [4][5] suitable ssop, tssop, vso not recommended [6] suitable
philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor product data rev. 02 21 june 2002 61 of 63 9397 750 09611 ? koninklijke philips electronics n.v. 2002. all rights reserved. 21. revision history table 63: revision history rev date cpcn description 02 20020621 - product data; second version; engineering change notice 853-2358 28518; supersedes initial version ucb1400-01 of 03 jan 2002 (9397 750 09242). modi?cations: ? section 2 features modi?ed. ? section 9.2.4 headphone driver modi?ed. ? section 9.5 power-down modes modi?ed. ? section 13 limiting values modi?ed: added v es parameter. ? section 14 static characteristics modi?ed. ? section 15 dynamic characteristics modi?ed. ? section 16 ac link characteristics modi?ed. 01 20020103 - objective data; initial version.
9397 750 09611 philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor ? koninklijke philips electronics n.v. 2002. all rights reserved. product data rev. 02 21 june 2002 62 of 63 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 22. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. 23. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 24. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. data sheet status [1] product status [2] de?nition objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be publish ed at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a.
? koninklijke philips electronics n.v. 2002. printed in the u.s.a all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 21 june 2002 document order number: 9397 750 09611 contents philips semiconductors ucb1400 audio codec with touch screen controller and power management monitor 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . 5 8 ac 97 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 resetting ucb1400 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.3 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3.1 ac-link digital serial interface protocol . . . . . . . . . . . . 7 8.3.2 ac-link audio output frame (sdata_out). . . . . . . . . 8 8.3.3 ac-link audio input frame (sdata_in) . . . . . . . . . . . 10 8.3.4 ac-link low power mode. . . . . . . . . . . . . . . . . . . . . . 13 8.4 accessing the ucb1400 . . . . . . . . . . . . . . . . . . . . . 14 8.5 variable sample rate signaling protocol . . . . . . . . . . 16 8.5.1 slotreq protocol . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.6 wake-up support . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.7 test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.7.1 ate in-circuit test mode . . . . . . . . . . . . . . . . . . . . . . 17 8.7.2 vendor-speci?c test mode . . . . . . . . . . . . . . . . . . . . 17 8.8 general purpose ios . . . . . . . . . . . . . . . . . . . . . . . . 18 8.9 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 audio codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.1 adc analog front-end . . . . . . . . . . . . . . . . . . . . . . . 20 9.1.1 line inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.2 microphone input . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.3 decimation ?lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.1.4 overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2 interpolation ?lter (dac). . . . . . . . . . . . . . . . . . . . . . 22 9.2.1 dsp features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2.2 noise shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2.3 filter stream dac. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.4 headphone driver. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.3 loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.4 pll and sample rates . . . . . . . . . . . . . . . . . . . . . . . 24 9.5 power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . 24 10 touch screen interface . . . . . . . . . . . . . . . . . . . . . . . 25 10.1 universal touch screen matrix . . . . . . . . . . . . . . . . . 25 10.2 operational modes. . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.2.1 position measurement . . . . . . . . . . . . . . . . . . . . . . . 26 10.2.2 pressure measurement . . . . . . . . . . . . . . . . . . . . . . 27 10.2.3 plate resistance measurement. . . . . . . . . . . . . . . . . 28 10.2.4 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2.5 mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.1 on-chip reference circuit. . . . . . . . . . . . . . . . . . . . . . 31 12 register de?nition . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12.1 reset register (index 0x00). . . . . . . . . . . . . . . . . . . . 35 12.2 master volume register (index 0x02) . . . . . . . . . . . . 35 12.3 mic volume register (index 0x0e) . . . . . . . . . . . . . . 36 12.4 record select register (index 0x1a) . . . . . . . . . . . . . 36 12.5 record gain register (index 0x1c) . . . . . . . . . . . . . . 37 12.6 general purpose register (index 0x20) . . . . . . . . . . . 37 12.7 power-down control/status register (index 0x26). . . 38 12.8 extended audio id register (index 0x28) . . . . . . . . . 39 12.9 extended audio status and control register (index 0x2a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.10 audio sample rate control register (index 0x2c and 0x32). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.11 io data register (index 0x5a) . . . . . . . . . . . . . . . . . . 41 12.12 io direction register (index 0x5c). . . . . . . . . . . . . . . 41 12.13 positive int enable register (index 0x5e) . . . . . . . . 42 12.14 negative int enable register (index 0x60) . . . . . . . . 42 12.15 int clear/status register (index 0x62) . . . . . . . . . . . 43 12.16 touch screen control register (index 0x64) . . . . . . . 43 12.17 adc control register (index 0x66) . . . . . . . . . . . . . . 44 12.18 adc data register (index 0x68) . . . . . . . . . . . . . . . . 45 12.19 feature control/status register 1 (index 0x6a) . . . . 46 12.20 feature control/status register 2 (index 0x6c) . . . . 47 12.21 test control register (index 0x6e). . . . . . . . . . . . . . . 48 12.22 extra interrupt register (index 0x70) . . . . . . . . . . . . . 48 12.23 vendor id1 and id2 registers (index 0x7c and 0x7e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14 static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 50 15 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 51 16 ac link characteristics . . . . . . . . . . . . . . . . . . . . . . . 53 17 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 18 application information . . . . . . . . . . . . . . . . . . . . . . . 56 19 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 20 soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 20.1 introduction to soldering surface mount packages . . 59 20.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 20.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 20.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 20.5 package related soldering information . . . . . . . . . . . 60 21 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 22 data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 23 de?nitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 24 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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