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| r stel-1173 2 functional description the stel-1173 numerically controlled oscillator (nco) uses digital techniques to provide a cost- effective solution for low noise signal sources. the nco device combines low power 1.5 m cmos technology with a unique architectural design resulting in a power efficient, high-speed sinusoidal waveform generator able to achieve fine tuning resolution and exceptional spectral purity with clock frequencies up to 50 mhz. the nco generates digital sine or cosine functions of very precise frequency to be used directly in digital signal processing applications or, in conjunction with a d/a converter, in analog frequency generation applications. the nco is designed to interface with and be controlled from an 8-bit microprocessor bus. the nco maintains a record of phase which is accurate to 48 bits. at each clock cycle, the number stored in the 48 bit d -phase register is added to the previous value of the phase accumulator. the number in the phase accumulator represents the current phase of the synthesized sine and cosine functions. the number in the d -phase register represents the change of phase for each cycle of the clock. this number is directly related to the output frequency by the following: f c x d -phase f o = 2 48 where: f o is the frequency of the output signal and: f c is the clock frequency. features n 48-bit frequency resolution n 50 mhz clock frequency (0 to 70 c) n sine or cosine output available n 12-bit amplitude resolution and 13-bit phase resolution gives high spectral purity, all spurs stel-1173 4 function block description address select logic block this block controls the writing of data into the device via the data 7-0 inputs. the data is written into the device on the rising edge of the wrn input, and the register into which the data is written is selected by the addr 2-0 inputs. the writing of data is also controlled with the csn input; this input must be low to enable writing. buffer register block the buffer register is used to temporarily store the d - phase data written into the device. this allows the data to be written asynchronously as six bytes per 48-bit d - phase word. the data is transferred from this register into the d - phase register after a falling edge on the ldstb input. d -phase register block this block controls the updating of the d - phase word used in the accumulator. the frequency data from the buffer register block is loaded into this block after a falling edge on the ldstb input. the sync output, which indicates the instant of frequency change at the output at the end of the pipeline delay, is generated in this block. phase accumulator block this block forms the core of the nco function. it is a high-speed, pipelined, 48-bit parallel accumulator, generating a new sum in every clock cycle. a carry input ( carry in ) allows the resolution of the accumulator to be expanded by means of an auxiliary nco or phase accumulator. the overflow signal is discarded (and is available at the carry out pin), since the required output is the modulo (2 48 ) sum only. this represents the modulo (2 p ) phase angle. sine lookup table block this block is the sine memory. the 13 most significant bits from the phase accumulator are used to address this memory to generate the 12-bit out 11-0 outputs. input signals reset the reset input is asynchronous and active low. when reset goes low, all registers including the 48- bit input buffer are cleared within 30 nsecs. the data on the out 11-0 bus will then be invalid for 6 clock cycles, and thereafter will remain at the value corresponding to zero phase, i.e., 2049 (801h), until a new frequency is loaded into the d -phase register with a ldstb command after the reset returns to a logic one. circuit description the sine and cosine functions are generated from the 13 most significant bits of the phase accumulator. the frequency of the nco is determined by the number stored in the d -phase register which may be programmed by an eight-bit microprocessor. the frequency programming capability of the nco is analogous to sampling a sine wave where the sampling function is the clock. if the output frequency is very low with respect to the clock (< f c /8096), then the nco output will sequence through each of the 8096 states of the sine function. as the output frequency is increased with respect to the clock the sine function will appear to be more discontinuous since there will be fewer samples in each cycle. at the nyquist limit, when the output frequency is exactly half the clock, the output waveform reduces to a square wave. the practical upper limit of the nco output frequency is about 40% of the clock frequency because spurious components created by sampling, which are at a frequency greater than half the clock frequency, become difficult to remove by filtering. the phase noise of the nco output signal may be determined by knowing the phase noise of the clock signal input, and the ratio of the output frequency to the clock frequency. this ratio squared times the phase noise power of the clock specified in a given bandwidth is the phase noise power that may be expected in that same bandwidth relative to the output frequency. the nco achieves its high operating frequency by making extensive use of pipelining in its architecture. the pipeline delays within the nco represent 20 clock cycles. this effectively limits the minimum possible frequency switching period of the nco. after new frequency data is entered, the load command is given. after the 20 cycle pipeline delay, the output will instantaneously switch frequency while maintaining phase coherence. after this, the next new frequency may be entered. if a 50 mhz clock were utilized, the nco could be continuously switched between programmed frequencies with a minimum practical average switching time of about 0.4 m sec. 5 stel-1173 clock all synchronous functions performed within the nco are referenced to the rising edge of the clock input. the clock signal should be nominally a square wave at a maximum frequency of 50 mhz. a non- repetitive clock waveform is permissible as long as the minimum duration positive or negative pulse on the waveform is always greater than 8 nanoseconds. at each positive transition of the clock signal, the number stored in the d -phase register is added to the contents of the phase accumulator and the result is placed in the phase accumulator. wrn on the rising edge of the wrn input, the information on the 8-bit data bus is transferred to the buffer register selected by the addr 2-0 bus. csn the csn (chip select) input is active low and can be used to control the writing of data into the chip. when this input is high all data writing via the data 7-0 bus is inhibited. addr 2 through addr 0 the three address lines addr 2-0 control the use of the data 7-0 bus for writing frequency data to the d -phase buffer registers as shown in the table below: addr 2 addr 1 addr 0 d -phase register field 0 0 0 bits0 (lsb) C7 0 0 1 bits 8C15 0 1 0 bits 16C23 0 1 1 bits 24C31 1 0 0 bits 32C39 1 0 1 bits 40C47 (msb) to write to all 48 bits of the phase write registers, the data 7-0 bus must be used 6 times. note that it is not necessary to reload unchanged bytes, and that the byte loading sequence may be random. data 7 through data 0 the eight bit data 7-0 bus is used to program the 48- bit d -phase register. data 0 is the least significant bit of the bus. ldstb on the rising edge of the clock following the falling edge of the ldstb input, the information in the 48-bit buffer register is transferred to the d -phase register. the frequency of the nco output will change 20 clock cycles after the ldstb command due to pipelining delays. carry in normal operation of the nco requires that carry in be set at a logic 0. when carry in is a logic 1, the effective value of the d -phase register is increased by one. two ncos can be cascaded together to obtain 96 bits of frequency resolution by using the carry out of the lower order nco and the carry in of the higher order nco. twoscomp when the twoscomp input is set high, the data appearing on the out 11-0 bus is presented in two's complement code, and when it is set low, the data is presented in offset binary code. the limits of the data values in both codes is shown below: code ? offset binary 2's complement minimum value +1 (001 h ) C 2047 (801 h ) maximum value +4095 (fff h ) +2047 (7ff h ) mean value +2048 (800 h ) 0 (000 h ) both number formats produce sine or cosine waves which are symmetrical about the phase quadrant axis and the mean-value magnitude axis. sine when the sine input signal is set to a logic low level, the output signal appearing on the out 11-0 bus is the cosine of the 48-bit accumulators 13 most significant bits (bits 47-35, with 47 being the msb). normally set high, this signal allows the nco to generate either sine or cosine signals. by using two devices, one set in the sine mode and the other set in the cosine mode, quadrature outputs may be obtained. the quadrature phase relationship of the two outputs will be maintained at all times provided the two devices are reset simultaneously and operate from a common clock signal. a high level on the sine input sets the output to be the sine of the 48-bit accumulators 13 most significant bits. the value of the output for a given phase value follows the relationship: 2s comp = 2047 x sin (360 x phase) offset bin = 2047 x sin (360 x phase) +2048 the result is accurate to within 1 lsb. when this input is set low the output will be the cosine of the 48-bit accumulators 13 most significant bits. the value of the output for a given phase value follows the relationship: 2s comp = 2047 x cos (360 x phase) offset bin = 2047 x cos (360 x phase) +2048 again, accurate to within 1 lsb. stel-1173 6 electrical characteristics absolute maximum ratings warning: stresses greater than those shown below may cause permanent damage to the device. exposure of the device to these conditions for extended periods may also affect device reliability. all voltages are referenced to v ss . symbol parameter range units t stg storage temperature C40 to +125 c (plastic package) v ddmax supply voltage on v dd C0.3 to + 7 volts v i(max) input voltage C0.3 to v dd + 0.3 volts i i dc input current 10 ma recommended operating conditions symbol parameter range units v dd supply voltage +5 5% volts (commercial) t a operating temperature (ambient) 0 to +70 c (commercial) output signals out 11-0 the signal appearing on the out 11-0 bus is derived from the 13 most significant bits of the phase accumulator. the 12-bit sine or cosine function is presented in offset binary or two's complement format, depending on the status of the twoscomp input. when the phase accumulator is zero, e.g., after a reset, the decimal value of the output is 2049 in offset binary and 1 in two's complement. the nominal phase (in degrees) of the sine wave output may be determined at any point by multiplying the decimal equivalent of the 13 most significant bits of the phase accumulator by (360/8192) and then adding (360/16384). out 11 is the msb, and out 0 is the lsb. carry out each time the contents of the phase accumulator exceeds the maximum value that can be represented by a 48 bit number the carry out signal goes high for one clock cycle. sync the normally high sync output goes low for one clock cycle, 20 clock cycles after a ldstb command, to indicate the end of the pipeline delay and the start of the new steady state condition. 7 stel-1173 d.c. characteristics (operating conditions: v dd = 5.0 v 5%, vss = 0 v, t a = 0 to 70 c, commercial symbol parameter min. typ. max. units conditions i dd(q) supply current, quiescent 1.0 ma static, no clock i dd supply current, operational 3.0 ma/mhz v ih(min) high level input voltage standard operating conditions 2.0 volts logic '1' extended operating conditions 2.25 volts logic '1' v il(max) low level input voltage 0.8 volts logic '0' i ih(min) high level input current 10 35 110 m a cin and csel , v in = v dd i ih(min) high level input current 10 m a all other inputs, v in = v dd i il(max) low level input current C10 m a cin and csel , v in = v ss i il(max) low level input current C15 C45 C130 m a all other inputs, v in = v ss v oh(min) high level output voltage 2.4 4.5 volts i o = C4.0 ma v ol(max) low level output voltage 0.2 0.4 volts i o = +4.0 ma i os output short circuit current 20 65 130 ma v out = v dd , v dd = max C10 C45 C130 ma v out = v ss , v dd = max c in input capacitance 2 pf all inputs c out output capacitance 4 pf all outputs a.c. characteristics (operating conditions: v dd = 5.0 v 5%, vss = 0 v, t a = 0 to 70 c, commercial stel-1173 (commercial) symbol parameter min. max units conditions t rs reset pulse width 30 nsec. t sr reset to clock setup 10 nsec. t su data , addr or csel 18 nsec. to wrn setup, and ldstb to clock setup t hd data , addr or csel 12 nsec. to wrn hold, and ldstb to clock hold t ch clock high 8 nsec. f clk = max. t cl clock low 8 nsec. f clk = max. t w wrn or frld pulse width 20 nsec. t cd clock to output delay 5 10 nsec. load = 15 pf stel-1173 8 nco frequency change nco reset sequence reset clock out 11-0 801 h not valid 12345 5 clock edges t rs data 7-0 out 11-0 ldstb sync clock wrn csn addr 2-0 don't care don't care don't care 20 clock edges old frequency new frequency don't care t su t hd t wr t ch t cl t su t ls t cd 9 stel-1173 if the stel-1173 is combined with a suitable high-speed dac, signals with spectral purity of better than C65 dbc can be generated up to 10 mhz. in this way a signal can be generated in the 70 mhz band for use in a baseband downconverter tracking oscillator. the very high frequency resolution of the stel- 1173 allows the incoming signal to be tracked very closely and with minimal "hunting", resulting in low phase noise. the phase continuous frequency switching characteristics of the stel-1173 also make it suitable for use in frequency hopping spread spectrum applications. data ldstb reset d/a clk clk 66-74 mhz 12 stel- 1173 nco 50 mhz clock sine bpf 6-14 mhz addr 0-2 ? bpf 66-74 mhz 60 mhz oscillator 3 8 wr about C75 dbc. the highest output frequency the nco can generate is half the clock frequency (f c /2), and the spurious components at frequencies greater than f c /2 can be removed by filtering. as the output frequency f o of the nco approaches f c /2, the "image" spur at f c Cf o (created by the sampling process) also approaches f c /2 from above. if the programmed output frequency is very close to f c /2 it will be virtually impossible to remove this image spur by filtering. for this reason, the maximum practical output frequency of the nco should be limited to about 40% of the clock frequency. spectral purity in many applications the nco is used with a digital to analog converter (dac) to generate an analog waveform which approximates an ideal sinewave. the spectral purity of this synthesized waveform is a function of many variables including the phase and amplitude quantization, the ratio of the clock frequency to output frequency, and the dynamic characteristics of the dac. the signals generated by the stel-1173 have 12 bits of amplitude resolution and 13 bits of phase resolution which results in spurious levels which are theoretically typical application high purity, high resolution synthesizer stel-1173 10 a spectral plot of the nco output after conversion with a dac (sony cx20202a-1) is shown below. in this case, the clock frequency is 50 mhz and the output frequency is programmed to 6.789 mhz. this 10-bit dac gives better performance than any of the currently available 12-bit dacs at clock frequencies higher than 10 or 20 mhz. the maximum non- harmonic spur level observed over the output frequency range shown in this case is C74 dbc. the spur levels are limited by the dynamic linearity of the dac. it is important to remember that when the output frequency exceeds 25% of the clock frequency, the second harmonic frequency will be higher than the nyquist frequency, 50% of the clock frequency. when this happens, the image of the harmonic at the frequency f c C 2f o , which is not harmonically related to the output signal, will become intrusive since its frequency falls as the output frequency rises, eventually crossing the fundamental output when its frequency crosses through f c /3. it would be necessary to select a dac with better dynamic linearity to improve the harmonic spur levels. (the dynamic linearity of a dac is a function of both its static linearity and its dynamic characteristics, such as settling time and slew rates.) at higher output frequencies the waveform produced by the dac will have large output changes from sample to sample. for this reason, the settling time of the dac should be short in comparison to the clock period. as a general rule, the dac used should have the lowest possible glitch energy as well as the shortest possible settling time. typical spectrum center frequency: 6.7 mhz frequency span: 10.0 mhz reference level: C5 dbm resolution bandwidth: 1 khz video bandwidth: 3 khz scale: log, 10 db/div output frequency: 6.789 mhz clock frequency: 50 mhz ! " # ! ! ! $ ! !" #$% &'"()"* + $#%# $% &'"()"* + , -&'"()"* ((( |
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