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db14-000176-02 LSI53C1020 pci-x to ultra320 scsi controller technical manual june 2002 version 2.0
ii version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an of?er of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic of?er is prohibited. document db14-000176-02, version 2.0 (june 2002) this document describes the lsi logic corporations LSI53C1020 pci-x to ultra320 scsi controller and will remain the of?ial reference source for all revisions/releases of this product until rescinded by an update. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright 2001, 2002 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, fusion-mpt, integrated mirroring, lvdlink, sdms, surelink, and tolerant are trademarks or registered trademarks of lsi logic corporation. arm and multi-ice are registered trademarks of arm ltd., used under license. all other brand and product names may be trademarks of their respective companies. ap to receive product literature, visit us at http://www.lsilogic.com. for a current list of our distributors, sales of?es, and design resource centers, view our web page located at http://www.lsilogic.com/contacts/na_salesof?es.html
LSI53C1020 pci-x to ultra320 scsi controller iii version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. preface this book is the primary reference and technical manual for the LSI53C1020 pci-x to ultra320 scsi controller. it contains a functional description for the LSI53C1020 and the physical and electrical speci?ations for the LSI53C1020. audience this document assumes that you have some familiarity with microprocessors and related support devices. the people who bene? from this book are: ? engineers and managers who are evaluating the LSI53C1020 for use in a system ? engineers who are designing the LSI53C1020 into a system organization this document has the following chapters and appendix: ? chapter 1, introduction , provides an overview of the LSI53C1020 features and capabilities. ? chapter 2, functional description , provides a detailed functional description of the LSI53C1020 operation. this chapter describes how the LSI53C1020 implements the pci/pci-x and scsi bus speci?ations. ? chapter 3, signal description , provides a detailed signal description of the LSI53C1020. ? chapter 4, pci host register description , provides a bit level description of the host register set of the LSI53C1020 host register set.
iv preface version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. ? chapter 5, speci?ations , provides the electrical and physical characteristics of the LSI53C1020 . ? appendix a, register summary , provides a register map for the LSI53C1020. related publications lsi logic documents fusion-mpt device management users guide, version 2.0, db15-000186-02 lsi logic world wide web home page www.lsilogic.com ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for scsi: understanding the small computer system interface, isbn 0-13-796855-8 scsi electronic bulletin board (719) 533-7950 pci special interest group 2575 n. e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344
preface v version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. conventions used in this manual the ?st time a word or phrase is de?ed in this manual, it is italicized. the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. signals that are active low end with a ?. hexadecimal numbers are indicated by the pre? ?x ?or example, 0x32cf. binary numbers are indicated by the pre? ?b ?or example, 0b0011.0010.1100.1111. revision history revision date remarks final version 2.0 4/2002 added the register summary appendix. updated the electrical characteristics. updated the index. preliminary version 1.0 2/2002 updated the description of fusion-mpt architecture in chapter 1. updated the external memory interface descriptions in chapter 2. added the test interface description to chapter 2. added the zero channel raid interface description to chapters 2 and 3. updated the mad power-on sense pin description in chapter 3. updated the signal descriptions and lists to include the zcr-related pins. updated the electrical and environmental characteristics in chapter 5. removed the ?ures relating to se scsi electrical and timing characteristics from chapter 5. removed the scsi timing information from chapter 5 and referred readers to the scsi speci?ation. removed the psbram interface and all related information. advance version 0.1 4/2001 initial release of document.
vi preface version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved.
LSI53C1020 pci-x to ultra320 scsi controller vii version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. contents chapter 1 introduction 1.1 general description 1-1 1.2 bene?s of the fusion-mpt architecture 1-5 1.3 bene?s of pci-x 1-6 1.4 bene?s of ultra320 scsi 1-7 1.5 bene?s of surelink (ultra320 scsi domain validation) 1-7 1.6 bene?s of lvdlink technology 1-8 1.7 bene?s of tolerant technology 1-8 1.8 summary of LSI53C1020 features 1-9 1.8.1 scsi performance 1-9 1.8.2 pci performance 1-10 1.8.3 integration 1-11 1.8.4 flexibility 1-11 1.8.5 reliability 1-12 1.8.6 testability 1-12 chapter 2 functional description 2.1 block diagram description 2-2 2.1.1 host interface module description 2-4 2.1.2 scsi channel module description 2-6 2.2 fusion-mpt architecture overview 2-7 2.3 pci functional description 2-8 2.3.1 pci addressing 2-8 2.3.2 pci commands and functions 2-9 2.3.3 pci arbitration 2-15 2.3.4 pci cache mode 2-15 2.3.5 pci interrupts 2-15 2.3.6 power management 2-16
viii contents version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.4 ultra320 scsi functional description 2-18 2.4.1 ultra320 scsi features 2-18 2.4.2 scsi bus interface 2-23 2.5 external memory interfaces 2-24 2.5.1 flash rom interface 2-24 2.5.2 nvsram interface 2-26 2.6 serial eeprom interface 2-27 2.7 zero channel raid 2-28 2.8 multi-ice test interface 2-30 chapter 3 signal description 3.1 signal organization 3-2 3.2 pci bus interface signals 3-4 3.2.1 pci system signals 3-4 3.2.2 pci address and data signals 3-5 3.2.3 pci interface control signals 3-6 3.2.4 pci arbitration signals 3-7 3.2.5 pci error reporting signals 3-7 3.2.6 pci interrupt signals 3-8 3.3 pci-related signals 3-8 3.4 scsi interface signals 3-9 3.5 memory interface 3-12 3.6 zero channel raid (zcr) interface 3-13 3.7 test interface 3-14 3.8 gpio and led signals 3-16 3.9 power and ground pins 3-17 3.10 power-on sense pins description 3-19 3.11 internal pull-ups and pull-downs 3-23 chapter 4 pci host register description 4.1 pci con?uration space register description 4-1 4.2 i/o space and memory space register description 4-32
contents ix version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. chapter 5 speci?ations 5.1 dc characteristics 5-1 5.2 tolerant technology electrical characteristics 5-7 5.3 ac characteristics 5-9 5.4 external memory timing diagrams 5-11 5.5 package drawings 5-13 appendix a register summary index customer feedback
x contents version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved.
xi version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figures 1.1 typical LSI53C1020 board application 1-3 1.2 typical LSI53C1020 system application 1-4 2.1 LSI53C1020 block diagram 2-3 2.2 paced transfer example 2-20 2.3 example of precompensation 2-21 2.4 flash rom block diagram 2-25 2.5 nvsram diagram 2-27 2.6 zcr circuit diagram for the LSI53C1020 and lsi53c1000r 2-29 3.1 LSI53C1020 functional signal grouping 3-3 5.1 lvd driver 5-3 5.2 lvd receiver 5-4 5.3 rise and fall time test condition 5-8 5.4 scsi input filtering 5-9 5.5 external clock 5-10 5.6 reset input 5-10 5.7 interrupt output 5-11 5.8 flash rom address timing 5-11 5.9 flash rom read timing 5-12 5.10 flash rom write timing 5-12 5.11 flash rom polling 5-13 5.12 LSI53C1020 456-pin bga top view 5-14 5.13 456-pin epbga (ky) mechanical drawing 5-20
xii version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved.
xiii version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. tables 2.1 pci/pci-x bus commands and encodings 2-10 2.2 power states 2-16 2.3 flash rom size programming 2-24 2.4 flash signature value 2-26 2.5 pci con?uration record in serial eeprom 2-28 2.6 20-pin multi-ice header pinout 2-30 3.1 pci system signals 3-4 3.2 pci address and data signals 3-5 3.3 pci interface control signals 3-6 3.4 pci arbitration signals 3-7 3.5 pci error reporting signals 3-7 3.6 pci interrupt signal 3-8 3.7 pci-related signals 3-8 3.8 scsi bus clock signal 3-9 3.9 scsi channel interface signals 3-10 3.10 scsi channel control signals 3-11 3.11 flash rom/nvsram interface signals 3-12 3.12 serial eeprom interface signals 3-13 3.13 zcr con?uration signals 3-13 3.14 jtag, ice, and debug signals 3-14 3.15 lsi logic test signals 3-15 3.16 gpio and led signals 3-16 3.17 power and ground pins 3-18 3.18 mad power-on sense pin options 3-20 3.19 flash rom size programming 3-22 3.20 pull-up and pull-down signal conditions 3-23 4.1 LSI53C1020 pci con?uration space address map 4-2 4.2 subsystem id register download conditions and values 4-15 4.3 multiple message enable field bit encoding 4-24 4.4 maximum outstanding split transactions 4-28 4.5 maximum memory read count 4-29 4.6 pci i/o space address map 4-32 4.7 pci memory [0] address map 4-33 4.8 pci memory [1] address map 4-33 4.9 interrupt signal routing 4-41 5.1 absolute maximum stress ratings 5-2
xiv version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 5.2 operating conditions 5-2 5.3 lvd driver scsi signals sack ,satn , sbsy , scd , sd[15:0] , sdp[1:0] , sio ,smsg , sreq , srst , ssel 5-3 5.4 lvd receiver scsi signals sack ,satn , sbsy , scd , sd[15:0] , sdp[1:0] , sio ,smsg , sreq , srst , ssel 5-3 5.5 diffsens scsi signal 5-4 5.6 input capacitance 5-4 5.7 8 ma bidirectional signals gpio[7:0], mad[15:0], madp[1:0], serialdata 5-5 5.8 8 ma pci bidirectional signals ack64/, ad[63:0], c_be[7:0]/, devsel/, frame/, irdy/, par, par64, perr/, req64/, serr/, stop/, trdy/ 5-5 5.9 input signals clk, clkmode_0, clkmode_1, dis_pci_fsn/, dis_scsi_fsn/, gnt/, iddtn, idsel, iopd_gnt/, pvt1, pvt2, scanen, scanmode, sclk, tck_chip, tck_ice, testaclk, testclken, testhclk, tdi_chip, tdi_ice, tms_chip, tms_ice, tn, trst_ice/, tst_rst/, zcr_en/ 5-6 5.10 8 ma output signals adsc/, adv/, alt_inta/, bwe[1:0]/, flshale[1:0]/, flshce/, inta/, mclk, moe/, pipestat[2:0], ramce/, req/, rtck_ice, serialclk, tdo_chip, tdo_ice, traceclk, tracepkt[7:0], tracesync 5-6 5.11 12 ma output signals a_led/, b_led/, hb_led/ 5-6 5.12 tolerant technology electrical characteristics for se scsi signals 5-7 5.13 external clock 5-9 5.14 reset input 5-10 5.15 interrupt output 5-10 a.1 LSI53C1020 pci registers a-1 a.2 LSI53C1020 pci i/o space registers a-3 a.3 LSI53C1020 pci memory [0] registers a-4
LSI53C1020 pci-x to ultra320 scsi controller 1-1 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. chapter 1 introduction this chapter provides a general overview of the LSI53C1020 pci-x to ultra320 scsi controller. this chapter contains the following sections: section 1.1, ?eneral description section 1.2, ?ene?s of the fusion-mpt architecture section 1.3, ?ene?s of pci-x section 1.4, ?ene?s of ultra320 scsi section 1.5, ?ene?s of surelink (ultra320 scsi domain validation) section 1.6, ?ene?s of lvdlink technology section 1.7, ?ene?s of tolerant technology section 1.8, ?ummary of LSI53C1020 features 1.1 general description the LSI53C1020 pci-x to single channel ultra320 scsi controller brings ultra320 scsi performance to host adapter, workstation, and server designs, making it easy to add a high-performance scsi bus to any pci or pci-x system. the LSI53C1020 supports both the pci local bus speci?ation, revision 2.2 , and the pci-x addendum to the pci local bus speci?ation, revision 1.0a. 1 the LSI53C1020 is pin compatible with the lsi53c1000r pci to ultra160 scsi controller to provide an easy and safe migration path to ultra320 scsi. the LSI53C1020 supports up to a 64-bit, 133 mhz pci-x 1. in some instances, this manual references pci-x explicitly. references to the pci bus may be inclusive of both the pci speci?ation and pci-x addendum, or may only refer to the pci bus depending on the operating mode of the device.
1-2 introduction version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. bus. the ultra320 scsi features for the LSI53C1020 include: double transition (dt) clocking, packetized protocol, paced transfers, quick arbitrate and select (qas), skew compensation, intersymbol interference (isi) compensation, cyclic redundancy check (crc), and domain validation technology. these features comply with the american national standard institute (ansi) t10 scsi parallel interface-4 (spi-4) draft speci?ation. dt clocking enables the LSI53C1020 to achieve data transfer rates of up to 320 megabytes per second (mbytes/s). packetized protocol increases data transfer capabilities with scsi information units. qas minimizes scsi bus latency by allowing the bus to directly enter the arbitration/selection bus phase after a scsi disconnect and skip the bus-free phase. skew compensation permits the LSI53C1020 to adjust for cable and bus skew on a per-device basis. paced transfers enable high speed data transfers during dt data phases by using the req/ack transition as a free running data clock. precompensation enables the LSI53C1020 to adjust the signal drive strength to compensate for the charge present on the cable. crc improves the scsi data transmission integrity through enhanced detection of communication errors. surelink domain validation detects the scsi bus configuration and adjusts the scsi transfer rate to optimize bus interoperability and scsi data transfer rates. surelink domain validation provides three levels of domain validation, assuring robust system operation. the LSI53C1020 supports a local memory bus, which supports a standard serial eeprom and allows local storage of the bios in flash rom memory. the LSI53C1020 supports programming of local flash rom memory for bios updates. figure 1.1 shows a typical LSI53C1020 board application connected to external rom memory.
general description 1-3 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 1.1 typical LSI53C1020 board application the LSI53C1020 integrates a high-performance ultra320 scsi core and a 64-bit, 133 mhz pci-x bus master direct memory access (dma) core. the LSI53C1020 employs two arm966e-s processors to meet the data transfer ?xibility requirements of the ultra320 scsi, pci, and pci-x speci?ations. separate arm processors support the scsi channel and the pci/pci-x interface. these processors implement the fusion-mpt architecture, a multithreaded i/o algorithm that supports data transfers between the host system and scsi devices with minimal host processor intervention. fusion-mpt technology provides an ef?ient architecture that solves the protocol overhead problems of previous intelligent and nonintelligent adapter designs. lvdlink technology is the lsi logic implementation of low voltage differential (lvd) scsi. lvdlink transceivers allow the LSI53C1020 to perform either single-ended (se) or lvd transfers. figure 1.2 illustrates a typical LSI53C1020 system application. flash rom memory control block LSI53C1020 64-bit, 133 mhz pci-x to ultra320 scsi pci-x interface memory address/data bus serial data controller serial eeprom serial clock scsi signals nvsram 68-pin- wide scsi connector and terminator
1-4 introduction version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 1.2 typical LSI53C1020 system application the LSI53C1020 supports the integrated mirroring (im) technology, which provides physical mirroring of the boot volume through LSI53C1020 firmware. this feature provides extra reliability for the systems boot volume without burdening the host cpu. keeping a second disk as a mirror requires the fusion-mpt firmware, which performs writes to both the boot drive and the mirrored drive. the runtime mirroring of the boot drive is transparent to the bios, drivers, and operating system. fixed disk, optical disk, printer, tape, and other scsi peripherals pci graphic accelerator pci fast ethernet memory controller memory pci-x bus interface controller central processing unit (cpu) processor bus pci-x bus LSI53C1020 pci-x to ultra320 scsi scsi bus LSI53C1020
bene?s of the fusion-mpt architecture 1-5 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. the im ?mware requires a con?uration mechanism, which enables con?uration of the mirroring attributes during initial setup or recon?uration after hardware failures or changes in the system environment. use the bios con?uration utility or the im dos con?uration utility to con?ure the im ?mware attributes. using the lsi logic bios and drivers adds support of physical device recognition for the purpose of domain validation and ultra320 scsi expander con?uration. host-based status software monitors the state of the mirrored drives and reports error conditions as they arise. 1.2 bene?s of the fusion-mpt architecture the fusion-mpt architecture provides an open architecture that is ideal for scsi, fibre channel, and other emerging interfaces. the i/o interface is interchangable at the system and application level; embedded software uses the same device interface for scsi and fibre channel implementations, just as application software uses the same storage management interfaces for scsi and fibre channel implementations. lsi logic provides fusion-mpt device drivers that are binary compatible between fibre channel and ultra320 scsi interfaces. the fusion-mpt architecture improves overall system performance by requiring only a thin device driver, which offloads the intensive work of managing scsi i/os from the system processor to the LSI53C1020. developed from the proven sdms solution, the fusion-mpt architecture delivers unmatched performance of up to 50,000 ultra320 scsi i/os per second with minimal system overhead or device maintenance. the use of thin, easy-to-develop, common os device drivers accelerates time to market by reducing device driver development and certification times. the fusion-mpt architecture provides an interrupt coalescing feature. interrupt coalescing allows an i/o controller to send multiple reply messages in a single interrupt to the host processor. sending multiple reply messages per interrupt reduces context switching of the host processor and maximizes the host processor ef?iency, which results in a signi?ant improvement of system performance. to use the interrupt coalescing feature, the host processor must be able to accept and manage multiple replies per interrupt.
1-6 introduction version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. the fusion-mpt architecture also provides built-in device driver stability because the device driver need not change for each revision of the LSI53C1020 silicon or ?mware. this architecture is a reliable, constant interface between the host device driver and the LSI53C1020. changes within the LSI53C1020 are transparent to the host device driver, operating system, and user. the fusion-mpt architecture also saves the user signi?ant development and maintenance effort because it is not necessary to alter or redevelop the device driver when a revision of the LSI53C1020 device or ?mware occurs. 1.3 bene?s of pci-x pci-x doubles the maximum clock frequency of the conventional pci bus. the pci-x addendum to the pci local bus speci?ation, revision 1.0a , de?es enhancements to the proven pci local bus speci?ation, revision 2.2 . pci-x provides more ef?ient data transfers by enabling registered inputs and outputs, improves buffer management by including transaction information with each data transfer, and reduces bus overhead by restricting the use of wait states and disconnects. pci-x also reduces host processor overhead by providing a wide range of error recovery implementations. the LSI53C1020 supports up to a 133 mhz, 64-bit pci-x bus and is backwards compatible with previous versions of the pci/pci-x bus. according to the pci-x addendum, the LSI53C1020 includes transaction information with all pci-x transactions to enable more ef?ient buffer management schemes. each pci-x transaction contains a transaction sequence identi?r (tag), the identity of the initiator, and the number of bytes in the sequence. the LSI53C1020 clocks pci-x data directly into and out of registers, which creates a more ef?ient data path. the LSI53C1020 increases bus ef?iency because it does not insert wait states after the initial data phase when acting as a pci-x target and never inserts wait states when acting as a pci-x initiator.
bene?s of ultra320 scsi 1-7 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 1.4 bene?s of ultra320 scsi ultra320 scsi is an extension of the spi-4 draft speci?ation that allows faster synchronous scsi data transfer rates than ultra160 scsi. when enabled, ultra320 scsi performs 160 megatransfers per second, resulting in approximately double the synchronous data transfer rates of ultra160 scsi. the LSI53C1020 performs 16-bit, ultra320 scsi synchronous data transfers as fast as 320 mbytes/s. this advantage is most noticeable in heavily loaded systems or large block size applications, such as video on-demand and image processing. ultra320 scsi doubles both the data and clock frequencies from ultra160 scsi. due to the increased data and clock speeds, ultra320 scsi introduces skew compensation and isi compensation. these new features simplify system design by resolving timing issues at the chip level. skew compensation adjusts for timing differences between data and clock signals caused by cabling, board traces, and so on. isi compensation enhances the first pulse after a change in state to ensure data integrity. ultra320 scsi includes crc, which offers higher levels of data reliability by ensuring complete integrity of transferred data. crc is a 32-bit scheme, referred to as crc-32. crc guarantees detection of all single or double bit errors, as well as any combination of bit errors within a single 32-bit range. 1.5 bene?s of surelink (ultra320 scsi domain validation) surelink domain validation software ensures robust scsi interconnect management and low-risk ultra320 scsi implementations by extending the domain validation guidelines documented in the spi-4 speci?ations. domain validation veri?s that the system is capable of transferring data at ultra320 scsi speeds, allowing the LSI53C1020 to renegotiate to a lower data transfer speed and bus width if necessary. surelink domain validation is the software control for the domain validation manageability enhancements in the LSI53C1020. surelink domain validation software provides domain validation management at boot time as well as during system operation. surelink domain validation provides three levels of integrity checking on a per-device basis: basic (level 1) with inquiry command; enhanced (level 2) with read/write buffer; and margined (level 3) with margining of drive strength and slew rates.
1-8 introduction version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 1.6 bene?s of lvdlink technology the LSI53C1020 supports lvd through lvdlink technology. this signaling technology increases the reliability of scsi data transfers over longer distances than are supported by se scsi. the low current output of lvd allows the i/o transceivers to be integrated directly onto the chip. to allow the use of the LSI53C1020 in both legacy and ultra320 scsi applications, this device features universal lvdlink transceivers that support lvd scsi and se scsi. 1.7 bene?s of tolerant technology the LSI53C1020 features tolerant technology, which provides active negation on the scsi drivers and input signal ?tering on the scsi receivers. active negation causes the scsi request, acknowledge, data, and parity signals to be actively driven high rather than passively pulled up by terminators. tolerant receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption. tolerant receivers ?ter the scsi bus signals to eliminate unwanted transitions, without the long signal delay associated with rc-type input ?ters. this improved driver and receiver technology helps ensure correct clocking of data. tolerant input signal ?tering is a built-in feature of the LSI53C1020 and all lsi logic fast scsi, ultra scsi, ultra2 scsi, ultra160 scsi, and ultra320 scsi devices. tolerant technology increases noise immunity, balances duty cycles, and improves scsi transfer rates. in addition, tolerant scsi devices do not cause glitches on the scsi bus at power-up or power-down, which protects other devices on the bus from data corruption. when used with the lvdlink transceivers, tolerant technology provides excellent signal quality and data reliability in real world cabling environments. tolerant technology is compatible with both the alternative one and alternative two termination schemes proposed by the ansi .
summary of LSI53C1020 features 1-9 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 1.8 summary of LSI53C1020 features this section provides a summary of the LSI53C1020 features and bene?s. it contains information on scsi performance , pci performance , integration , flexibility , reliability , and testability . 1.8.1 scsi performance the LSI53C1020 contains the following scsi performance features: supports ultra320 scsi paced transfers using a free running clock 320 mbytes/s scsi data transfer rate mandatory packetized protocol quick arbitrate and select (qas) skew compensation with bus training transmitter precompensation to overcome isi effects for scsi data signals retained training information (rti) offers a performance-optimized architecture two arm966e-s processors provide high performance with low latency designed for optimal packetized performance uses proven integrated lvdlink transceivers for direct attach to either lvd or se scsi buses with precision-controlled slew rates expander communication protocol (ecp) uses the fusion-mpt (message passing technology) drivers to provide full operating system support for the windows, linux , solaris, sco openserver, unixware, openunix 8, and netware operating systems
1-10 introduction version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 1.8.2 pci performance the LSI53C1020 supports the following pci features: 133 mhz, 64-bit pci/pci-x interface that: operates at 33 mhz or 66 mhz pci operates at up to 133 mhz pci-x supports 32-bit or 64-bit data supports 32-bit or 64-bit addressing through dual address cycles (dacs) provides a theoretical 1066 mbytes/s zero wait state transfer rate complies with the pci local bus speci?ation, revision 2.2 complies with the pci-x addendum to the pci local bus speci?ation, revision 1.0a complies with the pci power management interface speci?ation, revision 1.1 complies with the pc2001 system design guide offers unmatched performance through the fusion-mpt architecture provides high throughput and low cpu utilization to of?ad the host processor scsi interrupt steering logic (sisl) provides alternate interrupt routing for raid applications reduces interrupt service routine (isr) overhead with interrupt coalescing supports 32-bit or 64-bit data bursts with variable burst lengths supports the pci cache line size register supports the pci memory write and invalidate, memory read line, and memory read multiple commands supports the pci-x memory read dword, split completion, memory read block, and memory write block commands supports up to eight pci-x outstanding split transactions supports message signaled interrupts (msis)
summary of LSI53C1020 features 1-11 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 1.8.3 integration the following features make the LSI53C1020 easy to integrate: backwards compatible with previous revisions of the pci and scsi speci?ations pin compatible with the lsi53c1000r pci to ultra160 scsi controller low-risk migration path to ultra320 scsi from the lsi53c1000r full 32-bit or 64-bit pci/pci-x dma bus master reduces time to market with the fusion-mpt architecture single driver binary for scsi and fibre channel products thin, easy to develop drivers reduced integration and certi?ation effort integrated lvdlink transceivers 1.8.4 flexibility the following features increase the ?xibility of the LSI53C1020: universal lvd transceivers are backward compatible with se devices flexible programming interface to tune i/o performance or to adapt to unique scsi devices supports msi or pin-based (inta/ or alt_inta/) interrupt signaling capable of responding with multiple scsi ids compatible with 3.3 v and 5.0 v pci signaling drives and receives 3.3 v pci signals receives 5.0 v pci if the pci5vbias pin connects to 5.0 v, but does not drive 5.0 v signals on the pci bus
1-12 introduction version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 1.8.5 reliability the following features enhance the reliability of the LSI53C1020: isi compensation 2 kv electrostatic discharge (esd) protection on scsi signals latch-up protection greater than 150 ma voltage feed-through protection im technology provides physical mirroring of the boot volume high proportion of power and ground pins power and ground isolation of i/o pads and internal chip logic supports crc checking and generation in double transition (dt) phases comprehensive surelink domain validation technology: basic (level 1) with inquiry command enhanced (level 2) with read/write buffer margined (level 3) with margining of drive strength and slew rates tolerant technology provides: active negation of scsi data, parity, request, and acknowledge signals for improved scsi transfer rates input signal ?tering on scsi receivers improves data integrity, even in noisy cabling environments 1.8.6 testability these features enhance the testability of the LSI53C1020: all the scsi signals are accessible through programmed i/o jtag boundary scan arm multi-ice test interface for debugging purposes
LSI53C1020 pci-x to ultra320 scsi controller 2-1 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. chapter 2 functional description this chapter provides a subsytem level overview of the LSI53C1020, a discussion of the fusion-mpt architecture, and a functional description of the LSI53C1020 interfaces. this chapter contains the following sections: ? section 2.1, ?lock diagram description ? section 2.2, ?usion-mpt architecture overview ? section 2.3, ?ci functional description ? section 2.4, ?ltra320 scsi functional description ? section 2.5, ?xternal memory interfaces ? section 2.6, ?erial eeprom interface ? section 2.7, ?ero channel raid ? section 2.8, ?ulti-ice test interface the LSI53C1020 is a high-performance, intelligent pci-x to ultra320 scsi controller. the LSI53C1020 supports revision 2.2 of the pci local bus speci?ation , revision 1.0a of the pci-x addendum to the pci local bus speci?ation , and the proposed scsi parallel interface-4 (spi-4) draft standard. the LSI53C1020 employs the fusion-mpt architecture to ensure robust system performance, to support binary compatibility of host software between the lsi logic scsi and fibre channel products, and to signi?antly reduce software development time. refer to the fusion-mpt device management users guide for more information on the fusion-mpt architecture and how to control the LSI53C1020 using fusion-mpt technology.
2-2 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.1 block diagram description the LSI53C1020 consists of two major modules: a host interface module and an ultra320 scsi channel module. the modules consist of the following components: ? host interface module up to a 64-bit, 133 mhz pci/pci-x interface system interface i/o processor (iop) dma arbiter and router shared ram external memory interface ? flash rom memory controller ? nvsram timer and con?uration control ? device con?uration controller ? serial eeprom interface controller ? general purpose i/o (gpio) interface ? chip timer ? ultra320 scsi channel module datapath engine context manager ultra320 scsi core figure 2.1 illustrates the relationship between these modules.
block diagram description 2-3 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 2.1 LSI53C1020 block diagram ultra320 scsi datapath engine secondary bus scsi channel module ultra320 scsi (arm966e-s) context manager core shared ram timer, gpio, serial gpio eeprom external system interface dma arbiter and router pci/pci-x interface iop and eeprom memory host interface module (arm966e-s) pci-x pci/ flash rom/ primary bus nvsram bus to bus bridge
2-4 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.1.1 host interface module description the host interface module provides an interface between the host driver and the scsi channel. the host interface module controls system dma transfers and the host side of the fusion-mpt architecture. it also supports the external memory, serial eeprom, and gpio interfaces. this subsection provides a detailed explanation of the host interface submodules. 2.1.1.1 pci interface the LSI53C1020 provides a pci-x interface that supports up to a 64-bit, 133 mhz pci-x bus. the interface is compatible with all previous implementations of the pci specification. for more information on the pci interface, refer to section 2.3, ?ci functional description, page 2-8 . 2.1.1.2 system interface the system interface ef?iently passes messages between the LSI53C1020 and other i/o agents using a high-performance, packetized, mailbox architecture. the LSI53C1020 system interface coalesces pci interrupts to minimize traf? on the pci bus and maximize system performance. all host accesses to the iop, external memory, and timer and con?uration subsystems pass through the system interface and use the primary bus. the host system initiates data transactions on the primary bus with the system interface registers. pci memory space [0] and the pci i/o base address registers identify the location of the system interface register set. chapter 4, pci host register description , provides a bit-level description of the system interface register set. 2.1.1.3 i/o processor (iop) the LSI53C1020 i/o processor (iop) is a 32-bit arm966e-s risc processor. the iop controls the system interface and uses the fusion-mpt architecture to manage the host side of non-dma accesses to the ultra320 scsi bus. the context manager uses the fusion-mpt architecture to control the scsi side of data transfers. the iop and context manager completely manage all scsi i/os without host intervention. refer to section 2.2, ?usion-mpt architecture overview, page 2-7 , for more information on the fusion-mpt architecture.
block diagram description 2-5 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.1.1.4 dma arbiter and router the descriptor-based dma arbiter and router subsystem manages the transfer of memory blocks between local memory and the host system. the dma channel includes pci bus master interface logic, the internal bus interface logic, and a 256-byte system dma fifo. 2.1.1.5 shared ram the host interface module physically contains the 96 kbyte shared ram. however, both the host interface module and the scsi channel module access the shared ram. the shared ram holds a portion of the iop and context manager ?mware, as well as the request message queue and reply message queue. all non-dma data transfers that use the request and reply message queues pass through the shared ram. 2.1.1.6 external memory controller the external memory controller subsystem provides a direct interface between the primary bus and the external memory subsystem. mad[7:0] and madp[0] compose the external memory bus. the LSI53C1020 supports the flash rom and nvsram interfaces through the external memory controller. the flash rom is optional if the LSI53C1020 is not the boot device and a suitable driver exists to initialize the device. the LSI53C1020 uses the nvsram for im technology. for a detailed description of this block refer to section 2.5, ?xternal memory interfaces, page 2-24 . during power-up or reset the LSI53C1020 uses the mad[15:0] and madp[1:0] signals as power-on sense pins, which con?ure the LSI53C1020 through their pull-up or pull-down settings. refer to section 3.10, ?ower-on sense pins description, page 3-19 , for a description of the power-on sense pin con?uration options. 2.1.1.7 timer, gpio, and con?uration this subsystem provides a free running timer to allow event time stamping and also controls the gpio, led, and serial eeprom interfaces. the LSI53C1020 uses the free running timer to aid in tracking and managing scsi i/os. the LSI53C1020 generates the free running timers microsecond time base by dividing the scsi reference clock by 40.
2-6 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. the LSI53C1020 provides eight gpio pins (gpio[7:0]). these pins are under the control of the LSI53C1020 and default to the input mode upon pci reset. the LSI53C1020 also provides three led pins: a_led/, b_led/, and hb_led/. either ?mware or hardware control a_led/. the LSI53C1020 ?mware controls b_led/ and hb_led/ (heartbeat led). hb_led/ indicates that the iop is operational. a 2-wire serial interface provides a connection to a nonvolatile external serial eeprom. the serial eeprom stores pci con?uration parameters for the LSI53C1020. refer to section 2.6, ?erial eeprom interface, page 2-27 , for more information concerning the serial eeprom. 2.1.2 scsi channel module description the LSI53C1020 provides one scsi bus channel. an ultra320 scsi core, a datapath engine, and a context manager support this scsi channel. refer to section 2.4, ?ltra320 scsi functional description, page 2-18 , for an operational description of the LSI53C1020 scsi channel. 2.1.2.1 ultra320 scsi core the ultra320 scsi core controls the scsi bus interface. 2.1.2.2 datapath engine the datapath engine manages the scsi side of dma transactions between the scsi bus and the host system. 2.1.2.3 context manager the context manager is an arm966e-s processor. it controls the scsi channel side of the LSI53C1020 fusion-mpt architecture. the context manager controls the outbound queues, target mode i/o mapping, disconnect and reselect sequences, scatter/gather lists, and status reports.
fusion-mpt architecture overview 2-7 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.2 fusion-mpt architecture overview the fusion-mpt architecture provides two i/o methods for the host system to communicate with the iop: the system interface doorbell and the message queues. the system interface doorbell is a simple, message-passing mechanism that allows the pci host system and iop to exchange single, 32-bit dword messages. when the host system writes to the doorbell, the LSI53C1020 hardware generates a maskable interrupt to the iop, which can then read the doorbell value and take the appropriate action. when the iop writes a value to the doorbell, the LSI53C1020 hardware generates a maskable interrupt to the host system. the host system can then read the doorbell value and take the appropriate action. there are two, 32-bit message queues: the request message queue and the reply message queue. the host uses the request queue to request an action by the LSI53C1020, and the LSI53C1020 uses the reply queue to return status information to the host. the request message queue consists of only the request post fifo. the reply message queue consists of both the reply post fifo and the reply free fifo. the shared ram contains the message queues. communication using the message queues occurs through request messages and reply messages. request message frame descriptors are pointers to the request message frames and are passed through the request post fifo. the request message frame data structure is up to 128 bytes in length and includes a message header and a payload. the header uniquely identifies the message. the payload contains information that is specific to the request. reply message frame descriptors have one of two formats and are passed through the reply post fifo. when indicating the successful completion of a scsi i/o, the iop writes the reply message frame descriptor using the context reply format, which is a message context. if a scsi i/o does not complete successfully, the iop uses the address reply format. in this case, the iop pops a reply message frame from the reply free fifo, generates a reply message describing the error, writes the reply message to system memory, and writes the address of the reply message frame to the reply post fifo. the host can then read the reply message and take the appropriate action.
2-8 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. the doorbell mechanism provides both a high-priority communication path that interrupts the host system device driver and an alternative communication path to the message queues. because data transport through the system doorbell occurs a single dword at a time, use the LSI53C1020 message queues for normal operation and data transport. 2.3 pci functional description the host pci interface complies with the pci local bus speci?ation revision 2.2 and the pci-x addendum to the pci local bus speci?ation, revision 1.0a . the LSI53C1020 supports up to a 133 mhz, 64-bit pci-x bus. the LSI53C1020 provides support for 64-bit addressing with dual address cycle (dac). 2.3.1 pci addressing the three physical address spaces the pci speci?ation de?es are: ? pci con?uration space ? pci i/o space for operating registers ? pci memory space for operating registers the following sections describe the pci address spaces. 2.3.1.1 pci con?uration space the LSI53C1020 de?es the pci con?uration space registers for the pci function. the con?uration space is a contiguous 256 x 8-bit set of addresses. the system bios initializes the con?uration registers using pci con?uration cycles. the LSI53C1020 decodes c_be[3:0]/ to determine if a pci cycle intends to access the con?uration register space. the idsel signal behaves as a chip select signal that enables access to the con?uration register space only. the LSI53C1020 ignores con?uration read/write cycles when idsel is not asserted.
pci functional description 2-9 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.3.1.2 pci i/o space the pci speci?ation de?es i/o space as a contiguous, 32-bit i/o address that all system resources share, including the LSI53C1020. the i/o base address register determines the 256-byte pci i/o area that the pci device occupies. 2.3.1.3 pci memory space the LSI53C1020 contains two pci memory spaces: pci memory space [0] and pci memory space [1]. pci memory space [0] supports normal memory accesses while pci memory space [1] supports diagnostic memory accesses. the LSI53C1020 requires 64 kbytes of memory space. the pci speci?ation de?es memory space as a contiguous, 64-bit memory address that all system resources share. the memory [0] low and memory [0] high registers determine which 64 kbyte memory area pci memory space [0] occupies. the memory [1] low and memory [1] high registers determine which 64 kbyte memory area pci memory space [1] occupies. 2.3.2 pci commands and functions bus commands indicate to the target the type of transaction the master is requesting. the master encodes the bus commands on the c_be[3:0]/ lines during the address phase. the pci bus command encodings appear in table 2.1 .
2-10 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. the following sections describe how the LSI53C1020 implements these commands. table 2.1 pci/pci-x bus commands and encodings 1 1. the LSI53C1020 ignores reserved commands as a slave and never generates them as a master. c_be[3:0]/ pci command pci-x command supports as master supports as slave 0b0000 interrupt acknowledge interrupt acknowledge no no 0b0001 special cycle special cycle no no 0b0010 i/o read i/o read yes yes 0b0011 i/o write i/o write yes yes 0b0100 reserved reserved n/a n/a 0b0101 reserved reserved n/a n/a 0b0110 memory read memory read dword yes yes 0b0111 memory write memory write yes yes 0b1000 reserved alias to memory read block pci: n/a pci-x: no pci: n/a pci-x: yes 0b1001 reserved alias to memory write block pci: n/a pci-x: no pci: n/a pci-x: yes 0b1010 con?uration read con?uration read no yes 0b1011 con?uration write con?uration write no yes 0b1100 memory read multiple split completion yes yes 2 2. when acting as a slave in the pci mode, the LSI53C1020 supports this command as the pci memory read command. 0b1101 dual address cycle dual address cycle yes yes 0b1110 memory read line memory read block yes yes 2 0b1111 memory write and invalidate memory write block yes yes 3 3. when acting as a slave in the pci mode, the LSI53C1020 supports this command as the pci memory write command.
pci functional description 2-11 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.3.2.1 interrupt acknowledge command the LSI53C1020 ignores this command as a slave and never generates it as a master. 2.3.2.2 special cycle command the LSI53C1020 ignores this command as a slave and never generates it as a master. 2.3.2.3 i/o read command this command reads data from an agent mapped in the i/o address space. when decoding i/o commands, the LSI53C1020 decodes the lower 32 address bits and ignores the upper 32 address bits. the LSI53C1020 supports this command when operating in either the pci or pci-x bus mode. 2.3.2.4 i/o write command this command writes data to an agent mapped in the i/o address space. when decoding i/o commands, the LSI53C1020 decodes the lower 32 address bits and ignores the upper 32 address bits. the LSI53C1020 supports this command when operating in either the pci or pci-x bus mode. 2.3.2.5 memory read command the LSI53C1020 uses this command to read data from an agent mapped in the memory address space. the target can perform an anticipatory read if such a read produces no side effects. the LSI53C1020 supports this command when operating in the pci bus mode. 2.3.2.6 memory read dword command this command reads up to a single dword of data from an agent mapped in the memory address space and can only be initiated as a 32-bit transaction. the target can perform an anticipatory read if such a read produces no side effects. the LSI53C1020 supports this command when operating in the pci-x bus mode.
2-12 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.3.2.7 memory write command this command writes data to an agent mapped in the memory address space. the target assumes responsibility for data coherency when it returns ?eady. the LSI53C1020 supports this command when operating in either the pci or pci-x bus mode. 2.3.2.8 alias to memory read block command this command is reserved for future implementations of the pci speci?ation. the LSI53C1020 never generates this command as a master. when a slave, the LSI53C1020 supports this command using the memory read block command. 2.3.2.9 alias to memory write block command this command is reserved for future implementations of the pci speci?ation. the LSI53C1020 never generates this command as a master. when a slave, the LSI53C1020 supports this command using the memory write block command. 2.3.2.10 con?uration read command this command reads the con?uration space of a device. the LSI53C1020 never generates this command as a master, but does respond to it as a slave. a device on the pci bus selects the LSI53C1020 by asserting its idsel signal when ad[1:0] equal 0b00. during the address phase of a con?uration cycle, ad[7:2] address one of the 64 dword registers in the con?uration space of each device. c_be[3:0]/ address the individual bytes within each dword register and determine the type of access to perform. bits ad[10:8] address the pci function con?uration space (ad[10:8] = 0b000). the LSI53C1020 treats ad[63:11] as logical don? cares. 2.3.2.11 con?uration write command this command writes the con?uration space of a device. the LSI53C1020 never generates this command as a master, but does respond to it as a slave. a device on the pci bus selects the LSI53C1020 by asserting its idsel signal when bits ad[1:0] equal 0b00. during the address phase of a con?uration cycle, bits ad[7:2] address one of the 64 dword registers in the con?uration space of each device. c_be[3:0]/
pci functional description 2-13 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. address the individual bytes within each dword register and determine the type of access to perform. bits ad[10:8] decode the pci function con?uration space (ad[10:8] = 0b000). the LSI53C1020 treats ad[63:11] as logical don? cares. 2.3.2.12 memory read multiple command this command is identical to the memory read command, except it additionally indicates that the master intends to fetch multiple cache lines before disconnecting. the LSI53C1020 supports pci memory read multiple functionality when operating in the pci mode and determines when to issue a memory read multiple command instead of a memory read command. burst size selection the read multiple command reads multiple cache lines of data during a single bus ownership. the number of cache lines the LSI53C1020 reads is a multiple of the cache line size, which revision 2.2 of the pci speci?ation provides. the LSI53C1020 selects the largest multiple of the cache line size based on the amount of data to transfer. 2.3.2.13 split completion command split transactions in pci-x replace the delayed transactions in conventional pci. the LSI53C1020 supports up to eight outstanding split transactions when operating in the pci-x mode. a split transaction consists of at least two separate bus transactions: a split request, which the requester initiates, and one or more split completion commands, which the completer initiates. revision 1.0a of the pci-x addendum permits split transaction completion for the memory read block, alias to memory read block, memory read dword, interrupt acknowledge, i/o read, i/o write, configuration read, and configuration write commands. when operating in the pci-x mode, the LSI53C1020 supports the split completion command for all of these commands except the interrupt acknowledge command, which the LSI53C1020 neither responds to nor generates. 2.3.2.14 dual address cycles command the LSI53C1020 performs dual address cycles (dacs), according to the pci local bus speci?ation, revision 2.2 . the LSI53C1020 supports this command when operating in either the pci or pci-x bus mode.
2-14 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.3.2.15 memory read line command this command is identical to the memory read command except it additionally indicates that the master intends to fetch a complete cache line. the LSI53C1020 supports this command when operating in the pci mode. 2.3.2.16 memory read block command the LSI53C1020 uses this command to read from memory. the LSI53C1020 supports this command when operating in the pci-x mode. 2.3.2.17 memory write and invalidate command this command is identical to the memory write command, except it additionally guarantees a minimum transfer of one complete cache line. the master uses this command when it intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size register. the LSI53C1020 determines when to issue a write and invalidate command instead of a memory write command and supports this command when operating in the pci bus mode. alignment the LSI53C1020 uses the calculated line size value to determine if the current address aligns to the cache line size. if the address does not align, the LSI53C1020 bursts data using a noncache command. if the starting address aligns, the LSI53C1020 issues a memory write and invalidate command using the cache line size as the burst size. multiple cache line transfers the memory write and invalidate command can write multiple cache lines of data in a single bus ownership. the LSI53C1020 issues a burst transfer as soon as it reaches a cache line boundary. the pci local bus specification states that the transfer size must be a multiple of the cache line size. the LSI53C1020 selects the largest multiple of the cache line size based on the transfer size. when the dma buffer contains less data than the value cache line size register specifies, the LSI53C1020 issues a memory write command on the next cache boundary to complete the data transfer.
pci functional description 2-15 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.3.2.18 memory write block command the LSI53C1020 uses this command to burst data to memory. the LSI53C1020 supports this command when operating in the pci-x bus mode. 2.3.3 pci arbitration the LSI53C1020 contains a bus mastering function for the scsi function and for the system interface. the system interface bus mastering function manages dma operations as well as the request and reply message frames. the scsi channel bus mastering functions manage data transfers across the scsi channel. the LSI53C1020 uses a req/-gnt/ signal pair to arbitrate for access to the pci bus. to ensure fair access to the pci bus, the internal arbiter uses a round robin arbitration scheme to decide which of the two internal bus mastering functions can arbitrate for access to the pci bus. 2.3.4 pci cache mode the LSI53C1020 supports an 8-bit cache line size register. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. the LSI53C1020 determines when to issue a pci cache command (memory read line, memory read multiple, and memory write and invalidate), or pci noncache command (memory read or memory write command). 2.3.5 pci interrupts the LSI53C1020 signals an interrupt to the host processor either using pci interrupt pins, inta/ and alt_inta/, or using message signaled interrupts (msis). if using the pci interrupt pins, the interrupt request routing mode bits in the host interrupt mask register con?ure the routing of each interrupt to either the inta/ and/or the alt_inta/ pin. if using msi, the LSI53C1020 does not signal interrupts on inta/ or alt_inta/. note that enabling msi to mask pci interrupts is a violation of the pci speci?ation. the LSI53C1020 supports one requested message and disables msi after the chip powers-up or resets.
2-16 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. the host interrupt mask register also prevents the assertion of a pci interrupt to the host processor by selectively masking reply interrupts and system doorbell interrupts. this register masks both pin-based and msi-based interrupts. 2.3.6 power management the LSI53C1020 complies with the pci power management interface speci?ation, revision 1.1, and the pc2001 system design guide . the LSI53C1020 supports the d0, d1, d2, d3 hot , and d3 cold power states. d0 is the maximum power state, and d3 is the minimum power state. power state d3 is further categorized as d3 hot or d3 cold . powering the function off places it in the d3 cold power state. bits [1:0] of the power management control/status register independently control the power state of the pci device on the LSI53C1020. table 2.2 provides the power state bit settings. the following sections describe the pci function power states d0, d1, d2, and d3. as the device transitions from one power level to a lower one, the attributes that occur in the higher power state level carry into the lower power state level. for example, power state d2 includes the attributes for power state d1, as well as the attributes de?ed for power state d2. the following sections describe the pci function power states in conjunction with the scsi function. table 2.2 power states power management control and status register, bits [1:0] power state function 0b00 d0 maximum power 0b01 d1 snooze mode 0b10 d2 coma mode 0b11 d3 minimum power
pci functional description 2-17 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.3.6.1 power state d0 power state d0 is the maximum power state and is the power-up default state for each function. the LSI53C1020 is fully functional in this state. 2.3.6.2 power state d1 according to the pci power management interface speci?ation, power state d1 must have a power level equal to or lower than power state d0. a function in power state d1 places the scsi core in the snooze mode. in the snooze mode, a scsi reset does not generate an irq/ signal. 2.3.6.3 power state d2 according to the pci power management interface speci?ation, power state d2 must have a power level equal to or lower than power state d1. a function in this state places the scsi core in the coma mode. placing the pci function in power state d2 disables the scsi and dma interrupts, and suppresses the following pci con?uration space command register enable bits: ? i/o space enable ? memory space enable ? bus mastering enable ? serr/enable ? enable parity error response therefore, the memory and i/o spaces in a function cannot be accessed, and the pci function cannot be a pci bus master. if the pci function is changed from power state d2 to power state d1 or power state d0, the pci function restores the previous values of the pci command register and asserts any interrupts that were pending before the function entered power state d2.
2-18 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.3.6.4 power state d3 according to the pci power management interface speci?ation, power state d3 must have a power level equal to or lower than power state d2. power state d3 is the minimum power state and includes the d3 hot and d3 cold settings. d3 hot allows the device to transition to d0 using software. d3 cold removes power from the LSI53C1020. d3 cold can transition to d0 by applying vcc and resetting the device. placing a function in power state d3 puts the LSI53C1020 core in the coma mode, clears the pci command register, and continually asserts the function's soft reset. asserting soft reset clears all pending interrupts and 3-states the scsi bus. 2.4 ultra320 scsi functional description the ultra320 scsi channel supports wide scsi synchronous transfer rates up to 320 mbytes/s across an se or lvd scsi bus. the integrated lvdlink transceivers support both lvd and se signals and do not require external transceivers. the LSI53C1020 supports the ultra320 scsi, ultra160 scsi, ultra2 scsi, ultra scsi, and fast scsi interfaces. 2.4.1 ultra320 scsi features this section describes how the LSI53C1020 implements the features in the spi-4 draft speci?ation. 2.4.1.1 parallel protocol request (ppr) a scsi extended message negotiates the ppr parameters. the ppr parameters include the (1) transfer period; (2) maximum req/ack offset; (3) qas; (4) margin control settings (mcs); (5) transfer width; (6) iu_request; (7) write ?w; (8) read streaming; (9) rti; (10) precompensation enable; (11) information unit transfers; and the (12) dt data phases between an initiator and a target.
ultra320 scsi functional description 2-19 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.4.1.2 double transition (dt) clocking ultra160 scsi and ultra320 scsi implement dt clocking to provide speeds up to 80 megatransfers per second (megatransfers/s) for ultra160 scsi, and up to 160 megatransfers/s for ultra320 scsi. when implementing dt clocking, a scsi device samples data on both the asserting and deasserting edge of req/ack. dt clocking is only valid using an lvd scsi bus. 2.4.1.3 intersymbol interference (isi) compensation isi compensation uses paced transfers and precompensation to enable high data transfer rates. ultra320 scsi data transfers require isi compensation. paced transfers the initiator and target must establish a paced transfer agreement that speci?s the req/ack offset and the transfer period before using this feature. devices can only perform paced transfers during ultra320 scsi dt data phases. in paced transfers, the device sourcing the data drives the req/ack signal as a free running clock. the transition of the req/ack signal, either the assertion or the negation, clocks data across the bus. for successful completion of a paced transfer, the number of ack transitions must equal the number of req transitions and both the req and ack lines must be negated. the p1 line indicates valid data in 4-byte quantities by using its phase. the transmitting device indicates the start of valid data state by holding the state of the p1 line for the ?st two data transfer periods. beginning on the third data transfer period, the transmitting device continues the valid data state by toggling the state of the p1 line every two data transfer periods for as long as the data is valid. the transmitting device must toggle the p1 line coincident with the req/ack assertion. the method provides a minimum data valid period of two transfer periods. to pause the data transfer, the transmitting device reverses the phase of p1 by withholding the next transition of p1 at the start of the ?st two invalid data transfer periods. beginning with the third invalid data transfer period, the transmitting device toggles the p1 line every two invalid data transfer periods until it sends valid data. the transmitting device returns to the valid data state by reversing the phase of the p1 line. the invalid
2-20 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. data state must experience at least one p1 transition before returning to the valid data state. this method provides a minimum data invalid period of four transfer periods. figure 2.2 provides a waveform diagram of paced data transfers and illustrates the use of the p1 line. figure 2.2 paced transfer example the LSI53C1020 uses the ppr negotiation that the spi-4 draft standard describes to establish a paced transfer agreement for each initiator-target pair. precompensation when transmitting in the ultra320 scsi mode, the LSI53C1020 uses precompensation to adjust the strength of the req, ack, parity, and data signals. when a signal transitions to high or low, the LSI53C1020 boosts the signal drive strength for the ?st data transfer period, and then lowers the signal drive strength on the second data transfer period if the signal remains in the same state. the LSI53C1020 maintains the lower signal drive strength until the signal again transitions high or low. figure 2.3 illustrates the drivers performance with precompensation enabled and disabled. data not valid data valid data valid data not valid req ack p1 data
ultra320 scsi functional description 2-21 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 2.3 example of precompensation 2.4.1.4 packetized transfers packetized transfers are also referred to as information unit transfers. they reduce overhead on the scsi bus by merging several of the scsi bus phases. packetized transfers can only occur in dt data phases. the initiator and target must establish either a dt synchronous transfer agreement or a paced transfer agreement before performing packetized transfers. the number of bytes an information unit transfers is always a multiple of four. if the number of bytes to transfer in the information unit is not a multiple of four, the LSI53C1020 transmits pad bytes to bring the byte count to a multiple of four. normal drive strength boosted drive strength normal drive strength a. drivers with precompensation disabled b. drivers with precompensation enabled
2-22 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.4.1.5 quick arbitration and selection (qas) when using packetized transfers, qas allows devices to arbitrate for the bus immediately after the message phase. qas reduces the bus overhead and maximizes bus bandwidth by skipping the bus free phase that normally follows a scsi connection. to perform qas, the target sends a qas request message to the initiator during the message phase of the bus. qas-capable devices snoop the scsi bus for the qas request message. if a qas request message is seen, devices can immediately move to the arbitration phase without going to the bus free phase. the LSI53C1020 employs a fairness algorithm to ensure that all devices have equal bus access. 2.4.1.6 skew compensation the LSI53C1020 provides a method to account for and control system skew between the clock and data signals. skew compensation is only available when the device operates in the ultra320 scsi mode. the initiator-target pair uses the training sequences in the spi-4 draft standard to determine the skew compensation. depending on the state of the rti bit in the ppr negotiation, the LSI53C1020 can either execute this training pattern during each connection, or can execute the training pattern, store the adjustment parameters, and recall them on subsequent connections with the given device. the target determines when to execute the training pattern. 2.4.1.7 cyclic redundancy check (crc) ultra320 scsi and ultra160 scsi devices employ crc as an error detection code during the dt data phases. these devices transfer four crc bytes during the dt data phases to ensure reliable data transfers. 2.4.1.8 surelink domain validation surelink domain validation establishes the integrity of a scsi bus connection between an initiator and a target. under the surelink domain validation procedure, a host queries a device to determine its ability to communicate at the negotiated data transfer rate. surelink domain validation provides three levels of integrity checking: basic (level 1) with inquiry command; enhanced (level 2) with read/write buffer; and margined (level 3) with drive strength margining
ultra320 scsi functional description 2-23 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. and slew rate control. the basic check consists of an inquiry command to detect gross problems. the enhanced check sends a known data pattern using the read and write buffer commands to detect additional problems. the margined check veri?s that the physical parameters have a reasonable operating margin. use surelink domain validation only during the diagnostic system checks and not during normal system operation. if transmission errors occur during any of these checks, the system can reduce the transmission rate on a per-target basis to ensure robust system operation. 2.4.2 scsi bus interface this section describes the scsi bus modes that the LSI53C1020 supports and the scsi bus termination methods necessary to operate a high speed scsi bus. 2.4.2.1 scsi bus modes the LSI53C1020 supports se and lvd transfers. to increase device connectivity and scsi cable length, the LSI53C1020 features lvdlink technology, which is the lsi logic implementation of lvd scsi. lvdlink transceivers provide the inherent reliability of differential scsi and a long-term migration path for faster scsi transfer rates. the diffsens signal detects the different input voltages for hvd, lvd, and se. the LSI53C1020 drivers are tolerant of hvd signal strengths, but do not support the hvd bus mode. the LSI53C1020 scsi device 3-states its scsi drivers when it detects an hvd signal level. 2.4.2.2 scsi termination the terminator networks pull signals to an inactive voltage level and match the impedance seen at the end of the cable to the characteristic impedance of the cable. install terminators at the extreme ends of the scsi chain, and only at the ends; all scsi buses must have exactly two terminators. note: if using the LSI53C1020 in a design with an 8-bit scsi bus, designers must terminate all 16 data lines.
2-24 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.5 external memory interfaces the LSI53C1020 provides flash rom, nvsram, and serial eeprom interfaces. the flash rom interface stores the scsi bios and ?mware image. the flash rom is optional if the LSI53C1020 is not the boot device and a suitable driver exists to initialize the LSI53C1020. im technology requires an nvsram. the nonvolatile external serial eeprom stores con?uration parameters for the LSI53C1020. 2.5.1 flash rom interface the flash rom interface multiplexes the 8-bit address and data buses on the mad[7:0] pins. the interface latches the address into three 8-bit latches to support up to 1 mbyte of address space. the interface supports byte, word, and dword accesses. the LSI53C1020 dword aligns dword reads, word aligns word reads, and byte aligns byte reads. the remaining bits from word and byte reads are meaningless. the mad[2:1] power-on sense pin con?urations de?e the size of the flash rom address space. table 2.3 provides the pin encoding for these pins. by default, internal logic pulls these pins down to indicate that no flash rom is present. the LSI53C1020 de?es only the middle (ma[15:8]) and lower (ma[7:0]) address ranges if the flash rom addressable space is 64 kbytes or less. the LSI53C1020 de?es the upper (ma[21:16]), middle (ma[15:8]), and lower (ma[7:0]) address ranges if the flash rom addressable space is 128 kbytes or more. figure 2.4 provides an example of a flash rom con?uration. table 2.3 flash rom size programming mad[2:1] options flash rom size 0b00 no flash rom present (default) 0b01 up to 1024 kbytes 1 1. choose this setting for a 128 kbyte or 512 kbyte flash rom. 0b10 reserved 0b11
external memory interfaces 2-25 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 2.4 flash rom block diagram the LSI53C1020 implements a flash signature recognition mechanism to determine if the flash contains a valid image. the flash can be present and not contain a valid image either before its initial programming or during board testing. the first access to the flash is a 16-byte burst read beginning at flash address 0x000000. the LSI53C1020 compares the values read to the flash signature values that table 2.4 provides. if the signature values match, the LSI53C1020 performs the instruction located at flash address 0x000000. if the signature values do not match, the LSI53C1020 records an error and ignores the flash instruction. the flash signature does not include the first three bytes of flash memory because these bytes contain a branch offset instruction. d q ck flash rom (512 k x 8) mad[7:0] d[7:0] a[21:16] flshale[1]/ d q flshale[0]/ ck a[15:8] flshale[1]/ a[7:0] flshale[0]/ ce/ flshce/ oe/ moe/ we/ bwe[0]/ upper address middle address lower address d q ck
2-26 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.5.2 nvsram interface write journaling for im requires an nvsram. the LSI53C1020 fusion-mpt firmware is capable of maintaining a second disk as a mirror of the boot drive. to do so, the fusion-mpt firmware writes to both the boot drive and the mirror drive. the mirroring of the boot drive is transparent to the bios, drivers, and operating system. figure 2.5 provides a block diagram illustrating how to connect the nvsram. this design employs the cpld to latch the address instead of using separate address latches. when using an nvsram, pull the mad[3] power-on sense pin high during board boot-up. this con?ures the external memory interface as an nvsram interface. during operation, ramce/ selects the nvsram when mad[3] is pulled high. table 2.4 flash signature value flash address flash signature values bytes [3:0] 0xea xx xx xx bytes [7:4] 0x5a 0xea 0xa5 0x5a bytes [11:8] 0xa5 0x5a 0xea 0xa5 bytes [15:12] 0x5a 0xa5 0x5a 0xea
serial eeprom interface 2-27 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 2.5 nvsram diagram 2.6 serial eeprom interface the nonvolatile external serial eeprom stores configuration fields for the LSI53C1020. the serial eeprom contains fields for the subsystem id, subsystem vendor id, and the size of the pci diagnostic memory space. the LSI53C1020 must establish each of these parameters prior to reading system bios and loading the pci configuration space registers. the power-on option settings enable the download of pci configuration data from the serial eeprom. for more information on the setting of the power-on options, refer to section 3.10, ?ower-on sense pins description, page 3-19 . a 2-wire serial interface provides the connection to the serial eeprom. during initialization, the ?mware checks if a serial eeprom exists. firmware uses the checksum byte to determine if the con?uration held in the serial eeprom is valid. if the checksum fails, the ?mware checks for a valid nvdata signature. if a valid nvdata signature is found, the ?mware individually checksums each persistent con?uration page to ?d the invalid page or pages. table 2.5 provides the structure of the con?uration record in the serial eeprom. flshale[1:0]/ mad[7:0] mas[1:0] mad[7:0] mad[14:0] a[14:0] d[7:0] ramce/ moe/ bwe[0]/ ce/ oe/ we/ nvsram (32 k x 8) 3.3 v cpld cy37032
2-28 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.7 zero channel raid zero channel raid (zcr) capabilities enable the LSI53C1020 to respond to accesses from a pci raid controller card or chip that is able to generate zcr cycles. the LSI53C1020 zcr functionality is controlled through the zcr_en/ and the iopd_gnt/ signals. both of these signals have internal pull-ups and are active low. the zcr_en/ signal enables zcr support on the LSI53C1020. pulling zcr_en/ high disables zcr support on the LSI53C1020 and causes the LSI53C1020 to behave as a normal pci-x to ultra320 scsi controller. when zcr is disabled, the iopd_gnt/ signal has no effect on the LSI53C1020 operation. pulling zcr_en/ low enables zcr operation. when zcr is enabled, the LSI53C1020 responds to pci con?uration cycles when the iopd_gnt/ or idsel signal is asserted. connect the iopd_gnt/ pin on the LSI53C1020 to the pci gnt/ signal of the external i/o processor. this allows the i/o processor to perform pci con?uration cycles to the LSI53C1020 when the i/o processor is granted the pci bus. this con?uration also prevents the system processor from accessing the LSI53C1020 pci con?uration registers. LSI53C1020 based designs do not use the m66en pin to determine the pci bus speed. table 2.5 pci con?uration record in serial eeprom eeprom address con?uration data 0x00 subsystem id , bits [7:0] 0x01 subsystem id , bits [15:8] 0x02 subsystem vendor id , bits [7:0] 0x03 subsystem vendor id , bits [15:8] 0x04 pci diagnostic memory size 0x05?x09 reserved 0x0a checksum
zero channel raid 2-29 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 2.6 illustrates how to connect the LSI53C1020 to enable zcr. this ?ure also contains information for connecting the lsi53c1000r-based designs to a zcr design and migrating from lsi53c1000r-based designs to LSI53C1020-based designs. notice that the LSI53C1020 does not require the 2:1 mux. figure 2.6 zcr circuit diagram for the LSI53C1020 and lsi53c1000r zcr pci slot lsi53c1000r/ host system idsel (ac13) int a/ (a6) int b/ (b7) int c/ (a7) inta/ (ac8) int a/ int b/ int c/ tdi (a4) tms (a3) gnt/ (a17) zcr_en/ (n23) iopd_ gnt/ (ac5) no pop for no pop for LSI53C1020 2:1 mux a0 a1 s0 b0 vdd vdd LSI53C1020 only no pop for ad19 ad21 ad21 (b29) idsel (a26) 4.7 k ? vdd 4.7 k ? vdd 4.7 k ? vdd 0.1 k ? 0 ? 0.1 k ? note: to maintain proper interrupt mapping, select the address line for use as idsel on the lsi53c1000r/LSI53C1020 to be +2 address lines above idsel on zcr slot. 0.1 k ? 0 ? ls53c1000r lsi53c1000r LSI53C1020 220 ? int d/ (b8) int d/
2-30 functional description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 2.8 multi-ice test interface this section describes the lsi logic requirements for the multi-ice test interface. lsi logic recommends routing all test signals to a header on the board. the multi-ice test interface header is a 20-pin header for multi-ice debugging through the ice jtag port. this header is essential for debugging both the ?mware and the design functionality and must be included in board designs. the connector is a 20-pin header that mates with the idc sockets mounted on a ribbon cable. table 2.6 details the pinout of the 20-pin header. table 2.6 20-pin multi-ice header pinout pin number signal pin number signal 1 vdd 2 vdd 3 trst_ice/ 1 1. the designer must connect a 4.7 k ? resistor from this signal to 3.3 v. 4 vss 5 tdi_ice 1 6 vss 7 tms_ice 1 8 vss 9 tck_ice 1 10 vss 11 rtck_ice 12 vss 13 tdo_ice 14 vss 15 tst_rst/ 1 16 vss 17 no connect 18 vss 19 no connect 20 vss
LSI53C1020 pci-x to ultra320 scsi controller 3-1 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. chapter 3 signal description this chapter describes the input and output signals of the LSI53C1020. this chapter contains the following sections: ? section 3.1, ?ignal organization ? section 3.2, ?ci bus interface signals ? section 3.3, ?ci-related signals ? section 3.4, ?csi interface signals ? section 3.5, ?emory interface ? section 3.6, ?ero channel raid (zcr) interface ? section 3.7, ?est interface ? section 3.8, ?pio and led signals ? section 3.9, ?ower and ground pins ? section 3.10, ?ower-on sense pins description ? section 3.11, ?nternal pull-ups and pull-downs a slash (/) at the end of a signal indicates that the signal is active low. when the slash is absent, the signal is active high. nc designates a no connect signal.
3-2 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.1 signal organization the LSI53C1020 has six major interfaces: ? pci bus interface ? scsi bus interface ? memory bus interface ? zcr interface ? test interface ? gpio interface there are ?e signal types: i input, a standard input-only signal o output, a standard output driver (typically a totem pole output) i/o input and output (bidirectional) ppower g ground figure 3.1 contains the functional signal groupings of the LSI53C1020. figure 5.12 on page 5-14 provides a diagram of the LSI53C1020 456 ball grid array (bga). table 5.16 and table 5.17 ,on page 5-16 and page 5-18 respectively, provide pinout listings for the LSI53C1020.
signal organization 3-3 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 3.1 LSI53C1020 functional signal grouping adsc/ adv/ mclk flshale[1:0]/ flshce/ bwe[1:0]/ clk rst/ ad[63:0] c_be[7:0]/ pa r par64 ack64/ req64/ frame/ trdy/ irdy/ stop/ devsel/ idsel req/ gnt/ perr/ serr/ inta/ alt_inta/ mad[15:0] sclk sd[15:0] sdp[1:0] scd sio smsg sreq sbsy satn srst ssel diffsens LSI53C1020 test interface scsi bus interface system address and data interface control arbitration error reporting interrupt memory interface interface sctrl/ sack gpio and led signals madp[1:0] ramce/ serialdata serialclk moe/ tracepkt[7:0] pipestat[2:0] traceclk tracesync tck_ice tms_ice tdi_ice trst_ice/ rtck_ice tck_chip tst_rst/ tms_chip tdi_chip tdo_chip iddtn scanen gpio[7:0] a_led/ b_led/ hb_led/ a_rbias pci bus pvt2 tdo_ice pci-related signals clkmode_0 dis_scsi_fsn/ testhclk testaclk testclken scanmode tn dis_pci_fsn/ clkmode_1 zcr_en/ iopd_gnt/ zcr interface pvt1
3-4 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.2 pci bus interface signals this section describes the pci interface. the pci interface consists of the system, address and data, interface control, arbitration, error reporting, and interrupt signal groups. 3.2.1 pci system signals table 3.1 describes the pci system signals group. table 3.1 pci system signals signal name bga position type strength description clk ac22 i n/a refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. rst/ ab10 i n/a refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description.
pci bus interface signals 3-5 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.2.2 pci address and data signals table 3.2 describes the pci address and data signals group. table 3.2 pci address and data signals signal name bga position type strength description ad[63:0] w22, ab25, ac26, aa25, w23, y25, y26, v22, u22, v24, v23, u24, v25, w26, u23, u25, t22, t23, t25, r25, r22, p22, p23, r23, p24, p25, t26, r26, m26, l26, n25, n24, ae9, af8, ae10, ab11, ac11, ae11, ae12, ab12, ac12, ad13, ae13, af11, af16, ae14, ac15, ac14, ad17, ae19, ac18, ab17, ab18, af20, ae20, ac19, af23, ae22, ab19, ad21, af24, ac20, ae23, ac21 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. c_be[7:0]/ aa23, ac25, y23, ad26, ab13, ab14, ae18, ae21 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. par af19 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. par64 aa24 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description.
3-6 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.2.3 pci interface control signals table 3.3 describes the pci interface control signals group. table 3.3 pci interface control signals signal name bga position type strength description ack64/ ab20 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. req64/ ad22 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. frame/ ab15 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. irdy/ ae15 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. trdy/ ae16 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. devsel/ ac16 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. stop/ ab16 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. idsel ac13 i n/a refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description.
pci bus interface signals 3-7 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.2.4 pci arbitration signals table 3.4 describes the pci arbitration signals group. 3.2.5 pci error reporting signals table 3.5 describes the pci error reporting signals group. table 3.4 pci arbitration signals signal name bga position type strength description req/ ad10 o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. gnt/ ae8 i n/a refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. table 3.5 pci error reporting signals signal name bga position type strength description perr/ ae17 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. serr/ ac17 i/o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description.
3-8 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.2.6 pci interrupt signals table 3.6 describes the pci interrupt signal. 3.3 pci-related signals table 3.7 describes the pci-related signals group. table 3.6 pci interrupt signal signal name bga position type strength description inta/ ac8 o 8 ma pci refer to the pci local bus speci?ation, version 2.2 , and the pci-x addendum to the pci local bus speci?ation, version 1.0a ,for this signal description. the LSI53C1020 can route the interrupt signal to either inta/ or alt_inta/. the interrupt request routing mode bits, bits [9:8] in the host interrupt mask register, controls the routing of interrupt signals to either inta/ and/or alt_inta/. refer to the host interrupt mask register, page 4-41 ,for more detailed information. table 3.7 pci-related signals signal name bga position type strength description alt_inta/ af7 o 8 ma pci active low alternate interrupt a indicates that the pci function is requesting service from its host device driver. alt_inta/ is an open drain signal. the interrupt request routing mode bits, bits [9:8] in the host interrupt mask register, controls the routing of interrupt signals to either inta/ and/or alt_inta/. refer to the host interrupt mask register for more detailed information. pvt2, pvt1 af4, ae5 i n/a pvt2 and pvt1 provide biasing for pci signals. connect a 49.9 ? , 1% resistor between pvt2 and pvt1.
scsi interface signals 3-9 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.4 scsi interface signals this section describes the signals for the scsi channel interface. table 3.8 describes the scsi bus interface clock signal. in the lvd mode, the negative and positive signals form the differential pair. in the se mode, the negative signals represent the signal pin and the positive signals are a virtual ground. the LSI53C1020 does not support the hvd mode. if hvd signaling is present, the scsi channel 3-states its drivers. table 3.8 scsi bus clock signal signal name bga position type strength description sclk f3 i n/a scsi clock provides the 80 mhz reference clock source for the arm966e-s processors and all scsi-related timings.
3-10 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 3.9 describes the scsi channel interface signals group. table 3.10 describes the scsi channel control signals group. table 3.9 scsi channel interface signals signal name bga position type strength description sd[15:0] ? sd[15:0]+ y1, aa2, ab2, ad1, f2, g2, j4, h1, r4, t5, t2, u2, u5, v2, v4, w4 w5, y2, aa3, ac1, d1, g1, h4, h2, p3, r5, r2, t4, u4, u3, v5, v3 i/o se: 48 ma lvd: 12 ma scsi channel data signals. sdp[1:0] ? sdp[1:0]+ w2, p4 w1, p5 i/o se: 48 ma lvd: 12 ma scsi channel data parity signals. a_vddbias t1 p n/a a_vddbias provides power for the a_rbias circuit. a_rbias r1 i n/a connect a 9.76 k ? or 10.0 k ? resistor between the a_vddbias and a_rbias pins to generate the lvd signaling pad bias current. diffsens e2 i n/a the scsi channel differential sense pin detects the present mode of the scsi bus. this signal is 5 v tolerant and must connect to the diffsens signal on the physical scsi bus. se mode: driving this pin below 0.5 v (low) indicates an se bus and places the scsi channel in the se bus mode. lvd mode: driving between 0.7 v and 1.9 v (intermediate) indicates an lvd mode and places the scsi channel in the lvd bus mode. hvd mode: driving this pin above 2.0 v (high) indicates an hvd and causes the scsi channel to 3-state its scsi drivers.
scsi interface signals 3-11 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 3.10 scsi channel control signals signal name bga position type strength description scd ? scd+ sio ? sio+ smsg ? smsg+ sreq ? sreq+ sack ? sack+ sbsy ? sbsy+ satn ? satn+ srst ? srst+ ssel ? ssel+ k3 k4 k5 j5 l2 l1 j2 j3 m5 l5 n3 n4 m4 n5 m1 m2 l4 k2 i/o se: 48 ma lvd: 12 ma scsi channel command/data . scsi channel input/output . scsi channel message . scsi channel request . scsi channel acknowledge . scsi channel busy . scsi channel attention . scsi channel bus reset . scsi channel select.
3-12 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.5 memory interface table 3.11 describes the flash rom/nvsram interface signals group. table 3.11 flash rom/nvsram interface signals signal name bga position type strength description mclk e20 o 4 ma reserved. adsc/ d21 o 4 ma reserved. adv/ b23 o 4 ma reserved. mad[15:0] d22, e21, b25, d23, e22, c24, f22, e23, d26, e25, h22, f24, g23, d25, f23, g22 i/o 8 ma the memory address and data bus carries the memory and address signals for the flash rom and nvsram interfaces on mad[7:0]. these pins also provide the power-on sense options that con?ure operating parameters during chip power-up or reset. madp[1:0] c22, b24 i/o 8 ma the memory address and data parity signals provide parity checking for mad[15:0]. by default, the LSI53C1020 uses even parity. the user can enable odd parity through the fusion-mpt architecture. these pins also provide the power-on sense options that con?ure operating parameters during chip power-up or reset. moe/ g26 o 4 ma the LSI53C1020 asserts active low memory output enable to indicate that the selected nvsram or flash rom device can drive data. this signal is typically an asynchronous input to nvsram and/or flash rom devices. bwe[1:0]/ e24, h23 o 8 ma the LSI53C1020 asserts active low memory byte write enables to allow single byte writes to the nvsram. bwe0/ enables writes on mad[7:0]. ramce/ d20 o 8 ma when mad[3] is pulled high, the LSI53C1020 asserts active low synchronous ram chip enable to select the nvsram.
zero channel raid (zcr) interface 3-13 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 3.12 describes the serial eeprom interface signals group. 3.6 zero channel raid (zcr) interface table 3.13 describes the zcr con?uration signals group. flshce/ g25 o 8 ma the LSI53C1020 asserts active low flash chip enable to enable data transfers with a single 8-bit device. flshale[1:0]/ j24, k22 o 8 ma the flash rom and nvsram interfaces use active low flash address latch enable .for the flash rom, these signals provide clocks for address latches. for the nvsram, these signals provide the memory address strobe. table 3.11 flash rom/nvsram interface signals (cont.) signal name bga position type strength description table 3.12 serial eeprom interface signals signal name bga position type strength description serialclk j25 o 8 ma serial eeprom clock . this signal requires a 4.7 k ? external pull-up resistor when an eeprom is present. serialdata h26 i/o 8 ma serial eeprom data . this signal requires a 4.7 k ? external pull-up resistor when an eeprom is present. table 3.13 zcr con?uration signals signal name bga position type strength description zcr_en/ n23 i n/a this signal enables and disables zcr support on the LSI53C1020. by default, this signal is internally pulled high to disable zcr operation. pull this signal low to enable zcr operation. iopd_gnt/ ac5 i n/a when zcr is enabled on the LSI53C1020, the device only responds to pci con?uration cycles if iopd_gnt/ or idsel is asserted. connect iopd_gnt/ to pci gnt/ on the external i/o processor.
3-14 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.7 test interface table 3.14 describes the jtag, ice, and debug signals group. table 3.14 jtag, ice, and debug signals signal name bga position type strength description tst_rst/ ad5 i n/a active low test reset is for test purposes. tck_chip ac6 i n/a chip test clock provides a jtag test clock signal. tdi_chip af3 i n/a chip test data in provides the jtag test data in signal. tdo_chip ad6 o 8 ma chip test data out provides the jtag test data out signal. tms_chip ae4 i n/a chip test mode select provides the jtag test mode select signal. rtck_ice aa5 o 8 ma test clock acknowledge provides the jtag test clock acknowledge signal for the ice debug logic. trst_ice/ ab4 i n/a test reset provides the jtag test reset signal for the ice debug logic. tck_ice aa4 i n/a test clock provides the jtag test clock signal for the ice debug logic. tdi_ice ab3 i n/a test data in provides the jtag test data in signal for the ice debug logic. tdo_ice ad2 o 8 ma test data out provides the jtag test data out signal for the ice debug logic. tms_ice y5 i n/a test mode select provides the test mode select signal for the ice debug logic. traceclk b3 o 8 ma reserved. tracepkt[7:0] f4, g5, e3, c2, e4, f5, b2, d4 o 8 ma reserved. tracesync e5 o 8 ma reserved. pipestat[2:0] c3, e6, d5 o 8 ma reserved.
test interface 3-15 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 3.15 lists the lsi logic test signals group. table 3.15 lsi logic test signals signal name bga position type strength description scanen n22 i n/a scanen is for use only by lsi logic. scanmode e7 i n/a scanmode is for use only by lsi logic. iddtn y4 i n/a iddtn is for use only by lsi logic. clkmode_0 aa22 i n/a clkmode_0 is for use only by lsi logic. clkmode_1 ac2 i n/a clkmode_1 is for use only by lsi logic. dis_pci_fsn/ a24 i n/a pulling dis_pci_fsn/ low disables the pci fsn. pulling this pin high allows the chip to enable the pci fsn when operating in pci-x mode, or to disable the pci fsn when operating in pci mode. the LSI53C1020 controls the pci fsn. dis_scsi_fsn/ ac4 i n/a dis_scsi_fsn/ is for use only by lsi logic. testaclk ab6 i n/a testaclk is for use only by lsi logic. testhclk ae2 i n/a testhclk is for use only by lsi logic. tn c5 i n/a tn is for use only by lsi logic. testclken d7 i n/a testclken is for use only by lsi logic.
3-16 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.8 gpio and led signals table 3.16 describes the gpio and led signals group. table 3.16 gpio and led signals signal name bga position type strength description gpio[7:0] k25, l23, l25, m25, h25, k24, ae25, ac23 i/o 8 ma general purpose i/o pins . the LSI53C1020 controls these signals and can con?ure them as inputs or as outputs. these pins default to input mode after chip initialization. a_led/ j23 o 12 ma a_led/ either drives the scsi channel activity led or provides a general purpose i/o pin. a_led can be controlled by ?mware or driven by chip activity. b_led/ k23 o 12 ma b_led/ provides a secondary led or a general purpose i/o pin. firmware controls b_led/. hb_led/ c25 o 12 ma firmware blinks heart beat led at a 1.0-second interval when the iop is operational.
power and ground pins 3-17 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.9 power and ground pins table 3.17 describes the power and ground signals group.
3-18 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 3.17 power and ground pins signal name bga position type strength description vdd_io a1, a2, a6, a10, a14, a18, a22, a26, c7, c11, c15, c19, c23, d3, e26, f1, g24, h3, j26, k1, l24, m3, n26, p1, r24, t3, u26, v1, w24, y3, aa26, ab1, ac24, ad4, ad8, ad12, ad16, ad20, ae26, af1, af5, af9, af13, af17, af21, af25 p n/a vdd_io provides power for the pci bus drivers/receivers, scsi bus drivers/receivers, local memory interface drivers/receivers, and other i/o pins. vss_io a5, a9, a13, a17, a21, a25, b1, b26, c4, c8, c12, c16, c20, d24, e1, f26, g3, h24, j1, k26, l3, l11?16, m11?16, m24, n1, n11?16, p11?16, p26, r3, r11?16, t11?16, t24, u1, v26, w3, y24, aa1, ab26, ac3, ad7, ad11, ad15, ad19, ad23, ae1, af2, af6, af10, af14, af18, af22, af26 g n/a vss_io provides ground for the pci bus drivers/receivers, scsi bus drivers/receivers, local memory interface drivers/receivers, and other i/o pins. vdda 1 ab21, c1 p n/a vdda provides the analog circuit power for the pll circuit. vssa 1 ad24, h5 g n/a vssa provides the analog circuit ground for the pll circuit. vddc d2, d6, d15, e19, j22, m22, n2, ac7, ad3, ad25, ae3, ae24, af15 p n/a vddc provides power for the core logic. vssc b4, c14, c21, c26, f25, g4, l22, p2, ab5, ab7, ab8, ab23, ab24, ad14 g n/a vssc provides ground for the core logic. pci5vbias m23, w25, y22, ab22, ac10, ad9, ad18, ae6, af12 i n/a connect the pci 5 v tolerant pins to 5 v in a 5 v system or to 3.3 v in a 3.3 v system. nc a3, a4, a7, a8, a11, a12, a15, a16, a19, a20, a23, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15, b16, b17, b18, b19, b20, b21, b22, c6, c9, c10, c13, c17, c18, d8, d9, d10, d11, d12, d13, d14, d16, d17, d18, d19, e8, e9, e10, e11, e12, e13, e14, e15, e16, e17, e18, ab9, ac9, ae7 n/a no connect. 1. to reduce signal noise that can affect fsn functionality, place a ferrite bead in series with the vdda and vssa pins. lsi logic recommends a bead with a rating of 150 ? at 100 mhz.
power-on sense pins description 3-19 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.10 power-on sense pins description in addition to providing the address/data bus for the external memory interface, mad[15:0] and madp[1:0] provide 18 power-on sense pins that con?ure global operating conditions within the LSI53C1020. the mad[15:0] and madp[1:0] pins have internal pull-down current sinks and sense a logical 0 if no pull-up resistor is present on the pin. to program a particular option, allow the internal pull-down to pull the pin low or a 4.7 k ? resistor between the appropriate pin and vdd to pull the pin high. the LSI53C1020 samples these pins during pci reset and holds their values upon the removal of pci reset. table 3.18 provides the mad power-on sense pin con?uration options. lsi logic expects most con?urations to employ the default settings. provide pull-up options for all mad pins.
3-20 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. ? madp[1] , reserved. ? madp[0], pci-x mode by default, internal logic pulls this pin low to enable the pci-x mode on the LSI53C1020. pulling this pin high disables the pci-x mode on the LSI53C1020. pull this pin high when the host board does not support the pci-x mode. the setting of this pin must coincide with the setting of the pci_cap pin on the host board. when the pci-x mode is disabled, the pci-x extended capabilities register structure is not visible in pci configuration space. table 3.18 mad power-on sense pin options mad pin function pulled-down (default) pulled-up madp[1] reserved madp[0] pci-x mode enables the pci-x mode. disables the pci-x mode. mad[15] 133 mhz pci-x enables 133 mhz pci-x mode. disables the 133 mhz pci-x mode. mad[14] 64-bit pci con?ures a 64-bit pci bus. con?ures a 32-bit pci bus. mad[13] 66 mhz pci enables the 66 mhz pci mode. disables the 66 mhz pci mode. mad[12:11] reserved mad[10] id control has no effect. sets bit [15] of the subsystem id register to 0b1. mad[9:8] reserved mad[7] serial eeprom download enable enables the download of the pci con?uration information from the serial eeprom. disables the download of the pci con?uration information from the serial eeprom. mad[6] iop boot enable enables the iop boot process. disables the iop boot process. mad[5:4] reserved mad[3] nvsram sense has no effect. con?ures the LSI53C1020 to support an nvsram. mad[2:1] flash rom size con?ures the flash rom size according to table 3.19 . mad[0] reserved
power-on sense pins description 3-21 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. ? mad[15], 133 mhz pci-x by default, internal logic pulls this pin low to enable 133 mhz pci-x operation and to set the 133 mhz capable bit in the pci-x status register. pulling this pin high disables 133 mhz pci-x operation and clears the 133 mhz capable bit in the pci-x status register. ? mad[14], 64-bit pci by default, internal logic pulls this pin low to enable 64-bit pci operation and to set the 64-bit enable bit in the pci-x status register. pulling this pin high con?ures the pci connection as a 32-bit connection and clears the 64-bit enable bit in the pci-x status register. ? mad[13], 66 mhz pci by default, internal logic pulls this pin low to enable 66 mhz pci operation on the LSI53C1020 and to set the 66 mhz capable bit in the pci status register. pulling this pin high disables 66 mhz pci operation and clears the 66 mhz capable bit in the pci status register. ? mad[12:11], reserved. ? mad[10], id control by default, internal logic pulls this pin low. pulling this signal low either allows the serial eeprom to program bit 15 of the subsystem id register or allows this bit to default to 0b0. pulling this pin high sets this bit to 0b1. ? mad[9:8] , reserved. ? mad[7], serial eeprom download enable by default, internal logic pulls this pin low to enable the download of pci con?uration information from the serial eeprom. pulling this pin high disables the download of the pci con?uration information from the serial eeprom. disabling the download of pci con?uration information defaults the subsystem vendor id register to 0x1000 and defaults the subsystem id register to either 0x1000 if mad[10] is pulled low or to 0x9000 if mad[10] is pulled high. ? mad[6], iop boot enable by default, internal logic pulls this pin low. in the default mode, the iop starts the boot process and downloads ?mware from the flash rom. pulling this pin high causes the iop to await a rmware download from the host system. ? mad[5:4], reserved. ? mad[3], nvsram select by default, internal logic pulls this pin low, which has no effect on the LSI53C1020. pulling this pin high con?ures the external memory interface as an nvsram interface.
3-22 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. ? mad[2:1], flash rom size these pins program the size of the flash rom memory. refer to table 3.19 for the pin encoding. by default, internal logic pulls these pins low to indicate that a flash rom is not present in the system. ? mad[0] , reserved. table 3.19 flash rom size programming mad[2:1] options flash rom size 0b00 flash rom not present (default) 0b01 up to 1024 kbytes 1 1. choose this setting for a 128 kbyte or 512 kbyte flash rom. 0b10 reserved 0b11
internal pull-ups and pull-downs 3-23 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 3.11 internal pull-ups and pull-downs table 3.20 describes the pull-up and pull-down signals for the LSI53C1020. table 3.20 pull-up and pull-down signal conditions signal name bga position pull type mad[15:0], madp[1:0] d22, e21, b25, d23, e22, c24, f22, e23, d26, e25, h22, f24, g23, d25, f23, g22, c22, b24 internal pull-down. serialdata, serialclk h26, j25 internal pull-down. pull-up externally when connected to a serial eeprom. gpio[7:0] k25, l23, l25, m25, h25, k24, ae25, ac23 internal pull-down. tst_rst/ ad5 internal pull-up. tck_chip, tdi_chip, tms_chip ac6, af3, ae4 internal pull-down. trst_ice/, tck_ice, tdi_ice, tms_ice ab4, aa4, ab3, y5 internal pull-down. scanen, scanmode, iddtn, clkmode_0, clkmode_1, testaclk, testclken n22, e7, y4, aa22, ac2, ab6, d7 internal pull-down. dis_scsi_fsn/, testhclk, tn ac4, ae2, c5 internal pull-up. dis_pci_fsn/ a24 internal pull-down. pull up externally to enable correct operation of the pci fsn. zcr_en/, iopd_gnt/ n23, ac5 internal pull-up.
3-24 signal description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved.
LSI53C1020 pci-x to ultra320 scsi controller 4-1 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. chapter 4 pci host register description this chapter describes the pci host register space. this chapter contains the following sections: ? section 4.1, ?ci con?uration space register description ? section 4.2, ?/o space and memory space register description the register map at the beginning of each register description provides the default bit settings for the register. shading indicates a reserved bit or register. do not access reserved address areas. the pci system address space consists of three regions: con?uration space, memory space, and i/o space. pci con?uration space supports the identi?ation, con?uration, initialization, and error management functions for the LSI53C1020 pci device. pci memory space [0] and memory space [1] form the pci memory space. pci memory space [0] provides normal system accesses to memory, and pci memory space [1] provides diagnostic memory accesses. pci i/o space provides normal system access to memory. 4.1 pci con?uration space register description this section provides bit level descriptions of the fusion-mpt pci con?uration space registers. table 4.1 de?es the pci con?uration space registers. the LSI53C1020 enables, orders, and locates the pci extended capability register structures (power management, messaged signaled interrupts, and pci-x) to optimize device performance. the LSI53C1020 does not hard code the location and order of the pci extended capability structures. the address and location of the pci extended capability structures are subject to change. to access a pci extended capability
4-2 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. structure, follow the pointers held in the capability pointer registers and identify the extended capability structure with the capability id register for the given structure. table 4.1 LSI53C1020 pci con?uration space address map 31 24 23 16 15 8 7 0 offset page device id vendor id 0x00 4-3 status command 0x04 4-3 class code revision id 0x08 4-7 reserved header type latency timer cache line size 0x0c 4-8 i/o base address 0x10 4-10 memory [0] low 0x14 4-10 memory [0] high 0x18 4-11 memory [1] low 0x1c 4-11 memory [1] high 0x20 4-12 reserved 0x24 0x28 subsystem id subsystem vendor id 0x2c 4-13 expansion rom base address 0x30 4-15 reserved capabilities pointer 0x34 4-16 0x38 maximum latency minimum grant interrupt pin interrupt line 0x3c 4-17 reserved 0x40 0x7f power management capabilities pm next pointer pm capability id 4-19 pm data pm bse power management control/status 4-21 reserved message control msi next pointer msi capability id 4-23 message address 4-25 message upper address 4-25 message data 4-26 reserved pci-x command pci-x next pointer pci-x capability id 4-27 pci-x status 4-29 reserved
pci con?uration space register description 4-3 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x00C0x01 vendor id read only vendor id [15:0] this 16-bit register identi?s the manufacturer of the device. the vendor id is 0x1000. register: 0x02C0x03 device id read only device id [15:0] this 16-bit register identi?s the particular device. the default device id is 0x0030. register: 0x04C0x05 command read/write the command register provides coarse control over the pci functions ability to generate and respond to pci cycles. writing a zero to this register logically disconnects the LSI53C1020 pci function from the pci bus for all accesses except con?uration accesses. 15 0 vendor id 0001000000000000 15 0 device id 0000000000110000 15 876543210 command 0 0 0 0 0 0 00 00 00 0000
4-4 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. reserved [15:9] this ?ld is reserved. serr/ enable 8 setting this bit enables the LSI53C1020 to activate the serr/ driver. clearing this bit disables the serr/ driver. reserved 7 this bit is reserved. enable parity error response 6 setting this bit enables the LSI53C1020 pci function to detect parity errors on the pci bus and report these errors to the system. clearing this bit causes the LSI53C1020 pci function to set the detected parity error bit, bit 15 in the pci status register, but not to assert perr/ when the pci function detects a parity error. this bit only affects parity checking. the pci function always generates parity for the pci bus. reserved 5 this bit is reserved. write and invalidate enable 4 setting this bit enables the pci function to generate write and invalidate commands on the pci bus when operating in the conventional pci mode. reserved 3 this bit is reserved. enable bus mastering 2 setting this bit allows the pci function to behave as a pci bus master. clearing this bit disables the pci function from generating pci bus master accesses. enable memory space 1 this bit controls the ability of the pci function to respond to memory space accesses. setting this bit allows the LSI53C1020 to respond to memory space accesses at the address range speci?d by the memory [0] low , memory [0] high , memory [1] low , memory [1] high , and the expansion rom base address registers. clearing this bit disables the pci functions response to memory space accesses.
pci con?uration space register description 4-5 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. enable i/o space 0 this bit controls the pci functions response to i/o space accesses. setting this bit enables the pci function to respond to i/o space accesses at the address range the pci con?uration space i/o base address register speci?s. clearing this bit disables the pci functions response to i/o space accesses. register: 0x06C0x07 status read/write reads to this 16-bit register behave normally. to clear a bit location that is currently set, write the bit to one (1). for example, to clear bit 15 when it is set, and to not affect any other bits, write 0x8000 to the register. detected parity error (from slave) 15 this bit is set according to the pci local bus speci?ation, revision 2.2 , and pci-x addendum to the pci local bus speci?ation, revision 1.0a . signaled system error 14 the LSI53C1020 pci function sets this bit when asserting the serr/ signal. received master abort (from master) 13 a master device sets this bit when a master abort command terminates its transaction (except for special cycle). received target abort (from master) 12 a master device sets this bit when a target abort command terminates its transaction. reserved 11 this bit is reserved. 1514131211109876543 0 status 0000 0010 0 011 0 0 0 0
4-6 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. devsel/ timing [10:9] these two read-only bits encode the timing of devsel/ and indicate the slowest time that a device asserts devsel/ for any bus command except configuration read and configuration write. the LSI53C1020 only supports medium devsel/ timing. the possible timing values are as follows: data parity error reported 8 this bit is set according to the pci local bus speci?ation, revision 2.2 , and pci-x addendum to the pci local bus speci?ation, revision 1.0a . refer to bit 0 of the pci-x command register for more information. reserved [7:6] this ?ld is reserved. 66 mhz capable 5 the mad[13] power-on sense pin controls this bit. allowing the internal pull-down to pull mad[13] low sets this bit and indicates to the host system that the LSI53C1020 pci function is capable of operating at 66 mhz. pulling mad[13] high clears this bit and indicates to the host system that the LSI53C1020 pci function is not con?ured to operate at 66 mhz. refer to section 3.10, ?ower-on sense pins description, page 3-19 , for more information. new capabilities 4 the LSI53C1020 pci function sets this read-only bit to indicate a list of pci extended capabilities such as pci power management, msi, and pci-x support. reserved [3:0] this ?ld is reserved. 0b00 fast 0b01 medium 0b10 slow 0b11 reserved
pci con?uration space register description 4-7 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x08 revision id read/write revision id [7:0] this 8-bit register indicates the current revision level of the device. register: 0x09C0x0b class code read only class code [23:0] this 24-bit register identi?s the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identi?s a speci? register-level programming interface. the value of this register is 0x010000, which identi?s a scsi controller. 7 0 revision id xxxxxxxx 23 0 class code 000000010000000000000000
4-8 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x0c cache line size read/write cache line size [7:3] this 8-bit register speci?s the system cache line size in units of 32-bit words. in the conventional pci mode, the LSI53C1020 pci function uses this register to determine whether to use write and invalidate or write commands for performing write cycles. programming this register to a number other than a nonzero power of two disables the the use of the pci performance commands to execute data transfers. the pci function ignores this register when operating in the pci-x mode. reserved [2:0] this ?ld is reserved. register: 0x0d latency timer read/write latency timer [7:4] this 8-bit register speci?s, in units of pci bus clocks, the value of the latency timer for this pci bus master. if the LSI53C1020 initializes in the pci mode, the default value of this register is 0x00. if the LSI53C1020 initializes in the pci-x mode, the default value of this register is 0x40. reserved [3:0] this ?ld is reserved. 7320 cache line size 00000 0 0 0 7430 latency timer 0x00 0 0 0 0
pci con?uration space register description 4-9 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x0e header type read only header type [7:0] this 8-bit register identi?s the layout of bytes 0x10 through 0x3f in con?uration space and identi?s the LSI53C1020 as a single function pci device. register: 0x0f reserved reserved [7:0] this register is reserved. 7 0 header type 00000000 7 0 reserved 0 0 0 0 0 0 0 0
4-10 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x10C0x13 i/o base address read/write this i/o base address register maps the operating register set into i/o space. the LSI53C1020 requires 256 bytes of i/o space for this base address register. hardware sets bit 0 to 0b1. bit 1 is reserved and returns 0b0 on all reads. i/o base address [31:2] this ?ld contains the i/o base address. reserved [1:0] this ?ld is reserved. register: 0x14C0x17 memory [0] low read/write the memory [0] low register and the memory [0] high register map scsi operating registers into memory space [0]. this register contains the lower 32 bits of the memory space [0] base address. hardware programs bits [9:0] to 0b0000000100, which indicates that the memory space [0] base address is 64 bits wide and that the memory data is not prefetchable. the LSI53C1020 requires 1024 bytes of memory space. memory [0] low [31:0] this ?ld contains the memory [0] low address. 31 210 i/o base address 00000000000000000000000000000001 31 0 memory [0] low 000000000000000000000 0 0 0 0 0 0 0 0 1 0 0
pci con?uration space register description 4-11 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x18C0x1b memory [0] high read/write the memory [0] high register and the memory [0] low register map scsi operating registers into memory space [0]. this register contains the upper 32 bits of the memory space [0] base address. the LSI53C1020 requires 1024 bytes of memory space. memory [0] high [31:0] this ?ld contains the memory [0] high address. register: 0x1cC0x1f memory [1] low read/write the memory [1] low register and the memory [1] high register map the ram into memory space [1]. this register contains the lower 32 bits of the memory space [1] base address. hardware programs bits [12:0] to 0b0000000000100, which indicates that the memory space [1] base address is 64 bits wide and that the memory data is not prefetchable. the LSI53C1020 requires 64 kbytes of memory for memory space [1]. memory [1] low [31:0] this ?ld contains the memory [1] low address. 31 0 memory [0] high 00000000000000000000000000000000 31 0 memory [1] low 000000000000000000 0 0 0 0 0 0 0 0 0 0 0 1 0 0
4-12 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x20C0x23 memory [1] high read/write the memory [1] high register and the memory [1] low register map the ram into memory space [1]. this register contains the upper 32 bits of the memory space [1] base address. the LSI53C1020 requires 64 kbytes of memory for memory space [1]. memory [1] high [31:0] this ?ld contains the memory [1] high address. register: 0x24C0x27 reserved reserved [31:0] this register is reserved. register: 0x28C0x2b reserved reserved [31:0] this register is reserved. 31 0 memory [1] high 00000000000000000000000000000000 31 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pci con?uration space register description 4-13 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x2cC0x2d subsystem vendor id read only subsystem vendor id [15:0] this 16-bit register uniquely identifies the vendor that manufactures the add-in board or subsystem where the LSI53C1020 resides. this register provides a mechanism for an add-in card vendor to distinguish their cards from another vendors cards, even if the cards use the same pci controller (and have the same vendor id and device id). the external serial eeprom can hold a vendor-speci?, 16-bit value for this register, which the board designer must obtain from the pci special interest group (pci-sig). by default, an internal pull down on the mad[7] power-on sense pin enables the serial eeprom interface so that the LSI53C1020 can load this register from the serial eeprom at power-up. if the download from the eeprom fails, this register contains 0x0000. if the board designer disables the eeprom interface by pulling the mad[7] power-on sense pin high, this register returns a value of 0x1000. refer to section 3.10, ?ower-on sense pins description, page 3-19 , for more information. 15 0 subsystem vendor id xxxxxxxxxxxxxxxx
4-14 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x2eC0x2f subsystem id read only subsystem id [15:0] this 16-bit register uniquely identi?s the add-in board or subsystem where this pci device resides. this register provides a mechanism for an add-in card vendor to distinguish their cards from one another even if the cards use the same pci controller (and have the same vendor id and device id). the board designer can store a vendor-speci?, 16-bit value in an external serial eeprom. the id control power-on sense pin (mad[10]) and the serial eeprom enable power-on sense pin (mad[7]) control the value of this register. these pins have internal pull-downs. allowing mad[7] to remain internally pulled down enables the serial eeprom interface and permits the LSI53C1020 to load this register from the serial eeprom at power up. pulling mad[7] high disables the serial eeprom interface. allowing the id control pin to remain internally pulled low has no effect on this register. pulling the id control pin high sets bit [15] of this register. pulling the id control pin high takes precedence over all other settings for bit [15]. table 4.2 lists the configuration options for the power-on sense pins and settings for this register. if the serial eeprom interface is disabled and the id control pin is internally pulled low, this register contains 0x1000. if the serial eeprom interface is disabled and the id control pin is pulled high, this register contains 0x9000. if a download from the serial eeprom fails and the id control pin is internally pulled low, this register contains 0x0000. if a download from the serial eeprom fails and the id control pin is pulled high, this register contains 0x8000. refer to section 3.10, ?ower-on sense pins description, page 3-19 , for additional information. 15 0 subsystem id xxxxxxxxxxxxxxxx
pci con?uration space register description 4-15 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x30C0x33 expansion rom base address read/write this four-byte register contains the base address and size information for the expansion rom. expansion rom base address [31:11] these bits correspond to the upper 21 bits of the expansion rom base address. the host system detects the size of the external memory by first writing 0xffffffff to this register and then reading the register back. the LSI53C1020 responds with zeros in all don? care locations. the least significant one (1) that remains represents the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register returns ones in the upper 17 bits when written with 0xffffffff and read back. reserved [10:1] this ?ld is reserved. expansion rom enable 0 this bit controls if the device accepts accesses to its expansion rom. setting this bit enables address decoding. depending on the system con?uration, the device can optionally use an expansion rom. note that to access the expansion rom, the user must also set bit 1 in the pci command register. table 4.2 subsystem id register download conditions and values mad[7] state mad[10] low mad[10] high mad[7] low subsystem id = 0xxxxx bits [15:0] are downloaded. 1 (default) 1. the subsystem id register returns 0x0000 if the serial eeprom download fails. subsystem id = 0b1xxxxxxxxxxxxxxx bits [14:0] are downloaded with bit [15] set. 2 2. the subsystem id register returns 0x8000 if the serial eeprom download fails. mad[7] high subsystem id register = 0x1000. subsystem id = 0x9000. 31 11 10 1 0 expansion rom base address 000000000000000000000 0 0 0 0 0 0 0 0 0 00
4-16 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x34 capabilities pointer read only capabilities pointer [7:0] this 8-bit register indicates the location of the first extended capabilities register in pci configuration space. the value of this register varies according to system configuration. register: 0x35C0x37 reserved reserved [23:0] this register is reserved. register: 0x38C0x3b reserved reserved [31:0] this register is reserved. 7 0 capabilities pointer xxxxxxxx 23 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pci con?uration space register description 4-17 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x3c interrupt line read/write interrupt line [7:0] this 8-bit register communicates interrupt line routing information. power-on-self-test (post) software writes the routing information into this register as it con?ures the system. this register indicates the system interrupt controller input to which the pci functions interrupt pin connects. system architecture determines the values in this register. register: 0x3d interrupt pin read only interrupt pin [7:0] the encoding of this read-only register indicates which interrupt pin the function uses. the value for the pci function is 0x01, which indicates that pci function presents interrupts on the inta/ or alt_inta pins. the interrupt request routing mode bits, bits [9:8] in the host interrupt mask register, determine if the function presents interrupts on inta/, alt_inta, or both. 7 0 interrupt line 00000000 7 0 interrupt pin 00000001
4-18 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x3e minimum grant read only min_gnt [7:0] this 8-bit register speci?s the desired settings for the latency timer values in units of 0.25 s. min_gnt this register speci?s how long of a burst period the device needs. the LSI53C1020 sets this register to 0x10 indicating a burst period of 4.0 s. register: 0x3f maximum latency read only max_lat [7:0] this 8-bit register speci?s the desired settings for the latency timer values in units of 0.25 s. this register speci?s how often the device needs to gain access to the pci bus. the LSI53C1020 scsi function sets this register to 0x06 because it requires the pci bus every 1.5 s to maintain a data transfer rate of 320 mbytes/s. 7 0 minimum grant 00010000 7 0 maximum latency 00000110
pci con?uration space register description 4-19 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0xxx power management capability id read only power management capability id [7:0] this 8-bit register indicates the type of the current data structure. this register is set to 0x01 to indicate the power management data structure. register: 0xxx power management next pointer read only power management next pointer [7:0] this 8-bit register contains the pointer to the next item in the pci functions extended capabilities list. the value of this register varies according to system con?uration. 7 0 power management capability id 00000001 7 0 power management next pointer xxxxxxxx
4-20 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0xxx power management capabilities read only pme_support [15:11] these bits de?e the power management states in which the device asserts the power management event (pme) pin. the LSI53C1020 clears these bits because the LSI53C1020 does not provide a pme signal. d2_support 10 the pci function sets this bit because the LSI53C1020 supports power management state d2. d1_support 9 the pci function sets this bit because the LSI53C1020 supports power management state d1. aux_current [8:6] the pci function clears this ?ld because the LSI53C1020 does not support aux_current. device speci? initialization 5 the pci function clears this bit because no special initialization is required before a generic class device driver can use it. reserved 4 this bit is reserved. pme clock 3 the LSI53C1020 clears this bit because the chip does not provide a pme pin. version [2:0] the pci function programs these bits to 0b010 to indicate that the LSI53C1020 complies with the pci power management interface speci?ation, revision 1.1 . 15 11 10 9 8 6 5 4 3 2 0 power management capabilities 0 0 0 0 0 110000 00010
pci con?uration space register description 4-21 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0xxx power management control/status read/write pme_status 15 the pci function clears this bit because the LSI53C1020 does not support pme signal generation from d3 cold . data_scale [14:13] the pci function clears these bits because the LSI53C1020 does not support the power management data register. data_select [12:9] the pci function clears these bits because the LSI53C1020 does not support the power management data register. pme_enable 8 the pci function clears this bit because the LSI53C1020 does not provide a pme signal and disables pme assertion. reserved [7:2] this ?ld is reserved. power state [1:0] these bits determine the current power state of the LSI53C1020. power states are as follows: 15 14 13 12 9 8 7 2 1 0 power management control/status 00000000 0 0 0 0 0 000 0b00 d0 0b01 d1 0b10 d2 0b11 d3 hot
4-22 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0xxx power management bridge support extensions read only power management bridge support extensions [7:0] this 8-bit register indicates pci bridge specific functionality. the LSI53C1020 always returns 0x00 in this register. register: 0xxx power management data read only power management data [7:0] this 8-bit register provides an optional mechanism for the function to report state-dependent operating data. the LSI53C1020 always returns 0x00 in this register. register: 0xxx msi capability id read only msi capability id [7:0] this 8-bit register indicates the type of the current data structure. this register always returns 0x05, indicating message signaled interrupts (msis). 7 0 power management bridge support extensions 00000000 7 0 power management data 00000000 7 0 msi capability id 00000101
pci con?uration space register description 4-23 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0xxx msi next pointer read only msi next pointer [7:0] this 8-bit register points to the next item in the pci functions extended capabilities list. the value of this register varies according to system con?uration. register: 0xxx message control read/write reserved [15:8] this ?ld is reserved. 64-bit address capable 7 the pci function sets this read-only bit to indicate support of a 64-bit message address. multiple message enable [6:4] these read/write bits indicate the number of messages that the host allocates to the LSI53C1020. the host system software allocates all or a subset of the requested messages by writing to this ?ld. the number of allocated request messages must align to a power of two. table 4.3 provides the bit encoding of this ?ld. 7 0 msi next pointer xxxxxxxx 15 8 7 6 4 3 1 0 message control 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
4-24 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. multiple message capable [3:1] these read-only bits indicate the number of messages that the LSI53C1020 requests from the host. the host system software reads this ?ld to determine the number of requested messages. the number of requested messages must align to a power of two. the LSI53C1020 sets this ?ld to 0b000 to request one message. all other encodings of this ?ld are reserved. msi enable 0 system software sets this bit to enable msi. setting this bit enables the device to use msi to interrupt the host and request service. setting this bit also prohibits the device from using the inta/ or alt_inta/ pins to request service from the host. setting this bit to mask interrupts on the inta/ or alt_inta/ pins is a violation of the pci speci?ation. table 4.3 multiple message enable field bit encoding bits [6:4] encoding number of allocated messages 0b000 1 0b001 2 0b010 4 0b011 8 0b100 16 0b101 32 0b110 reserved 0b111 reserved
pci con?uration space register description 4-25 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0xxx message address read/write message address [31:2] this ?ld contains message address bits [31:2] for the msi memory write transaction. the host system speci?s and dword aligns the message address. during the address phase, the LSI53C1020 drives message address[1:0] to 0b00. reserved [1:0] this ?ld is reserved. register: 0xxx message upper address read/write message upper address [31:0] the LSI53C1020 supports 64-bit msi. this 32-bit register contains the upper 32 bits of the 64-bit message address, which the system speci?s. the host system software can program this register to 0x0000 to force the pci function to generate 32-bit message addresses. 31 2 1 0 message address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 message upper address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4-26 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0xxx message data read/write message data [15:0] system software initializes this 16-bit register by writing to it. the LSI53C1020 sends an interrupt message by writing a dword to the address held in the message address and message upper address registers. this register forms bits [15:0] of the dword message that the pci function passes to the host. the pci function drives bits [31:16] of this message to 0x0000. register: 0xxx pci-x capability id read only pci-x capability id [7:0] this 8-bit register indicates the type of the current data structure. this register returns 0x07, indicating the pci-x data structure. 15 0 message data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 pci-x capability id 00000111
pci con?uration space register description 4-27 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0xxx pci-x next pointer read only pci-x next pointer [7:0] this 8-bit register points to the next item in the devices capabilities list. the value of this register varies according to system con?uration. register: 0xxx pci-x command read/write reserved [15:7] this ?ld is reserved. maximum outstanding split transactions [6:4] these bits indicate the maximum number of split transactions the LSI53C1020 can have outstanding at one time. the LSI53C1020 uses the most recent value of this register each time it prepares a new sequence. note that if the LSI53C1020 prepares a sequence before the setting of this ?ld changes, the pci function initiates the prepared sequence with the previous setting. table 4.4 provides the bit encodings for this ?ld. 7 0 pci-x next pointer xxxxxxxx 15 76 43210 pci-x command 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
4-28 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. maximum memory read byte count [3:2] these bits indicate the maximum byte count the LSI53C1020 uses when initiating a sequence with one of the burst memory read commands. table 4.5 provides the bit encodings for this ?ld. table 4.4 maximum outstanding split transactions bits [6:4] encoding maximum outstanding split transactions 0b000 1 0b001 2 0b010 3 0b011 4 0b100 8 0b101 reserved 0b110 reserved 0b111 reserved
pci con?uration space register description 4-29 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. reserved 1 this bit is reserved. data parity error recovery enable 0 the host device driver sets this bit to allow the LSI53C1020 to attempt to recover from data parity errors. if the user clears this bit, and the LSI53C1020 is operating in the pci-x mode, the LSI53C1020 asserts serr/ whenever the master data parity error bit in the pci status register is set. register: 0xxx pci-x status read/write reserved [31:30] this ?ld is reserved. received split completion error message 29 the LSI53C1020 sets this bit upon receipt of a split completion message if the split completion error attribute bit is set. write a one (1) to this bit to clear it. designed maximum cumulative read size [28:26] these read-only bits indicate a number greater than or equal to the maximum cumulative size of all outstanding burst memory read transactions for the LSI53C1020 pci table 4.5 maximum memory read count bits [3:2] encoding maximum memory read byte count 0b00 512 0b01 1024 0b10 2048 0b11 reserved 31 30 29 28 26 25 23 22 21 20 19 18 17 16 15 8 7 3 2 0 pci-x status 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 x x x x x x x x x x x x x 0 0 0
4-30 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. device. the pci function must report the smallest value that correctly indicates its capability. the LSI53C1020 reports 0b001 in this ?ld to indicate a designed maximum cumulative read size of 2 kbytes. designed maximum outstanding split transactions [25:23] these read-only bits indicate a number greater than or equal to the maximum number of all outstanding split transactions for the LSI53C1020 pci device. the pci function must report the smallest value that correctly indicates its capability. the LSI53C1020 reports 0b100 in this ?ld to indicate that the designed maximum number of outstanding split transactions is eight. designed maximum memory read byte count [22:21] these read-only bits indicate a number greater than or equal to the maximum byte count for the LSI53C1020 device. the pci function uses this count to initiate a sequence with one of the burst memory read commands. the pci function must report the smallest value that correctly indicates its capability. the LSI53C1020 reports 0b10 in this ?ld to indicate that the designed maximum memory read bytes count is 2048. device complexity 20 the pci function clears this read-only bit to indicate that the LSI53C1020 is a simple device. unexpected split completion 19 the pci function sets this read-only bit when it receives an unexpected split completion. when set, this bit remains set until software clears it. write a one (1) to this bit to clear it. split completion discarded 18 the pci function sets this read-only bit when it discards a split completion. when set, this bit remains set until software clears it. write a one (1) to this bit to clear it. 133 mhz capable 17 the mad[15] power-on sense pin controls this read-only bit. allowing the internal pull-downs to pull mad[15] low sets this bit and enables 133 mhz operation of the pci bus.
pci con?uration space register description 4-31 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. pulling mad[15] high clears this bit and disables 133 mhz operation of the pci bus. refer to section 3.10, ?ower-on sense pins description, page 3-19 , for more information concerning the power-on sense pins. 64-bit device 16 the mad[14] power-on sense pin controls this read-only bit. allowing the internal pull-downs to pull mad[14] low sets this bit and indicates a 64-bit pci address/data bus. pulling mad[14] high clears this bit and indicates a 32-bit pci address/data bus. if using the LSI53C1020 on an add-in card, this bit must indicate the size of the pci address/data bus on the card. refer to section 3.10, ?ower-on sense pins description, for more information concerning the power-on sense pins. bus number [15:8] these read-only bits indicate the number of the LSI53C1020 bus segment. this pci function uses this number as part of its requester id and completer id. this ?ld is read for diagnostic purposes only. device number [7:3] these read-only bits indicate the device number of the LSI53C1020. this pci function uses this number as part of its requester id and completer id. this ?ld is read for diagnostic purposes only. function number [2:0] these read-only bits indicate the number in the function number field (ad[10:8]) of a type 0 pci configuration transaction. the pci function uses this number as part of its requester id and completer id. this field always returns 0b000 to indicate the single pci function on the LSI53C1020. this field is read for diagnostic purposes only.
4-32 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 4.2 i/o space and memory space register description this section describes the host interface registers in the pci i/o space and pci memory space. these address spaces contain the fusion-mpt interface register set. pci memory space [0] and pci memory space [1] form the pci memory space. pci memory [0] supports normal memory accesses while pci memory space [1] supports diagnostic memory accesses. for all registers except the diagnostic read/write data and diagnostic read/write address registers, access the address offset through either pci i/o space or pci memory space [0]. access to the diagnostic read/write data and diagnostic read/write address registers is only through pci i/o space. table 4.6 de?es the pci i/o space address map. table 4.7 de?es the pci memory space [0] address map. table 4.6 pci i/o space address map 31 0 offset page system doorbell 0x0000 4-34 write sequence 0x0004 4-35 host diagnostic 0x0008 4-36 test base address 0x000c 4-37 diagnostic read/write data 0x0010 4-38 diagnostic read/write address 0x0014 4-39 reserved 0x0018?x002f host interrupt status 0x0030 4-40 host interrupt mask 0x0034 4-41 reserved 0x0038?x003f request fifo 0x0040 4-42 reply fifo 0x0044 4-42 reserved 0x0048?x007f
i/o space and memory space register description 4-33 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 4.8 de?es the pci memory space [1] address map. a bit level description of the pci memory and pci i/o spaces follows. table 4.7 pci memory [0] address map 31 0 offset page system doorbell 0x0000 4-34 write sequence 0x0004 4-35 host diagnostic 0x0008 4-36 test base address 0x000c 4-37 reserved 0x0010?x002f host interrupt status 0x0030 4-40 host interrupt mask 0x0034 4-41 reserved 0x0038?x003f request fifo 0x0040 4-42 reply fifo 0x0044 4-42 reserved 0x0048?x007f shared memory 0x0080 0x(sizeof(mem0)-1) table 4.8 pci memory [1] address map 31 0 diagnostic memory 0x0000 0x(sizeof(mem1) ? 1)
4-34 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x00 system doorbell read/write the system doorbell register is a simple message passing mechanism that allows the system to pass single word messages to the embedded iop processor and vice versa. when a host system pci master writes to the host registers->doorbell register, the LSI53C1020 generates a maskable interrupt to the iop. the value written by the host system is available for the iop to read in the system interface registers->doorbell register. the iop clears the interrupt status after reading the value. conversely, when the iop writes to the system interface registers->doorbell register, the LSI53C1020 generates a maskable interrupt to the pci system. the host system can read the value written by the iop in the host registers->doorbell register. the host system clears the interrupt status bit and interrupt pin by writing any value to the host registers->interrupt status register. host doorbell value [31:0] during a write, this register contains the doorbell value that the host system passes to the iop. during a read, this register contains the doorbell value that the iop passes to the host system. 31 0 system doorbell 00000000000000000000000000000000
i/o space and memory space register description 4-35 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x04 write sequence read/write the write sequence register provides a protection mechanism against inadvertent writes to the host diagnostic register. reserved [31:4] this ?ld is reserved. write i/o key [3:0] to enable write access to the diagnostic read/write data , diagnostic read/write address , and host diagnostic register, perform five data-specific writes to the write i/o key. writing an incorrect value to the write i/o key invalidates the key sequence, and the host must rewrite the entire sequence. the write i/o key sequence is: 0x0004, 0x000b, 0x0002, 0x0007, and 0x000d. to disable write access to the diagnostic read/write data , diagnostic read/write address , and host diagnostic registers, perform a write of any value, except the write i/o key sequence, to the write sequence register. the diagnostic write enable bit, bit 7 in the host diagnostic register, indicates the write access status. 31 43 0 write sequence 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01011
4-36 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x08 host diagnostic read/write the host diagnostic register contains diagnostic controls and status information. this register can only be written when bit 7 of this register is set. reserved [31:8] this ?ld is reserved. diagnostic write enable 7 the LSI53C1020 sets this read-only bit when the host writes the correct write i/o key to the write sequence register. the LSI53C1020 clears this bit when the host writes a value other than the write i/o key to the write sequence register. flash bad signature 6 the LSI53C1020 sets this bit if the iop arm966e-s processor encounters a bad flash signature when booting from flash rom. the LSI53C1020 also sets the disarm bit (bit 1 in this register) to hold the iop arm processor in a reset state. the LSI53C1020 maintains this state until the pci host clears both the flash bad signature and disarm bits. reset history 5 the LSI53C1020 sets this bit if it experiences a power-on reset (por), pci reset, or testreset/. a host driver can clear this bit. diagnostic read/write enable 4 setting this bit enables access to the diagnostic read/write data and diagnostic read/write address registers. 31 876543210 host diagnostic 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001 00 0 x0
i/o space and memory space register description 4-37 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. ttl interrupt 3 setting this bit con?ures pci inta/ as a ttl output. clearing this bit con?ures pci inta/ as an open-drain output. use this bit for test purposes only. reset adapter 2 setting this write-only bit causes a hard reset within the LSI53C1020. the bit self-clears after eight pci clock periods. after deasserting this bit, the iop arm processor executes from its default reset vector. disarm 1 setting this bit disables the arm processor. diagnostic memory enable 0 setting this bit enables diagnostic memory accesses through pci memory space [1]. clearing this bit disables diagnostic memory accesses to pci memory space [1] and returns 0xffff on reads. register: 0x0c test base address read/write the test base address register speci?s the base address for memory space [1] accesses. test base address [31:16] the number of signi?ant bits is determined by the size of the pci memory space [1] in the serial eeprom. reserved [15:0] this ?ld is reserved. 31 16 15 0 test base address 0000000000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4-38 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x10 diagnostic read/write data read/write the diagnostic read/write data register reads or writes dword locations on the LSI53C1020 internal bus. this register is only accessible through pci i/o space and returns 0xffffffff if read through pci memory space. the host can enable write access to this register by writing the correct write i/o key to the write sequence register and setting bit 4, the diagnostic write enable bit, of the host diagnostic register. a write of any value other than the correct write i/o key to the write sequence register disables write access to this register. diagnostic read/write data [31:0] using this register, the LSI53C1020 reads/writes data at the address that the diagnostic read/write address register speci?s. 31 0 diagnostic read/write data 00000000000000000000000000000000
i/o space and memory space register description 4-39 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x14 diagnostic read/write address read/write the diagnostic read/write address register specifies a dword location on the internal bus. the address increments by a dword whenever the host system accesses the diagnostic read/write address register. this register is only accessible through pci i/o space and returns 0xffffffff if read through pci memory space. the host can enable write access to this register by writing the correct write i/o key to the write sequence register and setting bit 4, the diagnostic write enable bit, of the host diagnostic register. a write of any value other than the correct write i/o key to the write sequence register disables write access to this register. diagnostic read/write address [31:0] this register holds the address that the diagnostic read/write data register writes data to or reads data from. 31 0 diagnostic read/write address 00000000000000000000000000000000
4-40 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x30 host interrupt status read/write the host interrupt status register provides read-only interrupt status information to the pci host. a write to this register of any value clears the associated system doorbell interrupt. iop doorbell status 31 the LSI53C1020 sets this bit when the iop receives a message from the system doorbell but has yet to process it. the iop processes the system doorbell message by clearing the corresponding system request interrupt. reserved [30:4] this ?ld is reserved. reply interrupt 3 the LSI53C1020 sets this bit when the reply post fifo is not empty. the LSI53C1020 generates a pci interrupt when this bit is set and the corresponding mask bit in the host interrupt mask register is cleared. reserved [2:1] this ?ld is reserved. system doorbell interrupt 0 the LSI53C1020 sets this bit when the iop writes a value to the system doorbell. the host can clear this bit by writing any value to this register. the LSI53C1020 generates a pci interrupt when this bit is set and the corresponding mask bit in the host interrupt mask register is cleared. 31 30 43210 host interrupt status 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x0 x x0
i/o space and memory space register description 4-41 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. register: 0x34 host interrupt mask read/write the host interrupt mask register masks and/or routes the interrupt conditions that the host interrupt status register reports. reserved [ 31:10] this ?ld is reserved. interrupt request routing mode [9:8] this ?ld routes pci interrupts to the inta/ or alt_inta/ pins according to the bit encodings in table 4.9 . if the host system enables msi, the LSI53C1020 does not signal pci interrupts on the inta/ or alt_inta/ pins. reserved [7:4] this ?ld is reserved. reply interrupt mask 3 setting this bit masks reply interrupts and prevents the assertion of a pci interrupt for all reply interrupt conditions. 31 10987 43210 host interrupt mask x x x x x x x x x x x x x x x x x x x x x x00 x x x x1 x x1 table 4.9 interrupt signal routing bits [9:8] encodings interrupt signal routing 0b00 inta/ and alt_inta/ 0b01 inta/ only 0b10 alt_inta/ only 0b11 inta/ only
4-42 pci host register description version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. reserved [2:1] this ?ld is reserved. doorbell interrupt mask 0 setting this bit masks system doorbell interrupts and prevents the assertion of a pci interrupt for all system doorbell interrupt conditions. register: 0x40 request fifo read/write the request fifo register provides request free message frame addresses (mfas) to the host system on reads and accepts request post mfas from the host system on writes. request fifo [ 31:0] for reads, the request free mfa is empty and this register contains 0xffffffff. for writes, the register contains the request post mfa. register: 0x44 reply fifo read/write the reply fifo register provides reply post mfas to the host system on reads and accepts reply free mfas from the host system on writes. reply fifo [31:0] for reads, the request free mfa is empty and this register contains 0xffffffff. for writes, the register contains the reply free mfa. 31 0 request fifo 11111111111111111111111111111111 31 0 reply fifo 11111111111111111111111111111111
LSI53C1020 pci-x to ultra320 scsi controller 5-1 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. chapter 5 speci?ations this chapter speci?s the LSI53C1020 electrical and physical characteristics. it is divided into the following sections: ? section 5.1, ?c characteristics ? section 5.2, ?olerant technology electrical characteristics ? section 5.3, ?c characteristics ? section 5.4, ?xternal memory timing diagrams ? section 5.5, ?ackage drawings refer to the pci local bus speci?ation , the pci-x addendum to the pci local bus speci?ation , and the s csi parallel interface-4 draft speci?ation for pci, pci-x, and scsi timings and timing diagrams. the LSI53C1020 timings conform to the timings these speci?ations provide. 5.1 dc characteristics this section describes the LSI53C1020 dc characteristics. tables 5.1 through 5.11 give current and voltage speci?ations. figures 5.1 and 5.2 are lvd transceiver schematics.
5-2 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. the core voltage must come up before i/o voltage. the following equation must hold at all times: vdd_i/o (vdd_core + 2 v). table 5.1 absolute maximum stress ratings 1 1. stresses beyond those listed above can damage the device. these are stress ratings only; functional operation of the device at or beyond these values is not implied. symbol parameter min max unit test conditions t stg storage temperature ? 40 125 c v dd-core supply voltage ? 0.3 2.2 v v dd-io io supply voltage ? 0.3 3.9 v v in input voltage ? 0.5 v dd + 0.5 v i lp 2 latch-up current 150 ma ? 2v dc characteristics 5-3 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.1 lvd driver table 5.3 lvd driver scsi signals 1 ?ack ,satn , sbsy , scd , sd[15:0] , sdp[1:0] , sio , smsg , sreq , srst , ssel 1. v cm = 0.7?.8 v (common mode, nominal ~1.2 v), rbias = 10.0 k ?. symbol parameter min max unit test conditions i o + source (+) current ? 6.5 ? 13.5 ma asserted state i o ? sink ( ? ) current 6.5 13.5 ma asserted state i o + source (+) current 2.5 9.5 ma negated state i o ? sink ( ? ) current ? 2.5 ? 9.5 ma negated state i oz 3-state leakage 20 a r l 2 i o + r l 2 i o ? v cm + ? + ? table 5.4 lvd receiver scsi signals 1 ?ack ,satn , sbsy , scd , sd[15:0] , sdp[1:0] , sio , smsg , sreq , srst , ssel 1. v cm = 0.7?.8 v (common mode voltage, nominal ~1.2 v.) symbol parameter min max unit test conditions v i lvd receiver voltage asserting |30| mv differential voltage v i lvd receiver voltage negating ?| 30| mv differential voltage
5-4 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.2 lvd receiver v cm + ? + + + ? ? ? v i 2 v i 2 table 5.5 diffsens scsi signal symbol parameter min max unit test conditions v ih hvd sense voltage 2.4 3.6 v see note 1 1. v ih ,v il , and v s are speci?d in the spi-4 draft speci?ation. v s lvd sense voltage 0.7 1.9 v see note 1 v il se sense voltage vss ? 0.35 0.5 v see note 1 i oz 3-state leakage ? 10 10 av pin = 0 v, 3.6 v table 5.6 input capacitance symbol parameter min max unit test conditions c i input capacitance of input pads 7 pf guaranteed by design c io input capacitance of i/o pads 15 pf guaranteed by design c pci input capacitance of pci pads 8 pf guaranteed by design c lv d input capacitance of lvd pads 8 pf 6.5 pf pad; 1.5 pf package
dc characteristics 5-5 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 5.7 8 ma bidirectional signals gpio[7:0], mad[15:0], madp[1:0], serialdata symbol parameter min max unit test conditions v ih input high voltage 2.0 3.6 v v il input low voltage ? 0.3 0.8 v v oh output high voltage 2.4 vdd v ? 8ma v ol output low voltage vss 0.4 v 8 ma i oz 3-state leakage ? 10 10 av pin = 0 v, 5.25 v i pull pull-up current 25 a table 5.8 8 ma pci bidirectional signals ack64/, ad[63:0], c_be[7:0]/, devsel/, frame/, irdy/, par, par64, perr/, req64/, serr/, stop/, trdy/ symbol parameter min max unit test conditions v ih input high voltage 0.5 vdd pci5vbias 1 v v il input low voltage ? 0.5 0.3 vdd v v oh output high voltage 0.9 vdd vdd v ? 500 a v ol output low voltage vss 0.1 vdd v 1500 a i oz 3-state leakage ? 10 10 av pin = 0 v, 5.25 v i pull-down pull-down current 2 25 a 1. the maximum pci input voltage depends upon the operating mode of the pci bus, which pci5vbias determines. the maximum input voltage in a 5 v pci system is 5 v. the maximum input voltage in a 3.3 v pci system is vdd. refer to the signal description in section 3.9, ?ower and ground pins, page 3-17 , for more information concerning pci5vbias. 2. pull-down text does not apply to ad[31:0] and c_be[3:0]/.
5-6 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 5.9 input signals 1 clk, clkmode_0, clkmode_1, dis_pci_fsn/, dis_scsi_fsn/, gnt/, iddtn, idsel, iopd_gnt/, pvt1, pvt2, scanen, scanmode, sclk, tck_chip, tck_ice, testaclk, testclken, testhclk, tdi_chip, tdi_ice, tms_chip, tms_ice, tn, trst_ice/, tst_rst/, zcr_en/ symbol parameter min max unit test conditions v ih input high voltage 2.0 vdd + 0.5 v v il input low voltage ? 0.3 0.8 v i in 3-state leakage ? 10 10 av pin =0v, vdd + 0.5 v i pull-up pull current 25 a 1. do not place pulls on clk, gnt/, idsel, rst/, and sclk. the pull information given does not apply to these signals. table 5.10 8 ma output signals 1 adsc/, adv/, alt_inta/, bwe[1:0]/, flshale[1:0]/, flshce/, inta/, mclk, moe/, pipestat[2:0], ramce/, req/, rtck_ice, serialclk, tdo_chip, tdo_ice, traceclk, tracepkt[7:0], tracesync symbol parameter min max unit test conditions v oh output high voltage 2.4 vdd v ? 8ma v ol output low voltage vss 0.4 vdd v 8 ma i oz 3-state leakage ? 10 10 av pin = 0 v, 3.6 v i pull-up pull current 25 a 1. do not place pulls on req/ and serr/. the pull information given does not apply to these signals. table 5.11 12 ma output signals a_led/, b_led/, hb_led/ symbol parameter min max unit test conditions v oh output high voltage 2.4 vdd v ? 12 ma v ol output low voltage vss 0.4 vdd v 12 ma i oz 3-state leakage ? 10 10 av pin = 0 v, 3.6 v i pull-up pull current 25 a
tolerant technology electrical characteristics 5-7 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. 5.2 tolerant technology electrical characteristics the LSI53C1020 features tolerant technology, which includes active negation on the scsi drivers and input signal ?tering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. table 5.12 provides electrical characteristics for se scsi signals. figures 5.3 and 5.4 provide the reference information for testing scsi signals. table 5.12 tolerant technology electrical characteristics for se scsi signals 1 symbol parameter min max unit test conditions v oh 2 output high voltage 2.5 3.7 v i oh = 0 ma. v ol output low voltage 0.0 0.5 v i ol = 48 ma. v ih input high voltage 1.9 5.50 v signal false state. v il input low voltage ? 0.5 1.0 v referenced to v ss signal true state. v ik input clamp voltage ? 0.75 v v pp = min; i 1 = ? 20 ma. v th threshold, high to low 1.00 v v tl threshold, low to high 1.90 v v th ? tl hysteresis 375 mv i ih.hp hot plug high level current peak 1.5 ma transient duration of 10% of peak equals 20 s. this applies during physical insertion only. i oh2 output high current 0 7 ma v oh = 2.2 v. i ol output low current 48 ma v ol = 0.5 v. i osh2 short-circuit output high current 48 ma short to v dd 3 . i osl short-circuit output low current 22 ma short to v ss.
5-8 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.3 rise and fall time test condition i lh input high leakage 20 a ? 0.5 ac characteristics 5-9 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.4 scsi input filtering 5.3 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to section 5.1, ?c characteristics, page 5-1 , for more details). chip timing is based on simulation at worst-case voltage, temperature, and processing. timing has been developed with a load capacitance of 50 pf. table 5.13 and figure 5.5 provide external clock timing data. req/ or ack/ input t 1 v th note: t 1 is the input ?tering period. table 5.13 external clock symbol parameter 133 mhz pci-x 66 mhz pci-x 66 mhz pci 33 mhz pci unit min max min max min max min max t 1 pci bus clock period 1 1. for frequencies above 33 mhz, the clock frequency cannot be changed beyond the spread spectrum limits except while rst/ is asserted. 7.5 20 15 20 15 30 30 250 ns scsi clock period 25 25 25 25 25 25 25 25 ns t 2 pci clk low time 2 2. duty cycle not to exceed 60/40. 3?611ns sclk low time 10 15 10 15 10 15 10 15 ns t 3 pci clk high time 3 6 6 11 ns sclk high time 10 15 10 15 10 15 10 15 ns t 4 pci clk slew rate 1.5 4 1.5 4 1.5 4 1 4 v/ns
5-10 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.5 external clock table 5.14 and figure 5.6 provide reset input timing data. figure 5.6 reset input table 5.15 and figure 5.7 provide interrupt output timing data. clk, sclk 1.4 v t 1 t 3 t 4 t 2 table 5.14 reset input symbol parameter min max unit t 1 reset pulse width 10 ns t 2 reset deasserted setup to clk high 0 ns t 3 mad setup time to clk high (for con?uring the mad bus only) 20 ns t 4 mad hold time from clk high (for con?uring the mad bus only) 20 ns t 1 t 2 t 3 t 4 clk rst/ mad* note: *when enabled valid data table 5.15 interrupt output symbol parameter min max unit t 1 clk high to irq/ low 2 11 ns t 2 clk high to irq/ high 2 11 ns t 3 irq/ deassertion time 3 clk
external memory timing diagrams 5-11 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.7 interrupt output 5.4 external memory timing diagrams this section includes timing diagrams for external memory accesses. figure 5.8 to figure 5.11 illustrate accesses to the flash rom. figure 5.8 flash rom address timing t 1 t 2 t 3 irq/ clk addr_ addr_ addr_ addr_ addr_ clk mad flshale[1] flshale[0] flshce/ bwe[0]/ moe/ addr_ hi_set addr_ hi_hold addr_ mid_set addr_ mid_hold addr_ low_set addr_ lo_hold low order address middle order address high order address
5-12 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.9 flash rom read timing figure 5.10 flash rom write timing clk mad flshale[1] flshale[0] low order address data flshce/ bwe[0]/ moe/ addr_ low_set addr_ lo_hold read_setup read_ce rxfer last byte read fl_read_oe default: 21 clk fl_read_hold clk mad flshale[1] flshale[0] low order address valid write data flshce/ bwe[0]/ moe/ addr_ low_set write_data_set wxfer addr_ lo_hold fl_write ce_set fl_write_en default: 16 hclk fl_write ce_hold
package drawings 5-13 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.11 flash rom polling 5.5 package drawings figure 5.12 illustrates the signal locations on the ball grid array (bga). figure 5.13 provides the 456-epbga mechanical drawing for the LSI53C1020. flash operation addr an an an an an data read code* write data * code match bwe[0]/ flshce/ moe/ write read read read write read code read code write code
5-14 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.12 LSI53C1020 456-pin bga top view a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 vdd_io vdd_io nc nc vss_io vdd_io nc nc vss_io vdd_io nc nc vss_io b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 vss_io trace pkt1 traceclk vssc nc nc nc nc nc nc nc nc nc c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 vdda trace pkt4 pipestat2 vss_io tn nc vdd_io vss_io nc nc vdd_io vss_io nc d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 sd11+ vddc vdd_io trace pkt0 pipestat0 vddc testclken nc nc nc nc nc nc e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 vss_io diffsens trace pkt5 trace pkt3 trace sync pipestat1 scanmode nc nc nc nc nc nc f1 f2 f3 f4 f5 vdd_io sd11- sclk trace pkt7 trace pkt2 g1 g2 g3 g4 g5 sd10+ sd10 ? vss_io vssc trace pkt6 h1 h2 h3 h4 h5 sd8- sd8+ vdd_io sd9+ vssa j1 j2 j3 j4 j5 vss_io sreq- sreq+ sd9- sio+ k1 k2 k3 k4 k5 vdd_io ssel+ scd- scd+ sio- l1 l2 l3 l4 l5 l11 l12 l13 smsg+ smsg- vss_io ssel ? sack+ vss_io vss_io vss_io m1 m2 m3 m4 m5 m11 m12 m13 srst ? srst+ vdd_io satn ? sack ? vss_io vss_io vss_io n1 n2 n3 n4 n5 n11 n12 n13 vss_io vddc sbsy ? sbsy+ satn+ vss_io vss_io vss_io p1 p2 p3 p4 p5 p11 p12 p13 vdd_io vssc sd7+ sdp0 ? sdp0+ vss_io vss_io vss_io r1 r2 r3 r4 r5 r11 r12 r13 a_rbias sd5+ vss_io sd7 ? sd6+ vss_io vss_io vss_io t1 t2 t3 t4 t5 t11 t12 t13 a_vddbias sd5 ? vdd_io sd4+ sd6 ? vss_io vss_io vss_io u1 u2 u3 u4 u5 vss_io sd4 ? sd2+ sd3+ sd3 ? v1 v2 v3 v4 v5 vdd_io sd2 ? sd0+ sd1 ? sd1+ w1 w2 w3 w4 w5 sdp1+ sdp1 ? vss_io sd0 ? sd15+ y1 y2 y3 y4 y5 sd15 ? sd14+ vdd_io iddtn tms_ice aa1 aa2 aa3 aa4 aa5 vss_io sd14 ? sd13+ tck_ice rtck_ice ab1 ab2 ab3 ab4 ab5 ab6 ab7 ab8 ab9 ab10 ab11 ab12 ab13 vdd_io sd13 ? tdi_ice trst_ice/ vssc testaclk vssc vssc nc rst/ ad28 ad24 c_be3/ ac1 ac2 ac3 ac4 ac5 ac6 ac7 ac8 ac9 ac10 ac11 ac12 ac13 sd12+ clk mode_1 vss_io dis_scsi_ fsn/ iopd_gnt/ tck_chip vddc inta/ nc pci5vbias ad27 ad23 idsel ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 sd12 ? tdo_ice vddc vdd_io tst_rst/ tdo_chip vss_io vdd_io pci5vbias req/ vss_io vdd_io ad22 ae1 ae2 ae3 ae4 ae5 ae6 ae7 ae8 ae9 ae10 ae11 ae12 ae13 vss_io testhclk vddc tms_chip pvt1 pci5vbias nc gnt/ ad31 ad29 ad26 ad25 ad21 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 vdd_io vss_io tdi_chip pvt2 vdd_io vss_io alt_inta/ ad30 vdd_io vss_io ad20 pci5vbias vdd_io
package drawings 5-15 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.12 LSI53C1020 456-pin bga top view (cont.) a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 vdd_io nc nc vss_io vdd_io nc nc vss_io vdd_io nc dis_pci_ fsn/ vss_io vdd_io b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 nc nc nc nc nc nc nc nc nc adv/ madp0 mad13 vss_io c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 vssc vdd_io vss_io nc nc vdd_io vss_io vssc madp1 vdd_io mad10 hb_led/ vssc d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 nc vddc nc nc nc nc ramce/ adsc/ mad15 mad12 vss_io mad2 mad7 e14 e15 e16 e17 e18 e19 e20 e21 e22 e23 e24 e25 e26 nc nc nc nc nc vddc mclk mad14 mad11 mad8 bwe1/ mad6 vdd_io f22 f23 f24 f25 f26 mad9 mad1 mad4 vssc vss_io g22 g23 g24 g25 g26 mad0 mad3 vdd_io flshce/ moe/ h22 h23 h24 h25 h26 mad5 bwe0/ vss_io gpio3 serialdata j22 j23 j24 j25 j26 vddc a_led/ flshale1/ serialclk vdd_io k22 k23 k24 k25 k26 flshale0/ b_led/ gpio2 gpio7 vss_io l14 l15 l16 l22 l23 l24 l25 l26 vss_io vss_io vss_io vssc gpio6 vdd_io gpio5 ad34 m14 m15 m16 m22 m23 m24 m25 m26 vss_io vss_io vss_io vddc pci5vbias vss_io gpio4 ad35 n14 n15 n16 n22 n23 n24 n25 n26 vss_io vss_io vss_io scanen zcr_en/ ad32 ad33 vdd_io p14 p15 p16 p22 p23 p24 p25 p26 vss_io vss_io vss_io ad42 ad41 ad39 ad38 vss_io r14 r15 r16 r22 r23 r24 r25 r26 vss_io vss_io vss_io ad43 ad40 vdd_io ad44 ad36 t14 t15 t16 t22 t23 t24 t25 t26 vss_io vss_io vss_io ad47 ad46 vss_io ad45 ad37 u22 u23 u24 u25 u26 ad55 ad49 ad52 ad48 vdd_io v22 v23 v24 v25 v26 ad56 ad53 ad54 ad51 vss_io w22 w23 w24 w25 w26 ad63 ad59 vdd_io pci5vbias ad50 y22 y23 y24 y25 y26 pci5vbias c_be5/ vss_io ad58 ad57 aa22 aa23 aa24 aa25 aa26 clk mode_0 c_be7/ par64 ad60 vdd_io ab14 ab15 ab16 ab17 ab18 ab19 ab20 ab21 ab22 ab23 ab24 ab25 ab26 c_be2/ frame/ stop/ ad12 ad11 ad5 ack64/ vdda pci5vbias vssc vssc ad62 vss_io ac14 ac15 ac16 ac17 ac18 ac19 ac20 ac21 ac22 ac23 ac24 ac25 ac26 ad16 ad17 devsel/ serr/ ad13 ad8 ad2 ad0 clk gpio0 vdd_io c_be6/ ad61 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 vssc vss_io vdd_io ad15 pci5vbias vss_io vdd_io ad4 req64/ vss_io vssa vddc c_be4/ ae14 ae15 ae16 ae17 ae18 ae19 ae20 ae21 ae22 ae23 ae24 ae25 ae26 ad18 irdy/ trdy/ perr/ c_be1/ ad14 ad9 c_be0/ ad6 ad1 vddc gpio1 vdd_io af14 af15 af16 af17 af18 af19 af20 af21 af22 af23 af24 af25 af26 vss_io vddc ad19 vdd_io vss_io par ad10 vdd_io vss_io ad7 ad3 vdd_io vss_io
5-16 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 5.16 contains the pinout for the LSI53C1020. table 5.16 LSI53C1020 signal list by signal name nc e18 nc ab9 nc ac9 nc ae7 par af19 par64 aa24 pci5vbias ad9 pci5vbias ae6 pci5vbias ac10 pci5vbias af12 pci5vbias ad18 pci5vbias ab22 pci5vbias y22 pci5vbias w25 pci5vbias m23 perr/ ae17 pipestat0 d5 pipestat1 e6 pipestat2 c3 pvt1 ae5 pvt2 af4 ramce/ d20 req/ ad10 req64/ ad22 rst/ ab10 rtck_ice aa5 sack- m5 sack+ l5 satn- m4 satn+ n5 sbsy- n3 sbsy+ n4 scanen n22 scanmode e7 scd- k3 scd+ k4 sclk f3 sd0- w4 sd0+ v3 sd1- v4 sd1+ v5 sd2- v2 sd2+ u3 sd3- u5 sd3+ u4 sd4- u2 sd4+ t4 signal ball signal ball ack64/ ab20 ad0 ac21 ad1 ae23 ad2 ac20 ad3 af24 ad4 ad21 ad5 ab19 ad6 ae22 ad7 af23 ad8 ac19 ad9 ae20 ad10 af20 ad11 ab18 ad12 ab17 ad13 ac18 ad14 ae19 ad15 ad17 ad16 ac14 ad17 ac15 ad18 ae14 ad19 af16 ad20 af11 ad21 ae13 ad22 ad13 ad23 ac12 ad24 ab12 ad25 ae12 ad26 ae11 ad27 ac11 ad28 ab11 ad29 ae10 ad30 af8 ad31 ae9 ad32 n24 ad33 n25 ad34 l26 ad35 m26 ad36 r26 ad37 t26 ad38 p25 ad39 p24 ad40 r23 ad41 p23 ad42 p22 ad43 r22 ad44 r25 ad45 t25 ad46 t23 ad47 t22 ad48 u25 ad49 u23 ad50 w26 ad51 v25 ad52 u24 ad53 v23 ad54 v24 ad55 u22 ad56 v22 ad57 y26 ad58 y25 ad59 w23 ad60 aa25 ad61 ac26 ad62 ab25 ad63 w22 adsc/ d21 adv/ b23 alt_inta/ af7 a_led/ j23 a_rbias r1 a_vddbias t1 b_led/ k23 bwe0/ h23 bwe1/ e24 c_be0/ ae21 c_be1/ ae18 c_be2/ ab14 c_be3/ ab13 c_be4/ ad26 c_be5/ y23 c_be6/ ac25 c_be7/ aa23 clk ac22 clk mode_0 aa22 clk mode_1 ac2 devsel/ ac16 diffsens e2 dis_ pci_fsn/ a24 dis_ scsi_fsn/ ac4 flshale0/ k22 flshale1/ j24 flshce/ g25 frame/ ab15 gnt/ ae8 gpio0 ac23 gpio1 ae25 gpio2 k24 gpio3 h25 gpio4 m25 gpio5 l25 gpio6 l23 gpio7 k25 hb_led/ c25 iddtn y4 idsel ac13 inta/ ac8 iopd_gnt/ ac5 irdy/ ae15 mad0 g22 mad1 f23 mad2 d25 mad3 g23 mad4 f24 mad5 h22 mad6 e25 mad7 d26 mad8 e23 mad9 f22 mad10 c24 mad11 e22 mad12 d23 mad13 b25 mad14 e21 mad15 d22 madp0 b24 madp1 c22 mclk e20 moe/ g26 nc a3 nc a4 nc a7 nc a8 nc a11 nc a12 nc a15 nc a16 nc a19 nc a20 nc a23 nc b5 nc b6 nc b7 nc b8 nc b9 nc b10 nc b11 nc b12 nc b13 nc b14 nc b15 nc b16 nc b17 nc b18 nc b19 nc b20 nc b21 nc b22 nc c6 nc c9 nc c10 nc c13 nc c17 nc c18 nc d8 nc d9 nc d10 nc d11 nc d12 nc d13 nc d14 nc d16 nc d17 nc d18 nc d19 nc e8 nc e9 nc e10 nc e11 nc e12 nc e13 nc e14 nc e15 nc e16 nc e17 signal ball signal ball signal ball
package drawings 5-17 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 5.16 LSI53C1020 signal list by signal name (cont.) vss_io t14 vss_io t15 vss_io t16 vss_io t24 vss_io u1 vss_io v26 vss_io w3 vss_io y24 vss_io aa1 vss_io ab26 vss_io ac3 vss_io ad7 vss_io ad11 vss_io ad15 vss_io ad19 vss_io ad23 vss_io ae1 vss_io af2 vss_io af6 vss_io af10 vss_io af14 vss_io af18 vss_io af22 vss_io af26 vssa h5 vssa ad24 vssc b4 vssc c14 vssc c21 vssc c26 vssc f25 vssc g4 vssc l22 vssc p2 vssc ab5 vssc ab7 vssc ab8 vssc ab23 vssc ab24 vssc ad14 zcr_en/ n23 signal ball signal ball sd5- t2 sd5+ r2 sd6- t5 sd6+ r5 sd7- r4 sd7+ p3 sd8- h1 sd8+ h2 sd9- j4 sd9+ h4 sd10- g2 sd10+ g1 sd11- f2 sd11+ d1 sd12- ad1 sd12+ ac1 sd13- ab2 sd13+ aa3 sd14- aa2 sd14+ y2 sd15- y1 sd15+ w5 sdp0- p4 sdp0+ p5 sdp1- w2 sdp1+ w1 serialclk j25 serialdata h26 serr/ ac17 sio- k5 sio+ j5 smsg- l2 smsg+ l1 sreq- j2 sreq+ j3 srst- m1 srst+ m2 ssel- l4 ssel+ k2 stop/ ab16 tck_chip ac6 tck_ice aa4 tdi_chip af3 tdi_ice ab3 tdo_chip ad6 tdo_ice ad2 testaclk ab6 testclken d7 testhclk ae2 tms_chip ae4 tms_ice y5 tn c5 traceclk b3 tracepkt0 d4 tracepkt1 b2 tracepkt2 f5 tracepkt3 e4 tracepkt4 c2 tracepkt5 e3 tracepkt6 g5 tracepkt7 f4 tracesync e5 trdy/ ae16 trst_ice/ ab4 tst_rst/ ad5 vdd_io a1 vdd_io a2 vdd_io a6 vdd_io a10 vdd_io a14 vdd_io a18 vdd_io a22 vdd_io a26 vdd_io c7 vdd_io c11 vdd_io c15 vdd_io c19 vdd_io c23 vdd_io d3 vdd_io e26 vdd_io f1 vdd_io g24 vdd_io h3 vdd_io j26 vdd_io k1 vdd_io l24 vdd_io m3 vdd_io n26 vdd_io p1 vdd_io r24 vdd_io t3 vdd_io u26 vdd_io v1 vdd_io w24 vdd_io y3 vdd_io aa26 vdd_io ab1 vdd_io ac24 vdd_io ad4 vdd_io ad8 vdd_io ad12 vdd_io ad16 vdd_io ad20 vdd_io ae26 vdd_io af1 vdd_io af5 vdd_io af9 vdd_io af13 vdd_io af17 vdd_io af21 vdd_io af25 vdda c1 vdda ab21 vddc d2 vddc d6 vddc d15 vddc e19 vddc j22 vddc m22 vddc n2 vddc ac7 vddc ad3 vddc ad25 vddc ae3 vddc ae24 vddc af15 vss_io a5 vss_io a9 vss_io a13 vss_io a17 vss_io a21 vss_io a25 vss_io b1 vss_io b26 vss_io c4 vss_io c8 vss_io c12 vss_io c16 vss_io c20 vss_io d24 vss_io e1 vss_io f26 vss_io g3 vss_io h24 vss_io j1 vss_io k26 vss_io l3 vss_io l11 vss_io l12 vss_io l13 vss_io l14 vss_io l15 vss_io l16 vss_io m11 vss_io m12 vss_io m13 vss_io m14 vss_io m15 vss_io m16 vss_io m24 vss_io n1 vss_io n11 vss_io n12 vss_io n13 vss_io n14 vss_io n15 vss_io n16 vss_io p11 vss_io p12 vss_io p13 vss_io p14 vss_io p15 vss_io p16 vss_io p26 vss_io r3 vss_io r11 vss_io r12 vss_io r13 vss_io r14 vss_io r15 vss_io r16 vss_io t11 vss_io t12 vss_io t13 signal ball signal ball signal ball
5-18 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 5.17 contains the pinout for the LSI53C1020. table 5.17 LSI53C1020 signal list by bga position l4 ssel- l5 sack+ l11 vss_io l12 vss_io l13 vss_io l14 vss_io l15 vss_io l16 vss_io l22 vssc l23 gpio6 l24 vdd_io l25 gpio5 l26 ad34 m1 srst- m2 srst+ m3 vdd_io m4 satn- m5 sack- m11 vss_io m12 vss_io m13 vss_io m14 vss_io m15 vss_io m16 vss_io m22 vddc m23 pci5vbias m24 vss_io m25 gpio4 m26 ad35 n1 vss_io n2 vddc n3 sbsy- n4 sbsy+ n5 satn+ n11 vss_io n12 vss_io n13 vss_io n14 vss_io n15 vss_io n16 vss_io n22 scanen n23 zcr_en / n24 ad32 n25 ad33 n26 vdd_io ball signal ball signal a1 vdd_io a2 vdd_io a3 nc a4 nc a5 vss_io a6 vdd_io a7 nc a8 nc a9 vss_io a10 vdd_io a11 nc a12 nc a13 vss_io a14 vdd_io a15 nc a16 nc a17 vss_io a18 vdd_io a19 nc a20 nc a21 vss_io a22 vdd_io a23 nc a24 dis_ pci_fsn/ a25 vss_io a26 vdd_io b1 vss_io b2 tracepkt1 b3 traceclk b4 vssc b5 nc b6 nc b7 nc b8 nc b9 nc b10 nc b11 nc b12 nc b13 nc b14 nc b15 nc b16 nc b17 nc b18 nc b19 nc b20 nc b21 nc b22 nc b23 adv/ b24 madp0 b25 mad13 b26 vss_io c1 vdda c2 tracepkt4 c3 pipestat2 c4 vss_io c5 tn c6 nc c7 vdd_io c8 vss_io c9 nc c10 nc c11 vdd_io c12 vss_io c13 nc c14 vssc c15 vdd_io c16 vss_io c17 nc c18 nc c19 vdd_io c20 vss_io c21 vssc c22 madp1 c23 vdd_io c24 mad10 c25 hb_led/ c26 vssc d1 sd11+ d2 vddc d3 vdd_io d4 tracepkt0 d5 pipestat0 d6 vddc d7 testclken d8 nc d9 nc d10 nc d11 nc d12 nc d13 nc d14 nc d15 vddc d16 nc d17 nc d18 nc d19 nc d20 ramce/ d21 adsc/ d22 mad15 d23 mad12 d24 vss_io d25 mad2 d26 mad7 e1 vss_io e2 diffsens e3 tracepkt5 e4 tracepkt3 e5 tracesync e6 pipestat1 e7 scanmode e8 nc e9 nc e10 nc e11 nc e12 nc e13 nc e14 nc e15 nc e16 nc e17 nc e18 nc e19 vddc e20 mclk e21 mad14 e22 mad11 e23 mad8 e24 bwe1/ e25 mad6 e26 vdd_io f1 vdd_io f2 sd11- f3 sclk f4 tracepkt7 f5 tracepkt2 f22 mad9 f23 mad1 f24 mad4 f25 vssc f26 vss_io g1 sd10+ g2 sd10- g3 vss_io g4 vssc g5 tracepkt6 g22 mad0 g23 mad3 g24 vdd_io g25 flshce/ g26 moe/ h1 sd8- h2 sd8+ h3 vdd_io h4 sd9+ h5 vssa h22 mad5 h23 bwe0/ h24 vss_io h25 gpio3 h26 serialdata j1 vss_io j2 sreq- j3 sreq+ j4 sd9- j5 sio+ j22 vddc j23 a_led/ j24 flshale1/ j25 serialclk j26 vdd_io k1 vdd_io k2 ssel+ k3 scd- k4 scd+ k5 sio- k22 flshale0/ k23 b_led/ k24 gpio2 k25 gpio7 k26 vss_io l1 smsg+ l2 smsg- l3 vss_io ball signal ball signal ball signal
package drawings 5-19 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table 5.17 LSI53C1020 signal list by bga position (cont.) ae8 gnt / ae9 ad31 ae10 ad29 ae11 ad26 ae12 ad25 ae13 ad21 ae14 ad18 ae15 irdy / ae16 trdy / ae17 perr / ae18 c_be1 / ae19 ad14 ae20 ad9 ae21 c_be0 / ae22 ad6 ae23 ad1 ae24 vddc ae25 gpio1 ae26 vdd_io af1 vdd_io af2 vss_io af3 tdi_chip af4 pvt2 af5 vdd_io af6 vss_io af7 alt_inta / af8 ad30 af9 vdd_io af10 vss_io af11 ad20 af12 pci5vbias af13 vdd_io af14 vss_io af15 vddc af16 ad19 af17 vdd_io af18 vss_io af19 par af20 ad10 af21 vdd_io af22 vss_io af23 ad7 af24 ad3 af25 vdd_io af26 vss_io ball signal ball signal p1 vdd_io p2 vssc p3 sd7+ p4 sdp0- p5 sdp0+ p11 vss_io p12 vss_io p13 vss_io p14 vss_io p15 vss_io p16 vss_io p22 ad42 p23 ad41 p24 ad39 p25 ad38 p26 vss_io r1 a_rbias r2 sd5+ r3 vss_io r4 sd7- r5 sd6+ r11 vss_io r12 vss_io r13 vss_io r14 vss_io r15 vss_io r16 vss_io r22 ad43 r23 ad40 r24 vdd_io r25 ad44 r26 ad36 t1 a_vddbias t2 sd5- t3 vdd_io t4 sd4+ t5 sd6- t11 vss_io t12 vss_io t13 vss_io t14 vss_io t15 vss_io t16 vss_io t22 ad47 t23 ad46 t24 vss_io t25 ad45 t26 ad37 u1 vss_io u2 sd4- u3 sd2+ u4 sd3+ u5 sd3- u22 ad55 u23 ad49 u24 ad52 u25 ad48 u26 vdd_io v1 vdd_io v2 sd2- v3 sd0+ v4 sd1- v5 sd1+ v22 ad56 v23 ad53 v24 ad54 v25 ad51 v26 vss_io w1 sdp1+ w2 sdp1- w3 vss_io w4 sd0- w5 sd15+ w22 ad63 w23 ad59 w24 vdd_io w25 pci5vbias w26 ad50 y1 sd15- y2 sd14+ y3 vdd_io y4 iddtn y5 tms_ice y22 pci5vbias y23 c_be5/ y24 vss_io y25 ad58 y26 ad57 aa1 vss_io aa2 sd14- aa3 sd13+ aa4 tck_ice aa5 rtck_ice aa22 clkmode_0 aa23 c_be7/ aa24 par64 aa25 ad60 aa26 vdd_io ab1 vdd_io ab2 sd13- ab3 tdi_ice ab4 trst_ice/ ab5 vssc ab6 testaclk ab7 vssc ab8 vssc ab9 nc ab10 rst/ ab11 ad28 ab12 ad24 ab13 c_be3/ ab14 c_be2/ ab15 frame/ ab16 stop/ ab17 ad12 ab18 ad11 ab19 ad5 ab20 ack64/ ab21 vdda ab22 pci5vbias ab23 vssc ab24 vssc ab25 ad62 ab26 vss_io ac1 sd12+ ac2 clkmode_1 ac3 vss_io ac4 dis_ scsi_fsn/ ac5 iopd_gnt/ ac6 tck_chip ac7 vddc ac8 inta/ ac9 nc ac10 pci5vbias ac11 ad27 ac12 ad23 ac13 idsel ac14 ad16 ac15 ad17 ac16 devsel/ ac17 serr/ ac18 ad13 ac19 ad8 ac20 ad2 ac21 ad0 ac22 clk ac23 gpio0 ac24 vdd_io ac25 c_be6/ ac26 ad61 ad1 sd12- ad2 tdo_ice ad3 vddc ad4 vdd_io ad5 tst_rst/ ad6 tdo_chip ad7 vss_io ad8 vdd_io ad9 pci5vbias ad10 req/ ad11 vss_io ad12 vdd_io ad13 ad22 ad14 vssc ad15 vss_io ad16 vdd_io ad17 ad15 ad18 pci5vbias ad19 vss_io ad20 vdd_io ad21 ad4 ad22 req64/ ad23 vss_io ad24 vssa ad25 vddc ad26 c_be4/ ae1 vss_io ae2 testhclk ae3 vddc ae4 tms_chip ae5 pvt1 ae6 pci5vbias ae7 nc ball signal ball signal ball signal
5-20 speci?ations version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. figure 5.13 456-pin epbga (ky) mechanical drawing impor tant: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code ky.
LSI53C1020 pci-x to ultra320 scsi controller a1 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. appendix a register summary tables a.1 , a.2 , and a.3 provide a register summary. table a.1 LSI53C1020 pci registers register name offset 1 read/write page vendor id 0x00?x01 read only 4-3 device id 0x02?x03 read only 4-3 command 0x04?x05 read/write 4-3 status 0x06?x07 read/write 4-5 revision id 0x08 read/write 4-7 class code 0x09?x0b read only 4-7 cache line size 0x0c read/write 4-8 latency timer 0x0d read/write 4-8 header type 0x0e read only 4-9 reserved 0x0f reserved 4-9 i/o base address 0x10?x13 read/write 4-10 memory [0] low 0x14?x17 read/write 4-10 memory [0] high 0x18?x1b read/write 4-11 memory [1] low 0x1c?x1f read/write 4-11 memory [1] high 0x20?x23 read/write 4-12 reserved 0x24?x27; 0x28?x2b reserved 4-12 subsystem vendor id 0x2c?x2d read only 4-13 subsystem id 0x2e?x2f read only 4-14
a2 register summary version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. expansion rom base address 0x30?x33 read/write 4-15 capabilities pointer 0x34 read only 4-16 reserved 0x35?x37; 0x38?x3b reserved 4-16 interrupt line 0x3c read/write 4-17 interrupt pin 0x3d read only 4-17 minimum grant 0x3e read only 4-18 maximum latency 0x3f read only 4-18 power management capability id read only 4-19 power management next pointer read only 4-20 power management capabilities read only 4-20 power management control/status read/write 4-21 power management bridge support extensions read only 4-22 power management data read only 4-22 msi capability id read only 4-22 msi next pointer read only 4-23 message control read/write 4-23 message address read/write 4-25 message upper address read/write 4-25 message data read/write 4-26 pci-x capability id read only 4-26 pci-x next pointer read only 4-27 pci-x command read/write 4-27 pci-x status read/write 4-29 1. the offset of the pci extended capabilities registers can vary. access these registers through the next pointer and capability id registers. table a.1 LSI53C1020 pci registers (cont.) register name offset 1 read/write page
a3 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table a.2 LSI53C1020 pci i/o space registers register name offset read/write page system doorbell 0x00 read/write 4-34 write sequence 0x04 read/write 4-35 host diagnostic 0x08 read/write 4-36 test base address 0x0c read/write 4-37 diagnostic read/write data 0x10 read/write 4-38 diagnostic read/write address 0x14 read/write 4-39 reserved 0x18?x2f reserved host interrupt status 0x30 read/write 4-40 host interrupt mask 0x34 read/write 4-41 reserved 0x38?x3f reserved request fifo 0x40 read/write 4-42 reply fifo 0x44 read/write 4-42
a4 register summary version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. table a.3 LSI53C1020 pci memory [0] registers register name offset read/write page system doorbell 0x00 read/write 4-34 write sequence 0x04 read/write 4-35 host diagnostic 0x08 read/write 4-36 test base address 0x0c read/write 4-37 reserved 0x10?x2f reserved host interrupt status 0x30 read/write 4-40 host interrupt mask 0x34 read/write 4-41 reserved 0x38?x3f reserved request fifo 0x40 read/write 4-42 reply fifo 0x44 read/write 4-42
LSI53C1020 pci-x to ultra320 scsi controller ix-1 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. index numerics 12 ma output signals 5-6 133 mhz 1-10 133 mhz capable bit 4-30 133 mhz pci-x 1-3 , 3-20 , 3-21 , 5-9 133 mhz pci-x bit 4-30 33 mhz pci 5-9 64-bit address capable bit 4-23 64-bit device bit 4-31 64-bit enable bit 3-21 64-bit pci 1-3 , 1-10 , 3-20 , 3-21 66 mhz capable bit 3-21 , 4-6 66 mhz pci 3-20 , 3-21 , 5-9 66 mhz pci-x 5-9 8 ma output signals 5-6 a a_led/ 2-6 , 3-16 , 5-6 a_rbias 3-10 a_vddbias 3-10 absolute maximum stress ratings 5-2 ac characteristics 5-9 ack64/ 3-6 , 5-5 active low 3-1 active termination 2-23 ad[31:0] 5-5 ad[63:0] 3-5 , 5-5 address diagnostic read/write 4-39 latches 3-13 address reply 2-7 address/data bus 3-19 , 4-31 adsc/ 3-12 , 5-6 adv/ 3-12 , 5-6 air temperature 5-2 alias to memory read block 2-10 , 2-12 , 2-13 alias to memory write block 2-10 , 2-12 alignment 2-14 alt_inta/ 2-15 , 3-8 , 4-24 , 4-41 , 5-6 analog voltage 5-2 arbitration 2-15 arm multi-ice 1-12 arm966e-s 1-3 , 1-9 , 2-4 , 2-6 , 3-9 , 4-36 aux_current bit 4-20 b b_led/ 2-6 , 3-16 , 5-6 ball grid array 5-13 , 5-14 base address register i/o 2-4 , 4-10 memory [0] 4-10 memory [1] 4-11 bga top view 5-14 bidirectional signals 5-5 bios 2-8 , 2-27 bit 133 mhz capable 4-30 64-bit address capable 4-23 64-bit device 4-31 66 mhz capable 4-6 aux current 4-20 bus number 4-31 d1 support 4-20 d2 support 4-20 data parity error recovery enable 4-29 data parity error reported 4-6 data scale 4-21 data select 4-21 designed maximum cumulative read size 4-29 designed maximum memory read byte count 4-30 designed maximum outstanding split transactions 4-30 detected parity error (from slave) 4-5 device complexity 4-30 device number 4-31 device specific initialization 4-20 devsel/ timing 4-6 diagnostic memory enable 4-37 diagnostic read/write enable 4-36 diagnostic write enable 4-35 , 4-36 , 4-39 disarm 4-36 doorbell interrupt mask 4-42 enable bus mastering 4-4 enable i/o 4-5 enable memory space 4-4 enable parity error response 4-4 expansion rom enable 4-15 flash rom bad signature 4-36 function number 4-31 interrupt request routing mode 4-41 iop doorbell status 4-40 msi enable 4-24 multiple message 4-24 new capabilities 4-6 pme clock 4-20 pme enable 4-21 pme status 4-21 pme support 4-20 power management version 4-20 power state 4-21 received master abort (from master) 4-5
ix-2 index version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. received split completion error message 4-29 received target abort (from master) 4-5 reply interrupt 4-40 reply interrupt mask 4-41 reset adapter 4-37 reset history 4-36 serr/ enable 4-4 signalled system error 4-5 system doorbell interrupt 4-40 ttl interrupt 4-37 unexpected split completion 4-30 write and invalidate enable 4-4 block diagram 2-3 board application 1-3 boot device 2-5 , 2-24 boundary scan 1-12 burst size selection 2-13 bus mastering 2-15 , 2-17 number 4-31 pci commands 2-9 training 1-9 bwe[1:0]/ 3-12 , 5-6 c c_be[3:0]/ 2-8 , 2-9 , 2-12 , 5-5 c_be[7:0]/ 3-5 , 5-5 cache line size 1-10 , 2-13 , 2-14 , 4-8 alignment 2-14 register 2-15 , 4-8 capabilities pointer register 4-16 capability id 4-2 msi 4-22 pci-x 4-26 power management 4-19 capacitance input 5-4 checksum 2-27 , 2-28 class code register 4-7 clk 3-4 , 5-6 clkmode_0 3-15 , 3-23 , 5-6 clkmode_1 3-15 , 3-23 , 5-6 clock eeprom 3-13 , 3-23 external 5-9 pci 5-9 pme 4-20 sclk 3-9 , 5-9 scsi 3-9 skew control 2-22 cls 4-8 cls alignment 2-14 command register 2-18 , 4-3 common mode voltage 5-3 completer id 4-31 configuration parameters 2-24 read command 2-8 , 2-10 , 2-12 , 2-13 , 4-6 record 2-27 , 2-28 space 2-8 , 4-1 write command 2-10 , 2-12 , 2-13 , 4-6 configuration space 4-1 context manager 2-5 , 2-6 core voltage 5-2 crc 1-2 , 1-7 , 1-12 , 2-22 crc-32 1-7 current i/o supply 5-2 latch-up 5-2 , 5-8 cyclic redundancy check 1-2 , 1-7 , 2-22 d d0 2-16 , 4-21 d1 2-16 , 2-17 , 4-21 d1 support bit 4-20 d2 2-16 , 2-17 , 4-21 d2 support bit 4-20 d3 2-16 , 2-18 , 4-21 dac 1-10 , 2-8 , 2-10 , 2-13 data diagnostic read/write register 4-38 eeprom 3-13 parity error recovery enable bit 4-29 parity error reported bit 4-6 scale bit 4-21 select bit 4-21 datapath engine 2-6 dc characteristics 5-1 debug signals 3-14 debugging 1-12 delay filter 5-8 designed maximum cumulative read size bit 4-29 designed maximum memory read byte count bit 4-30 designed maximum outstanding split transactions bit 4-30 detected parity error (from slave) bit 4-5 device complexity bit 4-30 device driver stability 1-6 device id register 4-3 device number bit 4-31 device specific initialization bit 4-20 devsel/ 3-6 , 5-5 devsel/ timing bit 4-6 diagnostic memory 4-32 diagnostic memory enable bit 4-37 diagnostic read/write address register 4-35 , 4-36 , 4-39 diagnostic read/write data register 4-35 , 4-36 , 4-38 , 4-39 diagnostic read/write enable bit 4-36 diagnostic write enable bit 4-35 , 4-36 , 4-39 diffsens 2-23 , 3-10 , 5-4 dis_pci_fsn/ 3-15 , 3-23 , 5-6 dis_scsi_fsn/ 3-15 , 3-23 , 5-6 disarm bit 4-36 , 4-37 dma 1-11 , 2-5 , 2-6 , 2-15 arbiter and router 2-5 domain validation 1-2 , 1-7 , 1-12 , 2-22 doorbell 2-7 , 2-8 host 4-34 interrupt mask bit 4-42 status bit 4-40 system 4-34 , 4-40 system interface 2-7 system interrupt bit 4-40 double transition clocking 1-2 , 2-19 drawing mechanical 5-20 package 5-13 , 5-14 drive strength 1-7 , 2-20 , 2-22 driver lvd 5-3 dt clocking 1-2 , 2-19
index ix-3 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. dt data phase 2-18 dual address cycles command 1-10 , 2-8 , 2-10 , 2-13 e eeprom 2-5 , 2-6 , 2-27 , 3-13 , 3-21 , 3-23 configuration record 2-27 download enable 3-20 interface 2-27 , 3-13 electrostatic discharge 5-2 enable bus mastering bit 4-4 diagnostic memory bit 4-37 diagnostic write bit 4-36 i/o space bit 4-5 memory space bit 4-4 msi bit 4-24 parity error response bit 4-4 write and invalidate bit 4-4 esd 1-12 , 5-2 , 5-8 expansion rom base address 4-4 expansion rom base address register 4-15 expansion rom enable bit 4-15 external clock 5-9 memory controller 2-5 memory interface 2-24 memory interface timing diagrams 5-11 f ferrite bead 3-18 fibre channel 1-5 , 1-11 fifo dma 2-5 reply 4-42 reply free 2-7 reply post 2-7 , 4-40 request 4-42 request post 2-7 filter delay 5-8 filtering 5-9 flash rom 1-3 , 2-5 , 2-24 , 3-12 , 3-13 , 3-21 address space 2-24 address timing 5-11 bad signature bit 4-36 block diagram 2-25 configurations 2-24 interface 2-24 , 3-12 polling 5-13 read timing 5-12 signature recognition 2-25 , 2-26 size 3-20 , 3-22 write timing 5-12 flexibility 1-11 flshale[1:0]/ 2-25 , 3-13 , 5-6 flshce/ 2-25 , 3-13 , 5-6 frame/ 3-6 , 5-5 frames reply message 2-7 , 2-15 request message 2-7 , 2-15 free running timer 2-5 frequency synthesizer 3-15 , 3-18 , 3-23 function number bit 4-31 fusion-mpt 1-3 , 1-5 , 1-9 , 1-10 , 1-11 , 2-1 , 2-4 , 2-6 , 2-7 , 2- 8 , 2-26 , 3-12 , 4-1 g general description 1-1 gnt/ 2-15 , 2-28 , 3-7 , 5-6 gpio[7:0] 2-6 , 3-16 , 3-23 , 5-5 grant 2-15 ground signals 3-17 h hb_led/ 2-6 , 3-16 , 5-6 header type register 4-9 host diagnostic register 4-35 , 4-36 , 4-39 host doorbell value 4-34 host interface module 2-2 , 2-4 , 2-5 host interrupt mask register 2-16 , 3-8 , 4-40 , 4-41 host interrupt status register 4-40 , 4-41 host system 2-7 hot plug 5-7 hvd 2-23 , 3-9 , 3-10 sense voltage 5-4 hysteresis 5-7 i i/o base address 4-5 base address register 2-4 , 2-9 , 4-10 key 4-35 , 4-36 , 4-39 processor 2-4 , 2-28 read command 2-10 , 2-11 , 2-13 space 2-9 , 4-1 , 4-32 supply voltage 5-2 write command 2-10 , 2-11 , 2-13 i/o supply current 5-2 ice 3-14 id control 3-20 , 3-21 , 4-14 idc socket 2-30 idd-core 5-2 idd-i/o 5-2 iddtn 3-15 , 3-23 , 5-6 idsel 2-8 , 2-28 , 3-6 , 3-13 , 5-6 im 1-12 , 2-5 , 2-24 in-circuit emulator 3-14 information unit 2-18 , 2-21 input capacitance 5-4 filtering 5-9 maximum voltage 5-2 reset 5-10 signals 5-6 inta/ 2-15 , 3-8 , 4-24 , 4-37 , 4-41 , 5-6 integrated mirroring 1-12 , 2-5 , 2-24 , 2-26 integration 1-11 interface eeprom 2-27 external memory 2-24 flash rom 2-24 , 3-12 ice 3-14 jtag 3-14 nvsram 3-12 pci bus 3-4 scsi channel 3-10 serial eeprom 2-6 , 2-27 , 3-13 test 3-14
ix-4 index version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. interrupt 2-16 acknowledge command 2-10 , 2-11 , 2-13 alt_inta/ 2-15 coalescing 1-10 doorbell mask bit 4-42 inta/ 2-15 line register 4-17 message signalled 2-15 , 2-16 msi 1-11 output 5-10 pci 2-15 pin register 4-17 pins 2-15 reply 2-16 reply bit 4-40 reply mask bit 4-41 request routing mode bits 4-41 service routine 1-10 signal routing 4-41 system doorbell 2-16 , 4-40 system doorbell bit 4-40 ttl bit 4-37 intersymbol interference 1-7 , 1-12 iop 2-4 , 2-5 , 2-6 , 2-7 , 2-28 , 3-20 , 4-34 , 4-36 , 4-37 , 4-40 boot 3-20 , 3-21 iop doorbell status bit 4-40 iopd_gnt/ 2-28 , 3-13 , 3-23 , 5-6 irdy/ 3-6 , 5-5 isi 1-7 , 1-12 , 2-19 isr 1-10 iu_request 2-18 j jtag 1-12 , 3-14 junction temperature 5-2 k key i/o 4-35 , 4-36 , 4-39 l latch-up current 5-2 , 5-8 latch-up protection 1-12 latency timer 4-8 latency timer register 4-8 lead temperature 5-2 led 2-5 , 3-16 low voltage differential 2-23 lsi53c1000r 1-11 , 2-29 lvd 1-11 , 2-23 , 3-9 , 3-10 driver scsi signals 5-3 receiver scsi signals 5-3 receiver voltage 5-3 sense voltage 5-4 lvdlink 1-3 , 1-8 , 1-11 , 2-18 , 2-23 m mad[10] 4-14 mad[13] 4-6 mad[14] 4-31 mad[15:0] 2-5 , 3-12 , 3-19 , 3-23 , 5-5 mad[15] 4-30 mad[2:1] 2-24 mad[3] 2-26 mad[7:0] 2-5 , 2-24 , 3-12 mad[7] 4-13 , 4-14 madp[0] 2-5 madp[1:0] 2-5 , 3-12 , 3-19 , 3-23 , 5-5 margin control settings 2-18 master abort 4-5 master data parity error 4-29 max_lat 4-18 maximum latency register 4-18 maximum memory read byte count bits 4-28 maximum outstanding split transactions bits 4-27 maximum stress ratings 5-2 mclk 3-12 , 5-6 mcs 2-18 mechanical drawing 5-20 memory alias to read block 2-12 , 2-13 alias to write block 2-10 , 2-12 controller 2-5 flash rom size 3-22 read block command 1-10 , 2-10 , 2-12 , 2-13 , 2-14 read command 2-10 , 2-11 , 2-13 , 2-14 , 2-15 read dword command 1-10 , 2-10 , 2-11 , 2-13 read line command 1-10 , 2-10 , 2-14 , 2-15 read multiple command 1-10 , 2-10 , 2-13 , 2-15 space 2-9 , 4-1 write and invalidate command 1-10 , 2-10 , 2-14 , 2-15 write block command 1-10 , 2-10 , 2-12 , 2-15 write command 2-10 , 2-12 , 2-14 , 2-15 memory [0] high 4-4 , 4-11 memory [0] low 4-4 , 4-10 memory [1] high 4-4 , 4-12 memory [1] low 4-4 , 4-11 memory space description 4-32 message address register 4-25 message control register 4-23 message data register 4-26 message frame address 4-42 message passing technology 1-9 , 2-1 message queues 2-7 message signalled interrupts 2-15 , 2-16 message upper address register 4-25 mfa reply 4-42 request 4-42 request post 4-42 minimum grant register 4-18 moe/ 3-12 , 5-6 msi 1-10 , 1-11 , 2-15 , 2-16 capability id register 4-22 enable bit 4-24 message address 4-25 message data 4-26 message upper address register 4-25 multiple message 4-24 multiple message capable 4-24 next pointer register 4-23 multi-ice 2-30 multiple cache line transfers 2-14 multiple message capable 4-24 multiple message enable 4-23
index ix-5 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. n nc 3-1 , 3-18 new capabilities bit 4-6 no connect 3-1 nvsram 1-3 , 2-2 , 2-5 , 2-24 , 2-26 , 3-12 , 3-13 block diagram 2-27 integrated mirroring 2-26 interface 3-12 select 3-21 sense 3-20 write journaling 2-26 o operating conditions 5-2 operating free air temperature 5-2 output signals 5-6 p p1 line 2-19 paced transfers 1-2 , 2-19 package drawing 5-13 , 5-14 packetized protocol 1-2 , 1-9 , 2-21 par 3-5 , 5-5 par64 3-5 , 5-5 parallel protocol request 2-18 , 2-22 parity error 4-6 passive termination 2-23 pc2001 system design guide 1-10 , 2-16 pci 1-11 , 2-7 33 mhz 5-9 64-bit 3-20 , 3-21 66 mhz 3-20 , 3-21 , 5-9 66 mhz capable bit 4-6 address and data signals 3-5 address/data bus 3-19 , 4-31 addressing 2-8 alias to memory read block command 2-12 , 2-13 alias to memory write block command 2-12 arbitration 2-15 arbitration signals 3-7 benefits 1-6 bidirectional signals 5-5 bus commands 2-9 , 2-10 bus interface 3-4 cache line size register 2-14 cache mode 2-15 clk 5-9 command configuration read 2-8 , 2-10 , 2-12 configuration write 2-8 , 2-10 , 2-12 dual address cycle 2-10 , 2-13 dual address cycles 1-10 , 2-8 i/o read 2-10 , 2-11 i/o write 2-10 , 2-11 interrupt acknowledge 2-10 , 2-11 memory read 2-11 memory read block 1-10 , 2-10 , 2-12 , 2-14 memory read dword 1-10 , 2-10 , 2-11 memory read line 1-10 , 2-10 , 2-14 memory read multiple 1-10 , 2-10 , 2-13 memory write 2-10 , 2-12 memory write and invalidate 1-10 , 2-10 , 2-14 memory write block 1-10 , 2-10 , 2-15 special cycle 2-10 , 2-11 split completion 1-10 , 2-10 , 2-13 command register 4-15 configuration read command 2-10 , 2-12 , 2-13 , 4-6 configuration record 2-28 configuration space 2-8 , 2-27 , 4-1 address map 4-2 c_be[3:0]/ 2-8 , 2-9 configuration write command 2-10 , 2-12 , 2-13 , 4-6 dac 1-10 , 2-8 , 2-10 , 2-13 device complexity bit 4-30 dual address cycles command 2-10 , 2-13 encoding 2-10 error reporting signals 3-7 frequency synthesizer 3-15 , 3-18 , 3-23 fsn 3-15 , 3-18 , 3-23 functional description 2-8 i/o read command 2-10 , 2-11 , 2-13 i/o space 2-8 , 2-9 , 4-1 i/o space address map 4-32 i/o space and memory space description 4-32 i/o write command 2-10 , 2-11 , 2-13 interface 2-4 interface control signals 3-6 interrupt acknowledge command 2-10 , 2-11 , 2-13 interrupt signals 3-8 interrupts 2-15 , 4-41 , 4-42 memory [1] address map 4-33 memory read block command 2-13 , 2-14 memory read command 2-10 , 2-11 , 2-13 , 2-14 , 2-15 memory read dword command 2-11 , 2-13 memory read line command 2-10 , 2-14 , 2-15 memory read multiple command 2-10 , 2-13 , 2-15 memory space 2-8 , 2-9 , 2-27 , 4-1 memory space [0] 2-4 , 2-9 , 4-1 memory space [1] 2-9 , 4-1 memory write and invalidate command 2-10 , 2-14 , 2-15 memory write block command 2-12 , 2-15 memory write command 2-10 , 2-14 , 2-15 new capabilities bit 4-6 performance 1-10 power management 2-16 related signals 3-8 reset 4-36 special cycle command 2-10 , 2-11 , 4-5 split completion command 2-13 status 3-21 system address space 4-1 system signals 3-4 pci_cap 3-20 pci_gnt/ 3-13 pci5vbias 1-11 , 3-18 , 5-5 pci-sig 4-13 pci-x 1-10 , 1-11 , 2-8 133 mhz 3-20 , 5-9 133 mhz capable bit 4-30 64-bit device bit 4-31 66 mhz 5-9 alias to memory read block command 2-10 alias to memory write block command 2-10 benefits 1-6 bus commands 2-10 bus number 4-31 capability id register 4-26 command register 4-27
ix-6 index version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. data parity error recovery enable bit 4-29 designed maximum cumulative read size bit 4-29 designed maximum memory read byte count bit 4-30 designed maximum outstanding split transactions bit 4-30 device complexity bit 4-30 device number bit 4-31 function number bit 4-31 maximum memory read byte count bits 4-28 maximum outstanding split transactions bits 4-27 memory read block command 2-10 memory read dword command 2-10 memory write block command 2-10 mode 3-20 next pointer register 4-27 received split completion error message bit 4-29 split completion command 2-10 split completion discarded bit 4-30 status 3-21 status register 4-29 unexpected split completion bit 4-30 perr/ 3-7 , 5-5 pinout 5-16 , 5-18 pipestat[2:0] 3-14 , 5-6 pme 4-20 , 4-21 clock bit 4-20 enable bit 4-21 status bit 4-21 support bits 4-20 por 4-36 post 4-17 power management 2-16 aux_current bit 4-20 bridge support extensions register 4-22 capabilities register 4-20 capability id register 4-19 control/status 2-16 control/status register 2-16 , 4-21 d0 4-21 d1 4-21 d1 support bit 4-20 d2 4-21 d2 support bit 4-20 d3 2-18 , 4-21 data register 4-22 data scale bit 4-21 data select bit 4-21 device specific initialization bit 4-20 event 4-20 interface 1-10 next pointer register 4-19 pme clock bit 4-20 pme enable bit 4-21 pme status bit 4-21 power state bit 4-21 support bits 4-20 version bit 4-20 power signals 3-17 power state d0 2-16 d1 2-16 , 2-17 d2 2-16 , 2-17 d3 2-16 , 2-18 , 4-21 power state bit 4-21 power-on reset 4-36 power-on sense pins 3-19 ppr 2-18 , 2-20 , 2-22 precompensation 1-2 , 2-18 , 2-20 pull-ups and pull-downs 3-23 pvt1, pvt2 3-8 , 5-6 q qas 1-2 , 1-9 , 2-18 , 2-22 queue message 2-7 reply message 2-5 , 2-7 request message 2-5 , 2-7 quick arbitration and selection 1-2 , 1-9 , 2-18 , 2-22 r raid 2-28 , 3-13 ramce/ 2-26 , 3-12 , 5-6 read streaming 2-18 received master abort (from master) bit 4-5 received split completion error message bit 4-29 received target abort (from master) bit 4-5 register cache line size 4-8 capabilities pointer 4-16 class code 4-7 command 2-18 , 4-3 device id 4-3 diagnostic read/write address 4-39 diagnostic read/write data 4-38 expansion rom base address 4-15 header type 4-9 host diagnostic 4-36 host interrupt mask 2-16 , 3-8 , 4-41 host interrupt status 4-40 i/o base address 4-10 interrupt line 4-17 interrupt pin 4-17 latency timer 4-8 maximum latency 4-18 memory [0] high 4-11 memory [0] low 4-10 memory [1] high 4-12 memory [1] low 4-11 message address 4-25 message control 4-23 message data 4-26 message upper address 4-25 minimum grant 4-18 msi capability id 4-22 msi next pointer 4-23 pci memory [1] address map 4-33 pci-x capability id 4-26 pci-x command 4-27 pci-x next pointer 4-27 pci-x status 4-29 power management bridge support extensions 4-22 power management capabilities 4-20 power management capability id 4-19 power management control/status 2-16 , 4-21 power management data 4-22 power management next pointer 4-19 reply fifo 4-42 request fifo 4-42 revision id 4-7 status 4-5 subsystem id 4-14
index ix-7 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. subsystem vendor id 4-13 system doorbell 4-34 test base address 4-37 vendor id 4-3 write sequence 4-35 register map a-1 pci configuration space 4-2 pci i/o space 4-32 reliability 1-12 reply message 2-7 reply fifo register 4-42 reply free fifo 2-7 reply interrupt 2-16 reply interrupt bit 4-40 reply interrupt mask bit 4-41 reply message 2-5 , 2-7 , 2-15 , 4-42 reply mfa 4-42 reply post fifo 2-7 , 4-40 , 4-42 req/ 2-15 , 3-7 , 5-6 req/ack offset, 2-18 req64/ 3-6 , 5-5 request 2-15 request fifo register 4-42 request free mfa 4-42 request message 2-5 , 2-7 , 2-15 request post fifo 2-7 , 4-42 request post mfa 4-42 requester id 4-31 reset adapter bit 4-37 reset history bit 4-36 reset input timing 5-10 revision id register 4-7 rise and fall time test condition 5-8 rom 2-5 , 2-24 rom expansion enable bit 4-15 rom size 3-20 , 3-22 rst/ 3-4 , 5-9 rtck_ice 2-30 , 3-14 , 5-6 rti 2-18 rti bit 2-22 s sack+- 3-11 , 5-3 satn+- 3-11 , 5-3 sbsy+- 3-11 , 5-3 scanen 3-15 , 3-23 , 5-6 scanmode 3-15 , 3-23 , 5-6 scd+- 3-11 , 5-3 sclk 3-9 , 5-6 , 5-9 scsi bus interface 2-6 bus mastering functions 2-15 channel control signals 3-10 channel interface 3-10 channel module 2-5 , 2-6 clk 3-9 clock 3-9 core 2-6 crc 2-22 datapath engine 2-6 diffsens signal 5-4 domain validation 2-22 driver signals 5-3 dt clocking 1-2 , 2-19 information unit transfers 2-21 input filtering 5-9 interrupt steering logic 1-10 isi 2-19 lvd 2-23 paced transfers 2-19 packetized transfers 2-21 parallel protocol request 2-18 , 2-22 performance 1-9 ppr 2-18 , 2-22 precompensation 2-20 qas 2-18 , 2-22 quick arbitration and selection 2-22 receiver signals 5-3 se 2-23 single-ended 2-23 skew compensation 2-22 synchronous transfer 2-18 termination 2-23 tolerant technology 1-8 ultra320 features 2-19 sd[15:0]+- 3-10 , 5-3 sdp[1:0]+- 3-10 , 5-3 se 2-23 , 3-9 , 3-10 sense voltage 5-4 sense voltage 5-4 serial eeprom 2-5 , 2-6 , 2-24 , 2-27 , 3-21 , 3-23 , 4-13 , 4- 14 , 4-37 configuration record 2-27 download enable 3-20 , 3-21 interface 2-27 serialclk 3-13 , 3-23 serialdata 3-13 , 3-23 , 5-5 serr/ 3-7 , 4-29 , 5-5 , 5-6 serr/ enable bit 4-4 shared ram 2-5 , 2-7 si_o+- 3-11 signal grouping 3-3 list 5-16 , 5-18 no connect 3-1 types 3-2 signal descriptions a_led 3-16 a_rbias 3-10 a_vddbias 3-10 ack64/ 3-6 ad[63:0] 3-5 adsc/ 3-12 adv/ 3-12 alt_inta/ 3-8 b_led/ 3-16 bwe[1:0]/ 3-12 c_be[7:0]/ 3-5 clk 3-4 clkmode_0 3-15 clkmode_1 3-15 devsel/ 3-6 diffsense 3-10 dis_pci_fsn/ 3-15 dis_scsi_fsn/ 3-15 flshale[1:0]/ 3-13 flshce/ 3-13 frame/ 3-6 gnt/ 3-7 gpio[7:0] 3-16
ix-8 index version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. ground 3-17 hb_led/ 3-16 iddtn 3-15 idsel 3-6 inta/ 3-8 iopd_gnt/ 3-13 irdy/ 3-6 mad[15:0] 3-12 , 3-19 madp[1:0] 3-12 , 3-19 mclk 3-12 moe/ 3-12 nc 3-18 par 3-5 par64 3-5 pci5vbias 3-18 perr/ 3-7 pipestat[2:0] 3-14 power 3-17 power-on sense 3-19 pvt1, pvt2 3-8 ramce/ 3-12 req/ 3-7 req64/ 3-6 rst/ 3-4 rtck_ice 3-14 sack+- 3-11 satn+- 3-11 sbsy+- 3-11 scanen 3-15 scanmode 3-15 scd+- 3-11 sclk 3-9 sd[15:0]+- 3-10 sdp[1:0]+- 3-10 serialclk 3-13 serialdata 3-13 serr/ 3-7 si_o+- 3-11 smsg+- 3-11 sreq+- 3-11 srst+- 3-11 ssel+- 3-11 stop/ 3-6 tck_chip 3-14 tck_ice 3-14 tdi_chip 3-14 tdi_ice 3-14 tdo_chip 3-14 tdo_ice 3-14 testaclk 3-15 testclken 3-15 testhclk 3-15 tms_chip 3-14 tms_ice 3-14 tn 3-15 traceclk 3-14 tracepkt[7:0] 3-14 tracesync 3-14 trdy/ 3-6 trst_ice/ 3-14 tst_rst/ 3-14 vdd_io 3-18 vdda 3-18 vddc 3-18 vss_io 3-18 vssa 3-18 vssc 3-18 zcr_en/ 3-13 signal drive strength 2-20 , 2-22 signal list 5-16 , 5-18 signalled system error bit 4-5 signals bidirectional 5-5 flash rom/nvsram interface 3-12 gpio 3-16 ground 3-17 input 5-6 led 3-16 pci address and data 3-5 pci arbitration 3-7 pci error reporting 3-7 pci interface control 3-6 pci interrupt 3-8 pci system 3-4 pci-related 3-8 power 3-17 power-on sense 3-19 pull-ups and pull-downs 3-23 scsi channel 3-10 scsi channel control 3-10 serial eeprom interface 3-13 test interface 3-14 zero channel raid interface 3-13 signature recognition 2-25 single ended scsi 2-23 , 5-7 sio+- 5-3 sisl 1-10 skew compensation 1-2 , 1-7 , 1-9 , 2-22 slew rate 1-7 , 1-9 , 2-23 , 5-8 , 5-9 smsg+- 3-11 , 5-3 special cycle command 2-10 , 2-11 , 4-5 split completion command 1-10 , 2-10 , 2-13 split completion discarded bit 4-30 split completion error 4-29 split completion received error message 4-29 split completion unexpected 4-30 split transaction 1-10 , 4-30 sreq+- 3-11 , 5-3 srst+- 3-11 , 5-3 ssel+- 3-11 , 5-3 status iop doorbell bit 4-40 register 4-4 , 4-5 , 4-29 stop/ 3-6 , 5-5 stress ratings 5-2 subsystem id 2-27 , 2-28 , 3-21 , 4-15 subsystem id register 4-14 subsystem vendor id 2-27 , 2-28 , 3-21 subsystem vendor id register 4-13 supply current 5-2 supply voltage 5-2 surelink 1-2 , 1-7 , 1-12 , 2-22 , 2-23 system address space 4-1 system application 1-4 system bios 2-8 , 2-27 system doorbell 2-16 , 4-34 , 4-40 system doorbell interrupt bit 4-40 system doorbell register 4-34 system interface 2-4 , 2-15 bus mastering function 2-15 doorbell 2-7
index ix-9 version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. t ta 5-2 target abort 4-5 tck_chip 3-14 , 3-23 , 5-6 tck_ice 2-30 , 3-14 , 3-23 , 5-6 tdi_chip 3-14 , 3-23 , 5-6 tdi_ice 2-30 , 3-14 , 3-23 , 5-6 tdo_chip 3-14 , 5-6 tdo_ice 2-30 , 3-14 , 5-6 temperature junction 5-2 lead 5-2 operating free air 5-2 storage 5-2 termination 2-23 test base address register 4-37 test condition 5-8 test interface 2-30 , 3-14 testability 1-12 testaclk 3-15 , 3-23 , 5-6 testclken 3-15 , 3-23 , 5-6 testhclk 3-15 , 3-23 , 5-6 testreset/ 4-36 thermal resistance 5-2 timer 2-5 timing external memory 5-11 flash rom address 5-11 flash rom read 5-12 flash rom write 5-12 interrupt output 5-10 pci and pci-x 5-9 power-up 5-11 reset 5-10 timing diagrams 5-11 tj 5-2 tms_chip 3-14 , 3-23 , 5-6 tms_ice 2-30 , 3-14 , 3-23 , 5-6 tn 3-15 , 3-23 , 5-6 tolerant 1-8 , 1-12 , 5-7 traceclk 3-14 , 5-6 tracepkt[7:0] 3-14 , 5-6 tracesync 3-14 , 5-6 transfer period 2-18 transfer width 2-18 transfers information units 2-21 packetized 2-21 trdy/ 3-6 , 5-5 trst_ice 2-30 trst_ice/ 3-14 , 3-23 , 5-6 tst_rst/ 2-30 , 3-14 , 3-23 , 5-6 ttl interrupt bit 4-37 u ultra160 scsi dt clocking 1-2 , 2-19 parallel protocol request 2-22 ppr 2-22 ultra320 scsi 1-5 , 1-7 benefits 1-7 bus training 1-9 channel module 2-2 core 2-6 crc 2-22 domain validation 2-22 dt clocking 1-2 , 2-19 features 1-2 , 2-18 , 2-19 functional description 2-18 information unit 2-21 isi 1-7 , 2-19 paced transfers 2-19 packetized transfers 2-21 parallel protocol request 2-18 , 2-22 ppr 2-18 precompensation 2-20 qas 2-22 quick arbitration and selection 2-22 skew compensation 1-2 , 1-7 , 1-9 , 2-22 unexpected split completion bit 4-30 v vdd_core 5-2 vdd_io 3-18 , 5-2 vdda 3-18 vddc 3-18 vendor id register 4-3 version bit 4-20 voltage analog 5-2 common mode 5-3 core 5-2 feed-through protection 1-12 i/o 5-2 input maximum 5-2 supply 5-2 vss_io 3-18 vssa 3-18 vssc 3-18 w write and invalidate enable bit 4-4 write flow 2-18 write i/o key 4-35 , 4-36 , 4-39 write journaling 2-26 write sequence register 4-35 , 4-36 , 4-39 z zcr 2-28 , 2-29 , 3-13 zcr_en/ 2-28 , 3-13 , 3-23 , 5-6 zero channel raid 2-28 , 2-29 , 3-13
ix-10 index version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved.
LSI53C1020 pci-x to ultra320 scsi controller version 2.0 copyright 2001, 2002 by lsi logic corporation. all rights reserved. customer feedback we would appreciate your feedback on this document. please copy the following page, add your comments, and fax it to us at the number shown. if appropriate, please also fax copies of any marked-up pages from this document. impor tant: please include your name, phone number, fax number, and company address so that we may contact you directly for clari?ation or additional information. thank you for your help in improving the quality of our documents.
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