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april 1999 1 copyright ? 1997 by lsi logic corporation. all rights reserved. BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) datasheet lsi logics BIDIRECTIONAL transceiver for scsi is used to transmit and receive data on a scsi-2 or scsi-3 bus. the bus operates at rates up to 20 mhz, with a cable length up to 3 m and maximum stub lengths of 0.1 m. implementations that limit transfer rates to 5 mhz can extend the cable length to 6 m. scsi bus termination is assumed to be external to the scsi device. this transceiver conforms to the information technologyscsi-3 parallel interface speci?cation as well as to the american national standard for information systemsscsi-3 fast-20 , published by the x3t9.2 and x3t10 committees. this transceiver can operate with scsi-2, scsi-3 10-mhz interfaces, or scsi-3 fast-20 interfaces. these i/o cells operate at up to 20 mhz. this transceiver is implemented in g10? technology. figure 1 scsi bus interface fpo scsi controller 1 target devices pc or workstation 2 3 4 5 6 7 termi- nation termi- nation
2 BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) features and bene?ts speci?cations the following subsections provide the speci?cations for the scsi BIDIRECTIONAL 3.3-v transceivers. scsi BIDIRECTIONAL transceiver compliant with scsi-3 parallel interface speci?cation compliant with the american national standard for information systemsscsi-3 fast-20 reduces engineering effort of designing an interconnect to scsi bus v/i characteristics that meet the scsi bus drive requirements provides for direct silicon interconnect to a scsi transmission line on-chip 48 ma drivers 3.3-v v dd (5-vCtolerant) BIDIRECTIONAL i/o transceiver that provides maximum ?exibility in i/o path design available in the g10 cell-based product families (0.4 micron drawn gate length, 0.29 micron effective channel length) transfer rates up to 20 mhz active negation driver name: bdsescsif description: scsi 3.3-v BIDIRECTIONAL transceiver used with the scsi-2, scsi-3, and scsi-3 fast-20 buses width: 226.8 m m high, 112.0 m m wide coding syntax: u(io, zi, po) = bdsescsif (io, a, pi, en, tn, neg, htplg, iddtn)
BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) 3 figure 2 shows the schematic symbol for the BIDIRECTIONAL transceiver. figure 2 BIDIRECTIONAL transceiver logic diagram ta b l e 1 provides the loading characteristics for the input portion for the BIDIRECTIONAL transceiver. values are in standard loads. input protection ion a tn en zi po pi slew-rate controlled iddtn reference voltages htplg neg table 1 BIDIRECTIONAL transceivers loading characteristic version technology a en tn pi neg iddtn htplg bdsescsif lcbg10p 1.3 0.9 1.3 1.4 0.8 5.0 4.4
4 BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) input portion of BIDIRECTIONAL transceiver ta b l e 2 provides the truth table for the input portion. ta b l e 3 lists the dc characteristics and ta b l e 4 the ac timing for the BIDIRECTIONAL transceivers input portion. these speci?cations are valid only for the commercial operating range: junction temperature = 0 cto 125 c, v dd = 3.3 v 5%. table 2 BIDIRECTIONAL transceivers input portion truth table ion pi zi po 0x01 1011 1110 table 3 BIDIRECTIONAL transceivers input portion dc characteristics for 3.3-v and 5.0-v signaling symbol parameter test condition min typ max units v ih input high voltage 1 signal false state 1.9 5.25 v v il input low voltage referenced to v ss signal true state - 0.5 1.0 v v ik input clamp voltage v dd = min; ii = - 20 ma - 0.75 v v th threshold, high to low 1.00 1.30 v v tl threshold, low to high 1.60 1.90 v v th - v tl hysteresis 300 mv i il low level input current v i = 0.5 v, power on or power off, except during hot plug +/ - 20 m a (sheet 1 of 2)
BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) 5 note: max values apply over all v cc , temperature, and process conditions. ac timing measurements are made with t r ,t f (0.5 v - 2.3 v, 2.3 v - 0.5 v) less than 6ns. i ih high level input current v i = 2.7 v, power on or off, except during hot plug +/ - 20 m a iih.hp hot plug high level current peak transient duration to 10% of peak = 20 m s. applies during physical insertion only. +1.5 ma v dd supply voltage 3.14 3.30 3.45 v t j junction temp 0 125 c i lu latch up current - 2vBIDIRECTIONAL transceivers input portion dc characteristics for 3.3-v and 5.0-v signaling (cont.) symbol parameter test condition min typ max units (sheet 2 of 2) table 4 BIDIRECTIONAL transceivers input portion ac timing for 3.3-v and 5.0-v signaling (ns) delay path output standard load 0 2 4 8 12 16 ion to zi tplh 0.31 0.35 0.37 0.43 0.48 0.54 tphl 0.24 0.26 0.29 0.34 0.38 0.43
6 BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) output portion of BIDIRECTIONAL transceiver ta b l e 5 shows the truth table for the output portion of the BIDIRECTIONAL transceiver. . note: on a scsi bus, a high is negated, and a low is asserted. table 5 BIDIRECTIONAL transceivers output portion truth table iddtn neg a tn en ion 1 0 x x 1 high z 1 0 x 0 x high z 100100 101101 1 1 x x 1 high z 1 1 x 0 x high z 110100 11110 high z 0xxxx high z
BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) 7 ta b l e 6 lists the dc characteristics and ta b l e 7 the ac timing for the output portion of the BIDIRECTIONAL transceiver. these speci?cations are valid only for the commercial operating range: junction temperature = 0 cto125 c, v dd = 3.3 v 5%. figure 3 shows the timing test circuit for the output portion of the BIDIRECTIONAL transceiver. table 6 BIDIRECTIONAL transceivers output portion dc characteristics for 3.3-v and 5.0-v signaling symbol parameter min typ max units test condition v ol output low voltage 0.0 0.5 v i ol =48ma signal true state v oh output high voltage 2.0 3.24 v i oh = - 7ma signal false state requires v dd = 4.75 - 5.25 v i il low level output current +/ - 20 m a high z state: v i =0.5v,poweronorpower off, except during hot plug i ih high level output current +/ - 20 m a high z state: v i = 2.7 v, power on or off, except during hot plug i ih.hp hot plug high level current peak +1.5 ma high z state: transient duration to 10% of peak = 20 m s. this applies during physical insertion only. i l output leakage +/ - 10 m a high z state, v dd = max v dd supply voltage 3.14 3.30 3.45 v v ol and high z only t j junction temp 0 125 c i lu latch up current +/ - 100 ma - 2v 8 BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) figure 3 scsi output timing (rise time) test circuit ta b l e 7 provides the ac timing of the buffers output portion. note: values apply over all v cc , temperature, and process conditions. pads = 1. slew rate of signal from high to low = 520 mv/ns max slew (0.7C2.3 v), best case process, temperature, voltage, with 15-pf load, 10C90% of full amplitude. a 15 pf +/ - 5% test point 47 w +/ - 5% 2.5 v source scsi driver load capacitance ion table 7 BIDIRECTIONAL transceivers output portion ac timing (ns, slew) delay path output load (pf) 15 50 85 100 a to ion tplh 6.12 6.68 7.09 7.25 tphl 8.08 8.79 9.41 9.65 tpzl 6.17 7.51 8.22 8.50 tplz 10.18 9.95 9.73 9.66 en to ion tpzh 2.52 4.03 5.80 6.56 tpzl 6.76 7.56 8.27 8.55 tplz 10.19 9.95 9.74 9.67 tphz 1.55 1.55 1.55 1.55 tn to ion tpzh 2.30 4.07 5.85 6.61 tpzl 6.63 7.44 8.15 8.43 tplz 10.10 9.87 9.66 9.58 tphz 1.42 1.42 1.42 1.42
BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) 9 cell placement restrictions the following cells are designed to be used with bdsescsif in lcbg10p technology: pvdd2_sescsi: to supply vdd2 pvdd_sescsi: to supply 3.3 v to the i/o buffer pvss2_sescsi: to supply vss2 dvdd_sescsi: dummy cell for single-ended scsi cells the ?rst three cells in this list supply vdd2, 3.3-v i/o buffer, and vss2 to the scsi buffers. the dvdd_sescsi cell provides a protection diode between vddsescsi and vssio. adhere to the following guidelines when placing these cells: 1. at least one dummy cell must be placed at both ends of the scsi section. 2. there must be at least one pvdd_sescsi cell per ?ve scsi buffers; one v ss per two scsi buffers.
10 BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) power on reset cell figure 4 shows the schematic symbol for the power on reset cell. figure 4 power on reset cell recommended operating conditions ta b l e 8 provides the recommended operating conditions for the BIDIRECTIONAL scsi i/o transceiver. name: scsipor description: provides power-up timing to the output and BIDIRECTIONAL cells. this cell must be used; only one is needed for all i/o transceivers. width 226.8 m m high, 144.2 m m wide coding syntax u(htplg) = scsipor(); for 3.3 vdd v dd htplg table 8 recommended operating conditions symbol parameter minimum typical maximum unit v dd dc supply voltage 3.14 3.3 3.47 v t j junction temperature 0 30 125 c
BIDIRECTIONAL 3.3 v i/o transceiver for scsi-2, scsi-3, and scsi-3 fast-20 buses (lcbg10p) 11 notes
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