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rev 1.1.11 3/12/02 characteristics subject to change without notice. 1 of 22 www.xicor.com x9119 single digitally-controlled (xdcp ) potentiometer features 1024 resistor taps ?10-bit resolution 2-wire serial interface for write, read, and transfer operations of the potentiometer wiper resistance, 40 ? ? ? ? typical @ v cc = 5v four non-volatile data registers non-volatile storage of multiple wiper positions power on recall. loads saved wiper position on power up. standby current < 3? max ? cc : 2.7v to 5.5v operation 100k ? ? ? ? end to end resistance 100 yr. data retention endurance: 100,000 data changes per bit per register 14-lead tssop, 15-lead xbga low power cmos single supply version of the x9118 description the x9119 integrates a single digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 1023 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the 2-wire bus interface. the potentiometer has associated with it a volatile wiper counter register (wcr) and a four non-volatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. powerup recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. single supply / low power / 1024-tap / 2-wire bus a pplication n otes and d evelopment s ystem a v a i l a b l e an99 ?an115 ?an124 ?n133 ?an134 ?an135 functional diagram r h r l bus r w interface & control pot v cc v ss 2-wire bus address data status write read wiper 1024-taps transfer nc nc 100k ? power on recall wiper counter register (wcr) data registers (dr0-dr3) control interface preliminary information
x9119 ?preliminary information characteristics subject to change without notice. 2 of 22 rev 1.1.11 3/12/02 www.xicor.com circuit level applications vary the gain of a voltage ampli?r provide programmable dc reference voltages for comparators and detectors control the volume in audio circuits trim out the offset voltage error in a voltage ampli?r circuit set the output voltage of a voltage regulator trim the resistance in wheatstone bridge circuits control the gain, characteristic frequency and q-factor in ?ter circuits set the scale factor and zero point in sensor signal conditioning circuits vary the frequency and duty cycle of timer ics vary the dc biasing of a pin diode attenuator in rf circuits provide a control variable (i, v, or r) in feedback circuits system level applications adjust the contrast in lcd displays control the power level of led transmitters in communication systems set and regulate the dc biasing point in an rf power ampli?r in wireless systems control the gain in audio and home entertainment systems provide the variable dc bias for tuners in rf wireless systems set the operating points in temperature control systems control the operating point for sensors in industrial systems trim offset and gain errors in arti?ial intelligent systems detailed functional diagram scl a1 sda a2 wp interface and control circuitry v cc v ss dr0 dr1 dr2 dr3 wiper counter register (wcr) r h r l data r w 1024-taps 100k ? control power on recall a0
x9119 ?preliminary information characteristics subject to change without notice. 3 of 22 rev 1.1.11 3/12/02 www.xicor.com pin configuration pin assignments pin (tssop) pin (xbga) symbol function 1 d1, a3 nc no connect 2 b3 a0 device address for 2-wire bus 3 b2 nc no connect 4 c3 a2 device address for 2-wire bus 5 d3 scl serial clock for 2-wire bus 6 e3 sda serial data input/output for 2-wire bus 7e2 v ss system ground 8d2 wp hardware write protect 9 e1 a1 device address for 2-wire bus 10 c2 nc no connect 11 c1 r w wiper terminal of the potentiometer 12 b1 r h high terminal of the potentiometer 13 a1 r l low terminal of the potentiometer 14 a2 v cc system supply voltage v cc r l v ss 1 2 3 4 5 6 7 8 14 13 12 11 10 9 nc r w a2 a1 tssop r h x9119 xbga a0 nc sda nc scl wp x9119 a1 a2 a3 b1 b2 b3 c1 c2 c3 d1 d2 d3 e1 e2 e3 rl v cc nc rh nc a0 rw nc a2 nc wpn scl a1 v ss sda
x9119 ?preliminary information characteristics subject to change without notice. 4 of 22 rev 1.1.11 3/12/02 www.xicor.com pin descriptions bus interface pins s erial d ata i nput /o utput (sda) the sda is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. it receives device address, opcode, wiper register address and data sent from an 2-wire master at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock scl. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. s erial c lock (scl) this input is used by 2-wire master to supply 2-wire serial clock to the x9119. d evice a ddress (a 2 ? 0 ) the address inputs are used to set the least signi?ant 3 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9119. a maximum of 8 devices may occupy the 2- wire serial bus. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w the wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. bias supply pins s ystem s upply v oltage (v cc ) and s upply g round (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. other pins n o c onnect no connect pins should be left open. these pins are used for xicor manufacturing and testing purposes. principles of operation the x9119 is an integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. this section provides detail description of the following: resistor array description serial interface description instruction and register description resistor array description the x9119 is comprised of a resistor array. the array contains, in effect, 1023 discrete resistive segments that are connected in series (see figure 1). the physical ends of each array are equivalent to the ?ed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by the wiper counter register (wcr). the 10-bits of the wcr (wcr[9:0]) are decoded to select, and enable, one of 1024 switches. the wcr may be written directly. the data registers and the wcr can be read and written by the host system.
x9119 ?preliminary information characteristics subject to change without notice. 5 of 22 rev 1.1.11 3/12/02 www.xicor.com figure 1. detailed potentiometer block diagram serial data path from interface register 0 serial bus input parallel bus input counter register r h r l r w 10 10 c o u n t e r d e c o d e if wcr = 000[hex] then r w = r l if wcr = 3ff[hex] then r w = r h wiper (wcr) (dr0) circuitry register 1 (dr1) register 2 (dr2) register 3 (dr3) serial interface description s erial i nterface the x9119 supports a bidirectional bus oriented protocol. the protocol de?es any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the x9119 will be considered a slave device in all applications. c lock and d ata c onventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 3. s tart c ondition all commands to the x9119 are preceded by the start condition, which is a high to low transition of sda while scl is high. the x9119 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition is met. see figure 3. s top c ondition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. see figure 3. a cknowledge acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. the transmitting device, either the master or the slave, will release the sda bus after transmitting eight bits. the master generates a ninth clock cycle and during this period the receiver pulls the sda line low to acknowledge that it successfully received the eight bits of data. the x9119 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. if the command is followed by a data byte the x9119 will respond with a ?al acknowledge. see figure 2.
x9119 ?preliminary information characteristics subject to change without notice. 6 of 22 rev 1.1.11 3/12/02 www.xicor.com figure 2. acknowledge response from receiver scl from master data output from transmitter 1 89 start acknowledge data output from receiver a cknowledge p olling the disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms eeprom write cycle time. once the stop condition is issued to indicate the end of the nonvolatile write command the x9119 initiates the internal write cycle. ack polling, flow 1, can be initiated immediately. this involves issuing the start condition followed by the device slave address. if the x9119 is still busy with the write operation no ack will be returned. if the x9119 has completed the write operation an ack will be returned and the master can then proceed with the next operation. flow 1. ack polling sequence nonvolatile write command completed enterack polling issue start issue slave address ack returned? further operation? issue instruction issue stop no yes yes proceed issue stop no proceed
x9119 ?preliminary information characteristics subject to change without notice. 7 of 22 rev 1.1.11 3/12/02 www.xicor.com instruction and register description d evice a ddressing : i dentification b yte (id and a) following a start condition the master must output the address of the slave it is accessing. the most signi?ant four bits of the slave address are the device type identi?r. the id[3:0] bits is the device id for the x9119; this is ?ed as 0101[b] (refer to table 1). the a2?0 bits in the id byte is the internal slave address. the physical device address is de?ed by the state of the a2?0 input pins. the slave address is externally speci?d by the user. the x9119 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9119 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a2?0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the r/w bit is the lsb and is be used to program the device for read or write operations. i nstruction b yte and r egister s election the next byte sent to the x9119 contains the instruction and register pointer information. the three most signi?ant bits are used provide the instruction opcode (iop[2:0]). the rb and ra bits point to one of the four registers. the format is shown below in table 2. table 3 provides a complete summary of the instruction set opcodes. table 1. identification byte format table 2. instruction byte format register selected rb ra dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 id3 id2 id1 id0 a2 a1 a0 r/w 0101 (msb) (lsb) device type identifies internal slave address read or write bit i2 i1 i0 0 rb ra 0 0 (msb) (lsb) instruction opcode register selection
x9119 ?preliminary information characteristics subject to change without notice. 8 of 22 rev 1.1.11 3/12/02 www.xicor.com table 3. instruction set note: (1) 1/o = data is one or zero. instruction instruction set operation r/w i 2 i 1 i 0 0rbra 0 0 read wiper counter register 1 1 0 0 0 0 0 0 0 read the contents of the wiper counter register write wiper counter register 0 1 0 1 0 0 0 0 0 write new value to the wiper counter register read data register 1 1 0 1 0 1/0 1/0 0 0 read the contents of the data register pointed to rb-ra. write data register 0 1 1 0 0 1/0 1/0 0 0 write new value to the data register pointed to rb-ra. xfr data register to wiper counter register 1 1 1 0 0 1/0 1/0 0 0 transfer the contents of the data register pointed to by rb-ra.to the wiper counter register xfr wiper counter register to d ata regis- ter 0 1 1 1 0 1/0 1/0 0 0 transfer the contents of the wiper counter register to the data register pointed to by rb-ra. instruction and register description d evice a ddressing w iper c ounter r egister (wcr) the x9119 contains a wiper counter registers (see table 4) for the xdcp potentiometer. the wcr is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. the contents of the wcr can be altered in one of three ways: (1) it may be written directly by the host via the write wiper counter register instruction (serial load); (2) it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register; (3) it is loaded with the contents of its data register zero (r0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9119 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. power- up guidelines are recommended to ensure proper loadings of the dr0 value into the wcr. d ata r egisters (dr0 to dr3) the potentiometer has four 10-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the wiper counter register. all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as regular memory locations for system parameters or user preference data. bit 9?it 0 are used to store one of the 1024 wiper position (0 ~1023).
x9119 ?preliminary information characteristics subject to change without notice. 9 of 22 rev 1.1.11 3/12/02 www.xicor.com table 4. wiper control register, wcr (10-bit), wcr9?cr0: used to store the current wiper position (volatile, v) table 5. data register, dr (10-bit), bit 9?it 0: used to store wiper positions or data (non-volatile, nv) wcr9 wcr8 wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 vvvvvvvvvv (msb) (lsb) bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nv nv nv nv nv nv nv nv nv nv msb lsb four of the six instructions are four bytes in length. these instructions are: read wiper counter register ?read the current wiper position of the selected potentiometer, write wiper counter register ?change current wiper position of the selected potentiometer, read data register ?read the contents of the selected data register; write data register ?write a new value to the selected data register. the basic sequence of the four byte instructions is illustrated in figure 3. these four-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers. two instructions (see figure 4) require a two-byte sequence to complete. these instructions transfer data between the host and the x9119; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: xfr data register to wiper counter register ? this transfers the contents of one speci?d data register to the wiper counter register. xfr wiper counter register to data register ? this transfers the contents of the wiper counter register to the speci?d data register. see instruction format for more details. p ower u p and d own r equirements there are no restrictions on the power-up condition of vcc and the voltages applied to the potentiometer pins provided that the vcc is always more positive than or equal to the voltages at r h , r l , and r w , i.e. v cc r h , r l , r w . there are no restrictions on the power-down condition. however, the datasheet parameters for the dcp do not apply until 1milisecond after v cc reaches its ?al value. figure 3. two-byte instruction sequence s t a r t 01 0 1 a2 a1 a0 r/w a c k i2 i1 i0 0 rbra0 a c k scl sda s t o p 0 00 id3 id2 id1 id0 device id internal instruction opcode address register address
x9119 ?preliminary information characteristics subject to change without notice. 10 of 22 rev 1.1.11 3/12/02 www.xicor.com figure 4. four-byte instruction sequence (write or read for wcr or data registers) instruction format read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k wiper position (sent by slave on sda) m a c k wiper position (sent by slave on sda) m a c k s t o p 0101a2a1a0 r / w = 1 10000000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k wiper position (sent by master on sda) s a c k wiper position (sent by master on sda) s a c k s t o p 0101a2a1a0 r / w = 0 10100000 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode register addresses s a c k wiper position (sent by slave on sda) m a c k wiper position or data (sent by slave on sda) m a c k s t o p 0101a2a1a0 r / w = 1 1010rbra00 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t a c k a c k scl sda a c k s t o p a c k id3 id2 id1 id0 a2 a1 a0 r/w i2 0 0 0 x x0 0 xx x w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 i1 i0 0 rb ra 0 101 xx x device id internal address instruction opcode register address wiper or data position
x9119 ?preliminary information characteristics subject to change without notice. 11 of 22 rev 1.1.11 3/12/02 www.xicor.com write data register (dr) transfer wiper counter register (wcr) to data register (dr) transfer data register (dr) to wiper counter register (wcr) notes: (1) ?2 ~ a0? stand for the device addresses sent by the master. (2) wcrx refers to wiper position data in the wiper counter register s t a r t device type identi?r device addresses s a c k instruction opcode register addresses s a c k wiper position or data (sent by master on sda) s a c k wiper position or data (sent by master on sda) s a c k s t o p high-voltage write cycle 0101a2a1a0 r / w = 0 1100rbra00 xxxxxx w c r 9 w c r 8 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identi?r device addresses s a c k instruction opcode register addresses s a c k s t o p high-voltage write cycle 0101a2a1a0 r / w = 0 1110rbra00 s t a r t device type identi?r device addresses s a c k instruction opcode register addresses s a c k s t o p 0101a2a1a0 r / w = 1 1100rbra00
x9119 ?preliminary information characteristics subject to change without notice. 12 of 22 rev 1.1.11 3/12/02 www.xicor.com absolute maximum ratings temperature under bias.................... ?5? to +135? storage temperature......................... ?5? to +150? voltage on scl, sda, or any address input with respect to v ss ................................. ?v to +7v ? v = | (vh?l) | ......................................................5v lead temperature (soldering, 10 seconds) ........ 300 c i w (10 seconds) ..................................................?ma comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog characteristics (over recommended industrial (2.7v) operation conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot / 1023 or (r h ?r l ) / 1023, single pot (4) n = 0, 1, 2, ?1023; m =0, 1, 2, ? 1022. (5) esd rating on rh, rl, rw pins is 1.5kv (hbm, 1.0? leakage maximum), esd rating on all other pins is 2.0kv. symbol parameter limits test conditions min. typ. max. units r total end to end resistance 100 k ? end to end resistance tolerance ?0 % power rating 50 mw 25?, each pot i w wiper current ? ma r w wiper resistance 150 500 ? wiper current = 3ma, v cc = 3v r w wiper resistance 40 100 ? i w = 3ma, v cc = 5v v term voltage on any r h or r l pin v ss 5vv ss = 0v noise -120 dbv ref: 1v resolution 0.1 % absolute linearity (1) ? mi (3) r w(n)(actual) ?r w(n)(expected) , where n=8 to 1006 ?.5 mi (3) r w(n)(actual) ?r w(n)(expected) (5) relative linearity (2) ?.5 mi (3) r w(m + 1) ?[r w(m) + mi], where m=8 to 1006 ? mi (3) r w(m + 1) ?[r w(m) + mi] (5) temperature coefficient of r total 300 ppm/? ratiometric temp. coefficient 20 ppm/? c h /c l /c w potentiometer capacitancies 10/10/25 pf see macro model recommended operating conditions temp min. max. commercial 0 c +70 c industrial ?0 c +85 c device supply voltage (v cc ) limits (4) x9119 5v 10% x9119-2.7 2.7v to 5.5v
x9119 ?preliminary information characteristics subject to change without notice. 13 of 22 rev 1.1.11 3/12/02 www.xicor.com d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) endurance and data retention capacitance power-up timing notes: (6) this param eter is not 100% tested. (7) t pur and t puw are the delays required from the time the (last) power supply (vcc-) is stable until the speci? instruction can be issued. these parameters are not 100% tested. (8) this is not a tested or guaranteed parameter and should be used only as a guideline. symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 3maf scl = 400khz; v cc = +5.5v; sda = open; (for 2-wire, active, read and volatile write states only) i cc2 v cc supply current (nonvolatile write) 5maf scl = 400khz; v cc = +5.5v; sda = open; (for 2-wire, active, non-volatile write state only) i sb v cc current (standby) 3 av cc = +5.5v; v in = v ss or v cc ; sda = v cc ; (for 2-wire, standby state only) i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage ? v cc x 0.3 v v ol output low voltage 0.4 v i ol = 3ma v oh output high voltage parameter min. units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. units test conditions c in/out (6) input/output capacitance (si) 8 pf v out = 0v c in (6) input capacitance (scl, wp , a1 and a0) 6 pf v in = 0v symbol parameter min. max. units t r v cc (6) v cc power-up rate 0.2 50 v/ms t pur (7) power-up to initiation of read operation 1 ms t puw (7) power-up to initiation of write operation 50 ms
x9119 ?preliminary information characteristics subject to change without notice. 14 of 22 rev 1.1.11 3/12/02 www.xicor.com a.c. test conditions equivalent a.c. load circuit ac timinghigh-voltage write cycle timing i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 symbol parameter min. max. units f scl clock frequency 400 khz t cyc clock cycle time 2500 ns t high clock high time 600 ns t low clock low time 1300 ns t su:sta start setup time 600 ns t hd:sta start hold time 600 ns t su:sto stop setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 0 ns t r scl and sda rise time 300 ns t f scl and sda fall time 300 ns t aa scl low to sda data output valid time 250 ns t dh sda data output hold time 0 ns t i noise suppression time constant at scl and sda inputs 50 ns t buf bus free time (prior to any transmission) 1300 ns t su:wpa a0, a1, a2 setup time 0 ns t hd:wpa a0, a1, a2 hold time 0 ns r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel 5v 1533 ? 100pf sda output 3v 867 ? 100pf sda output
x9119 ?preliminary information characteristics subject to change without notice. 15 of 22 rev 1.1.11 3/12/02 www.xicor.com high-voltage write cycle timing xdcp timing symbol table symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instruction issued (all load instructions) 510s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x9119 ?preliminary information characteristics subject to change without notice. 16 of 22 rev 1.1.11 3/12/02 www.xicor.com timing diagrams start and stop timing input timing output timing t su:sta t hd:sta t su:sto scl sda t r (start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa
x9119 ?preliminary information characteristics subject to change without notice. 17 of 22 rev 1.1.11 3/12/02 www.xicor.com xdcp timing (for all load instructions) write protect and device address pins timing . scl sda r w (stop) lsb t wrl sda scl ... ... ... wp a0, a1, a2 t su:wpa t hd:wpa (start) (stop) (any instruction)
x9119 ?preliminary information characteristics subject to change without notice. 18 of 22 rev 1.1.11 3/12/02 www.xicor.com applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + v s v o r 2 r 1 } }
x9119 ?preliminary information characteristics subject to change without notice. 19 of 22 rev 1.1.11 3/12/02 www.xicor.com application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k ? + v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + r 2 + r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o
x9119 ?preliminary information characteristics subject to change without notice. 20 of 22 rev 1.1.11 3/12/02 www.xicor.com 15-ball bga (x9119tb15) a b top view (bump side down) side view (bump side down) bottom view (bump side up) c d e f k a j b note: drawing not to scale = die orientation mark symbol millimeters inches min nom. max min nom. max package width a 2.534 2.564 2.594 0.0998 0.1010 0.1021 package length b 3.271 3.301 3.331 0.1288 0.1300 0.1311 package height c 0.654 0.682 0.710 0.0258 0.0269 0.0280 body thickness d 0.444 0.457 0.470 0.0175 0.0180 0.0185 ball height e 0.210 0.225 0.240 0.0083 0.0089 0.0094 ball base diameter f 0.270 0.280 0.290 0.0106 0.0110 0.0114 ball pitch ?width j 0.5 0.0197 ball pitch ?length k 0.5 0.0197 ball to edge spacing ?width l 0.747 0.782 0.817 0.0294 0.0308 0.0322 ball to edge spacing ?length m 0.615 0.650 0.685 0.0242 0.0256 0.0270 l m a b c d e 1 2 3
x9119 ?preliminary information characteristics subject to change without notice. 21 of 22 rev 1.1.11 3/12/02 www.xicor.com packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package code v14 see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0?- 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x9119 ?preliminary information characteristics subject to change without notice. 22 of 22 rev 1.1.11 3/12/02 www.xicor.com limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending ordering information device v cc limits blank = 5v 10% ?.7 = 2.7 to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = ?0 c to +85 c package v14 = 14-lead tssop b15 = 15-lead xbga potentiometer organization pot t = 100k ? x9119 p t v y part mark convention 15 lead xbga top mark x9119tb15i-2.7 xaff x9119tb15 xafc

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