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TLC34076, TLC34076m data manual video interface palette slas054a october 1997 printed on recycled paper
important notice texas instruments (ti) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. ti warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (?critical applications?). ti semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the risk of the customer. use of ti products in such applications requires the written approval of an appropriate ti officer. questions concerning potential risk applications should be directed to ti through a local sc sales office. in order to minimize risks associated with the customer?s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does ti warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. copyright ? 1997, texas instruments incorporated
iii contents section title page 1 introduction 1?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 features 1 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 functional block diagram 1 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 terminal assignments 1 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 ordering information 1 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 terminal functions (TLC34076c and TLC34076m) 1 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . 2 detailed description 2?1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 microprocessor unit (mpu) interface 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 color palette ram 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 writing to the color palette ram 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 reading from the color palette ram 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 palette page register 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 input/output clock selection and generation 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 sclk 2 ? 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 vclk 2 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 multiplexing scheme 2 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 vga pass-through mode 2 ? 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.2 multiplexing modes 2 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.3 special nibble mode 2 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.4 true-color modes 2 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.5 multiplex control register 2 ? 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.6 read masking 2 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 reset 2 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 power-on reset 2 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 hardware reset 2 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 software reset 2 ? 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 vga pass-through mode default conditions 2 ? 17 . . . . . . . . . . . . . . . . . . . . . . . 2.6 analog output specifications 2 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 frame-buffer interface with little-endian and big-endian modes 2 ? 19 . . . . . . . . . . . . 2.8 hsync, vsync, and blank 2 ? 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 split shift register transfer vrams and special nibble mode 2 ? 20 . . . . . . . . . . . . . . 2.9.1 split shift register transfer vrams 2 ? 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.2 special nibble mode 2 ? 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 muxout output 2 ? 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 general control register 2 ? 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.1 hsyncout and vsyncout (bits 0 and 1) 2 ? 23 . . . . . . . . . . . . . . . . . . . . . . . 2.11.2 split shift register transfer enable (ssrt) and special nibble mode enable (snm) (bits 2 and 3) 2 ? 23 . . . . . . . . . . . . . . . . . . . 2.11.3 pedestal enable control (bit 4) 2 ? 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11.4 sync enable control (bit 5) 2 ? 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv 2.11.5 little-endian and big-endian mode control (bit 6) 2 ? 24 . . . . . . . . . . . . . . . . . . 2.11.6 muxout (bit 7) 2 ? 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12 test register 2 ? 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.1 frame-buffer data flow test 2 ? 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12. identification (id) code 2 ? 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.3 ones-accumulation screen integrity test 2 ? 25 . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.4 analog test 2 ? 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 electrical specifications 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 recommended operating conditions 3 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 electrical characteristics 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 electrical characteristics for TLC34076c over operating free-air temperature range 3 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 electrical characteristics for TLC34076m over operating free-air temperature range 3 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 operating characteristics 3 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 operating characteristics for TLC34076c over recommended ranges of supply voltage and operating free-air temperature 3 ? 4 . . . . . . . 3.4.2 operating characteristics for TLC34076m over recommended ranges of supply voltage and operating free-air temperature 3 ? 5 . . . . . . . . 3.5 timing requirements 3 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 timing requirements for TLC34076c over recommended ranges of supply voltages and operating temperature 3 ? 6 . . . . . . . . . . . . . . . . . . . . . 3.5.2 timing requirements for TLC34076m over recommended ranges of supply voltages and operating temperature 3 ? 8 . . . . . . . . . . . . . . . . . . . . . 3.6 switching characteristics for TLC34076c and TLC34076m over recommended ranges of supply voltages and operating temperature 3 ? 9 . . . . . . 3.7 timing diagrams 3 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix a sclk/vclk and the tms340x0 a ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix b printed circuit board layout considerations b ? 1 . . . . . . . . . . . . . . . . . . . . . . . appendix c sclk frequency < vclk frequency c ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . appendix d mechanical data d ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v list of illustrations figure title page 2 ? 1 dotclk/vclk/sclk relationship 2 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 sclk/vclk control timing (ssrt disabled, sclk frequency = vclk frequency) 2 ? 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 sclk/vclk control timing (ssrt enabled, sclk frequency = vclk frequency) 2 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 4 sclk/vclk control timing (ssrt disabled, sclk frequency = 4 y vclk frequency) 2 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 5 sclk/vclk control timing (ssrt enabled, sclk frequency = 4 y vclk frequency) 2 ? 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 6 equivalent circuit of the iog current output 2 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 7 7.5-ire, 8-bit composite video output 2 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 8 0-ire, 8-bit composite video output 2 ? 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 9 relationship between sflag/nflag, blank, and sclk 2 ? 20 . . . . . . . . . . . . . . . . . . . . . 2 ? 10 sflag/nflag timing in special nibble mode 2 ? 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 11 test-register control-word state diagrams 2 ? 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 12 internal comparator circuitry for analog test 2 ? 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 mpu interface timing 3 ? 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 video input/output timing 3 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 sflag/nflag timing (when ssrt function is enabled) 3 ? 13 . . . . . . . . . . . . . . . . . . . . .
vi list of tables table title page 2 ? 1 internal register map 2 ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 allocation of palette page register bits 2 ? 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 input clock selection register format 2 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 4 output clock selection register format 2 ? 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 5 vclk/sclk divide ratio selection (output clock selection register value in hex) 2 ? 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 6 mode and bus width selection 2 ? 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 7 true-color modes 2 ? 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 8 true-color bit definitions 2 ? 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 9 vga pass-through mode default conditions 2 ? 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 10 pixel data distribution in special nibble mode 2 ? 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 11 general control register bit functions 2 ? 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 12 test mode selection 2 ? 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 13 test register bit definitions for analog test 2 ? 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 14 bit coding for analog comparisons of bits d7 ? d4 2 ? 26 . . . . . . . . . . . . . . . . . . . . . . . . . .
1 ? 1 1 introduction the TLC34076c and TLC34076m are commercial and military versions, respectively, of a texas instruments video interface palette (vip) designed for lower system cost with a higher level of integration. lower system cost and higher integration are achieved by incorporating all the high-speed timing, synchronizing, and multiplexing logic usually associated with graphics systems into one device, thus greatly reducing chip count. since all high-speed signals (excluding the clock source) are contained on-chip, rf noise considerations are simplified. maximum flexibility is provided through the pixel multiplexing scheme, which allows for 32-, 16-, 8-, and 4-bit pixel buses to be accommodated without any circuit modification. this enables the system to be easily reconfigured for varying amounts of available video ram (vram). data can be split into 1, 2, 4, or 8 bit-planes. the TLC34076 is software-compatible with the imsg176/8 and brooktree ? bt476/8 color palettes. the TLC34076 vip is pin-for-pin compatible with the tlc34075 vip, but contains additional 24- and 16-bit true-color modes, as well as the ability to select little-endian or big-endian data formats for the pixel bus frame buffer interface. the TLC34076 features a separate vga bus that allows data from the feature connector of most vga-supported personal computers to be fed directly into the palette without the need for external data multiplexing. this allows a replacement graphics board to remain downward compatible by utilizing the existing graphics circuitry often located on the motherboard. the 24- and 16-bit true-color modes that are provided allow bits of color information to be transferred directly from the pixel port to the digital-to-analog converters (dacs). depending on which true-color mode is selected, an overlay function is provided using the remaining bits of the pixel bus. the 24-bit modes allow overlay with the eight remaining bits of the pixel bus, while the targa ? (5-5-5) 16-bit mode allows overlay with the one remaining bit of the divided pixel bus. the TLC34076 has a 256-by-24 color lookup table with triple 8-bit video d/a converters capable of directly driving a doubly terminated 75- ? line. sync generation is incorporated on the green output channel. hsync and vsync are fed through the device and optionally inverted to indicate screen resolution to the monitor. a palette page register provides the additional bits of palette address when 1, 2, or 4 bit-planes are used. this allows the screen colors to be changed with only one mpu write cycle. clocking is provided through one of four or five inputs (three ttl compatible and either one ecl compatible or two ttl compatible) and is software selectable. the video and shift clock outputs provide a software-selected divide ratio of the chosen clock input. the TLC34076 can be connected directly to the serial port of vram devices, eliminating the need for any discrete logic. support for split shift register transfers is also provided. 1.1 features ? versatile multiplexing interface to allow lower pixel bus rate ? high level of integration to provide lower system cost and complexity ? direct vga pass-through capability ? versatile pixel bus interface to support little-endian and big-endian data formats ? true-color (direct-addressing) mode to support various 24-bit and 16-bit formats ? compatible with 5-6-5 xga format ? compatible with 5-5-5 targa format ? interfaces directly to tms34010/tms34020 and other graphics processors ? triple 8-bit d/a converters brooktree is a trademark of the brooktree corporation. targa is a registered trademark of truevision incorporated.
1 ? 2 ? available in 85-, 110-,135-, and 170-mhz versions ? 256-word color palette ram ? palette page register ? on-chip voltage reference ? rs-343a-compatible outputs ? ttl-compatible inputs ? standard mpu interface ? pixel word mask ? on-chip clock selection ? interfaces directly to video ram ? supports split shift register transfers ? software downward-compatible with inmos ? imsg176/8 and brooktree bt476/8 color palettes ? tiga ? -software-standard compatible ? linepic ? 1- m cmos process linepic and tiga are trademarks of texas instruments incorporated. inmos is a trademark of inmos international limited.
1 ? 3 1.2 functional block diagram input 6 latch 4 8 32 test video mux output color read true-color page clock 24 mpu registers & control 8 32 8 32 32 32 32 32 8 24 control 8 4 vsyncout hsyncout iob iog ior 7 1 2 8 register mask 8 pipeline delay palette ram register 888 8 8 8 8 8 8 & control mux muxout rd rs0 ? rs3 clk3 vgablank blank vsync hsync vclk sclk sflag/ wr vga0 ? vga7 p0 ? p31 fs adjust nflag 8/6 dac dac dac clk0 ? clk3 v ref d0 ? d7 comp 16 16 24 32 15 8 1
1 ? 4 1.3 terminal assignments the terminal assignments for TLC34076c are shown in the 84-pin fn package; terminal assignments for TLC34076m are shown in the 84-pin ga package. 34 35 clk3 clk3 vga7 vga6 vga5 vga4 vga3 vga2 vga1 vga0 8/6 muxout sflag/nflag vgablank blank vsync hsync v dd gnd v dd gnd 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 36 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p17 p16 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 wr rd rs0 37 38 39 40 p28 10 9 8 7 6 11 5 p20 p21 p22 p23 p24 p25 p26 d7 rs3 d0 d1 d2 d3 d4 d5 321 4 41 42 43 44 45 84 83 33 rs1 p30 82 81 80 79 46 47 48 49 hsyncout vsyncout ior iog p31 gnd sclk p18 iob fs adjust 50 51 52 53 vclk clk0 clk2 78 77 76 75 ref v p19 p27 p29 v dd clk1 comp v dd gnd d6 rs2 84-pin fn package (top view)
1 ? 5 1.3 terminal assignments (continued)
&6 "! # # $ & # & "%"!
# # # # #
#
# #
# #
35.(0- 02 '-,+/.*/4 )04 0/ 401

# &6 "! " ! # # # 6
1 ? 6 1.3 terminal assignments (continued)
# # 3*+ $ & # & "%"!
# # # # #
#
# #
# #
46/(1. 13 '.-,0/*05 )15 10 512

# # &7 "! # &7 "! " ! # 7
1 ? 7 1.4 ordering information pixel clock frequency indicator must contain two or three characters: ? 85: 85-mhz pixel clock ? 110: 110-mhz pixel clock ? 135: 135-mhz pixel clock ? 170: 170-mhz pixel clock military extension package must contain two letters: fn: plastic, square, leaded chip carrier (formed leads) ga: 84-pin (12 x 12) ceramic pin-grid array TLC34076 ? (x)xx m pp
1 ? 8 1.5 terminal functions (TLC34076c and TLC34076m) terminal i/o description name no. no. i/o description blank , vgablank 60, 61 m9, l8 i blanking inputs. two blanking inputs are provided in order to remove any external multiplexing of the signals that may cause data and blank to skew. when the vga pass-through mode is set in the multiplex control register, the vgablank input is used for blanking; otherwise, blank is used. clk0 ? clk2 77, 76, 75 k2, l2, k3 i dot clock inputs. any of the three clocks can drive the dot clock at frequencies up to 135 mhz. when vga pass-through mode is active, clk0 is used by default. clk3, clk3 74, 73 m1, l3 i dual-mode dot clock input. the clock input is an ecl-compatible input, but a ttl clock may be used on either clk3 or clk3 when so selected in the input clock selection register. this input may be selected as the dot clock for any frequency of operation up to the device limit. it can also be used with a single-ended ecl clock source when the unused input is externally terminated to provide the proper common mode level. comp 52 k11 i compensation input. comp provides compensation for the internal reference amplifier. a resistor (optional) and ceramic capacitor are required between comp and v dd . the resistor and capacitor must be as close to the device as possible to avoid noise pickup (see appendix b for more details). d0 ? d7 36 ? 43 b12, c12, d11, d12, e11, e12, f11, f12 i/o mpu interface data bus. d0 ? d7 transfers data in and out of the register map and palette/overlay ram. fs adjust 51 l12 i full-scale adjustment. a resistor connected between fs adjust and ground controls the full-scale range of the dacs. gnd 44, 54, 56, 80 j2, l10, k10, g11 ground. all gnd terminals must be connected together. the analog and digital gnd terminals are connected internally. hsyncout, vsyncout 46, 47 h12, h11 o horizontal and vertical sync outputs. the hsyncout and vsyncout are the true/complement gate mentioned in the hsync and vsync description below (see section 2.8). hsync , vsync 58, 59 m10, l9 i horizontal and vertical sync inputs. hsync and vsync generate the sync level on the green current output. they are active-low inputs for the normal modes and are passed through a true/complement gate. for the vga pass-through mode, they are passed through to hsyncout and vsyncout without polarity change as specified by the control register (see section 2.8). ior, iog, iob 48, 49, 50 j12, j11, k12 o analog current outputs. the ior, iog, and iob outputs can drive a 37.5- ? load directly (doubly terminated 75- ? line), thus eliminating the need for any external buffering. terminal numbers shown are for the fn package. terminal numbers shown are for the ga package. notes: 1. although leaving unused terminals floating does not adversely affect device operation, tying unused terminals to ground lowers power consumption, thus is recommended. 2. all digital inputs and outputs are ttl compatible, unless otherwise noted.
1 ? 9 1.5 terminal functions (TLC34076c and TLC34076m) (continued) terminal i/o description name no. no. i/o description muxout 63 m7 o mux output control. muxout is software programmable. it is set low to indicate to external devices that vga pass-through mode is being used when the multiplex control register value is set to 2dh. when bit 7 of the general-control register is set high after the mode is set, this output goes high. this terminal is only used for external control; it affects no internal circuitry. p0 ? p31 29 ? 1, 84 ? 82 a10, b9, a9, b8, a8, b7, a7, b6, a6, a5, b5, a4, b4, a3, a2, b3, b2, c3, a1, c2, b1, c1, d2, d1, e2, e1, f1, f2, g1, g2, h1, h2 i pixel input port. this port can be used in various modes as shown in the mux control register. it is recommended that unused terminals be tied to ground. it also supports little-endian and big-endian data formats. all the unused terminals must be tied to gnd. rd 31 b10 i read strobe input. a low on rd initiates a read from the TLC34076 register map. reads are performed asynchronously and are initiated on the falling edge of rd (see figure 3 ? 1). rs0 ? rs3 32 ? 35 a12, c10, b11, c11 i register select inputs. rsx specifies the location in the register map that is to be accessed (see table 2 ? 1). sclk 79 k1 o shift clock output. sclk is selected as a submultiple of the dot clock input. sclk is gated off during blanking. sflag/ nflag 62 m8 i split shift register transfer flag or nibble flag input. sflag/nflag has two functions. when the general control register bit 3 = 0 and bit 2 = 1, the split shift register transfer function is enabled and a low-to-high transition on sflag/nflag during a blank sequence initiates an extra sclk cycle to allow a split shift register transfer in the vrams. when the general control register bit 3 = 1 and bit 2 = 0, special nibble mode is enabled and this input is sampled at the falling edge of vclk. a high value sampled indicates that the next sclk rising edge should latch the high nibble of each byte of the pixel data bus; a low value sampled indicates that the low nibble of each byte of the pixel data bus should be latched (see section 2.9). when the general control register bit 3 = 0 and bit 2 = 0, the condition of sflag/nflag is ignored. the condition of bit 3 = 1, bit 2 = 1 is not allowed, and device operation is unpredictable when they are so set. vclk 78 l1 o video clock output. vclk is user-programmable output for synchronization of the TLC34076 to a graphics processor. v dd 45, 55, 57, 81 j1, l11, g12 power. all v dd terminals must be connected. the analog and digital v dd terminals are connected internally. terminal numbers shown are for the fn package. terminal numbers shown are for the ga package. notes: 1. although leaving unused terminals floating does not adversely affect device operation, tying unused terminals to ground lowers power consumption, thus is recommended. 2. all digital inputs and outputs are ttl compatible, unless otherwise noted.
1 ? 10 1.5 terminal functions (TLC34076c and TLC34076m) (continued) terminal i/o description name no. no. i/o description vga0 ? vga7 65 ? 72 m6, l6, m5, l5, m4, l4, m3, m2 i vga pass-through bus. the vgan bus can be selected as the pixel bus for the vga pass-through mode. it does not allow for any multiplexing. v ref 53 m12 voltage reference for dacs. an internal voltage reference of nominally 1.235 v is supplied. a 0.1- f ceramic capacitor between v ref and gnd is recommended for noise filtering using either the internal or an external reference voltage. the internal reference voltage can be overridden by an externally supplied voltage. the typical connection is shown in appendix b. wr 30 a11 i write strobe input. a low on wr initiates a write to the TLC34076 register map. write transfers are asynchronous. the data written to the register map is latched on the rising edge of wr (see figure 3 ? 1). 8/6 64 l7 i dac resolution selection. the 8/6 terminal selects the data bus width (8 or 6 bits) for the dacs and is provided to maintain compatibility with the inmos imsg176/8 color palette. when this terminal is high, 8-bit bus transfers are used, with d7 being the msb and d0 the lsb. for 6-bit bus operation, while the color palette still has the 8-bit information, d5 shifts to the bit 7 position, d0 shifts to the bit 2 position, and the two lsbs are filled with zeros at the output mux to the dac. when read in the 6-bit mode, the palette holding register zeros the two msbs. terminal numbers shown are for the fn package. terminal numbers shown are for the ga package. notes: 1. although leaving unused terminals floating does not adversely affect device operation, tying unused terminals to ground lowers power consumption, thus is recommended. 2. all digital inputs and outputs are ttl compatible, unless otherwise noted.
2 ? 1 2 detailed description 2.1 microprocessor unit (mpu) interface the processor interface is controlled using read and write strobes (rd , wr ), four register select terminals (rs0 ? rs3), and the 8/6 select terminal. the select 8/6 terminal selects between 8-bit and 6-bit operation and is provided in order to maintain compatibility with the imsg176/8 color palette. this operation is carried out to utilize the maximum range of the dacs. the internal register map is shown in table 2 ? 1. the mpu interface operates asynchronously, with data transfers being synchronized by internal logic. all the register locations support read and write operations. table 2 ? 1. internal register map rs3 rs2 rs1 rs0 register addressed by mpu l l l l palette address register ? write mode l l l h color palette holding register l l h l pixel read mask l l h h palette address register ? read mode l h l l reserved l h l h reserved l h h l reserved l h h h reserved h l l l general control register h l l h input clock selection register h l h l output clock selection register h l h h multiplex control register h h l l palette page register h h l h reserved h h h l test register h h h h reset state 2.2 color palette ram the color palette ram is addressed by two internal 8-bit registers, one for reading from the ram and one for writing to the ram. these registers are automatically incremented following a ram transfer, allowing the entire palette to be read/written with only one access of the address register. when the address register increments beyond the last location in ram, it is reset to the first location (address 0). although all read and write accesses to the ram are asynchronous to sclk, vclk, and the dot clock, they are performed within one dot clock and so do not cause any noticeable disturbance on the display. the color palette ram is 24 bits wide for each location (8 bits each for red, green, and blue). when 6-bit mode is chosen (8/6 = low), the two msbs are still written to the color palette ram. however, when they are read back in the 6-bit mode, the two msbs are set to 0 to maintain compatibility with the imsg176/8 and bt476/8 color palettes. the output mux shifts the six lsbs to the six msb positions, fills the two lsbs with 0s, then feeds the 8 bits to the dac. with the 8/6 terminal held low, data on the lowest 6 bits of the data bus are internally shifted up by two bits to occupy the upper six bits at the output mux, and the bottom two bits are then cleared to 0. the test register and the ones-accumulation register both take data before the output mux to give the user the maximum flexibility. the color-palette ram-access methodology is described in the following two sections and is fully compatible with the inmos imsg176/8 and brooktree bt476/8 color palettes.
2 ? 2 2.2.1 writing to the color palette ram to load the color palette ram, the mpu must first write to the address register (write mode) with the address where the modification is to start. this action is followed by three successive writes to the palette-holding register with eight bits each of red, green, and blue data. after the blue data write cycle, the three bytes of color are concatenated into a 24-bit word and written to the color palette ram location specified by the address register. the address register then increments to point to the next color palette ram location, which the mpu may modify by simply writing another sequence of red, green, and blue data bytes. a block of color values in consecutive locations may be written to by writing the start address and performing continuous red, green, and blue write cycles until the entire block has been written. 2.2.2 reading from the color palette ram reading from the color palette ram is performed by writing the location to be read to the address register. this action initiates a transfer from the color palette ram into the holding register followed by an increment of the address register. three successive mpu reads from the holding register produce red, green, and blue color data (6 or 8 bits, depending on the 8/6 mode) for the specified location. following the blue read cycle, the contents of the color palette ram at the address specified by the address register are copied into the holding register and the address register is again incremented. as with writing to the color palette ram, a block of color values in consecutive locations may be read by writing the start address and performing continuous red, green, and blue read cycles until the entire block has been read. 2.2.3 palette page register the 8-bit palette page register provides high-speed color changing by removing the need for color palette ram reloading. when using 1, 2, or 4 bit-planes, the additional planes are provided by the palette page register; e.g., when using four bit-planes, the pixel inputs specify the lower four bits of the color palette ram address with the upper four bits being specified by the palette register. this provides the capability of selecting from 16 palette pages with only one chip access, thus allowing all the screen colors to be changed at the line frequency. a bit-to-bit correspondence is used; therefore, in the above configuration, palette page register bits 7 ? 4 map onto color palette ram address bits 7 ? 4 respectively. this is listed in table 2 ? 2. since there is only one bit of overlay data in the 5-5-5 true color modes, the page register fills the seven remaining msbs (same as one bit-plane in table 2 ? 2). all 8 bits need to be cleared to 0 in order to enable true color. the additional bits from the palette page register are inserted before the read mask and hence, are subject to masking. table 2 ? 2. allocation of palette page register bits number of color palette ram address bits bit planes msb lsb 8 m m m m m m m m 4 p7 p6 p5 p4 m m m m 2 p7 p6 p5 p4 p3 p2 m m 1 p7 p6 p5 p4 p3 p2 p1 m pn = nth bit from palette page register m = bit from pixel port 2.3 input/output clock selection and generation the TLC34076 provides a maximum of five clock inputs. three are dedicated to ttl inputs; the other two can be selected as either one ecl input or two extra ttl inputs. the ttl and ecl inputs can be used for video rates up to 135 mhz. the dual-mode clock input (ecl/ttl) is primarily an ecl input but can be used
2 ? 3 as a ttl-compatible input when the input clock selection register is so programmed. the clock source used at power-up is clk0; an alternative source can be selected by software during normal operation. this chosen clock input is used unmodified as the dot clock (representing the pixel rate to the monitor). the device does, however, allow for user programming of the sclk and vclk outputs (shift and video clocks) using the output clock selection register. the input/output clock selection registers are shown in tables 2 ? 3, 2 ? 4, and 2 ? 5. table 2 ? 3. input clock selection register format bits ? function ? 3 210 function ? 0 0 0 0 select clk0 as clock source 0 0 0 1 select clk1 as clock source 0 0 1 0 select clk2 as clock source 0 0 1 1 select clk3 as ttl clock source 0 1 0 0 select clk3 as ttl clock source 1 0 0 0 select clk3 and clk3 as ecl clock sources ? register bits 4, 5, 6, and 7 are don ? t care bits. ? when the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks are stabilized and running. clk0 is chosen at power-up to support the vga pass-through mode. table 2 ? 4. output clock selection register format bits ? function ? 5 43210 function ? 0 0 0 x x x vclk frequency = dotclk frequency 0 0 1 x x x vclk frequency = dotclk frequency/2 0 1 0 x x x vclk frequency = dotclk frequency/4 0 1 1 x x x vclk frequency = dotclk frequency/8 1 0 0 x x x vclk frequency = dotclk frequency/16 1 0 1 x x x vclk frequency = dotclk frequency/32 1 1 x x x x vclk output held at logic high level (default condition) x x x 0 0 0 sclk frequency = dotclk frequency x x x 0 0 1 sclk frequency = dotclk frequency/2 x x x 0 1 0 sclk frequency = dotclk frequency/4 x x x 0 1 1 sclk frequency = dotclk frequency/8 x x x 1 0 0 sclk frequency = dotclk frequency/16 x x x 1 0 1 sclk frequency = dotclk frequency/32 x x x 1 1 x sclk output held at logic level low (default condition) ? register bits 6 and 7 are don ? t care bits. ? when the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks are stabilized and running. these lines indicate the power-up conditions required to support the vga pass-through mode.
2 ? 4 table 2 ? 5. vclk/sclk divide ratio selectio (output clock selection register value in hex) vclk sclk bits 2. . .0 000 001 010 011 100 101 bits 5. . .3 divide dotclk by 1 2 4 8 16 32 000 1 00 01 02 03 04 05 001 2 08 09 0a 0b 0c 0d 010 4 10 11 12 13 14 15 011 8 18 19 1a 1b 1c 1d 100 16 20 21 22 23 24 25 101 32 28 29 2a 2b 2c 2d ? output clock selection register bits the ecl input can be used as a differential or single-ended input. when the clk3 input is used as a single-ended ecl input, clk3 must be externally terminated to set the input common-mode signal level. this can be done with a simple resistor divider, as is the case with fully differential ecl. sclk is designed to drive the vrams directly, and vclk is designed to work with video control signals like blank and sync. while sclk and vclk are designed as a general-purpose shift clock and video clock, respectively, they also interface directly with the tms340x0 graphics signal processor (gsp) family directly. even though sclk and vclk can be selected independently, there is still a relationship between the two as discussed in subsequent paragraphs. many system considerations have been carefully covered in the design, leaving maximum freedom to the user. internally, both sclk and vclk are generated from a common clock counter that increments on the rising edge of the dotclk. therefore, when vclk is enabled, it is in phase with sclk (see figure 2 ? 1). as an example) (dotclk/2 sclk as an example) (dotclk/4 vclk dotclk figure 2 ? 1. dotclk/vclk/sclk relationship the internal clock counter is reset to 0 any time the output clock-selection register (bits 5, 4, 2, 1) are all set to 1. this provides a simple mechanism to synchronize multiple vips, by providing a known phase relationship for the various system clocks. one can write directly to the output clock selection register to cause this to occur, or any of the various resets (for por, hardware, and software, see section 1.5) also causes the appropriate bits to be written and the counters to reset. it is up to the user to provide some means of disabling the dot-clock input to the part while this reset is occurring, when multiple parts are to be synchronized. appendix a discusses the sclk/vclk relationship specific to the tms340x0 gsp.
2 ? 5 2.3.1 sclk data is latched inside the device on the rising edge of load, which is basically the same as sclk but not disabled during blank active period. therefore, sclk must be set as a function of the pixel bus width and the number of bit planes. sclk can be selected as 1, 2, 4, 8, 16, or 32 divisions of the dot clock. when sclk is not used, the output is switched off and held low to protect against vram lock-up due to invalid sclk frequencies. sclk is also held low during the blank active period. the sclk control timing has been designed to interface directly with the external system vram. the shift register in the system vram should be updated during the blank active period. this allows the first sclk out of blank to clock the vram and enable the first group of pixel data to appear on the pixel bus, as well as at the TLC34076 pixel input port. the second sclk after blank latches the first group of pixel port data into the TLC34076. the trailing edge of vclk is used internally by the TLC34076 to sample and latch the blank input. when blank becomes active, sclk is disabled as soon as possible. for example, when sclk is high and the sampled blank goes low, sclk is allowed to complete the clock cycle and return to the low state. sclk is then held low until the sampled blank signal goes high. at this time, sclk is enabled to clock the vram again. the TLC34076 video blanking circuitry is designed with sufficient pipeline delay to allow the internally sampled blank signal to align with the pipelined rgb data to the video dacs. the logic described herein works in situations where the sclk period is shorter than, equal to, or longer than the vclk period. when the vram split shift-register operation is performed, the sclk timing is adjusted to work with the sflag input. basically, the split shift register operation inserts a sclk during the blank period. this causes the first group of pixel data to appear at the pixel port during the blank signal. the first sclk after blank then latches this data into the TLC34076. figure 2 ? 3 shows the case when the split shift register transfer (ssrt) function is enabled. when a rising edge occurs on the sflag input, one sclk with a minimum of 15-ns pulse duration is generated after the specified delay. since this is designed to meet vram timing requirements, the ssrt-generated sclk replaces the first sclk in the regular shift register transfer case as previously described (see to section 2.9 for a detailed explanation of the ssrt function). the default divide ratio for sclk is 1:1 as used in mode 0. depending on the frequency relationship between sclk and vclk, their phase relationship could be critical (see appendix c for a more detailed discussion).
2 ? 6 2.3.2 vclk the vclk frequency can be selected to be 1:1, 1:2, 1:4, 1:8, 1:16, or 1:32 of that of the dot clock, or it can be held at a high logic level, which is the vclk default condition. vclk is not used in vga pass-through mode. vclk is used by a gsp or custom-designed control logic to generate control signals (blank , hsync , and vsync ). as can be seen from figures 2 ? 2, 2 ? 3, 2 ? 4, and 2 ? 5, since the control signals are sampled by vclk, it is obvious that vclk has to be enabled. 2nd sclk at input terminal pixel data pipeline delay) before dotclk (internal signal blank for data latch) (internal signal load at input terminal blank vclk group group 1st last group of pixel data of pixel data latch last group of pixel data latch first group of pixel data latch last group 3rd group 4th group 5th group 6th group note a: either the ssrt function is disabled (general control register bit 2 = 0), or the sflag/nflag input is held low when the ssrt function is enabled (general-control register bit 2 = 1). figure 2 ? 2. sclk/vclk control timing (ssrt disabled, sclk frequency = vclk frequency)
2 ? 7 3rd and regular shift register transfer sclk between split shift register transfer sflag/nflag sclk at input terminal pixel data pipeline delay) before dotclk (internal signal blank for data latch) (internal signal load at input terminal blank vclk group 2nd group of pixel data latch last group of pixel data latch first group of pixel data latch last group group last 1st group of pixel data group 4th group 5th group 6th note a: the ssrt function is enabled (general control register bit 2 = 1). figure 2 ? 3. sclk/vclk control timing (ssrt enabled, sclk frequency = vclk frequency) sclk at input terminal pixel data pipeline delay) before dotclk (internal signal blank for data latch) (internal signal load at input terminal blank group 2nd group 1st vclk of pixel data latch last group of pixel data latch first group last group of pixel data group 4th group 3rd group 6th group 5th figure 2 ? 4. sclk/vclk control timing (ssrt disabled, sclk frequency = 4 vclk frequency)
2 ? 8 and regular shift register transfer sclk between split shift-register sclk at input terminal pixel data pipeline delay) before dotclk (internal signal blank for data latch) (internal signal load at input terminal blank of pixel data latch last group of pixel data latch first group 1st group of pixel data group 2nd group 3rd group 4th group 5th group 6th group last vclk sflag/nflag note a: either the ssrt function is disabled (general-control register bit 2 = 0), or the sflag/nflag input is held low when the ssrt function is enabled (general-control register bit 2 = 1). figure 2 ? 5. sclk/vclk control timing (ssrt enabled, sclk frequency = 4 vclk frequency) 2.4 multiplexing scheme the TLC34076 offers a highly versatile multiplexing scheme as illustrated in table 2 ? 6. the on-chip multiplexing allows the system to be reconfigured to the amount of ram available. for example, when only 256k bytes of memory are available, an 800-by-600 resolution mode with four bit-planes (4 bits per pixel) can be implemented using an 8-bit wide pixel bus. if, at a later date, another 256k bytes are added to another 8 bits of the pixel bus, the user has the option of using eight bit-planes at the same resolution or four bit-planes at a 1024 768 resolution. when an additional 512k bytes are added to the remaining 16 bits of the pixel bus, the user has the option of eight bit-planes at 1024 768 resolution or four bit-planes at 1280 1024 resolution. all the above can be achieved without any hardware modification and without any increase in the speed of the pixel bus.
2 ? 9 table 2 ? 6. mode and bus width selection mode mux control register bits ? data bits per pixel bus sclk divide pixel latching mode 5 43210 per pixel ? width divide ratio latching sequence ? 0 # 1 0 1 1 0 1 8 8 1 1) vga7 ? vga0 0 1 0 0 0 0 1 4 4 1) p0 2) p1 3) p2 4) p3 1 0 1 0 0 0 1 1 8 8 1) p0 2) p1 8) p7 . . . 1 0 1 0 0 1 0 1 16 16 1) p0 2) p1 16) p15 . . . 0 1 0 0 1 1 1 32 32 1) p0 2) p1 32) p31 . . . 0 1 0 1 0 0 2 4 2 1) p1 ? p0 2) p3 ? p2 0 1 0 1 0 1 2 8 4 1) p1 ? p0 2) p3 ? p2 3) p5 ? p4 4) p7 ? p6 2 0 1 0 1 1 0 2 16 8 1) p1 ? p0 2) p3 ? p2 8) p15 ? p14 . . . 0 1 0 1 1 1 2 32 16 1) p1 ? p0 2) p3 ? p2 16) p31 ? p30 . . . ? bits 6 and 7 are don ? t care bits. ? this is the number of bits of pixel port (or vga port in mode 1) information used as color data for each displayed pixel, often referred to as the number of bit planes. this may be color palette address data (modes 0 ? 5) or dac data (mode 6). the sclk divide ratio is the number used for the output clock selection register. it indicates the number of pixels per bus load, or the number of pixels associated with each sclk pulse. for example, with a 32-bit pixel bus width and 8 bit-planes, 4 pixels comprise each bus load. the sclk divide ratio is not automatically set by mode selection, but must be written to the output clock selection register. ? for each operating mode, the pixel latching sequence indicates the sequence in which pixel port or vga port data are latched into the device. the latching sequence is initiated by a rising edge on sclk. for modes in which multiple groups of data are latched, the sclk rising edge latches all the groups, and the pixel clock shifts them out starting with the low-numbered group. for example, in mode 3 with a 16-bit pixel bus width, the rising edge of sclk latches all the data groups, and the pixel clock shifts them out in the order p3 ? p0, p7 ? p4, p11 ? p8, and p15 ? 12 terminals. # mode 0 is the vga pass-through mode. note 1: although leaving unused pins floating does not adversely affect device operation, tying unused pins to ground lowers power consumption and, thus, is recommended.
2 ? 10 table 2 ? 6. mode and bus width selection (continued) mode mux control register bits ? data bits per pixel bus sclk divide pixel latching mode 5 43210 per pixel ? width divide ratio latching sequence ? 0 1 1 0 0 0 4 4 1 1) p3 ? p0 0 1 1 0 0 1 4 8 2 1) p3 ? p0 2) p7 ? p4 3 0 1 1 0 1 0 4 16 4 1) p3 ? p0 2) p7 ? p4 3) p11 ? p8 4) p15 ? p12 0 1 1 0 1 1 4 32 8 1) p3 ? p0 2) p7 ? p4 8) p31 ? p28 0 1 1 1 0 0 8 8 1 1) p7 ? p0 0 1 1 1 0 1 8 16 2 1) p7 ? p0 2) p15 ? p8 4 0 1 1 1 1 0 8 32 4 1) p7 ? p0 2) p15 ? p8 3) p23 ? p16 4) p31 ? p24 ? bits 6 and 7 are don ? t care bits. ? this is the number of bits of pixel port (or vga port in mode 1) information used as color data for each displayed pixel, often referred to as the number of bit-planes. this may be color palette address data (modes 0 ? 5) or dac data (mode 6). the sclk divide ratio is the number used for the output clock selection register. it indicates the number of pixels per bus load, or the number of pixels associated with each sclk pulse. for example, with a 32-bit pixel bus width and 8 bit-planes, four pixels comprise each bus load. the sclk divide ratio is not automatically set by mode selection, but must be written to the output clock selection register. ? for each operating mode, the pixel latching sequence indicates the sequence in which pixel port or vga port data are latched into the device. the latching sequence is initiated by a rising edge on sclk. for modes in which multiple groups of data are latched, the sclk rising edge latches all the groups, and the pixel clock shifts them out starting with the low-numbered group. for example, in mode 3 with a 16-bit pixel bus width, the rising edge of sclk latches all the data groups, and the pixel clock shifts them out in the order p3 ? p0, p7 ? p4, p11 ? p8, p15 ? p12. note 1: although leaving unused pins floating does not adversely affect device operation, tying unused pins to ground lowers power consumption and, thus, is recommended.
2 ? 11 table 2 ? 6. mode and bus width selection (continued) mode mux control register bits ? data bits per pixel bus sclk divide pixel latching mode 5 43210 per pixel ? width divide ratio latching sequence ? 5 # 0 1 1 1 1 1 4 16 4 nflag = 0: 1) p3 ? p0 2) p11 ? p8 3) p19 ? p16 4) p27 ? p24 nflag = 1: 1) p7 ? p4 2) p15 ? p12 3) p23 ? p20 4) p31 ? p28 6 || see table 2 ? 7 and table 2 ? 8 ? bits 6 and 7 are don ? t care bits. ? this is the number of bits of pixel port (or vga port in mode 1) information used as color data for each displayed pixel, often referred to as the number of bit-planes. this may be color palette address data (modes 0 ? 5) or dac data (mode 6). the sclk divide ratio is the number used for the output clock selection register. it indicates the number of pixels per bus load, or the number of pixels associated with each sclk pulse. for example, with a 32-bit pixel bus width and 8 bit-planes, 4 pixels comprise each bus load. the sclk divide ratio is not automatically set by mode selection, but must be written to the output clock selection register. ? for each operating mode, the pixel latching sequence indicates the sequence in which pixel port or vga port data are latched into the device. the latching sequence is initiated by a rising edge on sclk. for modes in which multiple groups of data are latched, the sclk rising edge latches all the groups, and the pixel clock shifts them out starting with the low-numbered group. for example, in mode 3 with a 16-bit pixel bus width, the rising edge of sclk latches all the data groups, and the pixel clock shifts them out in the order p3 ? p0, p7 ? p4, p11 ? p8, p15 ? p12. # mode 5 is special nibble mode, the only mode in which the pixel bus width is not equal to the actual physical width, in bits, of the pixel bus. in this mode, the pixel bus is physically 32 bits wide; depending on the value of sflag/nflag, either the upper or lower nibble of each of the four physical bytes is selected to comprise the 16 bits of pixel data (equal to four 4-bit pixels). || mode 6 is true color mode, in which 24 bits of color information are transferred directly from the pixel port to the dacs; overlay is implemented with the remaining eight bits of the pixel bus. the distribution of pixel port data to the dacs is as follows: p31 ? p24 are passed to the blue dac, p23 ? p16 are passed to the green dac, and p15 ? p8 are passed to the red dac. p7 ? p0 generate overlay data; this operation can be disabled by either grounding p7 ? p0 or by clearing the read mask (see subsection 2.4.6). note 1: although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground lowers power consumption and, thus, is recommended. 2.4.1 vga pass-through mode mode 0, the vga pass-through mode, emulates the vga modes of most personal computers. the advantage of this mode is that the TLC34076 can take data presented on the feature connectors of most vga-compatible pc systems into the device on a separate bus, thus requiring no external multiplexing. this feature is particularly useful for systems in which the existing graphics circuitry is on the motherboard. in this instance, it enables implementation of a drop-in graphics card that maintains compatibility with all existing software by using the on-board vga circuitry but routing the emerging bit-plane data through the TLC34076. this is the default mode at power-up. when the vga pass-through mode is selected after the device is powered up, the clock selection register, the general control register, and the pixel read mask register are set to their default states automatically.
2 ? 12 since this mode is designed with the feature connector philosophy, all the timing is referenced to clk0, which is used by default for the vga pass-through mode. for all the other normal modes, clk0 ? clk3 are the oscillator sources for dotclk, vclk, and sclk; all the data and control timing is referenced to sclk. 2.4.2 multiplexing modes in addition to the vga pass-through mode, there are four multiplexing modes available, all of which are referred to as normal modes. in each normal mode, a pixel bus width of 8, 16, or 32 bits may be used. modes 1, 2, and 3 also support a pixel bus width of 4 bits. data should always be presented on the least significant bits of the pixel bus. for example, when a 16-bit-wide pixel bus is used and there are 8 bits per pixel, each 8-bit pixel should be presented on p0 ? p7. all the unused pixel bus terminals should be connected to gnd. mode 1 uses a single bit-plane to address the color palette. the pixel port bit is fed into bit 0 of the palette address, with the seven high-order address bits being defined by the palette page register (see subsection 2.2.3). this mode has uses in high-resolution monochrome applications such as desktop publishing. this mode allows the maximum amount of multiplexing (a 32:1 ratio), thus giving a pixel bus rate of only 4 mhz at a screen resolution of 1280 1024 pixels. although only a single-bit plane is used, alteration of the palette page register at the line frequency allows 256 different colors to be displayed simultaneously with two colors per line. mode 2 uses two bit-planes to address the color palette. the 2 bits are fed into the low-order address bits of the palette with the six high-order address bits being defined by the palette page register. this mode allows a maximum divide ratio of 16:1 on the pixel bus and is a 4-color alternative to mode 1. mode 3 uses four bit-planes to address the color palette. the 4 bits are fed into the low-order address bits of the palette with the four high-order address bits being defined by the palette page register. this mode provides 16 pages of 16 colors and can be used at sclk divide ratios of 1:8. mode 4 uses eight bit-planes to address the color palette. since all 8 bits of palette address are specified from the pixel port, the page register is not used. this mode allows dot-clock-to-sclk ratios of 1:1 (8-bit bus), 2:1 (16-bit bus) or 4:1 (32-bit bus). therefore, in a 32-bit configuration, a 1024 768 pixel screen can be implemented with an external data rate of only 16 mhz. all normal multiplexing modes can support little-endian (default) and big-endian data formats at the pixel bus inputs (see subsection 2.6.1). 2.4.3 special nibble mode mode 5 is the special nibble mode, which is enabled when the general-control register snm bit 3 is set to 1 and the general-control register ssrt bit 2 is cleared to 0 (see section 2.11). when the special nibble mode is enabled, it takes precedence over the other modes, and the mux control register setup is ignored. the sflag/nflag input is then used as a nibble flag to indicate which nibble of each byte holds the pixel data. special-nibble mode is a variation of the 4-bit pixel mode with a 16-bit pixel width. all 32 inputs (p0 p31) are connected as four bytes, but the 16-bit data bus is composed of either the lower or upper nibble of each of the four bytes (for more detailed information, see subsection 2.9.2). since this mode uses four bit-planes for each pixel, they are fed into the low-order address bits of the palette, with the 4 high-order address bits being defined by the palette page register (see subsection 2.2.3). 2.4.4 true-color modes mode 6 is the true-color mode in which 24, 16, or 15 bits of data are transferred from the pixel port directly to the dacs, but with the same amount of pipeline delay as the overlay data and the control signals (blank and sync). depending on which true-color mode is selected, overlay is provided by utilizing the remaining bits of the pixel bus to address the palette ram (see tables 2 ? 6 and 2 ? 7). this results in a 24-bit ram output that is then used as overlay information to the dacs. when all of the overlay inputs are cleared to 0, no overlay information is displayed. when a nonzero value is input, the color palette ram is addressed and the resulting data is then fed through to the dacs and receives priority over the true-color data.
2 ? 13 table 2 ? 7. true-color modes mode mux control register bits ? data bits per pixel bus sclk divide overlay bits per pixel latching mode 5 43210 bits per pixel ? bus width divide ratio bits per pixel (4) latching sequence ? 6 # 6a 0 0 1 0 0 0 15 16 1 1 1) p15 ? p0 6b 0 0 1 0 0 1 16 16 1 n/a 1) p15 ? p0 6c 0 0 1 0 1 0 15 32 2 1 1) p15 ? p0 2) p31 ? p16 6d 0 0 1 0 1 1 16 32 2 n/a 1) p15 ? p0 2) p31 ? p16 6e 0 0 1 1 1 0 24 32 1 8 1) p31 ? p0 6f 0 0 1 1 0 1 24 32 1 8 1) p31 ? p0 ? bits 6 and 7 are don ? t care bits. ? this is the number of bits of pixel port (or vga port in mode 1) information used as color data for each displayed pixel, often referred to as the number of bit-planes. this may be color palette address data (modes 0 ? 5) or dac data (mode 6). the sclk divide ratio is the number used for the output clock selection register. it indicates the number of pixels per bus load, or the number of pixels associated with each sclk pulse. for example, with a 32-bit pixel bus width and eight bit-planes, four pixels comprise each bus load. the sclk divide ratio is not automatically set by mode selection, but must be written to the output clock selection register. ? for each operating mode, the pixel latching sequence indicates the sequence in which pixel port or vga port data are latched into the device. the latching sequence is initiated by a rising edge on sclk. for modes in which multiple groups of data are latched, the sclk rising edge latches all the groups, and the pixel clock shifts them out starting with the low-numbered group. for example, in mode 6d with a 32-bit pixel bus width, the rising edge of sclk latches all the data groups, and the pixel clock shifts them out in the order p15 ? p0 and p31 ? p16. # mode 6 is true-color mode in which 24 bits of color information are transferred directly from the pixel port to the dacs; overlay is implemented with the remaining 8 bits of the pixel bus. the distribution of pixel port data to the dacs is as follows: p31 ? p24 are passed to the blue dac, p23 ? p16 are passed to the green dac, and p15 ? p8 are passed to the red dac. p7 ? p0 generate overlay data; this operation can be disabled by either grounding p7 ? p0 or by clearing the read mask (see subsection 2.4.6). note 1: although leaving unused terminals floating does not adversely affect device operation, tying unused terminals to ground lowers power consumption and is recommended.
2 ? 14 mode 6a is the targa compatible (5-5-5) true-color mode. in this 16-bit mode, there are 5 bits of red, 5 bits of green, 5 bits of blue, and an additional overlay bit (see table 2 ? 8 for the bit definitions). table 2 ? 8. true-color bit definitions little endian pixel bus p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 data bus d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 a b c o r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 d r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 e o7 o6 o5 o4 o3 o2 o1 o0 r7 r6 r5 r4 r3 r2 r1 r0 f b7 b6 b5 b4 b3 b2 b1 b0 g7 g6 g5 g4 g3 g2 g1 g0 pixel bus p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 data bus d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a o r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 b r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 c o r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 d r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 e g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 f r7 r6 r5 r4 r3 r2 r1 r0 o7 o6 o5 o4 o3 o2 o1 o0 big endian pixel bus p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 data bus d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a b c b0 b1 b2 b3 b4 g0 g1 g2 g3 g4 r0 r1 r2 r3 r4 o d b0 b1 b2 b3 b4 g0 g1 g2 g3 g4 g5 r0 r1 r2 r3 r4 e b0 b1 b2 b3 b4 b5 b6 b7 g0 g1 g2 g3 g4 g5 g6 g7 f o0 o1 o2 o3 o4 o5 o6 o7 r0 r1 r2 r3 r4 r5 r6 r7 pixel bus p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 data bus d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 a b0 b1 b2 b3 b4 g0 g1 g2 g3 g4 r0 r1 r2 r3 r4 o b b0 b1 b2 b3 b4 g0 g1 g2 g3 g4 g5 r0 r1 r2 r3 r4 c b0 b1 b2 b3 b4 g0 g1 g2 g3 g4 r0 r1 r2 r3 r4 o d b0 b1 b2 b3 b4 g0 g1 g2 g3 g4 g5 r0 r1 r2 r3 r4 e r0 r1 r2 r3 r4 r5 r6 r7 o0 o1 o2 o3 o4 o5 o6 o7 f g0 g1 g2 g3 g4 g5 g6 g7 b0 b1 b2 b3 b4 b5 b6 b7 mode 6b is the xga compatible (5-6-5) true-color mode. this 16-bit mode has 5 bits of red, 6 bits of green, and 5 bits of blue data. the overlay function is not enabled in this mode (see table 2 ? 8 for the exact bit definitions). mode 6c is a multiplexed version of mode 6a that allows two 16-bit targa-compatible words to be latched into the TLC34076 pixel port with one sclk. in this mode, the 16-bit word latched on pixel port inputs
2 ? 15 p0 ? p15 is executed first, while the word latched on p16 ? p31 is executed last. the user should program the sclk divide ratio in the output-clock selection register to divide by two (see table 2 ? 8 for the exact bit definitions). mode 6d is a multiplexed version of mode 6b that allows two 16-bit xga-compatible words to be latched into the TLC34076 pixel port with one sclk. in this mode, the 16-bit word latched on pixel port inputs p0 ? p15 is executed first, while the word latched on p16 ? p31 is executed last. the user should program the sclk divide ratio in the output-clock selection register to divide by 2 (see table 2 ? 8 for the bit definitions). mode 6e is a 24-bit true-color mode that features 8 bits of data for each color, as well as 8 bits of overlay information. the order in which the color and overlay fields appear in the 32-bit word are the reverse of mode 6f (see table 2 ? 8 for the bit definitions). mode 6f is the 24-bit true-color mode used on the TLC34076. it also features 8 bits of data for each color, as well as 8 bits of overlay information (see table 2 ? 8 for the bit definitions). since only 5 bits (6 bits for green in mode 6b and 6d) are provided for each color in the 16-bit true-color modes (6a ? 6d), the color data is internally shifted by the TLC34076 to the five msb positions (six msb positions for green in modes 6b and 6d) before being presented to the 3-color dacs. the remaining lower 3 bits (lower 2 bits for green in modes 6b and 6d) then clear to 0. when in true-color modes 6a or 6c, the internal palette page register fills the remaining seven msbs of overlay data (see subsection 2.2.3). this occurs in these modes because there is only 1 bit of overlay information presented in the true-color word. in order to enable the true-color data to the dacs, all 8 overlay bits must be reset to 0. this can be accomplished by either writing zeros to the internal palette page register and the overlay bit, or by writing zeros to the internal read mask (see subsection 2.4.6). when in true-color modes 6e or 6f, the data input only works in the 8-bit mode. in other words, when only 6 bits are to be used, the two lsb inputs for each color must be tied to gnd. however, the palette, which is used by the overlay input, is still governed by 8/6 -input terminal and the output multiplexer (mux) selects 8-bit data or 6-bit data accordingly. the 8/6 -input terminal is also valid in the other 16-bit modes as well. both little-endian (default) and big-endian data formats are supported by the true-color modes (see subsection 2.6.1 and table 2 ? 8 for more information). 2.4.5 multiplex control register the mux is controlled using the 8-bit mux control register. the bit fields of the register are in table 2 ? 6 and table 2 ? 7. as an example of how to use table 2 ? 6, suppose that the design goals specify a system with 8 data bits per pixel and the lowest possible sclk rate. table 2 ? 6 shows that, for non-vga pass-through operation, only mode 4 supports an 8-bit pixel depth. the lowest possible sclk rate within mode 4 is 1:4. this set of conditions are selected by writing the value 1eh to the mux control register. the pixel latching sequence column shows that, in this mode, pixel-input ports p7 ? p0 should be connected to the earliest displayed pixel plane, followed by p15 ? p8, p23 ? p16, and then p31 ? p24 as the last displayed pixel plane. assuming that vclk is programmed as dotclk/4, table 2 ? 5 shows that the 1:4 sclk ratio is selected by writing the value 12h to the output clock selection register. the special nibble mode should also be disabled (see subsections 2.9.2 and 2.11.2). when the mux control register is loaded with 2dh, the TLC34076 enters the vga pass-through mode which is the same condition as the default power-up mode. more details are given in subsection 2.5.4.
2 ? 16 2.4.6 read masking the read mask register enables or disables a pixel address bit from addressing the color palette ram. each palette address bit is logically anded with the corresponding bit from the read mask register before addressing the palette. this function is performed after the addition of the page register bits and, therefore, a zeroing of the read mask results in one unique palette location (location 0) and is not affected by the palette page register contents. note also that the read mask can zero the overlay data in the true-color modes. this is a handy way to disable the overlay (enable true-color data to the dacs) for a whole screen. 2.5 reset there are three ways to reset the TLC34076: ? power-on reset ? hardware reset ? software reset 2.5.1 power-on reset there is a power-on reset (por) circuit built into the TLC34076. this por works at power-on only. even though this circuitry is provided, it is still recommended for the user to design a hardware reset circuit to ensure the reset condition after power-up as described in subsection 2.5.2. once the voltage is stabilized, the default condition for all registers is the vga mode. when the TLC34076 is reset, the sclk and vclk counters are reset as well (see section 2.3 and subsection 2.5.4). 2.5.2 hardware reset the TLC34076 resets whenever rs3 ? rs0 = hhhh and a rising edge occurs on wr input. resetting of the TLC34076 is most reliable when many rising wr edges occur during the time rs=hhhh. this scheme (bursting wr strobes until the power supply voltage stabilizes) is suggested at power up when a hardware reset approach is used. the default reset condition is vga mode, and the values for each register are shown in subsection 2.5.4. also when the TLC34076 is reset, the sclk and vclk counters are reset (see section 2.3). 2.5.3 software reset whenever the mux control register is set for vga pass-through mode after power up, all registers are initialized accordingly. since vga pass-through mode is the default condition at power up and hardware reset, the act of selecting the vga pass-through mode through programming the mux control register is viewed as a software reset. therefore, whenever mux control register bits 5 ? 0 are set to 2dh, the TLC34076 initiates a software reset. this also resets the sclk and vclk counters (see section 2.3). this is referred to as a software reset, since it is typically initiated by software, unlike por or hardware resets.
2 ? 17 2.5.4 vga pass-through mode default conditions the value contained in each register after hardware or software reset is shown in table 2 ? 9. table 2 ? 9. vga pass-through mode default conditions register name default value mux control register 2dh input clock selection register 00h output clock selection register 3fh palette page register 00h general control register 03h pixel read mask register ffh palette address register xxh palette holding register xxh test register (pointing to color palette red value) 2.6 analog output specifications the dac outputs are controlled by current sources (three for iog and two each for ior and iob) as shown in figure 2 ? 6. in the normal case, there is a 7.5-ire (institute of radio engineers: predecessor to the ieee) difference between blank and black levels, which is shown in figure 2 ? 7. when a 0-ire pedestal is desired, it can be selected by resetting bit 4 of the general control register (see subsection 2.11.3). the video output for a 0-ire pedestal is shown in figure 2 ? 8. note: for a 75- ? doubly terminated load, the v ref = 1.235 v, r set = 523 ? , rs-343a levels and tolerances in recommended operating conditions are assumed. iog r l 15 pf g0 ? g7 blank (iog only) sync v aa figure 2 ? 6. equivalent circuit of the iog current output
2 ? 18 92.5 ire 40 ire 7.5 ire white black sync [ma] 26.67 9.05 7.62 0.00 [v] 1.000 0.340 0.286 0.000 [ma] 19.05 1.44 0.00 [v] 0.714 0.054 0.000 green red/blue blank figure 2 ? 7. 7.5-ire, 8-bit composite video output white black/ blank sync 100 ire [ma] 25.24 7.62 0.00 [v] 0.95 0.286 0.000 [ma] 17.62 0.00 [v] 0.66 0.000 green red/blue 43 ire pedestal figure 2 ? 8. 0-ire, 8-bit composite video output
2 ? 19 a resistor (r set ) is needed to connect fs adjust to gnd to control the magnitude of the full-scale video signal. the ire relationships in figures 2 ? 7 and 2 ? 8 are maintained regardless of the full-scale output current. the relationship between r set and the full-scale output current iog is: r set ( ? ) = k1 v ref (v) / iog (ma) the full-scale output current on ior and iob for a given r set is: ior, iob (ma) = k2 v ref (v) / r set ( ? ) where k1 and k2 are defined as: ire level iog ior, iob ire level 8-bit output 6-bit output 8-bit output 6-bit output 7.5-ire k1 = 11,294 k1 = 11,206 k2 = 8,067 k2 = 7,979 0-ire k1 = 10,684 k1 = 10,600 k2 = 7,462 k2 = 7,374 2.7 frame-buffer interface with little-endian and big-endian modes the TLC34076 provides two clock signals for controlling the frame-buffer interface. they are sclk and vclk. sclk can clock out data directly from the vram shift registers. split shift-register transfer functionality is also supported. vclk clocks and synchronizes control inputs like hsync , vsync , and blank . the pixel data presented at the inputs is latched at the rising edge of sclk in normal mode or the rising edge of clk0 in vga pass-through mode. control inputs hsync , vsync , and blank are sampled and latched at the falling edge of vclk in normal mode, while hsync , vsync , and vgablank are latched at the rising edge of clk0 in vga pass-through mode. both data and control signals are lined up at the dac outputs to the monitor through the internal pipeline delay, so external glue logic is not required. the outputs of the dacs are capable of directly driving a 37.5- ? load, as in the case of a doubly terminated 75- ? cable (see figures 2 ? 7 and 2 ? 8 for nominal output levels). the frame-buffer interface (pixel bus) supports both little-endian and big-endian data formats for all normal multiplexing and true-color modes of operation. the data-format mode select is controlled by general control register bit 6 (see section 2.11). when gcr bit 6 is cleared to 0 (default), the format is set to the little-endian mode. when gcr bit 6 is set to 1, the format is set to the big-endian mode. in a big-endian mode design the external vram data bus bits must be connected in reverse order to the TLC34076 pixel bus (i.e. d31 connected to p0, and d0 connected to p31, etc.). this ensures that the least significant channel always provides the first pixel to be displayed in the normal multiplexing modes. 2.8 hsync , vsync , and blank for the normal modes, hsync and vsync are active-low pulses, and they are passed through true/complement gates to the hsyncout and vsyncout outputs. the output polarities of hsyncout and vsyncout can be programmed through the general control register. however, for the vga pass-through mode, the polarities needed for monitors are already provided at the feature connector from which hsync and vsync are sourced, so the TLC34076 passes hsync and vsync through to hsyncout and vsyncout without polarity change. as described in section 2.3 and figures 2 ? 2 through 2 ? 5, the blank , hsync , and vsync inputs are sampled and latched on the falling edge of vclk in the normal modes, and they are latched on the rising edge of the clk0 input in the vga pass-through mode (see figure 3 ? 2 for the detailed timing).
2 ? 20 the hsync and vsync inputs are used for both the vga pass-through and normal modes. when the application uses both vga pass-through and normal modes, an external multiplexer is needed to select hsync and vsync between the vga pass-through mode and the normal mode. the muxout signal is designed for this purpose (see sections 2.10 and 2.11). the hsync , vsync , and blank signals have internal pipeline delays to align with the data at the dac outputs. due to the sample and latch timing delay, it is possible to have active sclk pulses after the blank input becomes active. the relationship between vclk and sclk and the internal vclk sample and latch delay need to be carefully reviewed and programmed (see section 2.3 and figures 2 ? 2 and 2 ? 3 for more details). as shown in figure 2 ? 6 for the iog dac output, active hsync and vsync signals turn off the sync current source (after the pipeline delay) independent of the blank signal level. in real applications, hsync and vsync should only be active (low) when blank is active (low). to alter the polarity of the hsyncout and vsyncout outputs in the normal modes, the mpu must set or clear the corresponding bits in the general control register (see subsection 2.11.1). again, these two bits affect only the normal modes, not the vga pass-through mode. these bits default to 1. 2.9 split shift register transfer vrams and special nibble mode the following paragraphs describe the operation of the split shift register when effecting a transfer from the vrams, and the use of the special nibble mode. the special nibble mode provides a variation of the 4-bit pixel mode with a 16-bit bus width. 2.9.1 split shift register transfer vrams the TLC34076 directly supports split shift register transfer (ssrt) vrams. in order to allow the vrams to perform a split shift-register transfer, an extra sclk cycle must be inserted during the blank sequence. this is initiated when the ssrt enable bit is set to 1, the snm bit is reset to 0 , and a rising edge on the sflag/nflag input terminal is detected. an sclk pulse is generated within 20 ns of the rising edge of the sflag/nflag signal. a minimum 15-ns high logic level duration is provided to satisfy all of the 15-ns vram requirements. by controlling the sflag/nflag rise time, the delay time from the rising edge of the vram trg signal to sclk can be satisfied. the relationship between the sclk, sflag/nflag, and blank signals is shown in figure 2-9. sclk input sflag/nflag register bit 2) (general control ssrt enable blank figure 2 ? 9. relationship between sflag/nflag, blank , and sclk when sflag/nflag is designed as an r-s latch set by split shift register transfer timing and reset by blank going high, the delay from blank high to sflag/nflag low cannot exceed one-half of a sclk cycle; otherwise, the sclk generation logic may fail.
2 ? 21 when the ssrt function is enabled but sflag/nflag is held low, sclk runs as if the ssrt function is disabled. the sflag/nflag input is not qualified by the blank signal and needs to be held low whenever an ssrt sclk pulse is not desired (see subsection 2.3.1 and figures 2 ? 2 through 2 ? 8 for more system details). 2.9.2 special nibble mode special nibble mode is enabled when the snm bit (bit 3 in the general control register) is set to 1 and the ssrt bit (bit 2 in the general control register) is reset to 0 (see section 2.11). the special nibble mode provides a variation of the 4-bit pixel mode with a 16-bit bus width. while all 32 inputs (p0 ? p31) are connected as four bytes, the 16-bit data bus is composed of the lower or upper nibble of each of the four bytes, depending on the level of the sflag/nflag input. the pixel data is distributed to the 16-bit data bus as shown in table 2 ? 10. table 2 ? 10. pixel data distribution in special nibble mode snm bit = 1, ssrt bit = 0 sflag/nflag = 1 sflag/nflag = 0 p7 ? p4 p15 ? p12 p23 ? p20 p31 ? p28 p3 ? p0 p11 ? p8 p19 ? p16 p27 ? p24 the sflag/nflag value is not latched by the TLC34076; therefore, it should stay at the same level during the whole active display period, changing levels only during the blank signal active time. (see to figure 2 ? 10, which is similar to figure 2 ? 2 except that the blank signal timing reference to sflag/nflag is explained). the sflag/nflag input has to meet the setup time and hold the data long enough to ensure that no pixel data is missed. caution: if pixel data are not held valid until both sclk and blank go low, the last few pixels can be missed.
2 ? 22 sampled load input sflag/nflag of pixel data latch first group of pixel data latch last group valid don ? t care valid (at its input pin) last group of pixel data sclk pixel data blank blank vclk notes: a. if the data is not held valid until sclk and blank both go low, the last few pixels could be missed. b. setup time to the next vclk falling edge after blank goes high must be met; otherwise, the first pixel data could be missed. group 2nd group 1st group 4th group 3rd group 5th (see note a) (see note b) figure 2 ? 10. sflag/nflag timing in special nibble mode special nibble mode operates at the line frequency when blank is active. however, the typical application of this mode is double frame buffers with pixel data width of 4 bits. while one frame buffer is being displayed on the monitor, the other frame buffer can accept new picture information. sflag/nflag indicates which frame buffer is being displayed. snm and ssrt must be mutually exclusive. unpredictable operation occurs when both the snm and ssrt bits are set to 1. the mux control register should be set up as shown in table 2 ? 6. however, the snm bit takes precedence over the other mux control register selections. in other words, when the mux control register is set up for another mode but special nibble mode is still enabled in the general control register, the input multiplex circuit takes whatever sclk divide ratio the mux control register specifies and performs the nibble operation causing operational failure. during special nibble mode, the input mux circuit latches all 8-bit inputs but only passes on the specified nibble. the specified nibble is stored in the four lsbs of the next register pipe after the input latch, and the four msbs are cleared to 0 in that register. the register pipe contents are then passed to the read mask block. with this structure, the palette page register still functions normally, providing good flexibility to users. when the general control register bit 3 = 0 and bit 2 = 0, both split shift-register transfers and the special nibble mode are disabled and the sflag/nflag input is ignored.
2 ? 23 2.10 muxout output muxout is a ttl-compatible output. it is software programmable and controls external devices. its typical application is to select the hsync and vsync inputs between the vga pass-through mode and the normal modes. this output is driven low at power up or when the vga pass-through mode is selected; at any other time it can be programmed to the desired polarity through the general control register bit 7. 2.11 general control register the general control register controls hsync and vsync polarity, split shift register transfer enabling, special nibble mode, little-endian and big-endian modes, sync control, the ones-accumulation clock source, and the vga pass-through indicator. the bit field definitions are given in table 2 ? 11: table 2 ? 11. general control register bit functions general control register bit function 7 6543210 function x x x x x x x 0 hsyncout is active-low x x x x x x x 1 hsyncout is active-high (default) x x x x x x 0 x vsyncout is active-low x x x x x x 1 x vsyncout is active-high (default) x x x x x 0 x x disable split shift register transfer (default) x x x x 0 1 x x enable split shift register transfer x x x x 0 x x x disable special nibble mode (default) x x x x 1 0 x x enable special nibble mode x x x 0 x x x x 0-ire pedestal (default) x x x 1 x x x x 7.5-ire pedestal x x 0 x x x x x disable sync (default) x x 1 x x x x x enable sync x 0 x x x x x x little-endian mode (default) x 1 x x x x x x big-endian mode 0 x x x x x x x muxout is low (default) 1 x x x x x x x muxout is high 2.11.1 hsyncout and vsyncout (bits 0 and 1) hsyncout and vsyncout polarity inversion is provided to allow indication to monitors of the current screen resolution. since the polarities for the vga pass-through mode are provided at the feature connector, the inputs to the TLC34076 already have right polarities for monitors, so the TLC34076 passes them through with pipeline delay (see section 2.8). these 2 bits work only in the normal modes, and the input horizontal and vertical syncs are active-low incoming pulses. these 2 bits default to 1 but can be changed by software. 2.11.2 split shift register transfer enable (ssrt) and special nibble mode enable (snm) (bits 2 and 3) section 2.9 provides a detailed description for ssrt and snm. 2.11.3 pedestal enable control (bit 4) bit 4 specifies whether a 0- or 7.5-ire blanking pedestal is to be generated on the video outputs. having a 0-ire blanking pedestal means that the black and blank levels are the same. ? 0 = 0-ire pedestal (default) ? 1 = 7.5-ire pedestal
2 ? 24 2.11.4 sync enable control (bit 5) bit 5 specifies whether or not sync information is to be output onto iog (see table 2 ? 11). bit settings are: ? 0 = disable sync (default) ? 1 = enable sync 2.11.5 little-endian and big-endian mode control (bit 6) bit 6 specifies either little-endain or big-endian data format for the pixel bus frame-buffer interface (see subsection 2.7.1). settings are : ? 0 = little endian (default) ? 1 = big endian 2.11.6 muxout (bit 7) bit 7 indicates to external circuitry that the device is running in vga pass-through mode. the muxout bit does not affect the operation of the device (see section 2.10). bit settings are: ? 0 = muxout is low (default in vga pass-through mode) ? 1 = muxout is high 2.12 test register there are three test functions provided in the TLC34076, and they are all controlled and monitored through the test register. the three test functions are: ? data flow check ? dac analog test ? screen integrity test the test register has two ports: one for a control word that is accessed by writing to the register location, and one for the data word that is accessed by reading from the register location. depending on the channel written in the control word, the data read presents the information for that channel. the control word is 3 bits long and occupies d2 ? d0 bit positions. it specifies which of the eight channels to inspect. table 2 ? 12 and state machine diagrams (see figure 2 ? 11) show how each channel is addressed. table 2 ? 12. test mode selection d2 d1 d0 channel 0 0 0 color palette red value 0 0 1 color palette green value 0 1 0 color palette blue value 0 1 1 identification code 1 0 0 ones-accumulation red value 1 0 1 ones-accumulation green value 1 1 0 ones-accumulation blue value 1 1 1 analog test
2 ? 25 011 010 001 000 110 101 100 111 id code rd rd rd rd reset blue green red rd rd rd red blue green rd data flow check dac analog test screen integrity test figure 2 ? 11. test-register control-word state diagrams 2.12.1 frame-buffer data flow test the TLC34076 provides a means to check all the data entering each dac but before the output mux 8/6 shift. when accessing these color channels, the data entering the dacs should be kept constant for the entire mpu read cycle. this can be done either by slowing down the dot clock or ensuring that the data is constant for a sufficiently long series of pixels. the value read is the data stored in the color palette location addressed by the data in the input mux. the read operation causes a post-increment to point to the next color channel, and the post-increment of blue wraps back to red as shown in the state diagram of figure 2 ? 11. for example, when bits d2 ? d0 are written as 001, then three successive reads are performed, and the values read out are green, blue, and red in this sequence. 2.12.2 identification (id) code the id code can be used as a software identification for different versions. the id code in the TLC34076 is static and can be read without consideration of the dot clock or video signals. to be user-friendly, the read post-increment applies to the id register as well. however, when the state machine goes into the color channel, it does not return to the id code unless the user writes 011 (binary) to bits d2, d1, and d0 again. if the test register was first written as 011 (binary) in bits d2, d1, and d0, then, when six successive reads are performed, the first value read is the id, and the last value read is the green. the id value defined for the TLC34076 is 76 (hex). 2.12.3 ones-accumulation screen integrity test a technique called ones accumulation can detect errors in fixed screen displays. this type of error detection is useful for system checkout and field diagnostics. each of the 256 24-bit words in the TLC34076 internal color palette ram is composed of three bytes, one each for the red, green, and blue components of the word. when bits d2 ? d0 are programmed with the appropriate binary value (see subsection 2.12.4), the TLC34076 monitors the corresponding color byte that is output by the color palette ram. for example, when bits d2 ? d0 are programmed with the value 100, the TLC34076 monitors the red byte. as the current frame is scanned, for each color palette ram word accessed, the designated color byte is checked to see how many 1 bits it contains, and this number is added to a temporary accumulator, the entire byte is checked, even when 6-bit mode is selected. for example, when the designated color byte contains the value 41h (0100 0001), then the value 2 is added to the temporary accumulator, as 41h contains two bits set at 1. this process is continued until an entire frame has been scanned; the same color byte is monitored for the entire frame. the temporary accumulator truncates any overflow above the value 255. due to circuit speed limitations, the ones accumulation is
2 ? 26 calculated at a speed of (dotclk frequency)/2. during the vertical retrace activated by a falling edge on the TLC34076 vsync input, the value in the temporary accumulator is transferred into the ones accumulation register, and then the temporary accumulator is reset to 0. the ones-accumulation register is updated only on the falling edge of vsync , not by any vertical sync pulses coded into the composite video signal. before the next frame scan begins, the TLC34076 automatically changes the value in bits d2 ? d0 so that the ones accumulation performed during the next frame scan is for a different color byte (see the screen integrity test state diagram of figure 2 ? 11). as long as the screen display remains fixed, the ones-accumulation value for a particular color byte should not change; when it does, an error has occurred. since ones accumulation is calculated at dotclk/2 rate, there is uncertainty as to whether it starts its accumulation on an odd or even pixel. regardless of whether the accumulation is performed on odd or even pixels, subsequent screens are accumulated starting at the same point every time, unless the part is reset or the dotclk source changes. 2.12.4 analog test an analog test compares the voltage amplitudes of the analog red-green-blue (rgb) outputs to each other and to a 145-mv reference. this enables the mpu to determine whether the crt monitor is connected to the analog rgb outputs or not and whether the dacs are functional. to perform an analog test, bits d2 ? d0 must be set to 111; d7 ? d4 bits are set as shown in table 2 ? 13. bit d3 contains the result of the analog test. the bit coding for the analog comparison of bits d2 ? d7 is shown in table 2 ? 14. table 2 ? 13. test register bit definitions for analog test bit definition read/write d7: red select read/write d6: green select read/write d5: blue select read/write d4: 145-mv reference select read/write d3: result read table 2 ? 14. bit coding for analog comparisons of bits d7 ? d4 d7 ? d4 operation if d3 = 1 if d3 = 0 0000 normal operation don ? t care don ? t care 1010 red dac compared to blue dac red > blue red < blue 1001 red dac compared to 145-mv reference red > 145 mv red < 145 mv 0110 green dac compared to blue dac green > blue green < blue 0101 green dac compared to 145-mv reference green > 145 mv green < 145 mv note 2: all the outputs have to be terminated to compare the voltage.
2 ? 27 figure 2 ? 12 is a schematic of the internal comparator circuitry for the analog comparison test. + ? ior or iog iob or 145 mv blank (internal signal) d c d3 q figure 2 ? 12. internal comparator circuitry for analog test the result of the analog comparison is strobed into bit d3 at the falling edge of an internal signal derived from the input blank signal. in order to have stable inputs to the comparator, the dac should be set to a constant level between syncs. for normal operation, the data flow check, and the screen integrity test, bits d7 ? d4 must be set to 0.
2 ? 28
3 ? 1 3 electrical specifications 3.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage, v dd (see note 1) 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i ? 0.5 v to v dd + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog output short-circuit duration to any power supply or common unlimited . . . . . . . . operating free-air temperature range, t a: TLC34076c 0 c to 70 c . . . . . . . . . . . . . . . . . TLC34076m ? 55 c to 125 c . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . junction temperature, t j 175 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . case temperature for 10 seconds t c : fn and ga package 260 c . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to the gnd terminal. 3.2 recommended operating conditions min nom max unit v dd supply voltage 4.75 5 5.25 v v ref reference voltage 1.15 1.235 1.26 v v ih high-level input voltage ttl inputs 2.4 v dd +0.5 v v il low-level input voltage ttl inputs 0.8 v v id differential input voltage ecl inputs 0.6 6 v v ic common-mode input voltage ecl inputs 2.85 3.15 v dd ? 0.5 v r l output load resistance 37.5 ? r set fs adjust resistor 523 ? t a o p erating free air tem p erature TLC34076c 0 70 c t a operating free - air temperature TLC34076m ? 55 125 c
3 ? 2 3.3 electrical characteristics 3.3.1 electrical characteristics for TLC34076c over operating free-air temperature range parameter test conditions min typ ? max unit v oh high-level output voltage i oh = ? 800 a 2.4 v v lllttlt d0 ? d7, muxout , vclk i ol = 3.2 ma 0.4 v v ol low-level output voltage hsyncout, vsyncout i ol =15ma 0.4 v sclk i ol =18ma 0.4 i ih high level in p ut current ttl inputs v i = 2.4 v 1 a i ih high - level input current ecl inputs v i =4v 1 a i il low level in p ut current ttl inputs v i = 0.8 v ? 1 a i il low - level input current ecl inputs v i = 0.4 v ? 1 a TLC34076-85 450 pseudo-color TLC34076-110 v dd = 5 v, 475 mode TLC34076-135 dd , see note 2 535 i dd suppl y TLC34076-170 525 ma i dd y current TLC34076-85 475 ma true-color TLC34076-110 v dd = 5 v, 475 mode TLC34076-135 dd , see note 2 475 TLC34076-170 475 i oz high-impedance-state output current 10 a c i in p ut ca p acitance ttl inputs f = 1 mhz, v i = 2.4 v 4 p f c i input capacitance ecl inputs f = 1 mhz, v i =4v 4 pf ? all typical values are at v dd = 5 v, t a = 25 c. note 2: i dd is measured with the dot clock running at the maximum specified frequency, sclk frequency = dotclk frequency/4, and the palette ram loaded with full-range toggling patterns (00h/00h/ffh/ffh/00h/ 00h/ffh/ffh/ . . .). pseudo-color mode is also known as color indexing mode.
3 ? 3 3.3.2 electrical characteristics for TLC34076m over operating free-air temperature range parameters test conditions min typ ? max unit v oh high-level output voltage i oh = ? 800 a, v dd = 4.75 v 2.4 v d0 ? d7, muxout , vclk i ol = 3.2 ma, v dd = 4.75 v 0.4 v ol low-level output voltage hsyncout, vsyncout i ol = 15 ma, v dd = 4.75 v 0.4 v sclk i ol = 18 ma, v dd = 4.75 v 0.4 i ih high level in p ut current ttl inputs v i = 2.4 v, v dd = 5.25 v 10 a i ih high - level input current ecl inputs v i =4v, v dd = 5.25 v 10 a i il low level in p ut current ttl inputs v i = 0.8 v, v dd = 5.25 v ? 10 a i il low - level input current ecl inputs v i = 0.8 v, v dd = 5.25 v ? 10 a i dd suppl y pseudo-color mode TLC34076m-135 v dd = 5 v, 535 ma i dd y current true-color mode TLC34076m-135 dd , see note 2 475 ma i oz high-impedance-state output current v dd = 5.25 v 10 25 a c i in p ut ca p acitance ttl inputs f = 1 mhz, v i = 2.4 v 4 p f c i input capacitance ecl inputs f = 1 mhz, v i =4v 4 pf ? all typical values are at v dd = 5 v, t a = 25 c. note 2: i dd is measured with the dot clock running at the maximum specified frequency, sclk frequency = dotclk frequency/4, and the palette ram loaded with full-range toggling patterns (00h/00h/ffh/ffh/00h/ 00h/ffh/ffh/ . . .). pseudo-color mode is also known as color-indexing mode.
3 ? 4 3.4 operating characteristics the following tables outline the operating characteristics for the TLC34076c and TLC34076m. 3.4.1 operating characteristics for TLC34076c over recommended ranges of supply voltage and operating free-air temperature parameter test conditions min typ max unit resolution (each dac) 8/6 high 8 bits resolution (each dac) 8/6 low 6 bits e l end-point linearity error 8/6 high 1 lsb e l y (each dac) 8/6 low 1/4 lsb e d differential linearity error 8/6 high 1 lsb e d error (each dac) 8/6 low 1/4 lsb gray-scale error 5% white level relative to blank 17.69 19.05 20.4 white level relative to black (7.5 ire only) 16.74 17.62 18.5 ma black level relative to blank (7.5 ire only) 0.95 1.44 1.9 output current blank level on ior, iob 0 5 50 a (see note 4) blank level on iog (with sync enabled) 6.29 7.6 8.96 ma sync level on iog (with sync enabled) 0 5 50 a one lsb (8/6 high) 69.1 a one lsb (8/6 low) 276.4 a dac-to-dac matching outputs 2% 5% dac-to-dac crosstalk ? 20 db v oc output compliance voltage ? 1 1.2 v v ref voltage reference output voltage 1.15 1.235 1.26 v z o output impedance 50 k ? c o output capacitance f = 1 mhz, i out = 0 13 pf clock and data feedthrough ? 20 db glitch impulse (see note 3) 50 pv-s normal mode 1 sclk + 9 dotclk vga pass-through mode 7.5 dotclk notes: 3. glitch impulse does not include clock and data feedthrough. the ? 3-db test bandwidth is twice the clock rate. 4. unless otherwise specified, test conditions for rs343-a video signals are those listed in the recommended operating conditions, using external voltage reference v ref = 1.235 v and r set = 523 ? . when using the internal voltage reference, r set may need to be adjusted to meet these limits.
3 ? 5 3.4.2 operating characteristics for TLC34076m over recommended ranges of supply voltage and operating free-air temperature parameter test conditions min typ ? max unit resolution (each dac) 8/6 high 8 bits resolution (each dac) 8/6 low 6 bits e l end-point linearity error 8/6 high 1 lsb e l y (each dac) 8/6 low 1/4 lsb e d differential linearit y error 8/6 high 1 lsb e d y (each dac) 8/6 low 1/4 lsb gray-scale error 5% white level relative to blank 17.69 19.05 20.4 white level relative to black (7.5 ire only) 16.74 17.62 18.5 ma black level relative to blank (7.5 ire only) 0.95 1.44 1.9 i o output current blank level on ior, iob ? 50 5 50 a i o (see note 4) blank level on iog (with sync enabled) 6.29 7.6 8.96 ma sync level on iog (with sync enabled) ? 50 5 50 a one lsb (8/6 high) 69.1 a one lsb (8/6 low) 276.4 a dac-to-dac matching outputs 2% 5% dac-to-dac crosstalk ? 20 db v oc output compliance voltage ? 0.4 1.2 v v ref voltage reference output voltage 1.1 1.235 1.3 v z o output impedance 50 k ? c o output capacitance f = 1 mhz, i o = 0 13 pf clock and data feedthrough ? 20 db glitch impulse (see note 3) 50 pv-s pi p eline delay normal mode 1 sclk + 9 dot clock p eriods pipeline delay vga pass-through mode 7.5 dot clock periods ? all typical values are at v dd = 5 v, t a = 25 c. notes: 3. glitch impulse does not include clock and data feedthrough. the ? 3-db test bandwidth is twice the clock rate. 4. unless otherwise specified, test conditions for rs343-a video signals are those listed in the recommended operating conditions, using external voltage reference v ref = 1.235 v and r set = 523 ? . when using the internal voltage reference, r set may need to be adjusted to meet these limits.
3 ? 6 3.5 timing requirements the following tables outline the timing requirements for the TLC34076c and TLC34076m. 3.5.1 timing requirements for TLC34076c over recommended ranges of supply voltages and operating temperature (see note 5) -85 -110 unit min max min max unit dotclk frequency 85 110 mhz clk0 frequency for vga pass-through mode 85 85 mhz t cycle time clk0 clk3 (see figure 3 2) ttl 11.8 9.1 ns t cyc cycle time , clk0 ? clk3 (see figure 3 ? 2) ecl 11.8 9.1 ns t su1 setup time, rs0 ? rs3 valid before rd or wr (see figure 3 ? 1) 10 10 ns t h1 hold time, rs0 ? rs3 valid after rd or wr low (see figure 3 ? 1) 10 10 ns t su2 setup time, d0 ? d7 valid before wr (see figure 3 ? 1) 35 35 ns t h2 hold time, d0 ? d7 valid after wr high (see figure 3 ? 1) 0 0 ns t su3 setup time, vga0 ? vga7 and hsync , vsync , and vgablank valid before clk0-clk3 (see figure 3 ? 2) 2 2 ns t h3 hold time, vga0 ? vga7 and hsync , vsync , and vgablank valid after clk0 high (see figure 3 ? 2) 2 2 ns t su4 setup time, p0 ? p31 valid before sclk (see figure 3 ? 2) 2 2 ns t h4 hold time, p0 ? p31 valid after sclk high (see figure 3 ? 2) 5 5 ns t su5 setup time, hsync , vsync , and blank valid before vclk low (see figure 3 ? 2) 5 5 ns t h5 hold time, hsync , vsync , and blank valid after vclk (see figure 3 ? 2) 2 2 ns t w1 pulse duration, rd or wr low (see figure 3 ? 1) 50 50 ns t w2 pulse duration, rd or wr high (see figure 3 ? 1) 30 30 ns t 3 pulse duration clk0 clk3 high (see figure 3 2) ttl 4 3.5 ns t w3 pulse duration , clk0 ? clk3 high (see figure 3 ? 2) ecl 4 3.5 ns t 4 pulse duration clk0 clk3 low (see figure 3 2) ttl 4 3.5 ns t w4 pulse duration , clk0 ? clk3 low (see figure 3 ? 2) ecl 4 3.5 ns t w5 pulse duration, sflag/nflag high (see note 6 and figure 3 ? 3) 30 30 ns notes: 5. ttl input signals are 0 to 3 v with less than 3 ns rise/fall time between the 10% and 90% levels, unless otherwise specified. ecl input signals are v dd ? 1.8 v to v dd ? 0.8 v with less than 2 ns rise/fall time between the 20% and 80% levels. for input and output signals, timing reference points are at the 10% and 90% signal levels. analog output loads are less than 10 pf. d0 ? d7 output loads are less than 50 pf. all other output loads are less than 50 pf, unless otherwise specified. 6. this parameter applies when the split shift ? register transfer (ssrt) function is enabled (see subsection 2.9.1 for details).
3 ? 7 3.5.1 timing requirements for TLC34076c over recommended ranges of supply voltages and operating temperature (see note 5) (continued) -135 -170 unit min max min max unit dotclk frequency 135 170 mhz clk0 frequency for vga pass-through mode 85 85 mhz t clock cycle time clk0 clk3 (see figure 3 2) ttl 7.4 7.4 ns t cyc clock cycle time , clk0 - clk3 (see figure 3 ? 2) ecl 7.4 5.8 ns t su1 setup time, rs0 ? rs3 valid before rd or wr (see figure 3 ? 1) 10 10 ns t h1 hold time, rs0 ? rs3 valid after rd or wr low (see figure 3 ? 1) 10 10 ns t su2 setup time, d0 ? d7 valid before wr (see figure 3 ? 1) 35 35 ns t h2 hold time, d0 ? d7 valid after wr high (see figure 3 ? 1) 0 0 ns t su3 setup time, vga0 ? vga7, hsync , vsync , and vgablank valid before clk0 (see figure 3 ? 2) 2 2 ns t h3 hold time, vga0 ? vga7, hsync , vsync , and vgablank valid after clk0 high (see figure 3 ? 2) 2 2 ns t su4 setup time, p0 ? p31 valid before sclk (see figure 3 ? 2) 0 0 ns t h4 hold time, p0 ? p31 valid after sclk high (see figure 3 ? 2) 5 5 ns t su5 setup time, hsync , vsync , and blank valid before vclk low (see figure 3 ? 2) 5 5 ns t h5 hold time, hsync , vsync , and blank valid after vclk low (see figure 3 ? 2) 2 2 ns t w1 pulse duration, rd or wr low (see figure 3 ? 1) 50 50 ns t w2 pulse duration, rd or wr high (see figure 3 ? 1) 30 30 ns t 3 pulse duration clk0 clk3 high (see figure 3 2) ttl 3 3 ns t w3 pulse duration , clk0 ? clk3 high (see figure 3 ? 2) ecl 3 2.5 ns t 4 pulse duration clk0 clk3 low (see figure 3 2) ttl 3 3 ns t w4 pulse duration , clk0 ? clk3 low (see figure 3 ? 2) ecl 3 2.5 ns t w5 pulse duration, sflag/nflag high (see note 6 and figure 3 ? 3) 30 30 ns notes: 5. ttl input signals are 0 to 3 v with less than 3 ns rise/fall time between the 10% and 90% levels, unless otherwise specified. ecl input signals are v dd ? 1.8 v to v dd ? 0.8 v with less than 2 ns rise/fall time between the 20% and 80% levels. for input and output signals, timing reference points are at the 10% and 90% signal levels. analog output loads are less than 10 pf. d0 ? d7 output loads are less than 50 pf. all other output loads are less than 50 pf, unless otherwise specified. 6. this parameter applies when the split shift-register transfer (ssrt) function is enabled (see subsection 2.9.1 for details).
3 ? 8 3.5.2 timing requirements for TLC34076m over recommended ranges of supply voltages and operating temperature (see note 5) min nom max unit dot-clock frequency 135 mhz clk0 frequency for vga pass-through mode 85 mhz t cycle time clk0 clk3 (see figure 3 2) ttl 7.4 ns t c cycle time , clk0 ? clk3 (see figure 3 ? 2) ecl 7.4 ns t su1 setup time, rs0 ? rs3 valid before rd or wr (see figure 3 ? 1) 10 ns t h1 hold time, rs0 ? rs3 valid after rd or wr low (see figure 3 ? 1) 10 ns t su2 setup time, d0 ? d7 valid before wr (see figure 3 ? 1) 35 ns t h2 hold time, d0 ? d7 valid after wr high (see figure 3 ? 1) 0 ns t su3 setup time, vga0 ? vga7 and hsync , vsync , and vgablank valid before clk0-clk3 (see figure 3 ? 2) 2 ns t h3 hold time, vga0 ? vga7 and hsync , vsync , and vgablank valid after clk0 high (see figure 3 ? 2) 2 ns t su4 setup time, p0 ? p31 valid before sclk (see figure 3 ? 2) 0 ns t h4 hold time, p0 ? p31 valid after sclk high (see figure 3 ? 2) 8 ns t su5 setup time, hsync , vsync , and blank valid before vclk (see figure 3 ? 2) 5 ns t h5 hold time, hsync , vsync , and blank valid after vclk low (see figure 3 ? 2) 2 ns t w1 pulse duration, rd or wr low (see figure 3 ? 1) 50 ns t w2 pulse duration, rd or wr high (see figure 3 ? 1) 30 ns t 3 pulse duration clk0 clk3 high (see figure 3 2) ttl 3 ns t w3 pulse duration , clk0 ? clk3 high (see figure 3 ? 2) ecl 3 ns t 4 pulse duration clk0 clk3 low (see figure 3 2) ttl 3 ns t w4 pulse duration , clk0 ? clk3 low (see figure 3 ? 2) ecl 3 ns t w5 pulse duration, sflag/nflag high (see note 6 and figure 3 ? 3) 30 ns ? all typical values are at v dd = 5 v, t a = 25 c. notes: 5. ttl input signals are 0 to 3 v with less than 3 ns rise/fall time between the 10% and 90% levels, unless otherwise specified. ecl input signals are v dd ? 1.8 v to v dd ? 0.8 v with less than 2 ns rise/fall time between the 20% and 80% levels. for input and output signals, timing reference points are at the 10% and 90% signal levels. analog output loads are less than 10 pf. d0 ? d7 output loads are less than 50 pf. all other output loads are less than 50 pf, unless otherwise specified. 6. this parameter applies when the split shift register transfer (ssrt) function is enabled (see subsection 2.9.1 for details).
3 ? 9 3.6 switching characteristics for TLC34076c and TLC34076m over recommended ranges of supply voltages and operating temperature parameter -85 -110 unit parameter min typ ? max min typ ? max unit sclk frequency (see note 7) 85 85 mhz vclk frequency 85 85 mhz t en enable time, rd low to d0 ? d7 valid (see figure 3 ? 1) 40 40 ns t dis disable time, rd high to d0 ? d7 disabled (see figure 3 ? 1) 17 17 ns t v valid time, d0 ? d7 valid after rd high (see figure 3 ? 1) 5 5 ns t plh propagation delay, sflag/nflag high to sclk (see note 8 and figure 3 ? 3) 0 20 0 20 ns t d1 delay time, rd low to d0 ? d7 starting to turn on (see figure 3 ? 1) 5 5 ns t d2 delay time, selected input clock high/low to dotclk (internal signal) high/low (see figure 3 ? 2) 7 7 ns t d3 delay time, dotclk high/low to vclk high/low (see figure 3 ? 2) 6 6 ns t d4 delay time, vclk high/low to sclk high/low (see note 9 and figure 3 ? 2) 0 5 0 5 ns t d5 delay time, dotclk high/low to sclk high/low (see figure 3 ? 2) 8 8 ns t d6 delay time, dotclk high to ior/iog/iob active (analog output delay time) (see note 10 and figure 3 ? 2) 20 20 ns t d7 analog output settling time (see note 11 and figure 3 ? 2) 8 6 ns t d8 delay time, dotclk high to hsyncout and vsyncout valid (see figure 3 ? 2) 5 3 ns t w6 pulse duration, sclk high (see note 12 and figure 3 ? 3) 15 55 15 55 ns t r rise time at hsyncout analog output (see note 13 and figure 3 ? 2) 2 2 ns analog output skew 0 2 0 2 ns ? all typical values are at v dd = 5 v, t a = 25 c. notes: 7. sclk can drive an output capacitive load up to 60 pf with worst-case transition time between the 10% and 90% levels less than 4 ns (typical 3 ns). sclk can drive output capacitive loads up to 120 pf, with typical transition time (10% to 90%) of 4 ns. 8. this parameter applies when the split shift-register transfer (ssrt) function is enabled (see subsection 2.9.1 for details). 9. vclk frequency = sclk frequency. 10. measured from the 90% point of the rising edge of dotclk to 50% of the full-scale transition. 11. measured from the 50% point of the full-scale transition to the point at which the output has settled, within 1 lsb (settling time does not include clock and data feedthrough). 12. sclk can be programmed to latch pixel data at the input port up to this limit. however, the sclk output buffer can only be used up to the sclk frequency limit of 85 mhz. 13. measured between 10% and 90% of the full-scale transition.
3 ? 10 3.6 switching characteristics (TLC34076c and TLC34076m) over recommended ranges of supply voltages and operating temperature (continued) parameter -135 -170 unit parameter min typ ? max min typ ? max unit sclk frequency (see note 7) 85 85 mhz vclk frequency 85 85 mhz t en enable time, rd low to d0 ? d7 valid (see figure 3 ? 1) 40 40 ns t dis disable time, rd high to d0 ? d7 disabled (see figure 3 ? 1) 17 17 ns t v valid time, d0 ? d7 valid after rd high (see figure 3 ? 1) 5 5 ns t plh propagation delay, sflag/nflag high to sclk (see note 8 and figure 3 ? 3) 0 20 0 20 ns t d1 delay time, rd low to d0 ? d7 valid (see figure 3 ? 1) 5 5 ns t d2 delay time, selected input clock high/low to dotclk (internal signal) high/low (see figure 3 ? 2) 7 7 ns t d3 delay time, dotclk high/low to vclk high/low (see figure 3 ? 2) 6 6 ns t d4 delay time, vclk high/low to sclk high/low (see note 9 and figure 3 ? 2) 0 5 0 5 ns t d5 delay time, dotclk high/low to sclk high/low (see figure 3 ? 2) 8 8 5 ns ? all typical values are at v dd = 5 v, t a = 25 c. notes: 7. sclk can drive output capacitive loads up to 60 pf, with worst case transition time between 10% and 90% levels less than 4 ns (typical 3 ns). sclk can drive output capacitive loads up to 120 pf, with typical transition time (10% to 90%) of 4 ns. 8. this parameter applies when the split shift-register transfer (ssrt) function is enabled (see subsection 2.9.1 for details). 9. vclk frequency = sclk frequency. 10. measured from the 90% point of the rising edge of dotclk to 50% of the full-scale transition. 11. measured from the 50% point of the full-scale transition to the point at which the output has settled, within 1 lsb (settling time does not include clock and data feedthrough). 12. sclk can be programmed to latch pixel data at the input port up to this limit. however, the sclk output buffer can only be used up to the sclk frequency limit of 85 mhz. 13. measured between 10% and 90% of the full-scale transition.
3 ? 11 3.6 switching characteristics (TLC34076c and TLC34076m) over recommended ranges of supply voltages and operating temperature (continued) parameter -135 -170 unit parameter min typ ? max min typ ? max unit t d6 delay time, dotclk high to ior/iog/iob active (analog output delay time) (see note 10 and figure 3 ? 2) 20 20 ns t d7 analog output settling time (see note 11 and figure 3 ? 2) 6 5 ns t d8 delay time, dotclk high to hsyncout and vsyncout valid (see figure 3 ? 2) 3 3 ns t w6 pulse duration, sclk high (see note 8 and figure 3 ? 3) 15 55 ns pixel data latching frequency (see note 12) 110 mhz t r rise time at hsyncout analog output (see note 13 and figure 3 ? 2) 2 2 ns analog output skew 0 2 0 2 ns ? all typical values are at v dd = 5 v, t a = 25 c. 8. this parameter applies when the split shift-register transfer (ssrt) function is enabled (see subsection 2.9.1 for details). 10. measured from the 90% point of the rising edge of dotclk to 50% of the full-scale transition. 11. measured from the 50% point of the full-scale transition to the point at which the output has settled, within 1 lsb (settling time does not include clock and data feedthrough). 12. sclk can be programmed to latch pixel data at the input port up to this limit. however, the sclk output buffer can only be used up to the sclk frequency limit of 85 mhz. 13. measured between 10% and 90% of the full-scale transition.
3 ? 12 3.7 timing diagrams (input) d0 ? d7 (output) d0 ? d7 rd ,wr rs0 ? rs3 valid data in, wr low data out, rd low ???????????????? ???????????????? ????? ????? t su1 t h1 t w1 t w2 t en t dis t d1 t v t h2 t su2 figure 3 ? 1. mpu interface timing
3 ? 13 vsyncout hsyncout ior,iog,iob (normal mode) hsync , vsync , blank p0 ? p31 (vga pass-through mode) hsync, vsync , vgablank vga0 ? vga7, sclk vclk (internal signal) dotclk clk0 ? clk3 valid valid data data ???????????? ???????????? ?????????????? ?????????????? ???????????????? ???????????????? t cyc t w3 t w4 t d2 t d2 t d3 t d3 t d4 t d4 t d5 t d5 t h3 t su3 t h4 t su4 t h5 t su5 t d6 t d7 t r t d8 data figure 3 ? 2. video input/output timing sclk sflag/ nflag blank t w5 t w6 t plh figure 3 ? 3. sflag/nflag timing (when ssrt function is enabled)
3 ? 14
a ? 1 appendix a sclk/vclk and the tms340x0 while the TLC34076 sclk and vclk outputs are designed for compatibility with all graphics systems, they are also tightly coupled with the tms340x0 graphics system processors. all the timing requirements of the tms340x0 have been considered. however, there are a few points that need to be explained with regard to applications. vclk all the video control signals in the tms340x0 (i.e., blank , hsync , and vsync ) are triggered and generated from the falling edge of vclk. the fact that the TLC34076 uses the falling edge to sample and latch the blank input gives users maximum freedom to choose the frequency of vclk and interconnect the TLC34076 with the tms340x0 gsp without glue logic. needless to say, the vclk frequency needs to be selected to be compatible with the minimum vclk period required by the tms340x0. in the tms340x0, the same vclk falling edge that generates blank requests a screen refresh. when the vclk period is longer than 16 tqs (tq is the period of the tms340x0 clkin), it is possible that the last sclk pulse could be used falsely to transfer the vram data from memory to the shift register along with the last pixel transfer. the first sclk pulse for the next scan line would then shift the first pixel data out of the pipe and the screen would then falsely start from the second pixel. sclk and sflag the TLC34076 sclk signal is compatible with current 10 ns and slower vrams. when split-shift register transfers are used, one sclk pulse has to be generated between the regular shift register transfer and the split-shift register transfer to ensure correct operation. the sflag input is designed for this purpose. sflag can be generated from a programmable logic array and triggered by the rising edge of the tr /qe signal or the rising edge of the ras signal of the regular shift register transfer cycle. tr /qe can be used if the minimum delay from when the vram trg signal goes high to sclk going high can be met by the programmable logic array delay; otherwise, ras can be used.
a ? 2
b ? 1 appendix b printed circuit board layout considerations printed circuit board (pcb) considerations a four-layer printed-circuit board (pcb) should be used with the TLC34076, one layer each for 5-v power and gnd and two layers for signals. the layout should be optimized for the lowest possible noise on the TLC34076 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of v dd and gnd terminals should be minimized so as to reduce inductive ringing. the terminal assignments for the TLC34076 p0 ? p31 inputs were selected for minimum interconnect lengths between these inputs and the vram pixel data outputs. the TLC34076 should be located as close to the output connectors as possible to minimize noise pickup and reflections due to impedance mismatching. ground plane a single ground plane is recommended for both the TLC34076 and the rest of the logic. separate digital and analog ground planes are not needed. power plane split power planes are recommended for the TLC34076 and the rest of the logic. the TLC34076 and its associated analog circuitry should have their own power plane, referred to as av cc in figure b ? 1. the two power planes should be connected at a single point through a ferrite bead as shown in figures b ? 1, b ? 2, and b ? 3. this bead should be located within 3 inches of the TLC34076. supply decoupling bypass capacitors should be installed using the shortest leads possible, being consistent with reliable operation to reduce the lead inductance. for the best performance, a 0.1- f ceramic capacitor in parallel with a 0.01- f chip capacitor should be used to decouple each of the three groups of power terminals to gnd. these capacitors should be placed as close as possible to the device as shown in figure b ? 2. when a switching power supply is used, the designer should pay close attention to reducing power supply noise and should consider using a 3-terminal voltage regulator for supplying power to av cc . comp and v ref terminals a 100- ? resistor (optional) and 0.1- f ceramic capacitor (approximate values) should be connected in series between the device comp and v dd terminals in order to avoid noise and color-smearing problems. also, whether an internal or external voltage reference is used, a 0.1- f capacitor should be connected between the device v ref and gnd terminals to further stabilize the video image. the resistor and capacitor values may vary depending on the board layout; experimentation may be required in order to determine optimum values.
b ? 2 av cc l1 d1 TLC34076 iob iog ior fs adjust gnd v ref v dd to video connector gnd v cc c10 c11 r1 c5-c7 c1-c3 r5 r4 r3 r2 comp c9 c12 r6 location description c1-c3, c9-c10, c12 0.1- f ceramic capacitor c5-c7 0.01- f ceramic chip capacitor c11 33- f tantalum capacitor l1 ferrite bead r1 1000- ? 1% metal-film resistor r2 523- ? 1% metal-film resistor r3, r4, r5 75- ? 1% metal-film resistor r6 100- ? 5% resistor d1 1.2-v voltage reference figure b ? 1. typical connection diagram and components (shaded area is optional)
b ? 3 the board edge of TLC34076 r6 d1 c3 c7 l1 c11 + r5 r4 r3 r2 db15 or db9 connecator c2 c6 c4 c1 c10 u1 p1 c5, c8 r1 c9 c12 figure b ? 2. typical component placement (component side) the board edge of v cc v cc v cc av cc figure b ? 3. typical split power plane (solder side)
b ? 4
c ? 1 appendix c sclk frequency < vclk frequency the vclk and sclk outputs generated by the TLC34076 are both free-running clocks. the video control signals (i.e., hsync , vsync , and blank ) are normally generated from vclk, and a fixed relationship between the video control signals and vclk can, therefore, be expected. the TLC34076 samples and latches the blank input on the falling edge of vclk. it then looks at the load signal to determine when to disable or enable sclk at its output terminal. the decision is deterministic when the sclk frequency is greater than or equal to the vclk frequency. however, when the sclk frequency is less than the vclk frequency, the appearance of the sclk waveform at its output terminal when blank is sampled low on the vclk falling edge can vary (see figures c ? 1 and c ? 2). to avoid this variation in the sclk output waveform, the sclk and vclk frequencies should be chosen so that htotal is evenly divisible by the ratio of vclk frequency:sclk frequency; that is: remainder of htotal vclk frequency sclk frequency 0 for example, if htotal is even, vclk frequency = dotclk frequency/8, and sclk frequency = dotclk frequency/16, then the formula above is satisfied. note: when htotal starts at zero (as in the tms340x0 gsp), then the formula becomes: remainder of (htotal 1) vclk frequency sclk frequency 0 vclk blank load (internal signal for data latch) sclk at output terminal figure c ? 1. vclk and sclk phase relationship (case 1)
c ? 2 vclk blank load (internal signal for data latch) sclk at output terminal figure c ? 2. vclk and sclk phase relationship (case 2)
d ? 1 appendix d mechanical data fn (s-pqcc-j**) plastic quad chip carrier 4040005 / b 03/95 20 pin shown 0.026 (0,66) 0.032 (0,81) d2 / e2 0.020 (0,51) min 0.180 (4,57) max 0.120 (3,05) 0.090 (2,29) d2 / e2 0.013 (0,33) 0.021 (0,53) seating plane max d2 / e2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) max 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) nom 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) min 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) 18 19 14 13 d d1 1 3 9 e1 e 4 8 min max min pins ** 20 28 44 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 52 68 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) d / e 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) no. of d1 / e1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) m 0.007 (0,18) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-018
d ? 2 mechanical data (continued) ga-gb (s-cpga-p12 x 12) ceramic pin grid array package 4040114-5 / b 10/94 down cavity up cavity down cavity cavity up outline small outline large maximum pins within matrix ? 144 c1 0.025 (0,63) 0.060 (1,52) 0.060 (1,52) 0.040 (1,02) c b1 0.095 (2,41) 0.205 (5,21) 0.205 (5,21) 0.110 (2,79) b a1 1.180 (29,97) 1.235 (31,37) 1.280 (32,51) dim min max notes 1.240 (31,50) a a or a1 sq 4 places dia typ 1.100 (27,94) typ 0.050 (1,27) dia 0.120 (3,05) 0.016 (0,41) 0.022 (0,55) 0.140 (3,56) b or b1 c or c1 j h g f e d c a b 12 3 4 567 8 9 k 10 l 11 12 m 0.100 (2,54) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. index mark may appear on top or bottom depending on package vendor. d. pins are located within 0.005 (0,13) radius of true position relative to each other at maximum material condition and within 0.015 (0,38) radius relative to the center of the ceramic. e. this package can be hermetically sealed with metal lids or with ceramic lids using glass frit. f. the pins can be gold-plated or solder-dipped. g. falls within mil-std-1835 cmga4-pn and cmga16-pn and jedec mo-067ad and mo-066ad, respectively

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