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YMF795 apl-2 automobile sound player-2 yamaha corporation YMF795 catalog catalog no.:lsi-4mf795a20 2005. 11 outline YMF795 is a sound source lsi to reproduce high quality melody and effect sound for in-car product. yamaha's original fm synthesizer embedded as a sound source can create various timbres, and also a sequencer embedded can simultaneously generate up to four sounds with four different timbres without giving load to the controller. serial port is prepared as a controller interface, and no restriction of data capacity is present because melody data is reproduced in real-time through fifo. a built-in amplifier to drive the dynamic speaker w ith 500mw power allows connecting a speaker directly. this lsi is equipped with an analog-output pin also for the earphone jack. in addition, supporting the standby mode can reduce the consumption current to 1 a during the standby. features yamaha's original fm sound source function built-in sequencer capable of producing up to 4 different sounds simultaneously (4 independent timbres available). 500mw output speaker amplifier sound quality correcting equalizer circuit serial interface arbitrary frequency of input clock from 2.685 mhz to 27.853 mh z in 55.93 khz steps, as well as 2.688, 8.4, 12.6, 14.4, 19.2, 19.68, 19.8, and 27.82 mhz clock inputs analog output for earphone power-down mode (typ. 1 a or less) supply voltage (digital and analog): 3.3v10 % 24-pin ssop. the plating of pins is lead-free. (YMF795-ez)
YMF795 -2- contents general description of YMF795 .................................................................................................. ................ 3 block description .............................................................................................................. ........................... 4 pin configuration.............................................................................................................. ............................ 5 pin description ................................................................................................................ ............................. 6 block diagram.................................................................................................................. ............................ 7 register map................................................................................................................... .............................. 8 explanation of registers....................................................................................................... ........................ 9 musical score data register .................................................................................................................... 9 timbre data register ............................................................................................................................. 14 other control data ............................................................................................................................... . 17 power-down control division diagram............................................................................................ ............ 21 explanation of each bit ........................................................................................................ ....................... 21 on reset ....................................................................................................................... .............................. 24 settings and procedure requi red for a pi ece generation......................................................................... ..... 24 clock freque ncy setting........................................................................................................ ..................... 24 on interrupt sequence .......................................................................................................... ...................... 25 state tran sitio n ............................................................................................................... ............................ 26 operation in fifo empty condition.............................................................................................. .............. 28 reproduction method assuming occu rrence of empty state........................................................................ 2 8 example of peripheral circuit.................................................................................................. .................... 29 (1) circuit diagram and wiring diagram when two power supplies are used: ............................................... 30 (2) circuit diagram and wiring diagram when one power supply and one voltage regulator ic are used: ... 31 volume level adjustment in monophonic sound and 4-sound generation ................................................. 33 sound quality corr ection circuit ............................................................................................... ................ 35 serial i/f sp ecifications...................................................................................................... ........................ 37 electrical characteristics ..................................................................................................... ....................... 38 general description of fm sound generator ...................................................................................... ......... 43 external dimensions............................................................................................................ ........................ 44
YMF795 -3- general description of YMF795 YMF795 is controlled through the serial interf ace. internal configuration the lsi has is shown below. data inputted to the serial interface is converted into the parallel data and transferred to each function block according to its index address. the musical score data is stored in the 32-word fifo first and then transferred to the se quencer which interprets data to control sound generation of the fm synthesizer. the timbre register is where up to 8 timbre data can be stored. and, as the sequencer controlling register, registers for start/stop and tempo are provided. in order to have sound generate, the following controls must be performed to this lsi. 1) initial status setting (cancellation of power-down, clock selection, etc). 2) timbre data setting. 3) writing of the musical score data in to fifo before starting the sequence. 4) to write the next musical score data write before the fifo becomes empty, and to receive the interrupt signal from fifo during reproduction. (for the details, refer to ?s ettings and procedure required for a piece generation? (p.24). serial interface fifo 32word /irq sequencer fm synthesizer d/a + volume amp timbre register musical score dat a tempo start/stop timbre allocation timbre data volume, power management, etc. sdin sync sclk spout hpout
YMF795 -4- block description 1) serial interface block the block receives serial data and then identifies its index data to send control data to each function block. 2) fifo block fifo temporarily stores musical score data. musical score data up to 32 can be stored. the musical score data are processed in the sequencer when they are generated as sounds and those processed are deleted one after another. when the amount of remaining data amount in fifo r eaches the value or less of register setting (irq point), it outputs an interrupt signal to the outside to request the subsequent musical score data. 3) sequencer block when the sequencer receives the start command, it sequentially starts reading the musical score data which have been stored in fifo. the processed musical score data are deleted. 4) timbre register block the block stores timbre data in this register which can set up to 8 timbres. settings of this register must be completed before sound generation. the register is initialized by hardware reset; however, in the following operations, contents of a register are not cleared, and the value written last is held. ? software reset (clr bit of index32h) ? during power-down mode, and after its cancellation. 5) fm synthesizer block the block synthesizes and generates timbres according to settings. four s ounds can be generated at the same time. 6) d/a, volume, and amplifier blocks the output from the synthesizer is d/a-converted, and volume processing is performed. after that, the data is output from the speaker or the earphone output pin.
YMF795 -5- pin configuration < 24-pin ssop top view > 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk_i sdin sync sclk avss vref hpout eq1 eq2 e q 3 testo / rst /testi /irq dvdd dvss spout2 spout1 spvss spvss avdd avdd
YMF795 -6- pin description no. pin i/o function 1 clk_i ish clock input pin 2 - be sure to use in no-connection. the pin is nowhere connected in the chip. 3 sdin i serial i/f data input 4 sync i serial i/f synchronous signal input 5 sclk ish serial i/f bit clock input 6 - be sure to use in no-connection. the pin is nowhere connected in the chip. 7 avss - analog ground 8 vref a analog reference voltage pin connect a 0.1 f capacitor between this pin and analog ground pin. 9 hpout ao analog output pin for earphone 10 eq1 ao equalizer pin 1 11 eq2 ai equalizer pin 2 12 eq3 ao equalizer pin 3 13 14 avdd - analog power supply (+3.3v) connect 0.1 f and 4.7 f capacitors between this pin and analog ground pin 15 16 spvss - analog ground exclusively used for speaker 17 spout1 ao speaker output pin 1 18 spout2 ao speaker output pin 2 19 dvss - digital ground 20 dvdd - digital power supply (+3.3 v) connect 0.1 f and 4.7 f capacitors between this pin and digital ground pin. 21 /irq o interrupt signal output 22 /testi i lsi test input pin (be sure to connect to dvdd.) 23 /rst i hardware reset pin 24 testo o lsi test output pin (be sure to use in no-connection) note : ish = schmitt input pin ai = an alog input pin a0 = analog output pin
YMF795 -7- block diagram concerning ain signal inputted into equalizer circuit it is possible to make the analog mixing between synthesizer output and other analog source in the equalizer circuit and output the resulting sound through the speaker. sync sdin sclk clk_i /rst /irq eq1 vref serial i/f dvdd dvss fmvol 32 -step power down control register fm synthesizer simultaneous sound generation 4-tone dac amp avdd avss timing generator hpout hpvol 32 -step fifo 16b 32w eq2 eq3 vref cr circuit for eq spvss spvol 32 -step ain * se q uencer + ? vref spout1 spout2
YMF795 -8- register map index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description bl1 bl0 nt3 nt2 nt1 nt0 ch1 ch0 vib ti3 ti2 ti1 ti0 tk2 tk1 tk0 note data $00h 0 0 1 1 0 0 ch1 ch0 vche ti3 ti2 ti1 ti0 vch2 vch1 vch0 rest data ml2 ml1 ml0 vib egt sus rr3 rr2 rr1 rr0 dr3 dr2 dr1 dr0 ar3 ar2 $10 - 2fh ar1 ar0 sl3 sl2 sl1 sl0 tl5 tl4 tl3 tl2 tl1 tl0 wav fl2 fl1 fl0 timbre data (for 1 operator) $30h 0 v32 v31 v30 0 v22 v21 v20 0 v12 v11 v10 0 v02 v01 v00 timbre allocation data $31h 0 0 0 0 0 0 0 0 t7 t6 t5 t4 t3 t2 t1 t0 tempo data $32h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr st fm control $33h 0 0 0 0 0 0 0 0 0 0 0 0 0 clksel clk_i select $34h 0 0 0 0 0 0 0 0 0 0 irqe irq point irq control $35h 0 0 0 0 0 0 0 0 0 0 0 v4 v3 v2 v1 v0 speaker volume $36h 0 0 0 0 0 0 0 0 0 0 0 v4 v3 v2 v1 v0 fm volume $37h 0 0 0 0 0 0 0 0 0 0 0 v4 v3 v2 v1 v0 hpout volume $38h 0 0 0 0 0 0 0 0 0 0 0 ap4 ap3 ap2 ap1 dp power management $39h 0 0 0 0 0 0 0 clkset clk_i select $40 - efh reserved (access prohibited) reserved $f0 - ffh for lsi test(access prohibited) lsi test note : access to the spaces of ?reserved? and ?for lsi test? in the above table is prohibited. be sure to write ?0? to the empty bit, although writing ?1? there will not affect the lsi operation.
YMF795 -9- explanation of registers the YMF795 has three types of control registers: musical score data, timbre data, and other control data. musical score data register $00h musical score data the musical score data are written into the 32-word fifo. there are two types of musical score data: note data and rest data. note data default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $00h bl1 bl0 nt3 nt2 nt1 nt0 ch1 ch0 vib ti3 ti2 ti1 ti0 tk2 tk1 tk0 bl1 ? bl0 : octave block setting three octave blocks are available for sound range setting. the setting range is 1 to 3. do not set ?0.? in addition, the sound generation range is affected by th e coefficient called ?multiple (multiplying factor for sound generation frequency).? by combining the octave block and multiple settings, sounds can be generated in the range as listed in the table blow. since the setting range of ?multiple? coefficient is 0 to 7, actually, sounds wider than those given in the table below can be generated. multiple = 1 (x1) multiple = 2 (x2) multiple = 4 (x4) bl[1:0] = 01b c#3 (139hz) d3 (147hz) d#3 (156hz) e3 (165hz) f3 (175hz) f#3 (185hz) g3 (196hz) g#3 (208hz) a3 (220hz) a#3 (233hz) b3 (247hz) c4 (262hz) c#4 (277hz) d4 (294hz) d#4 (311hz) e4 (330hz) f4 (349hz) f#4 (370hz) g4 (392hz) g#4 (415hz) a4 (440hz) a#4 (466hz) b4 (494hz) c5 (523hz) c#5 (554hz) d5 (587hz) d#5 (622hz) e5 (659hz) f5 (698hz) f#5 (740hz) g5 (784hz) g#5 (831hz) a5 (880hz) a#5 (932hz) b5 (988hz) c6 (1046hz) bl[1:0] = 10b c#4 (277hz) d4 (294hz) d#4 (311hz) e4 (330hz) f4 (349hz) f#4 (370hz) g4 (392hz) g#4 (415hz) a4 (440hz) a#4 (466hz) b4 (494hz) c5 (523hz) c#5 (554hz) d5 (587hz) d#5 (622hz) e5 (659hz) f5 (698hz) f#5 (740hz) g5 (784hz) g#5 (831hz) a5 (880hz) a#5 (932hz) b5 (988hz) c6 (1046hz) c#6 (1109hz) d6 (1175hz) d#6 (1245hz) e6 (1319hz) f6 (1397hz) f#6 (1480hz) g6 (1568hz) g#6 (1661hz) a6 (1760hz) a#6 (1865hz) b6 (1976hz) c7 (2093hz) bl[1:0] = 11b c#5 (554hz) d5 (587hz) d#5 (622hz) e5 (659hz) f5 (698hz) f#5 (740hz) g5 (784hz) g#5 (831hz) a5 (880hz) a#5 (932hz) b5 (988hz) c6 (1046hz) c#6 (1109hz) d6 (1175hz) d#6 (1245hz) e6 (1319hz) f6 (1397hz) f#6 (1480hz) g6 (1568hz) g#6 (1661hz) a6 (1760hz) a#6 (1865hz) b6 (1976hz) c7 (2093hz) c#7 (2217hz) d7 (2349hz) d#7 (2489hz) e7 (2637hz) f7 (2794hz) f#7 (2960hz) g7 (3136hz) g#7 (3322hz) a7 (3520hz) a#7 (3729hz) b7 (3951hz) c8 (4186hz)
YMF795 -10- nt3 - nt0 : pitch setting four bits from nt3 to 0 are used to specify the pitch. the bit assignment is as follows. nt[3:0] pitch 0h setting prohibited 1h c# 2h d 3h d# 4h setting prohibited 5h e 6h f 7h f# 8h setting prohibited 9h g ah g# bh a ch setting prohibited dh a# eh b fh c about ?setting prohibited.? although lsi never hangs, unusual sound may be generated. never set it. ch1 - ch0 : part setting as the sound source section can simultaneously generate sounds in 4 parts, set the part of a note by using ch1 and 0 bits. ch[1:0] part setting 00b 0 01b 1 10b 2 11b 3 vib : vibrato setting this bit is used to set on/off of vibrato function for each note: ?0? for off and ?1? for on. the vibrato frequency is 6.4 hz and the modulation depth is 13.47 cent. note that vibrato function becomes off when vib bit of timbre data ($10-2fh) is ?0.?
YMF795 -11- ti3 - ti0 : interval setting these bits are used to set the interval time before the processing of the next note and rest. the interval ?48? represents the time for the whole note. ti [3:0] interval 0h 0 1h 2 2h 3 3h 4 4h 6 5h 8 6h 9 7h 12 8h 18 9h 24 ah 48 bh 0 ch 16 dh 24 eh 36 fh 48 tk2 ? tk0 : note (sound length) designation these 3 bits are used to designate the note (sound length). depending on the value of interval setting (ti3 - 0), the length varies as shown in the following table. the interval ?48? represents the time for the whole note. ti [3:0] = 0 to ah ti [3:0] = b to fh tk[2:0] 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 sound length 1 2 3 5 7 8 11 17 15 23 29 32 35 41 47 tie, slur
YMF795 -12- caution when key is turned on again while release rate is not co mpletely finished yet in the same channel, timbre may change. this happens in both sustained sound and d ecaying s ound. the reason why it happens is that both envelope and phase in the career side and modulator side of the fm sound source deviate. the hardware creating the phase and envelope of fm sound source starts its operation according to the following two conditions. - end of the release rate. - occurrence of key on. timbre data is created on the assumption that modulator, phase between careers, and envelope operate at the same timing; therefore, timbre may vary when this condition is not met. description mentioned above is explained with the envelope waveform. for example, assume that a timbre of which only release time differs between carrier and modulator is present. if operation is in the state completely stopped, it shifts to the attack rate in conjunction with key on. if the previous sound generation is being released and is not in a state completely stopped, the release settings is forcibly hastened (8.94 ms) and a stopped state is shifted to the attack rate state. (dotted line of a) although envelope indicated in a solid line changes to the attack rate state soon at the second key on, shifting to the attack rate state is not immediately performed because s ound indicated in a dotted line is not completely stopped. the release time is hastened to stop the state, and then the state stopped is shifted to the attack rate state. the starting time deviation of both envelopes and phase caused by this deviation causes a change of timbre. how to avoid this symptom: be sure to observe ?try to pronounce under the condition that the release is completely stopped.? t k ti a t k timbre varies.
YMF795 -13- rest data default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $00h 0 0 1 1 0 0 ch1 ch0 vche ti3 ti2 ti1 ti0 vch2 vch1vch0 ch1 - ch0 : part setting using ch1 or 0 bit, set the part of each rest. ch[1:0] part designation 00b 0 01b 1 10b 2 11b 3 ti3 - ti0 : interval setting these bits are used to set the interval time before the processing of the next note and rest. the interval ?48? represents the time for the whole note. the following table is exactly the same as that for the note data. ti [3:0] interval 0h 3 1h 2 2h 3 3h 4 4h 6 5h 8 6h 9 7h 12 8h 18 9h 24 ah 48 bh 1 ch 16 dh 24 eh 36 fh 48 vche, vch2 ? vch0 : timbre change function although the maximum number of timbres that can be simultaneously used is four, the timbre can be changed during sound reproduction by setting these bits. set vche to ?1? and set a timbre number by using vch2 to vch0. switching of timbre in rest data is made according to the designated time of the sequence data. after the next note to generate, the timbre in a part specified by ch0 and ch1 will be changed. make the change of a timbre after sound generation of a part to change is completely stopped. the state at which sound generation is completely stopped is not a state where tk (sound length) is ended but a state where release time of envelope is completed. note that unusual sound may be instantaneously generated if switching the timbre while sound generation is not completely stopped. if the timbre allocation is changed by using this function, the $30h register itself will be rewritten.
YMF795 -14- timbre data register $10 ? 2fh timbre data eight timbre data can be registered into the register and four data out of them can be simultaneously reprodu ced. timbre is made by setting both [parameters for the modulator] and [parameters for the carrier]. (for details of the modulator and the carrier, please refer to ?general description of fm sound generator? (page 41)). index 10h, 11h ?? 1st timbre_ timbre data for the modulator index 12h, 13h ?? 1st timbre_ timbre data for the carrier index 14h, 15h ?? 2nd timbre_ timbre data for the modulator index 16h, 17h ?? 2nd timbre_ timbre data for the carrier ?????omitted?????. index 2ch, 2dh ?? 8th timbre_ timbre data for the modulator index 2eh, 2fh ?? 8th timbre_ timbre data for the carrier the following bit assignment is used for both modulator and carrier. the setting must be completed before any sound is generated. change of the timbre parameter during sound generation is prohibited. timbre data default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 even ml2 ml1 ml0 vib egt sus rr3 rr2 rr1 rr0 dr3 dr2 dr1 dr0 ar3 ar2 odd ar1 ar0 sl3 sl2 sl1 sl0 tl5 tl4 tl3 tl2 tl1 tl0 wav fl2 fl1 fl0 ml2 - ml0 : multiple setting ?multiple? is the multiplying factor for sound generating frequency. the output frequency is determined by the octave, pitch, and multiple settings on the carrier side. adjusting the multiple on the modulator side allows various timbre creation. ml [2:0] multiplying factor for frequency 0h x 1/2 1h x 1 2h x 2 3h x 3 4h x 4 5h x 5 6h x 6 7h x 7
YMF795 -15- vib : vibrato this bit is used to set on/off of vibrato function. ?0? for off, ?1? for on. the vibrato frequency is 6.4 hz and the modulation depth is 13.47cent. egt : envelope waveform type this bit is used to select the type of the envelope waveform. ?0? for the decaying s ound and ?1? for the sustained sound. envelope waveforms shown below are for the decaying s ound and sustained sound. ar3 - ar0 : attack rate setting ?attack rate? is a time interval from the time sound starts generating (-48db) to the time sound r eaches at the maximum volume (0db). the table on the next page is shown as the time taken from -48db to 0db. dr3 - dr0 : decay rate setting ?decay rate? is a time interval taken for decay from 0 db to the time it reaches at the sustain level (sl). the table on the next page is shown as the time taken from 0 db to -48 db. rr3 - rr0 : release rate setting definition of the release rate differs between decaying s ound and sustained sound. ? decaying s ound: d ecaying time from the sustain level to the end of the s ound generation. the sound d ecays taking 286 ms (time taken from 0 db to -48 db) after the end of the sound generation. ? sustained sound: d ecaying time from the end of the s ound generation. a r d r r r s l 0db - 48db when sus=on egt=0 decaying sound length of sound generated a r d r r r s l 0db -48db when sus=on egt=1 sustained sound length of sound generated
YMF795 -16- sl3 - sl0 : sustain level setting the sustain level, in the case of decaying s ound, is the transition level from the d ecay rate to the release rate, and in the case of sustained sound, is a level held. sl sl3 sl2 sl1 sl0 weighted bit (db) -24 -12 -6 -3 ar[3:0] dr[3:0] rr[3:0] attack rate -48 to 0db (ms) decay rate, release rate 0 to -48db (ms) fh 0 2.23 eh 4.65 8.94 dh 9.30 17.88 ch 18.59 35.76 bh 37.19 71.52 ah 74.38 143.04 9h 148.76 286.07 8h 297.51 572.14 7h 595.03 1144.25 6h 1190.05 2288.56 5h 2380.10 4577.12 4h 4760.21 9154.25 3h 9520.42 18308.50 2h 19040.84 36617.00 1h 0h tl5 - tl0 : total level setting this function is used to set the envelope level. tl tl5 tl4 tl3 tl2 tl1 tl0 weighted bit (db) -24 -12 -6 -3 -1.5 -0.75 sus : sustain on/off setting ?0? : off ?1? : on the release rate changes to ?6? (2.29s) when the sound length comes to the end. wav : waveform selection the modulator and carrier can generate a sine wave; however, can generate a half-wave rectified waveform by setting this bit. setting this bit allo ws creation using wider timbres. ?0? : sine wave ?1? : half-wave rectified waveform of a sine wave. fl2 - fl0 : feed-back setting this function is available only for the operator of modulator. these bits specify the feedback modulation depth. be sure to set ?0? to the operator of the carrier side. this is effective function for generating the strings timbres. fl [2:0] 0 1 2 3 4 5 6 7 modulation rate 0 /16 / 8 / 4 / 2 2 4 wav=0 wav=1
YMF795 -17- other control data $30h timbre allocation data one piece can be generated at the same time up to four parts, and timbre can be assigned for each part. the data is used by allocating four timbres out of eight timbres registered in the timbre data register to each part. default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $30h 0 v32 v31 v30 0 v22 v21 v20 0 v12 v11 v10 0 v02 v01 v00 ?x? of vx[2:0] indicates the part no. vx[2:0] and timbre data are as follows. vx[2:0] timbre data to use 0h timbre set in the index of 10 to 13h is used. 1h timbre set in the index of 14 to 17h is used. 2h timbre set in the index of 18 to 1bh is used. 3h timbre set in the index of 1c to 1fh is used. 4h timbre set in the index of 20 to 23h is used. 5h timbre set in the index of 24 to 27h is used. 6h timbre set in the index of 28 to 2bh is used. 7h timbre set in the index of 2c to 2fh is used. $31h tempo data this register sets ?tempo? for reproduction of a pi ece. setting data is equal to ( 8739/tempo)-1. tempo is the number of crotchets that can be reproduced in one minute. default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $31h 0 0 0 0 0 0 0 0 t7 t6 t5 t4 t3 t2 t1 t0 $32h fm section control default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $32h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr st st : this bit is used to control start/stop of a piece. ?1? for start and ?0? for stop. fifo becomes empty when st is set to ?0.? clr : this bit is used to initialize the whole lsi by the software. all the registers except ? timbre data register? of index 10 to 2fh are initialized. bit clr itself is not cleared ev en if setting to ?1.? in normal operation, write ?0? into the bit clr..
YMF795 -18- $33h clock selection default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $33h 0 0 0 0 0 0 0 0 0 0 0 0 0 clksel this register is used to set the clock frequency inputte d through clk_i pin when making the clock setting in the preset mode. a clock with any frequency can be input during the reset period. (for details of the clock setting, see ?on clock frequency setting? (page 24)). cksel [2:0] clock frequency (mhz) 0h(*) 2.688 1h 19.200 2h 19.680 3h 19.800 4h 8.400 5h 14.400 6h 27.821 7h 12.600 (*)when clock is set in the programmable mode, set clksel[2:0] to ?0h?. $34h interrupt control default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $34h 0 0 0 0 0 0 0 0 0 0 irqe irq point the musical score data is taken into the fifo which has a capacity for 32 data. as the sounds are reproduced, the data in fifo are processed and deleted. and when the amount of data remaining in fifo becomes less than the setting value of irq point, an interrupt signal is generated. at this point, set ?0? to irqe and then write the subsequent musical score data into fifo. be sure to write data in excess of the irq point. after wr iting the data, reset irqe to ?1? and wait another interrupt signal. irq point can be set in 32 ways from 0 (empty) to 31 (1 data vacancy). irqe is the interrupt enable bit. ?1? indicates enable.
YMF795 -19- $35h speaker volume control $36h fm volume control $37h earphone output volume control default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $35-7h 0 0 0 0 0 0 0 0 0 0 0 v4 v3 v2 v1 v0 these bits are used to set the volume of each source. the volume setting consists of 31 steps and mute state, and can be set in 1db steps. as the mute is selected in the default state, cancel and use the mute state before sound generation. and, be sure to power down the volume after muting it. relation between register setting value and volume. v[4:0] volume(db) v[4:0] volume(db) v[4:0] volume(db) v[4:0] volume(db) 00h mute 08h -23 10h -15 18h -7 01h -30 09h -22 11h -14 19h -6 02h -29 0ah -21 12h -13 1ah -5 03h -28 0bh -20 13h -12 1bh -4 04h -27 0ch -19 14h -11 1ch -3 05h -26 0dh -18 15h -10 1dh -2 06h -25 0eh -17 16h - 9 1eh -1 07h -24 0fh -16 17h - 8 1fh 0 $38h power management control default: 001eh index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $38h 0 0 0 0 0 0 0 0 0 0 0 ap4 ap3 ap2 ap1 dp these bits are used to control the power-down. 1 digital line and 4 analog lines can be independently controlled. (for details, refer to ? power-down control division diagram?.) setting all bits to ?1? will minimize the power of the entire lsi. dp : setting of ?1? can power down the entire digital section. ap1 : setting of ?1? can power down the vref circuit in the analog section. ap2 : setting of ?1? can power down the fm volume, speaker volume, equalizer circuit, and the non-inverted amplifier side of speaker output section. ap3 : setting of ?1? can power down the inverted amplifier side of the speaker output section. ap4 : setting of ?1? can power down the dac and earphone output volume. after initialization, the analog section (ap1 to ap4) is in the power-down state.
YMF795 -20- $39h clock setting default: 0000h index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 $39h 0 0 0 0 0 0 0 clkset the register is used to set the clock frequency that is input through the clk_i pin when the setting is made in the programmable mode. be sure to complete the setting before its sound generation. a clock with any frequency can be input during the reset period. for details of the clock setting, see ?clock frequency setting? (page 24). clkset [8:0] clock frequency(mhz) 000000000b (preset mode) 000000001b prohibition : : 000101111b prohibition 000110000b 2.684658000 000110001b 2.740588375 : : 111110001b 27.797396375 111110010b 27.853326750 111110011b prohibition : : 111111111b prohibition the values that can be set to clkset are ?000000000b?, and ?000110000b? to ?111110010b.? when other value is set, the operation is not guaranteed. a value to set to clkset can be found by using the following formula. clkset = clock frequency [khz] / 447.443 8 for example, when the clock frequency is 3 mhz: clkset = 3000 / 447.443 8 is about 54 = 000110110b and, actual clock frequency to be set is as follows. clock frequency [khz] = 54 447.443 / 8 = 3020.24[khz] = 3.02024[mhz]
YMF795 -21- power-down control division diagram power-down of the lsi can be controlled for each divided internal function. the power-down is controlled by index 38h. explanation of each bit dp0 this is the bit to power o ff the whole digital section. consumption current of the digital part can be minimized because internal clock stops. contents of the registers are held but data in the fifo are cleared. ap1 this is the bit to power off the vref circuit. if ap1 is set to ?1?, the whole analog section stops. because an analog center voltage is made by vref circuit. ap2 this is the bit to power off the fm volume section, eq circuit, speaker volume, and non-inverted amplifier side of speaker output section. sync sdin sclk /rst /irq eq1 vref serial i/f dvdd dvss vol 32-ste p power down control register ram fm synthesizer simultaneous sound generation 4-tone dac amp avdd avss timing generator hpout vol 32-ste p fifo 16b 32w eq eq2 eq3 spout1 vref controlled by using dp bit controlled by using ap4 bit controlled by using ap3 bit controlled by using ap1 bit controlled by using ap2 bit vol 32-step clk_i spvss spout2
YMF795 -22- ap3 this is the bit to power off the inverted am plifier side of the speaker output section. turning the inverted amplifier side power on after turning the vref circuit and a non-inverted amplifier power on can reduce pop noise. ap4 this is the bit to power off the dac and the hp volume section. cautions for transition to the power-down 1. be sure to shift a state to the power-down after the sound generation stops. 2. power-down of the digital and analog section can be made at the same time. be sure to mute fm volume and hp volume in advance for the reduction of noise during power-down transition. the registers to which the digital section cannot access during the power-down are as follows. index register functions $00h musical score data $10-2fh timbre data $30h timbre allocation $31h tempo data $34h irq control cautions for cancellation of the power-down 1. the time of 64clk_i is necessary from the setting of dp=0 until the digital sec tion returns to the normal operation. be sure to access the registers after waiting for the time. 2. perform the return procedure in this order when the whole analog section was powered off or the analog power supply is off. ? set ap1 to ?0.? vref goes up at the maximum of 50ms. do not set ap2 to ap4 to ?0? until vref goes up. ? set ap2 to ?0.? ? set ap3 and ap4 to ?0? after at least 10 s. ? here, analog section is made available. consumption current can be reduced more, by setting ap4 to ?1? when only speaker amplifier section is used, and by setting ap2 and ap3 to ?1? when only headphone is used without speaker amplifier. analog power supply off mode analog power supply can be powered off only when sound generation is being stopped. be sure to set ap1 to ap4 to ?1? before powering off the analog power supply. or, pop noise may occur.
YMF795 -23- example of the setting in each case. depending on how the function is used, bit se ttings can be combined as shown below. ap1 ap2 ap3 ap4 caution analog section whole power-down 1 1 1 1 be sure to set all volumes to ?mute? first, then set all bits to ?1? simultaneously. use of only earphone output. 0 1 1 0 set the fm and speaker volumes to ?mute.? use of only speaker. 0 0 0 1 set the hp and fm volumes to ?mute.?
YMF795 -24- on reset this lsi can be initialized by setting /rst pin to ?l.? a nd, clr bit is provided in $32h to allow the software to initialize the lsi. hardware reset initializes the lsi and returns it to the default condition. all the registers except the timbre data register of index 10h to 2fh are initialized by the software reset. a counter for the amount of fifo data is cleared to ?empty? state. input of clk_i is required during reset. be sure to control so that clk_i is input at least more than 100 clocks during the reset. after the reset cancellation, access a register after waiting at least 64 clocks of clk_i. settings and procedure required for a piece generation necessary settings and procedure are as follows. 1. set the clksel ($33h) or clksel ($39h) according to the clock frequency i nputted for clk_i. 2. cancel the power-down mode of the analog section. (see ?cautions for cancellation of the power-down? (page22). 3. set the timbre data ($10-2fh), timbre allocation data ($30h), tempo data ($31h) and volumes ($35-37h) as required. 4. write musical score data ($00h) for 32 data (that is, to fifo_full). 5. set the irq point value of $34h. 6. set the irqe of $34h to ?1.? 7. set the st bit of $32h to ?1? to start the melody. clock frequency setting two modes for clock frequency setting are supported: ?preset mode? and ?programmable mode.? preset mode: a clock is selected from 2.688 / 8.4 / 12.6 / 14.4 /19.2 / 19.68 / 19.8 / 27.82 mhz. programmable mode: a clock is selected from 2.685 mhz to 27.853 mhz in 55.93 khz steps. 1) when the preset mode is used: clock frequency setting can be made in the preset mode by setting a value to $33h. in this case, set $39h to ?000000000b.? operation is not guaranteed if other value is set. when a value is not set to both $33h and $39h (default cond ition), a condition that 2.688 mhz is set in the preset mode is given. 2) when the programmable mode is used: clock frequency setting can be made in the programmable mode by setting a value to $39h. in this case, set $33h to ?000b.? operation is not guaranteed if other value is set. a value that can be set to $39h is ?000000000b? and ?000110000b? to ?111110010b.? operation is not guaranteed if other value is set.
YMF795 -25- on interrupt sequence an interrupt from lsi (/irq-?l?) occurs when the amount of data in the fifo becomes less than the setting value. for example, supposing that 10h (16b) is set to the irq point of $34h, the fifo becomes full before starting a piece as described in ?settings and procedure required for a piece generation.? once a piece is started, the data in the fifo decreases as the musical score data is processed. when the am ount of remaining data becomes 16 bytes or less, /irq pin becomes ?l? and occurrence of an interrupt is sent to the external microprocessor. when an interrupt signal is detected, set irqe to ?0? and write the musical score data into the fifo before it becomes empty. as overwriting the data into the filled fifo is prohib ited, write the data into fifo by the amount not causing the overwriting (16 data in this case). flow chart set each register according to the explanation of ?settings and procedure required for a piece generation.? start the playback. as a piece is played back, the musical score data are processed in the lsi. the remaining data in fifo is lower than no irq point set in the $34h ? yes set the irq enable bit (irqe) to ?0 ? and write data into the fifo. cautions for the write operation is the following two points: be sure to write data before fifo becomes empty. overwriting the data into the filled fifo is prohibited. do you want to stop the piece? no yes stop the piece. (st=0)
YMF795 -26- state transition the figure shown below is a state transition diagram of the YMF795. sequence to turn the power supply on. a way to turn the analog side power on after turning the dig ital side power on to initialize the hardware is ideal. if the analog power supply is turned on before the hardware is initialized, noise may be generated. initialized hardware reset stop play standby play analog powerdown mode power on digital poweron ready write setup data fifo data write start stop analog poweron ready power on digital powerdown mode power off
YMF795 -27- description of each state digital power on ready this is a state before turning on the digital power supply. hardware reset input the hardware reset to the lsi in conjunction with the power-on of the digital power supply. analog power on ready this is a state before turning on the analog power supply. turn on the analog power supply after the initialization of the digital section. analog power down mode this is a state in which power consumption of the analog section is the minimum. operation state is shifted to this operation mode after the analog power supply is turned on. in order to pro ceed to the next step ?initialized? state, follow the procedure described on page 22. be sure to shift from the ?initialized? state in order to shift to this operation mode from a state except analog power on. (that is, each volume must be set to ?muite.?) a point to power down can be selected according to the usage. for details, refer to the description of power-down on pages of 21, 22, and 23. be sure to power off the analog power supply from this state. initialized this state is given after the power down mode of the analog and the digital section. and, shift to the power-down mode from this state. stop this is a state in which volume mute cancellation and the timbre data setting has been completed. in this state, the fifo is empty. this state returns when the melody reproduction is stopped. and, transition to the power-down of th e digital section is possible from this state. this state will return when the power-down is cancelled. play standby this is a state that is given immediately before the playback of a piece after the write of musical score data into fifo. setting bit st to ?1? will shift to the next ?play? state. transition to the power-down of the digital section is possible from this state. however, the st ate will return to ?stop? state after the power-down cancellation. play this is a state in which a piece is being played back . setting bit st to ?0? will sh ift to the ?stop? state. transition to the power-down of the digital section from this state is prohibited. (noise may be generated.) digital power down mode this is a state in which the digital section is in the power-down state. (dp bit = ?1?) this state can reduce the power consumption of the digital section because a clock is not i nput to the lsi even if it is input to clk_i pin. make the hp volume and fm volume mute state before shifting to this mode.
YMF795 -28- operation in fifo empty condition if fifo become empty during reproduction the musical score data written last is processed continuously until the next data is written. if the last data written is a note data, that note is reproduced continuously. if the last data written is a rest data, the rest state is held. reproduction method assuming occurrence of empty state in the normal reproduction, occurrence of fifo empty is prohibited; however, even simple processing can generate a short tone if the above features are effectively used. processing for interrupt is not required. make the processing according to the following flow. short tone is 1 to 32 word data block. if data block exceeds 33 words, make the processing by the usual repr oduction flow using interrupt. 1) complete the following pr ocedure in advance: power on analog power down mode initialized stop (see the figure of ? state transition? (page 26). 2) start the reproduction in the fifo empty state. 3) write the data block to be reproduced into fifo. 4) immediately after writing (after 0 to 20s), the musical score data are internally processed and its reproduction starts. as reproduction goes on, the data in fifo are processed and cleared. 5) when fifo becomes empty, if the last data in the data block is a note data, that note is reproduced continuously and if it is a rest data, the rest state is held until the next data block is written into fifo. 6) when reproducing the next data block, go to step 3). to stop the reproduction set st to ?0.? then, the data counter of fifo will be cleared and the state returns to a state of step 1).
YMF795 -29- example of peripheral circuit on /rst pin a schmitt circuit is not used for /rst pin in this device; therefore, please design a board in consideration of noise to the /rst line. sclk sdin sync dvss dvdd YMF795 /rst +3.3v re s et # s yn c sdin sc lk clk_i c lk avdd avss /irq irq# spout1 spout2 vref 0.1uf eq1 eq2 c1 eq3 r1 r2 c2 hpout headphone ain +3.3v 0.1uf 4.7uf 0.1uf 4.7uf spvss speaker amp.
YMF795 -30- precautions for the use of separate power supplies: a lsi with multiple power supply inputs needs to pay attention to the followings for [power supply connection] and [ground connection]. we explain it here by giving an analog circuit power supply and a digital circuit power supply as an example. [power supply connection] when a power supply for analog circuits of this lsi and a power supply for digital circuits of this lsi can be separately prepared (including a case where a power supply for the lsi's analog circuits is shared with analog circuits of the later stage) please refer to ?(1) circuit diagram and wiring di agram when two power supplies are used:? on the contrary, when multiple power supplies cannot be prepared, please refer to ?(2) circuit diagram and wiring diagram when one power supply and one voltage regulator ic are used:? and, when ?(1) circuit diagram and wiring diagram when two power supplies are used:? is selected, room for improvement of analog performance becomes big, but you need to consider avoidance of time interval difference between power supplies at the time of power-on (power-off). [ground connection] the ground connection is common to ?(1) circuit diagram and wiring diagram when two power supplies are used:? and ?(2) circuit diagram and wiring diagram when one power supply and one voltage regulator ic are used:? in each case, grounds must not be separated. (1) circuit diagram and wiring diagram when two power supplies are used: ? be sure to connect vss pin to avss pin near the lsi. excessive inductance between vss pin and avss pin may cause malfunctions and failures.
YMF795 -31- (2) circuit diagram and wiring diagram when one power supply and one voltage regulator ic are used: ? be sure to connect vss pin to avss pin near the lsi. excessive inductance between vss pin and avss pin may cause malfunctions and failures. ? connect the ground pin of the voltage regulator ic used for analog circuits near avss pin to prevent influence of digital circuit's current change. ? the later analog circuits shall consider the avss pin as a reference potential.
YMF795 -32- warning for the device which makes sound through speaker a speaker radiates heat in a voice-coil by air flow accompanying vibration of a diaphragm. when dc signal (several hz or less) is input, heat radiation characteristics falls rapidly. in addition, even if it is used lower than the rated input, it may lead to voice-coil burnout, smoke, or ignition of a speaker. in order to avoid such situations, be sure to implement one or more preventive measures from the followings. 1. don?t select settings (sound creation) which may generate dc signal. (since thoroughness of this preventive measure is generally difficult, we recommend the combined use with the following 2, 3, and 4) 2. add the equivalent of dc cut digital filter for cutting dc signal into a digital section. (as long as ?built-in? is not mentioned in the manual, there is no such built-in circuit inside of a device). 3. add a dc cut capacitor for cutting dc signal into an analog section. (when addition is specified in the example of a recommended circuit diagram, be sure to add) 4. when a latter stage device exists in the signal path from this device to speaker, be sure to realize the dc cut is realized in a latter stage device. in addition, the above-mentioned measures are based on the assumption that the device itself, dc cut capacitor, and a latter stage device will be in a normal operation. therefor e, it is also necessary to implement measures based on the assumption of these part failures. warning for short circuit at speaker pins overcurrent breakdown, extraordinary heat, or package me lting is caused if a short circuit is made between two outputs, between output and power suppl y, and between output and ground, b ecause of high drive performance of the speaker amplifier output. in order to avoid such situations, be sure to implement one or more preventive measures from the followings. 1. adoption of a power supply with overcurrent protection circuit for the speaker amplifier. 2. provision of an overcurrent protection circuit in the speaker amplifier circuit. (this device does not have the circuit) 3. provision of a thermal shutdown circuit in the speaker amplifier section. (this device does not have the circuit) in addition, the above-mentioned measures are based on the assumption that overcurrent circuit or thermal shutdown circuit will work normally. therefore, it is also necessary to take measures based on the assumption of these part failures. moreover, consider the followings as well. - design the board so that speaker amplifier output is not short-circuited easily even if foreign body or solder bridge is present. - warning to customers of risk that may be caused by a short circuit of the speaker amplifier output.
YMF795 -33- volume level adjustment in monophonic sound and 4-sound generation the volume level outputted from dac varies depending on the number of the pronunciation. when one tone (*) is output from the fm sound source, output voltage amplitude from dac becomes 0.4125 vp-p. when multiple sounds are pronounced at the same time, output voltage amplitude varies depending on phase of each waveform, but when the waveforms with the same phase are overlapped, it becomes 0.825 vp-p in 2-tone, 1.2375 vp-p in 3-tone, and 1.65 vp-p in 4-tone. (*: this explanation is made on the assumption that volume adjustment (total level of carrier) of one tone is 0 db.) an assumption of 300 mw output. output power of 300 mw can be obtained from the speaker when rl is 8 ? and a voltage between spout1 and 2 is 1.55 vrms. at this time, btl output amplitude becomes 1.552 1.414=4.38 vp-p, and eq3 pin is 4.38/3.8=1.15 vp-p. (gain with the speaker amplifier is +11.6 db= 3.8 times.) assurance of volume level in monophonic sound. ?gain adjustment in the eq amplifier section? is recommended as a way to assure the volume level in monophonic sound. the gain depends on the resistance ratio between r1 and r2, and gain is equal to r2/r1. the gain of 3 times to 4 times is recommended. + - dac r1 vref fm vol hp vol hpout eq1 eq2 eq3 r2 sp vol btl driver +11.6db spout1 spout2 rl=8 ? fm sound source
YMF795 -34- example of the recommended level adjustment in all the system turn down either fm or sp volume a little as a default (-3 db to -6 db or so). this is made for previously assuring a volume of which gain is increased, because either volume may be controlled by user eq amplifier gain of 3 times to 4 times or so is r ecommended to secure the output level to some extent in monophonic sound. (for example, r1=22 k ? , r2=82 k ? ). when monophonic sound is generated in this condition (fm volume as 0db), eq1 is 0.4125 vp-p, and if gain of the eq amplifier is four times, eq3 becomes 1.65 vp-p. when -4 db is given by spvol, voltage between spout1 and 2 becomes 3.96 vp-p, and resultantly 245 mw output power can be obtained with the speaker (rl=8 ? ). a level adjustment of 4-sound simultaneous generation when normal music is played back, the amplitude of dac seldom swings to 1.65 vp-p. therefore, the same gain settings as that of monophonic sound can be made but if distortion of its sound is a little significant, turn down the gain of eq amplif ier or adjust the fm and/or sp volume. a level adjustment of hpout adjust the gain outside the lsi to increase gain of the hpout side.
YMF795 -35- sound quality co rrection circuit sound quality and gain can be corrected by using an external circuit connected to eq1 to 3 pins. the internal circuit configuration of eq1 to 3 pin and example of the external circuit are as follows. gain and filter characteristic can be controlled by a value of c1, c2, r1, and r2. gain = r2 / r1. the recommended values: r1 = 22 k ? and r2 = 82 k ? (gain = 3.7 times). filter cutoff frequency of f1 and f2 is: f1 = 1/ (2 r1c1). f2 = 1/ (2 r2c2). if c1 = 0.022 f and c2 = 120 pf, the cutoff frequency of f1 = 330 hz and f2 = 16 khz. moreover, the circuit enclosed with the dotted line is required when mixing with analog signal from ain is desired. the level adjustment for mixing depends on the resistance ratio r2/rx of rx and r2. the value of rx should be 82 k ? when mixing of amplitude of one time is required. f1 f2 gain1 gain1 -3db gain freq + vref - eq2 eq3 fm vol eq1 r1 r2 c2 c1 rx c3 ain
YMF795 -36- using a resister r3 can obtain the following frequency characteristic. gain1= (r2+r3) /r1. gain2=r3/r1. filter cutoff frequency of f1 and f2 is: f1=1/ (2 r1c1). f2=1/ (2 r2c2). f1 f2 gain1 gain1-3db gain freq + vref - eq2 eq3 fm vol eq1 r1 r2 c2 c1 r3 gain2
YMF795 -37- serial i/f specifications YMF795 is controlled by the three serial interface lines of sclk, sync, and sdin. relation between sdin and sclk the lsi takes in the value of sdin at the rising edge of sclk. input the sdin so that setup/hold time is assured with respect to the rising edge of sclk. (for details of timing specification, see ?4. ac characteristics? in ?electric characteristics?) about sdin the above figure has the period at which no data is transferred between index data and control data, but this period is not necessarily required. data of 24-bit can be transferred in succession. when transfer in 8 bits is required, divide the control data in two of high-order 8 bits and low-order 8 bits. the interval between the first high-order 8 bits and the next low-order 8 bits transfer is not especially defined. however, if excessive interval is given, time taken to complete one transfer becomes long. pay attention so that fifo does not become empty when writing the mu sical score data into the fifo. about sync both type1 and type2 in the above figure are available. the lsi considers the rising edge of sync as the completion of one data transfer.. the lsi sees sdin for 24sclk before the rising edge of sync as valid data. (sdin for 16sclk are valid data when only control data is transferred.) the length of the period of ?h? is not especially defined, but for the waveform of type 2, control so that the period of ?l? is assured at least 100 ns. malfunction may be caused when a rising edge of sync comes close to a rising edge of sclk. consider so that a rising edge of sclk does not generate within 50ns with respect to a rising edge of sync. about the data transfer only control data. when the sdin for sclk16 is input between a rising edge of sync and the next rising edge of sync, the lsi judges it as the musical score data ($00h) to take it in. use this transfer when transferring musical score data fast. sclk 8 clk 16 clk sync type1 sdin msb lsb msb lsb index data (8bit) control data (16bit) 6 7 1 0 15 1 0 msb 6 7 sync type2
YMF795 -38- electrical characteristics 1. absolute maximum ratings parameter symbol min. max. unit supply voltage (analog) avdd -0.3 4.6 v s upply voltage (digital) dvdd -0.3 4.6 v analog input voltage v ina -0.3 avdd+0.3 v digital input voltage v ind -0.3 dvdd+0.3 v storage temperature t stg -50 125 c note) dvss = avss= spvss = 0v 2. recommended operating conditions parameter symbol min. typ. max. unit operating voltage (analog) avdd 3.0 3.3 3.6 v operating voltage (digital) dvdd 3.0 3.3 3.6 v operating ambient temperature t op -40 25 85 c note) dvss = avss = spvss = 0v 3. dc characteristics parameter symbol condition min. typ. max. unit high-level input voltage v ih 0.7 dvdd - - v low-level input voltage v il - - 0.2 dvdd v high-level output voltage v oh i out = -1ma 0.8 dvdd - - v low-level output voltage v ol i out = 1ma - - 0.4 v schmitt width vsh 1.0 v input leakage current il -10 10 a input capacity ci 10 pf note) t op =-40 to 85c, dvdd=3.30.3v, capacitor load=50pf
YMF795 -39- 4. ac characteristics conditions: input signal of v ih =0.8dvdd, v il =0.1dvdd. timing measurement at v ih =0.7dvdd, v il =0.2dvdd. 4-1. clk_i ,reset parameter symbol min. typ. max. unit clk_i clock period tcclk_period 35.8 ns clk_i ?l? pulse width tcclk_low 12 ns clk_i ?h? pulse width tcclk_high 12 ns /rst active ?l? pulse width trst_low 100 clk_i sclk start delay time (after /rst inactive) trst2clk 64 clk_i note) t op =-40 to 85c, dvdd=3.30.3v, capacitor load=50pf ? clk_i? indicates the number of clocks inputted through the clk_i pin. clk_i duty hardware reset
YMF795 -40- 4-2. serial interface parameter symbol min. typ. max. unit sclk clock period tsclk_period 430 ns sclk ?l? pulse width tsclk_low 200 ns sclk ?h? pulse width tsclk_high 200 ns sclk rise time trise_sclk 20 ns sclk fall time tfall_sclk 20 ns sync ?h? pulse width tsync_high 100 - ns sync rise time trise_sync 20 ns sync fall time tfall_sync 20 ns sync delay time tdelay_sync 0 ns sync ?l? pulse width sync_low 100 ns sync sclk setup time tsetup_sync 50 ns sdin setup time tsetup_sdin 50 ns sdin hold time thold_sdin 50 ns sdin rise time trise_din 20 ns sdin fall time tfall_din 20 ns note) t op =-40 to 85c, dvdd=3.30.3v, capacitor load=50pf
YMF795 -41- 5. power consumption parameter min. typ. max. unit digital part in n ormal operation 550 2200 a analog part without sound generation 10 13 ma analog part at output 300mw , 8 ? load 186 ma in power-down mode 0.1 1 a note) t op =-40 to 85c, dvdd= avdd = 3.30.3v, capacitor load=50pf 6. analog characteristics sp amplifier parameter min. typ. max. unit gain setting (fixed) 1.9 times minimum resister load (rl) 8 ? maximum output voltage amplitude (rl=8 ? ) 5.5 vp-p maximum output power (rl=8 ? , thd+n 1.0%) 500 mw thd + n (rl=8 ? , f=1khz, 300mw output) 0.025 % noise level without signal (a-filter) -90 dbv note) t op =25c, dvdd = avdd = 3.3v eq amplifier parameter min typ max. unit gain setting range 30 db maximum output voltage amplitude 3.0 vp-p thd + n ( f=1khz) 0.05 % noise level without signal (a-filter) -90 dbv input impedance 10 m ? feedback resistance eq2-eq3 20 k ? note) t op =25c, dvdd = avdd = 3.3v sp volume parameter min typ max unit volume setting range -30 0 db volume step width 1 db decay rate in mute 80 db note) t op =25c, dvdd = avdd = 3.3v
YMF795 -42- fm volume parameter min typ max unit volume setting range -30 0 db volume step width 1 db decay rate in mute 80 db minimum load resistance 20 k ? maximum output voltage amplitude 3.0 vp-p output impedance 300 600 ? note) t op =25c, dvdd = avdd = 3.3v hp volume parameter min typ max unit volume setting range -30 0 db volume step width 1 db decay rate in mute 80 db minimum load resistance 20 k ? maximum output voltage amplitude 3.0 vp-p output impedance 300 600 ? note) t op =25c, dvdd = avdd = 3.3v vref parameter min typ max unit vref voltage 0.5avdd v note) t op =25c, dvdd = avdd = 3.3v dac parameter min typ max unit resolution 12 bit full-scale analog output (*1) 1.65 vp-p thd+n (f= 1khz) 0.5 % noise level without signal (f=400hz to 20khz) -90 dbv frequency characteristic (f=50hz to 20khz) -3.0 (2*) +0.5 db note) t op =25c, dvdd = avdd = 3.3v *1: when four fm tones are simultaneously generated in the same phase. *2: degradation of high-frequency response due to aperture effect.
YMF795 -43- general description of fm sound generator ?fm? stands for frequency modulation. the fm sound generator utilizes the higher harmonic wave produced by the frequency modulation for synthesis of the musical sounds with the use of this fm system enables a comparatively simple circuit to produce such waveform that has a harmonic wave including disharmonious sounds, it is possible to create a wide range of sounds from the synthesized sounds of the natural musical instruments to the electronic sounds. the diagram below shows the most basic configuration of the fm system. the "operator" refers to the section where a sine wave is generated and the combination of the operators is called "algorithm". the operator in the front stage is called "modulator" and that in the rear stage "carrier". each operator is capable of setting the frequency and the envelope waveform. the configuration in the above diagram can be expressed in the formula as follows. fm(t) = a sin( ct + b sin mt ) a : amplitude of the carrier. b : amplitude of the modulator. c : angle frequency of the carrier m : angle frequency of the modulator in addition, a system called "feedback fm" is available to create a wider range of sounds. in this system, the frequency modulation is fed back as shown in the diagram in the following page. b is called "feed-back ratio". using the feed-back fm function, it is possible to produce the strings type sounds. m phase generator operator 1 : modulator i operator 2 : carrier c f sin wave table c phase generator a sin wave table envelope generator envelope generator
YMF795 -44- external dimensions
YMF795

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