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1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. features fully compatible with pc card standard & cfa(compact flash association) standard. support 3 variations of mode access ? i/o card mode ? memory card mode ? true- ide mode +5.5v / +3.0v single power supply. internal error correction logic ? data interleave to 2 for each 256 bytes. ? error correction of 1 byte random error per 128 bytes of data. ? automatic on-the-? y, in-buffer error correction. compatible with all pc card service and socket service. integrated pc card attribute memory of 256 bytes(cis). 4 pc card function register support. support host-side write protect. automatic wake up from power-down on host reset or command write. sector data transfers without microprocessor intervention. operation environment ? temperature 0c ~ 65c ? humidity 8% ~ 95% compactflash tm card description the wedc compactflash? card consists of a compactflash? controller, which supports toshiba/ samsung nand type flash. the compactflash? card meets cfa speci? cation v1.4, and provides error correcting code (ecc) reliability to detect and correct errors automatically. * this product is subject to change without notice. notes: compactflash? is a trademark of sandisk corporation and is licensed royalty- free to the cfa, which in turn will license it royalty-free to cfa members. cfa: compactflash? association. product types card density model no. 32mb 7p032cfa80xxc25 64mb 7p064cfa80xxc25 128mb 7p128cfa80xxc25 256mb 7p256cfa80xxc25 512mb 7p512cfa80xxc25 1024mb 7p1024cfa80xxc25 2048mb 7p2048cfa80xxc25 4096mb 7p4g0cfa80xxc25 xx = housing 00 = wedc logo 01 = no logo
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. block diagram d0 to d15 host interface bvd2/1spkr/dasp# a0 to a10 ce1#, ce2# oe#, atasel# we# iord# controller control signal fce/7..01 flash memory data bus fad [7:0]/fbd[7:0] iowr# reg# reset/reset# csel# rdy/bsy#/ireq#/intrq wp/iois16# inpack# bvd1/stschg#/pdiag# wait#/iordy
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. pin assignments and pin type pc card memory mode pc card i/o mode true ide mode 4 pin num signal name pin type in ,out type pin num signal name pin type in ,out type pin num signal name pin type in ,out type 1 gnd ground 1 gnd ground 1 gnd ground 2 d03 i/o i1z,oz3 2 d03 i/o i1z,oz3 2 d03 i/o i1z,oz3 3 d04 i/o i1z,oz3 3 d04 i/o i1z,oz3 3 d04 i/o i1z,oz3 4 d05 i/o i1z,oz3 4 d05 i/o i1z,oz3 4 d05 i/o i1z,oz3 5 d06 i/o i1z,oz3 5 d06 i/o i1z,oz3 5 d06 i/o i1z,oz3 6 d07 i/o i1z,oz3 6 d07 i/o i1z,oz3 6 d07 i/o i1z,oz3 7 ce1# i i3u 7 ce1# i i3u 7 cso# i i3z 8 a10 i i1z 8 a10 i i1z 8 a10 2 i i1z 9 oe# i i3u 9 oe# i i3u 9 ata# sel i i3u 10 a09 i i1z 10 a09 i i1z 10 a09 2 i i1z 11 a08 i i1z 11 a08 i i1z 11 a08 2 i i1z 12 a07 i i1z 12 a07 i i1z 12 a07 2 i i1z 13 v cc power 13 v cc power 13 v cc power 14 a06 i i1z 14 a06 i i1z 14 a06 2 i i1z 15 a05 i i1z 15 a05 i i1z 15 a05 2 i i1z 16 a04 i i1z 16 a04 i i1z 16 a04 2 i i1z 17 a03 i i1z 17 a03 i i1z 17 a03 2 1 i1z 18 a02 i i1z 18 a02 i i1z 18 a02 i i1z 19 a01 i i1z 19 a01 i i1z 19 a01 i i1z 20 a00 i i1z 20 a00 i i1z 20 a00 i i1z 21 d00 i/o i1z, oz3 21 d00 i/o i1z, oz3 21 d00 i/o i1z, oz3 22 d01 i/o i1z, oz3 22 d01 i/o i1z, oz3 22 d01 i/o i1z, oz3 23 d02 i/o i1z, oz3 23 d02 i/o i1z, oz3 23 d02 i/o i1z, oz3 24 wp o ot3 24 iois16# o ot3 24 iois16# o on3 25 cd2# o ground 25 cd2# o ground 25 cd2# o ground 26 cd1# o ground 26 cd1# o ground 26 cd1# o ground 27 d11 1 i/o i1z,oz3 27 d11 1 i/o i1z,oz3 27 d11 1 i/o i1z,oz3 28 d12 1 i/o i1z,oz3 28 d12 1 i/o i1z,oz3 28 d12 1 i/o i1z,oz3 29 d13 1 i/o i1z,oz3 29 d13 1 i/o i1z,oz3 29 d13 1 i/o i1z,oz3 30 d14 1 i/o i1z,oz3 30 d14 1 i/o i1z,oz3 30 d14 1 i/o i1z,oz3 31 d15 1 i/o i1z,oz3 31 d15 1 i/o i1z,oz3 31 d15 1 i/o i1z,oz3 32 ce2 1 # i i3u 32 ce21# i i3u 32 cs1 1 # i i1z 33 vs 1 # o ground 33 vs 1 # o ground 33 vs 1 # o ground 34 iord# i i3u 34 iord# i i3u 34 iord# i i3z 35 iowr# i i3u 35 iowr# i i3u 35 iowr# i i3z 36 we# i i3u 36 we# i i3u 36 we 3 #i i3u 37 rdy/bsy o ot1 37 ireq o ot1 37 intrq o oz1 38 v cc power 38 v cc power 38 v cc power 39 csel# i i2z 39 csel# i i2z 39 csel# i i2u 40 vs2# o open 40 vs2# o open 40 vs2# o open 41 reset i i2z 41 reset i i2z 41 reset# i i2z 42 wait# o ot1 42 wait# o ot1 42 iordy o on1 43 inpack# o ot1 43 inpack# o ot1 43 inpack# o oz1 44 reg# i i3u 44 reg# i i3u 44 reg 3 #i i3u 45 bvd2 i/o i1u, ot1 45 spkr# i/o i1u, ot1 45 dasp# i/o i1u, on1
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. pin assignments and pin type (cont'd) pc card memory mode pc card i/o mode true ide mode 4 pin num signal name pin type in ,out type pin num signal name pin type in ,out type pin num signal name pin type in ,out type 46 bvd1 i/o i1u, ot1 46 stschg# i/o i1u, ot1 46 pdiag# i/o i1u, on1 47 d08 1 i/o 11z, oz3 47 d08 1 i/o i1z, oz3 47 d08 1 i/o i1z, oz3 48 d09 1 i/o 11z, oz3 48 d09 1 i/o i1z, oz3 48 d09 1 i/o i1z, oz3 49 d10 1 i/o 11z, oz3 49 d10 1 i/o 11z, oz3 49 d10 1 i/o i1z, oz3 50 gnd ground 50 gnd ground 50 gnd ground notes : 1. these signals are required only for 16 bit access and not required when installed in 8 bit systems. devices should allow for 3-state signals not to consume current. 2. should be grounded by the host. 3. should be tied to v cc by the host. 4. optional for ce + cards, required for compactflash storage cards.
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. electrical specifications absolute maximum rating symbol parameter rating units v cc power supply -0.3 to 6.0 v v in input voltage -0.3 to v cc +0.3 v v out output voltage -0.3 to v cc +0.3 v t stg storage temperature -40 to 125 c dc characteristics: i) recommended operating conditions: symbol parameter min. max. units v cc power supply 3.0 5.5 v v in input voltage 0 v cc v t opr operating temperature -20 65 c ii) general dc characteristics: symbol parameter conditions min typ max units i il input low current no pull up/down -1 1 a i ih input high current no pull up/down -1 1 a i oz tri-state leakage current -10 10 a c in input capacitance 4 pf c out output capacitance 4 pf c bid bi-direction capacitance 4 pf iii) dc electrical characteristics: symbol parameter min typ max units v il input low voltage 0.3v cc v v ih input high voltage 0.7v cc v v il schmitt input low voltage 1.22 v v ih schmitt input high voltage 2.08 v v ol output low voltage 0.4 v v oh output high voltage 2.3 1 v r i input pull up/down resistance 75 k?
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. ac characteristics: attribute memory read timing speci? cation attribute memory access time is de? ned as 300ns. detailed timing specs are shown in table below. speed version 300 ns item symbol ieee symbol min ns. max ns. read cycle time tc(r) t avav 300 address access time ta(a) t avqv 300 card enable access time ta(ce) t elqv 300 output enable access time ta(oe) t glqv 150 output disable time from ce tdis(ce) t ehqz 100 output disable time from oe tdis(oe) t ghqz 100 address setup time tsu(a) t avgl 30 output enable time from ce ten(ce) t elqnz 5 output enable time from oe ten(oe) t glqnz 5 data valid from address change tv(a) t axqx 0 note: all times are in nanoseconds. dout signi? es data provided by the compactflash storage card or cf+ card to the system. the ce# signal or both the oe# signal and the we# signal must be de-asserted between consecutive cycle operations. con? guration register (attribute memory) write timing speci? cation the card con? guration write access time is de? ned as 250ns. detailed timing speci? cations are shown in table below. speed version 250 ns item symbol ieee symbol min ns max ns write cycle time tc(w) t avav 250 write pulse width tw(we) t wlwh 150 address setup time tsu(a) t avwl 30 write recovery time trec(we) t wmax 30 data setup time for we tsu(d-weh) t dvwh 80 data hold time th(d) t wmdx 30 note: all times are in nanoseconds. din signi? es data provided by the system to the compactflash storage card or cf+ card. common memory read timing speci? cation item symbol ieee symbol min ns. max ns. output enable access time ta(oe) t glqv 125 output disable time from oe tdis(oe) t ghqz 100 address setup time tsu(a) t avgl 30 address hold time th(a) t ghax 20 ce setup before oe tsu(ce) t elgl 0 ce hold following oe th(ce) t gheh 20 wait delay falling from oe tv(wt-oe) t glwtv 35 data setup for wait release tv(wt) t qvwth 0 wait width time tw(wt) t wtlwth 350 (3000 for cf+) note: the maximum load on -wait# is 1 lsttl with 50pf total load. all times are in nanoseconds. dout signi? es data provided by the compactflash storage card or cf+ card to the system. the wait# signal may be ignored if the oe# cycle to cycle time is greater than the wait width time. the max wait wi dth time can be determined from the card information structure. the wait width time meets the pcmcia speci? cation of 12ps but is intentionally less in this speci? cati on.
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. ac characteristics (cont'd): i/o input (read) timing speci? cation item symbol ieee symbol min ns. max ns. data delay after iord td(iord) t iglqv 100 data hold following iord th(iord) t ighqx 0 iord width time tw(iord) t igligh 165 address setup before iord tsua(iord) t avigl 70 address hold following iord tha(iord) t ighax 20 ce setup before iord tsuce(iord) t eligl 5 ce hold following iord thce(iord) t igheh 20 reg setup before iord tsureg(iord) t rgligl 5 reg hold following iord threg(iord) t ighrgh 0 inpack delay falling from iord tdfinpack(iord) t iglial 045 inpack delay rising from iord tdrinpack(iord) t ighiah 45 iois16 delay falling from address tdfiois16(adr) t avisl 35 iois16 delay rising from address tdriois16(adr) t avish 35 wait delay falling from iord tdwt(iord) t iglwtl 35 data delay from wait rising td(wt) t wthqv 0 wait width time tw(wt) t wtlwth 350 (3000 for cf+) note: maximum load on wait#, inpack# and i0is16# is 1 lsttl with 50pf total load. all times are in nanoseconds. minimum time from wait# high to iord# high is onsec, but minimum iord# width must still be met. dout signi? es data provided by the compactflash storage card or cf+ card to the sys tem. wait width time meets pcmcia speci? cation of 12ps but is intentionally less in this spec. i/o output (write) timing speci? cation item symbol ieee symbol min ns. max ns. data setup before iowr tsu(iowr) t dviwh 60 data hold following iowr th(iowr) t iwhdx 30 iowr width time tw(iowr) t iwliwh 165 address setup before iowr tsua(iowr) t aviwl 70 address hold following iowr tha(iowr) t iwhax 20 ce setup before iowr tsuce(iowr) t eliwl 5 ce hold following iowr thce(iowr) t iwheh 20 reg setup before iowr tsureg(iowr) t rgliwl 5 reg hold following iowr threg(iowr) t iwhrgh 0 iois16 delay falling from address tdfiois16(adr) t avisl 35 iois16 delay rising from address tdriois16(adr) t avish 35 wait delay falling from iowr tdwt(iowr) t iwlwtl 35 iowr high from wait high tdriowr(wt) t wtjiwh 0 wait width time tw(wt) t wtlwth 350 (3000for cf+) note: the maximum load on wait#, inpack#, and i0is16# is 1 lsttl with 50pf total load. all times are in nanoseconds. minimum time from wait# high to iowr# high is onsec, but minimum iowr# width must still be met. din signi? es data provided by the system to the compactflash storage card or cf+ ca rd. the wait width time meets the pcmcia speci? cation of 12ps but is intentionally less in this speci? cation.
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. ac characteristics (cont'd): true ide mode i/o input (read) timing speci? cation item symbol ieee symbol min ns. max ns. data delay after iord td(iord) t iglqv 100 data hold following iord th(iord) t ighqx 0 iord width time tw(iord) t igligh 165 address setup before iord tsua(iord) t avigl 70 address hold following iord tha(iord) t ighax 20 ce setup before iord tsuce(iord) t eligl 5 ce hold following iord thce(iord) t igheh 20 i0is16 delay falling from address tdfiois16(adr) t avisl 35 i0is16 delay rising from address tdriois16(adr) t avish 35 note: the maximum load on -i0is16 is 1 lsttl with 50pf total load. all times are in nanoseconds. minimum time from wait# high to iord# high is 0 nsec, but minimum iord# width must still be met. dout signi? es data provided by the compactflash storage card or cf+ card to the system. true ide mode i/o output (write) timing speci? cation item symbol ieee symbol min ns. max ns. data setup before iowr tsu(iowr) t dviwh 60 data hold following iowr th(iowr) t iwhdx 30 iowr width time tw(iowr) t iwliwh 165 address setup before iowr tsua(iowr) t aviwl 70 address hold following iowr tha(iowr) t iwhax 20 ce setup before iowr tsuce(iowr) t eliwl 5 ce hold following iowr thce(iowr) t iwheh 20 i0is16 delay falling from address tdfiois16(adr) t avisl 35 i0is16 delay rising from address tdriois16(adr) t avish 35 note: the maximum load on -i0is16 is 1 lsttl with 50pf total load. all times are in nanoseconds. minimum time from wait# high to iowr# high is 0 nsec, but minimum iowr# width must still be met. din signi? es data provided by the system to the compactflash storage card or cf+ card.
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. package dimensions 4xr 0.5mm .1 (4xr.020 in . 004) 41.66mm .13(1.640 in . 005) 42.80mm .10(1.685 in . 004) 0.63mm .07(.025 in . 003) .01mm .07(.039 in . 003) 26 50 125 .99mm .05 (.039 in . 002) .01mm .07(.039 in . 003) 3.30mm .10 (.130 in . 004) 1.60mm .05 (.063 in . 002) 0.76mm .07(0.30 in . 003) m m 0 0 . 3 x 2 7 0 . n i 8 1 1 . x 2 ( . ) 3 0 0 m m 0 4 . 6 3 n i 3 3 4 . 1 ( 5 1 . . ) 6 0 0 2.44mm .07 (.096 in . 003) m m 8 7 . 5 2 x 2 5 1 0 . 1 x 2 ( 7 0 . . ) 3 0 0 m m 0 0 . 2 1 x 2 0 1 . n i 2 7 4 x 2 ( . ) 4 0 0 2.15mm .07 (.085 in x .003) optional configuration (see note) top view note: the optional notched con? guration was shown in the cf speci? cation rev. 1.0. in speci? cation rev. 1.2, the notch was removed for ease of tooling. this optional con? guration can be used but it is not recommended. physical specifications length: 36.40 0.15mm (1.433 .006in.) width: 42.80 0.10mm (1.685 .004in.) thickness (including label area) 3.3mm 0.10mm (.130 .004in)
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. part numbering guide wed 7p xxx cfa 80 xx c 25 wedc flash memory size compact flash commercial flash housing: 00 = wedc logo 01 = blank housing commercial temp speed
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs wed7pxxxcfa80xxc25 july 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. document title compactflash? card revision history rev # history release date status rev 0 initial release march 2005 final rev 1 1.1 added "ed" to part marking july 2005 final

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