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1998 data sheet m pd3729 mos integrated circuit the m pd3729 is a high-speed and high sensitive color ccd (charge coupled device) linear image sensor which changes optical images to electrical signal and has the function of color separation. the m pd3729 has 3 rows of 5000 pixels, and it is a 2-output/color type ccd sensor with 2 rows/color of charge transfer register, which transfers the photo signal electrons of 5000 pixels separately in odd and even pixels. therefore, it is suitable for 400 dpi/a3 high-speed color digital copiers and so on. features ? valid photocell : 5000 pixels 3 ? photocell's pitch : 10 m m ? line spacing : 40 m m (4 lines) red line-green line, green line-blue line ? color filter : primary colors (red, green and blue), pigment filter (with light resistance 10 7 lx?hour) ? resolution : 16 dot/mm (400 dpi) a3 (297 420 mm) size (shorter side) ? drive clock level : cmos output under 5 v operation ? data rate : 30 mhz max. (15 mhz/1 output) ? output type : 2 outputs in phase/color ? power supply : +12 v ? on-chip circuits : reset feed-through level clamp circuits voltage amplifiers ordering information part number package m pd3729d ccd linear image sensor 24-pin ceramic dip (400 mil) document no. s12883ej1v0ds00(1st edition) date published november 1998 n cp(k) printed in japan the information in this document is subject to change without notice. 5000 pixels 3 color ccd linear image sensor
m pd3729 2 block diagram 4 6 910 3 2 1 24 23 22 20 19 15 5 12 21 16 14 13 11 clb 1l gnd gnd v od 2 1 gnd (blue) tg1 (blue) tg2 (green) tg3 (red) v out 2 (blue, even) v out 1 (blue, odd) v out 3 (green, odd) v out 4 (green, even) v out 6 (red, even) v out 5 (red, odd) 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s4999 s5000 d129 d134 (green) photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s4999 s5000 d129 d134 (red) photocell transfer gate transfer gate ccd analog shift register ccd analog shift register d27 d128 s1 s2 s4999 s5000 d129 d134 rb fff f f f f f f f
m pd3729 3 pin configuration (top view) ccd linear image sensor 24-pin ceramic dip (400 mil) ? m pd3729d photocell structure diagram photocell array structure diagram (line spacing) m 10 m m 7 m m m 3 channel stopper aluminum shield blue photocell array 10 m m green photocell array 10 m m red photocell array 10 m m 4 lines (40 m) m 4 lines (40 m) m 1 v out 4 output signal 4 (green, even) 2 v out 6 output signal 6 (red, even) 3 v out 5 output signal 5 (red, odd) 4 gnd ground 5 v od output drain voltage reset gate clock 6 rb no connection 7 nc no connection 8 nc shift register clock 1 9 1 shift register clock 2 10 2 transfer gate clock 3 (for red) 11 tg3 ground 12 gnd 23 24 21 20 19 18 17 16 15 14 13 v out 3 v out 2 gnd clb 1l nc nc 2 1 tg1 tg2 output signal 3 (green, odd) output signal 2 (blue, even) ground reset feed-through level clamp clock last stage shift register clock 1 no connection no connection shift register clock 2 shift register clock 1 transfer gate clock 1 (for blue) transfer gate clock 2 (for green) 22 v out 1 output signal 1 (blue, odd) 5000 5000 5000 red green blue 1 1 1 f f f f f f f f f f
m pd3729 4 absolute maximum ratings (t a = +25 c) parameter symbol ratings unit output drain voltage v od C0.3 to +15 v shift register clock voltage v f 1 , v f 1l , v f 2 C0.3 to +15 v reset gate clock voltage v f rb C0.3 to +15 v reset feed-through level clamp clock voltage v f clb C0.3 to +15 v transfer gate clock voltage v f tg1 to v f tg3 C0.3 to +15 v operating ambient temperature t a C25 to +70 c storage temperature t stg C40 to +100 c caution exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. recommended operating conditions (t a = +25 c) parameter symbol min. typ. max. unit output drain voltage v od 11.4 12.0 12.6 v shift register clock high level v f 1h , v f 1lh , v f 2h 4.5 5.0 5.5 v shift register clock low level v f 1l , v f 1ll , v f 2l C0.3 0 +0.5 v reset gate clock high level v f rbh 4.5 5.0 5.5 v reset gate clock low level v f rbl C0.3 0 +0.5 v reset feed-through level clamp clock high level v f clbh 4.5 5.0 5.5 v reset feed-through level clamp clock low level v f clbl C0.3 0 +0.5 v transfer gate clock high level v f tg1h to v f tg3h 4.5 v f 1h note v f 1h note v transfer gate clock low level v f tg1l to v f tg3l C0.3 0 +0.5 v data rate 2f f rb C 2 30 mhz note when transfer gate clock high level (v f tg1h to v f tg3h ) is higher than shift register clock high level (v f 1h ), image lag can increase.
m pd3729 5 electrical characteristics t a = +25 c, v od = 12 v, f f rb = 1 mhz, data rate = 2 mhz, storage time = 10 ms, light source: 3200 k halogen lamp +c-500s (infrared cut filter, t = 1mm), input signal clock = 5 v p-p parameter symbol test conditions min. typ. max. unit saturation voltage v sat 1.5 2.0 C v saturation exposure red ser 0.32 lx ? s green seg 0.37 lx ? s blue seb 0.29 lx ? s photo response non-uniformity prnu v out = 1 v 6 18 % average dark signal note 1 ads1 light shielding 1.0 5.0 mv ads2 0.5 5.0 mv dark signal non-uniformity note 1 dsnu1 light shielding 2.0 5.0 mv dsnu2 1.0 5.0 mv power consumption p w 500 700 mw output impedance z o 0.3 0.5 k w response red r r 4.3 6.2 8.1 v/lx ? s green r g 3.8 5.4 7.0 v/lx ? s blue r b 4.7 6.8 8.9 v/lx ? s image lag note 1 il1 v out = 1 v 2.0 5.0 % il2 1.0 5.0 % offset level note 2 v os 4.0 5.0 6.0 v output fall delay time note 3 t d v out = 1 v 25 ns register imbalance ri v out = 1 v 0 4.0 % total transfer efficiency tte v out = 1 v, 95 98 % data rate = 30 mhz response peak red 630 nm green 540 nm blue 460 nm dynamic range note 1 dr11 v sat /dsnu1 1000 times dr12 v sat /dsnu2 2000 times dr21 v sat / s 1 2000 times dr22 v sat / s 2 4000 times reset feed-through noise note 2 rftn light shielding C500 +200 +500 mv random noise note 1 s 1 light shielding C 1.0 C mv s 2 C 0.5 C mv notes 1. ads1, dsnu1, il1, dr11 and dr21 show the specification of v out 1 and v out 2. ads2, dsnu2, il2, dr12 and dr22 show the specification of v out 3 to v out 6. 2. refer to timing chart 2 . 3. when the fall time of f 1l (t2) is the typ. value (refer to timing chart 2 ).
m pd3729 6 input pin capacitance (t a = +25 c, v od = 12 v) parameter symbol pin name pin no. min. typ. max. unit shift register clock pin capacitance 1 c f 1 f 1 9 500 800 pf 15 500 800 pf shift register clock pin capacitance 2 c f 2 f 2 10 500 800 pf 16 500 800 pf last stage shift register clock pin capacitance c f l f 1l 19 50 pf reset gate clock pin capacitance c f rb f rb 6 50 pf reset feed-through level clamp clock pin capacitance c f clb f clb 20 50 pf transfer gate clock pin capacitance c f tg f tg1 14 70 pf f tg2 13 70 pf f tg3 11 70 pf remark pins 9 and 15 ( f 1), 10 and 16 ( f 2) are each connected inside of the device.
m pd3729 7 timing chart 1 (for each color) note input the f rb and f clb pulses continuously during this period, too. 9 11 13 10 12 14 tg1 to 1 2 rb clb v out 1, 3, 5 v out 2, 4, 6 tg3 1 3 5 7 15 17 19 21 23 25 2 4 6 8 16 18 20 22 24 26 optical black (96 pixels) invalid photocell (6 pixels) valid photocell (5000 pixels) invalid photocell (6 pixels) 28 30 120 122 27 29 119 121 123 125 127 129 124 126 128 130 131 132 5126 5128 5130 5132 5125 5127 5129 5131 5133 5135 5137 5134 5136 5138 1l note note f f f f f f f
m pd3729 8 timing chart 2 (for each color) f tg1 to f tg3, f 1, f 2 timing chart 90 % t10 t1' t5 t6 t4 t3 t2' t d v os rftn 10 % t11 t9 t8 t7 t1 t2 90 % 1 2 1l rb clb v out 1 to v out 6 10 % 90 % 10 % 10 % 90 % 10 % 90 % 10 % f f f f f 1 t15 tg1 to tg3 t13 90 % 10 % t12 t14 90 % t16 2 f f f f
m pd3729 9 symbol min. typ. max. unit t1, t2 0 50 ns t1, t2 0 5 ns t3 20 50 ns t4 20 100 C ns t5, t6 0 20 ns t7 20 150 ns t8, t9 0 20 ns t10 C10 note 1 +50 C ns t11 C5 note 2 +50 ns t12 5000 10000 ns t13, t14 0 50 ns t15, t16 900 1000 ns notes 1. min. of t10 shows that the f rb and f clb overlap each other. 2. min. of t11 shows that the f 1l and f clb overlap each other. f 1, f 2 cross points f 1l, f 2 cross points remark adjust cross points ( f 1, f 2) and ( f 1l, f 2) with input resistance of each pin. rb clb 90 % 90 % t10 f f 1l clb 90 % 90 % t11 f f 1 2 2 v or more 2 v or more 2 1l 2 v or more 0.5 v or more f f f f
m pd3729 10 definitions of characteristic items 1. saturation voltage: v sat output signal voltage at which the response linearity is lost. 2. saturation exposure: se product of intensity of illumination (i x ) and storage time (s) when saturation of output voltage occurs. 3. photo response non-uniformity: prnu the output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. this is calculated by the following formula. 4. average dark signal: ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula. prnu (%) = x = x j : output voltage of valid pixel number j d x d x : maximum of ? x j - x ? x 5000 s j=1 5000 x j 100 x register dark dc level v out d x ads (mv) = d j : dark signal of valid pixel number j 5000 s j=1 5000 d j
m pd3729 11 5. dark signal non-uniformity: dsnu absolute maximum of the difference between ads and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula. 6. output impedance: z o impedance of the output pins viewed from outside. 7. response: r output voltage divided by exposure (ix ? s). note that the response varies with a light source (spectral characteristic). 8. image lag: il the rate between the last output voltage and the next one after read out the data of a line. ads dsnu register dark dc level v out v 1 il (%) = 100 v out v out f tg light v out on off v 1 d j : dark signal of valid pixel number j dsnu (mv) : maximum of ? d j - ads ? j = 1 to 5000
m pd3729 12 9. register imbalance: ri the rate of the difference between the averages of the output voltage of odd and even pixels, against the average output voltage of all the valid pixels. n : number of valid pixels v j : output voltage of each pixel 10. random noise: s random noise s is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). v i : a valid pixel output signal among all of the valid pixels for each color this is measured by the dc level sampling of only the signal level, not by cds (correlated double sampling). v 1 v 100 v 2 ? ? line 2 line 100 line 1 v out s (mv) = , v = s i=1 100 (v i ?v) 2 s i=1 100 v i 100 100 1 ri (%) = 2 n j = 1 n 2 (v 2j ?1 v 2j ) 1 n j = 1 n v j 100 ? ?
m pd3729 13 standard characteristic curves dark output temperature characteristic storage time output voltage characteristic (t a = +25 ?) operating ambient temperature t a (?) storage time (ms) 8 4 2 1 0.5 0.25 0.1 10 0 20304050 relative output voltage relative output voltage 2 1 0.2 0.1 1510 100 b b g g r 80 60 40 20 0 400 500 600 700 800 wavelength (nm) response ratio (%) total spectral response characteristics (without infrared cut filter) (t a = +25 ?)
m pd3729 14 application circuit example remark the inverters shown in the above application circuit example are the 74ac04. +5 v 10 w + 0.1 f 47 f/25 v b1 b3 b2 b6 b4 b5 1 2 3 4 5 6 7 8 9 10 11 12 v out 4 v out 6 v out 5 gnd v od 1l nc nc 1 2 tg3 gnd v out 3 v out 1 v out 2 gnd clb nc nc 2 1 tg1 tg2 rb 18 17 16 15 14 13 24 23 22 21 20 19 47 w 2 w 2 w 2 w 2 w 2 w 2 w 2 w 47 w 47 w 1 2 tg rb pd3729 clb 1l +12 v + 0.1 f 10 f/16 v +5 v + 0.1 f 10 f/16 v m m m m mm m f f f ff f f f f f f f f f f f +12 v 110 w 4.7 k w 47 f/25 v 2sa1005 2sc945 1 k w 47 w + 0.1 f ccd v out b1 to b6 equivalent circuit m m
m pd3729 15 package drawing 2.0 0.3 4 0.25 0.05 name dimensions refractive index glass cap 67.0 8.5 1.0 1.5 1 the 1st valid pixel the edge of the package 2 the 1st valid pixel the center of the pin1 3 the surface of the chip the top of the glass cap (reference) 4 the bottom of the package the surface of the chip 24d-1ccd-pkg1-1 68.0 0.4 10.03 0.15 10.6 0.6 9.4 0.7 2 0.46 0.05 1.27 0.05 3.50 0.5 0.97 0.3 3.30 0.32 (4.33) (2.33) the 1st valid pixel 2.54 10.16 27.94 ccd linear image sensor 24-pin ceramic dip (400mil) 3 (unit : mm) 1
m pd3729 16 recommended soldering conditions when soldering this product, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. for more details, refer to our document "semiconductor device mounting technology manual"(c10535e) . type of through-hole device m pd3729d: ccd linear image sensor 24-pin ceramic dip (400 mil) process conditions partial heating method pin temperature: 300 c or below, heat time: 3 seconds or less (per pin)
m pd3729 17 [memo]
m pd3729 18 [memo]
m pd3729 19 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out- pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd3729 [memo] the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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