specifications package outlines [dimensions in mm] TFG-756DVX7 full dip double-sealed vcxo crystal clock oscillator features cmos logic output dip-14 pin package compatible hermetically double-sealed metal package voltage controlled oscillator table a absolute maximum ratings supply voltage input voltage output voltage output current storage temperature v cc v in v o i o t stg parameter symbol rating -0.5 to +7.0 v -0.5 to v cc +0.5 v -0.5 to v cc +0.5 v 20 ma -40 to +85 c *1 inclusive of calibration tolerance at +25 c, operating temperature, operating voltage range. *2 rise time (0 to +4.75v) of vcc > 150 s parameter 40 to 100 mhz 50 ppm max. 150 ppm min. +2.5 v 2.5v 0 c to +70 c +5.0 v 5% see table a (max.) v oh =vcc-0.5 v min. / v ol =+0.5 v max. 40 to 60 % see table a (max.) 30 pf max. 4 ms max. frequency frequency stability pullability control voltage range operating temperature supply voltage supply current output voltage symmetry rise/fall time load capacitance start-up time fo ? f/fo vcont topr vcc icc v oh v ol sym tr/tf c l t st TFG-756DVX7 (*1) at vcont=0 to +5.0v, ref=+2.5 v dc, pin #1 dc, pin #14 vcc=+5.25v i oh =-4ma pin #8 i ol =+4ma at 50% vcc at 20% to 80% vcc conditions pin #1 #7 # 8 #14 co nne c ti on co ntr o l v o lta ge g nd / cas e out p u t vcc d c 13.2 max. 4.0 min. 4.57 7.62 7.11 max. 20.8 max. marking 12.19 solder dip 15.24 #14 #8 #1 0.79 ?0.46 #7 toyocom mhz japan model frequency date code denotes pin #1 location test circuit see test circuit page test-7 (2001. 2.) 40 fo fo 60 freq. (mhz) icc (ma) tr,tf (ns) 60 < fo fo 100 60 4 50 3
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