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vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 2 of 12 document revision history 1: document revision from to date description changed by checked by a a b b c 2000.09.19 2001.08.20 2004.02.25 first release item 1 was updated: 1.) (whole document) description of the module was changed from ? MGLS-19264-HT-LED03? to ?MGLS-19264-HT-LED03 or mgls-19264-ht-g-hv-led3g.? item 1 was updated: (based on test specification: vl-ts-mgls19264-xx, rev. f, 2003 .09.20). 1.) (page 5, figure 1) module specification was changed from rev. 0 to rev. 1. 2.) (page 8, table 5) supply voltage (lcd), supply current (logic & lcd), and supply current (lcd) & vled were updated. philip cheng philip cheng helen he k.p.ho michael tse yu hao
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 3 of 12 contents page no. 1. general description 4 2. mechanical specifications 4 3. interface signals 6 4. absolute maximum ratings 7 4.1 electrical maximum ratings (ta=25 dd against v0 12
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 4 of 12 varitronix limited specification of lcd module type item no.: mgls19264-07 1. general description x 192x 64 dot stn positive yellow transflective dot matrix lcd module. x viewing direction: 6 o?clock. x driving scheme: 1:64 multiplexed drive, 1/9 bias. x ?hitachi? hd61202ufs flat pack or equivalent lcd column drivers. x ?hitachi? hd61203ufs flat pack or equivalent lcd segment driver. x yellow-green led03 backlight 2. mechanical specifications the mechanical detail is shown in fig. 1 and summarized in table 1 below. table 1 parameter specifications unit outline dimensions 100.0(w) x 60.0(h) x 13.0(d)max. mm viewing area 84.0(w) x 31.0(h) mm active area 78.67(w) x 26.19(h) mm display format 192(horizontal) x 64 (vertical) dots dot size 0.36(w) x 0.36(h) mm dot spacing 0.05(w) x 0.05(h) mm dot pitch 0.41(w) x 0.41(h) mm weight: tbd grams
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 5 of 12 figure 1: module specification
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 6 of 12 3. interface signals table 2 pin no. symbol description 1 /csa chip selection a: in order to interface data for input or output. 2 /csb chip selection b: in order to interface data for input or output. 3 vss ground 4 vdd power supply for logic (+5v) 5 v0 power supply for lcd driver 6 d/i data or instruction select input d/i=high: display ram data on d0-d7. d/i=low: display instruction data on d0-d7. 7 r/w read/write control signal input pin. r/w = high: cpu to read data appearing at db0 to db7. r/w = low: data of db0 to db7 is latched at the falling edge of e. 8 e chip enable. e = high: read data appears at db0 to db7 as e is at high level. e = low: write data of db0 to db7 is latched at the fall of e. 9 db0 data input/output (lsb). 10 db1 data input/output. 11 db2 data input/output. 12 db3 data input/output. 13 db4 data input/output. 14 db5 data input/output. 15 db6 data input/output. 16 db7 data input/output (msb). - a anode of optional led backlight. - k cathode of optional led backlight.
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 7 of 12 4. absolute maximum ratings 4.1 electrical maximum ratings(ta = 25 oc) table 3 parameter symbol min. max. unit power supply voltage (logic) vdd?vss -0.3 +7.0 v power supply voltage (lcd drive) vlcd =vdd?v0 -0.3 +17.0 v input voltage vin -0.3 vdd+0.3 v note: the modules may be destroyed if they are used beyond the absolute maximum ratings. all voltage values are referenced to gnd = 0v. 4.2 environmental condition table 4 operating temperature (topr) storage temperature (tstg) item min. max. min. max. remark a mbient temperature -20 q c +70 q c -30 q c +80 q c dry h umidity 95% max. rh for ta d 40q c < 95% rh for ta > 40 q c no condensation v ibration (iec 68-2-6) cells must be mounted on a suitable connector frequency: 10 a 55 hz amplitude: 0.75 mm duration: 20 cycles in each direction. 3 directions shock (iec 68-2-27) h alf-sine pulse shape pulse duration: 11 ms peak acceleration: 981 m/s 2 = 100g number of shocks: 3 shocks in 3 mutually perpendicular axes. 3 directions
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 8 of 12 5. electrical specifications 5.1 typical electrical characteristics at ta = 25 q c, vdd = 5v r 5%, vss=0v. table 5 parameter symbol conditions min. typ. max. unit supply voltage (logic) vdd ?vss 4.75 5.00 5.25 v supply voltage (lcd) vlcd =vdd ?v0 vdd = 5v, note (1) 14.5 15.0 15.5 v v ih ?high? level, note (2) 2.0 - vdd v input signal voltage (note 2) v il ?low? level, note (2) 0 - 0.8 v character mode, vdd = 5v - 3.8 5.7 ma supply current (logic & lcd) idd checker board mode, vdd = 5v - 4.0 6.0 ma character mode, vdd = 5v, note (1) - 3.3 5.0 ma supply current (lcd) i0 checker board mode, vdd = 5v - 3.5 5.3 ma supply voltage of yellow-green led03 backlight vled03 forward current =140ma number of led dies =28 3.9 4.1 4.3 v note (1): there is tolerance in optimum lcd driving voltage during production and it will be within the specified range. note (2): applies to /csa, /csb, e, r/w, db0~db7.
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 9 of 12 5.2 timing specifications at ta = -20 q c to +70 q c, vdd = +5v r 5%, vss = 0v. refer to fig. 2 & 3 , the bus timing diagram. table 6 parameter symbol min. typ. max. unit e cycle time t cyc 1000 - - ns e high level width p weh 450 - - ns e low level width p wel 450 - - ns e rise time tr - - 25 ns e fall time tf - - 25 ns address setup time t as 140 - - ns address hold time t ah 10 - - ns data setup time t dsw 200 - - ns data delay time t ddr - - 320 ns data hold time (write) t dhw 10 - - ns data hold time (read) t dhr 20 - - ns
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 10 of 12 figure 2: mpu w r ite t i m i ng
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 1 1 of 12 figure 3: mpu read t i m i ng
vl-fs-mgls19264-07 rev . c (mgls12864-ht-led03) feb/2004 p age 12 of 12 5.3 t i ming diagram of vdd against v0. power on sequence shall m eet the requirem e nt of figure 4, the tim ing diagram of vdd against v0. vdd 0v 0v v0 95% 50ms(typical) logic supply voltage lcd supply voltage figure 4: t i m i ng diagram of vdd against v0. ?v aritronix lim ited reserves the right to change this specification.? f ax:(852) 2343-9555. url:http://www .varitronix.com - end -

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