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| 1. general description the pcu9661 is an advanced single master mode i 2 c-bus controller. it is a fourth generation bus controller designed for data intensive i 2 c-bus data transfers. it has a transmit only transfer rate of up to 5 mbi ts/s using the new ultra fast-mode (ufm) bus with push-pull topology. the serial channel has a generous 4352 byte data buffer which makes the pcu9661 the ideal companion to any cpu that needs to transmit and receive large amounts of serial data with minimal interruptions. the pcu9661 is an 8-bit parallel-bus to i 2 c-bus protocol converter. it can be configured to communicate with up to 64 slaves in one se rial sequence with no intervention from the cpu. the controller also has a sequence lo op control feature that allows it to automatically retransmit a stored sequence. its onboard oscillator and pl l allow the controller to g enerate the cl ocks for the i 2 c-bus and for the interval timer used in sequence looping. this feature greatly reduces cpu overhead when data refresh is required in fault tolerant applications. an external trigger input allows data synchronization with external events. the trigger signal controls the rate at which a stor ed sequence is re-transmitted over the i 2 c-bus. error reporting is handled at the transaction level, channel level, and controller level. a simple interrupt tree and interrupt masks allow further customization of interrupt management. the controller parallel bus interface runs at 3.3 v and the i 2 c-bus i/os logic levels are referenced to a dedicated v dd(io) input pin with a range of 3.0 v to 5.5 v. 2. features and benefits ? parallel-bus to i 2 c-bus protocol converter and interface ? 5 mbit/s unidirectional data transfer ultra fast-mode (ufm) channel (push-pull driver) ? internal oscillator trimmed to 1 % accuracy reduces ex ternal components ? 4352-byte ufm channel buffer ? three levels of reset: software channel rese t, global software reset on parallel bus, global hardware reset pin ? communicates with up to 64 slaves in one serial sequence ? sequence looping wit h interval timer ? jtag port available for boundary scan testing during board manufacturing process ? trigger input synchronizes serial comm unication exactly with external events ? maskable interrupts ? operating supply voltage: 3.0 v to 3.6 v (device and host interface) pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller rev. 1 ? 12 september 2011 product data sheet
pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 2 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller ? i 2 c-bus i/o supply voltage: 3.0 v to 5.5 v ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? esd protection exceeds 8000 v hbm per jesd22-a114 and 1000 v cdm per jesd22-c101 ? packages offered: lqfp48 3. applications ? add ufm i 2 c-bus port to controllers/processors that do not have one ? add additional ufm i 2 c-bus ports to controllers/proce ssors that need multiple i 2 c-bus ports ? converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire printed-circuit board ? entertainment systems ? led matrix control ? data intensive i 2 c-bus transfers 4. ordering information table 1. ordering information type number topside mark package name description version PCU9661B pcu9661 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 3 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 5. block diagram fig 1. block diagram tck trst tms tdi tdo 002aag233 v dd(io) oscillator ctrlintmsk ctrlpreset interrupt control buffer control control block ce wr rd int reset power-on/ power-down reset d0 d1 d2 d3 d4 d5 d6 d7 v dd a0 a1 a2 a3 a4 a5 pcu9661 channel 2 ufm i 2 c-bus control status2_[n] control ctrlstatus usda2 uscl2 4352-byte buffer bus interface trig a6 a7 dc/dc regulator pll transel tranofs slatable tranconfig bytecount intmsk data framecnt refrate sclper sdadly chstatus mode device_id ctrlrdy preset jtag pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 4 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration for lqfp48 PCU9661B d6 d7 a0 v ss a1 a2 a3 v dd v ss v ss a4 n.c. a5 n.c. a6 n.c. a7 n.c. v dd v ss tck d5 tdi d4 tdo v dd v dd v ss v ss d3 int d2 usda2 v dd uscl2 v ss v ss(io) v dd(io) d1 d0 002aag234 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 tms ce trig reset trst v dd rd wr table 2. pin description symbol pin type description a0 3 i address inputs: selects the bus controller?s internal registers and ports for read/write operations. address is registered when ce is low and whether wr or rd transitions low. a0 is the least significant bit. a1 4 i a2 5 i a3 6 i a4 9 i a5 10 i a6 11 i a7 12 i d0 37 i/o data bus: bidirectional 3-state data bus used to transfer commands, data and status between the bus controller and the host. d0 is the least significant bit. data is registered on the rising edge of wr when ce is low. d1 38 i/o d2 41 i/o d3 42 i/o d4 45 i/o d5 46 i/o d6 1 i/o d7 2 i/o pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 5 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller trst 13 i jtag test reset input. for normal operation, hold low (v ss ). tms 14 i jtag test mode select input. for normal operation, hold high (v dd ). tck 15 i jtag test clock input. for normal operation, hold high (v dd ). tdi 16 i jtag test data in input. for normal operation, hold high (v dd ). tdo 17 o jtag test data out output. for normal operation, do not connect (n.c.). int 20 o interrupt request: active low, open-drain, output. this pin requires a pull-up device. usda2 21 o channel 2 ultra fast-mode i 2 c-bus serial data output. push-pull drive. no pull-up device is needed. uscl2 22 o channel 2 ultra fast-mode i 2 c-bus serial clock output. push-pull drive. no pull-up device is needed. wr 31 i write strobe: when low and ce is also low, the content of the data bus is loaded into the addressed register. data are latched on the rising edge of wr . ce may remain low or transition with wr . rd 32 i read strobe: when low and ce is also low, causes the contents of the addressed regist er to be presented on the data bus. the read cycle begins on the falling edge of rd . data lines are driven when rd and ce are low. ce may transition with rd . ce 33 i chip enable: active low input signal. when low, data transfers between the host and the bus controller are enabled on d0 to d7 as controlled by the wr , rd and a0 to a7 inputs. when high, places the d0 to d7 lines in the 3-state condition. during the initialization period, ce must transition with rd until controller is ready. trig 34 i trigger input: provides the trigger to start a new frame. reset 36 i reset: active low input. a low leve l resets the device to the power-on state. internally pulled high through weak pull-up current. v dd(io) 24 power i/o power supply: 3.0 v to 5.5 v. power supply reference for i 2 c-bus pins. sets the voltage reference point for v il /v ih and the output drive rail for the ufm channel. v ss(io) 23 power i/o supply ground. can be tied to v ss . v dd 7, 18, 30, 40, 44, 48 power power supply: 3.0 v to 3.6 v. all v dd pins must be tied together externally. v ss 8, 19, 29, 35, 39, 43, 47 power supply ground. all v ss pins must be tied together externally. n.c. 25, 26, 27, 28 - not connected table 2. pin description ?continued symbol pin type description pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 6 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7. functional description 7.1 general the pcu9661 acts as an interface device between standard high-speed parallel buses and the serial i 2 c-bus. on the i 2 c-bus, it acts as a master. data transfer between the i 2 c-bus and the parallel-bus host is carried out on a buffered basis, using either an interrupt or polled handshake. 7.2 internal oscillator and pll the pcu9661 contains an inte rnal 12.0 mhz oscillator and 156 mhz pll which are used for all internal and i 2 c-bus timing. the oscillator and pll require up to t init(po) to start up and lock after power-up. the o scillator is not shut down if the serial bus is disabled. 7.3 buffer description remark: in the following section a ?transaction ? is defined as a contiguous set of commands and/or data sent/received to/from a single slave. a ?sequence? is a set of transactions stored in the buffer. the pcu9661 serial channel has a 4352-byte data buffer (see section 7.3.2 ? buffer size ? ) that allows several transactions to be exec uted before an interrupt is generated. this allows the host to request se veral transactions (up to maximum buffer size on each channel) in a single sequence and lets the p cu9661 perform it without the intervention of the host each time a requested transaction is performed. the host can then perform other tasks while the pcu9661 executes the requested sequences. by following a simple procedure, the i 2 c-bus controller can store several i 2 c-bus transactions directed to different slaves addresses on any of the channels. let us consider the scenario where the host has done the initialization (mode, masks, and other configuration) and writes data into the buffer. the host starts by programming the buffer configuration registers tranconfig (number of slaves and bytes per slave) and then the slatable (slave addresses). then the host programs the transel (transaction data bu ffer selection) and the tranofs (byte offset selection) to 00h to set the memory pointers to the beginning of the buffer (the default value is 00h af ter a power-on or reset ). next, the host transfers the data into data until the entire sequence is loaded. care should be taken so as to not overflow the buffer with excessive read/write commands. in the event of an overflow, represented by the be bit in the ctrlstatus register, will be set to logic 1. the int pin will be set low if the bemsk bit in the ctrlintmsk register is logic 0. to recover the channel, a channel reset is required. all configuration and data needs to be checked by the host and resent to the i 2 c-bus controller. (see section 7.3.2 ? buffer size ? .) after sending all the commands and data it wanted to the i 2 c-bus controller, the host writes to the control register to begin da ta transmission on the serial channel. the transactions will be sent on the i 2 c-bus in the order in which the slave addresses are listed in the slatable, separated by a restar t condition. the last transaction in the sequence will end with a stop condition. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 7 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.3.1 buffer management assumptions ? repeated starts will be sent betw een two consecutive transactions. ? after the last operation on a channel is completed, a st op will be sent. 7.3.2 buffer size the pcu9661 serial channel has a 4352-byte buf fer assigned to it. the contents of the buffers should only be modified during channel idle states. the buffer size represents the memory allocated for the data block only. the slave address table and configuration bytes are contained in other locations and do not need to be included in the required buffer size calculation. for example, to calculate the size of the memory needed to write 26 bytes to 10 slaves: 10 slaves ? 26 bytes/slave = 260 bytes for the write transactions a total of 260 bytes of buffer space is required to complete the sequence. remark: note that the bytes required to store the 10 slave addresses are not included in the calculation since they are st ored in the slatable register. 7.4 error reporting and handling in case of any transaction error conditions, the device will load the transaction error status in the status2_[n], generate an interrupt, if unmasked, by pulling down the int pin and update the chstatus and ctrlstatus registers. the status for the individual sla addresses will be stored in the status2_[n] registers. 7.5 registers the pcu9661 contains several registers that are used to configure the operation of the device, status reporting, and to send data. t he device also contains global registers for chip level control and status reporting. the status2_[n] registers are channel-level direct access registers. the data, slatable, tranconfig, and bytecount registers are auto-increment registers. the memory access pointer to the data registers can be programmed using the transel and tranofs registers. see section 7.5.1.2 ? control ? control register ? , for information on the pointer reset bits bptrrst and aiptrrst. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 8 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller table 3. pcu9661 register address map - direct register access 7 6 5 4 3 2 1 0 register name access write access while ch active description default size (bytes) channel status registers 0 0 [3f:00] reserved r no reserved 00h 64 0 1 [3f:00] reserved r no reserved 00h 64 1 0 channel 2 transaction number (hex) status2_[n] r no individual transaction status (direct address) ([7:2] = 0 in ufm) 00h 64 channel 2 (ufm) registers 11100000control r/w yes [1] channel 2 control ([7] = 1) 00h 1 0 0 0 1 chstatus r no channel 2 status ([5:1] = 0 in ufm) 00h 1 0 0 1 0 intmsk r/w yes channel 2 interrupt mask ([5:1] = don?t care) 00h 1 0 0 1 1 slatable r/w no channel 2 slave addr ess table (auto-increment) 00h 64 0 1 0 0 tranconfig r/w yes, for trancount [2] channel 2 transaction configuration (auto-increment) 00h 65 0 1 0 1 data r/w yes channel 2 data (auto-increment) 00h bufsize [3] 0 1 1 0 transel r/w yes channel 2 transaction data buffer select 00h 1 0 1 1 1 tranofs r/w yes channel 2 transaction data buffer byte offset 00h 1 1 0 0 0 bytecount r no channel 2 transmitted byte count (auto-increment) 00h 64 1 0 0 1 framecnt r/w no channel 2 frame count 01h 1 1 0 1 0 refrate r/w no channel 2 frame refresh rate 00h 1 1 0 1 1 sclper r/w no channel 2 clock period 20h 1 1 1 0 0 sdadly r/w no channel 2 sda delay 08h 1 1101mode [4] r/w no channel 2 mode 83h 1 1110- - no reserved 00h 1 1 1 1 1 preset r/w yes channel 2 parallel reset 00h 1 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 9 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller [1] except tp and te. changing polarity of tp whil e te is active will cause a false trigger. [2] the transaction count (tranconfig[0]) can be wr itten to during the idle period between sequences. [3] refer to section 7.3.2 ? buffer size ? for channel memory allocation. [4] unused bits in the ufm register set will return 0b when read and writes will be ignored. [5] controller ready = ffh immediately after por or after a hardware reset or global reset. it will clear (00h) once the initial ization routine is done. global registers 11110000ctrlstatusr yes controller status 00h 1 0 0 0 1 ctrlintmsk r/w yes master interrupt mask 00h 1 0010- r no reserved 08h 0011- r no reserved 00h 0100- r no reserved 00h 0101- r no reserved 00h 0 1 1 0 device_id r no device id e1h 0 1 1 1 ctrlpreset r/w yes master parallel reset 00h 1 1 1 1 1 ctrlrdy [5] r no controller ready register ffh 1 table 3. pcu9661 register address map - direct register access ?continued 7 6 5 4 3 2 1 0 register name access write access while ch active description default size (bytes) pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 10 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.1 channel registers 7.5.1.1 status2_[n] ? transaction status registers status2_[n] is an 8-bit ? 64 read-only registers that prov ide status information for a given transaction. only the 2 lower bits ar e used; the top bits will always read 0. the controller will auto-clear the st atus2_[n] registers at each start of a sequence when framecnt = 1 and only at the first start when framecnt ? 1. each register byte can be accessed by direct addressing so that the host can choose to read the status on one or more individual transactions without having to read all 64 status bytes. remark: when status2_[n] = 00h, no interrupt is requested and the transaction is in the done/idle state. during program execution, the tr and ta bits behave as follows: example, we are to transfer 3 transactions in a sequence. all init ialization is completed (loading of sla, tranconfig, data) and device is ready for serial transfer. before the sta bit is set, the status2_[n] register will contain: status2_[0] = 0 status2_[1] = 0 status2_[2] = 0 status2_[3] = 0 : after sta is set: status2_[0] = 2 status2_[1] = 1 status2_[2] = 1 status2_[3] = 0 : since there is no timing requirement in setting the sta bit after the initialization, the device will update the first status when the sta bit is set and will always go fr om 0 to 2 (idle to transaction active). table 4. status2_[n] - transaction status code register bit description bit symbol description 7:2 st[7:2] always reads 0000 00 1 ta transaction active. when 1, the transaction is currently active on the serial bus. no interrupt is requested. 0 tr transaction ready. when 1, a transaction is loaded in the buffer and waiting to be executed. no interrupt is requested. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 11 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.1.2 control ? control register control is an 8-bit register. the sto bit is affected by the bus controller hardware: it is cleared when a stop condition is present on the i 2 c-bus. table 5. control - control register bit description address: channel 2 = e0h. legend: * reset value bit symbol access value description 7 stoseq r/w stop sequence bit. 1 when the stoseq bit is set while the channel is active, a stop condition will be transmitted immediately following the end of the current sequ ence being transferred on the i 2 c-bus. no further buffered transactions will be carried out and the channel will return to the idle state. normal error reporting will occur up until the last bit. when a stop condition is detected on the bus, the hardware clears the stoseq flag. 0* when stoseq is reset, no action will be taken. 6 sta r/w the start flag. 1 the sta bit is set to begin a sequence. the sta bit may be set only at a valid idle state. the controller will reset the bit under the following conditions: ? a sequence is done and framecnt = 1. ? a sequence loop is done and framecnt > 1. ? the stoseq bit is set, framecnt = 0, and the current sequence is done. ? the stoseq bit is set, framecnt > 1, and the current sequence is done. ? the sto bit is set and the current byte transaction is done. this bit cannot be set if the chen bit is 0. 0* when the sta bit is reset, no start condition will be generated. 5 sto r/w the stop flag. 1 when the sto bit is set while the channel is active, a stop condition will be transmitted immediately following the current data or slave address byte being transferred on the i 2 c-bus. no further buffered transactions will be carried out and the channel will return to the idle state. normal error reporting will occur up until the last bit. when a stop condition is detected on the bus, the hardware clears the sto flag. 0* when the sto bit is reset, no action will be taken. 4 tp r/w trigger polarity bit. cannot be changed while channel is active. 1 trigger will be detected on a falling edge. 0* trigger will be detected on a rising edge. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 12 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller remark: due to a small latency between setting the sta bit and the ability to detect a trigger pulse, if the sta bit is set simultaneously to an incoming trigger pulse, the pulse will be ignored and the contro ller will wait for the next trigger to send the start. if the sto or stoseq bit are set at anytime while the sta bit is 0, then no action will be taken and the write to these bits is ignored. remark: sto has priority over stoseq. 3 te r/w trigger enable (te) bit controls the trigger input used for frame refresh. te cannot be changed while channel is active. when the trigger input is enabled, the trigger will override the contents of the framecnt register and will start triggering when sta bit is set. thereafter, when a trigger tick is detected, the controller will issue a start command and the stored sequence will be transferred on the serial bus. 1 when te = 1, the sequence is controlled by the trigger input. 0* when te = 0, the trigger inputs are ignored. 2 bptrrst w 1 resets auto increment pointers for bytecount. reads back as 0. 1 aiptrrst w 1 resets auto increment pointers for slatable and tranconfig. the data register auto-increment pointer will be set to the value that corresponds to transel and tranofs registers. reads back as 0. remark: to reset the data pointer, write 00h to transel. 0 - w 0 reserved. user must write 0 to this bit. table 5. control - control register bit description ?continued address: channel 2 = e0h. legend: * reset value bit symbol access value description pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 13 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller [1] loop idle is defined as the time elapsed from a stop to the start of the next sequence while sta = 1. [2] channel active is defined by the ctrlstatus[5:3] bits. table 6. control register bits sta, sto, stoseq operation/behavior channel state (initialization steps) next write action by host results framecnt te sta sto stoseq idle (reset, tranconfig, slatable, data, sta = 0) 1 0 0 x x no action. 1 0 1 x x start transmitted on serial bus followed by sequence stored in buffer. active (reset, load tranconfig, slatable, data, sta = 1 1 0 x 0 x no change; cannot write sta while active. 1 0 x 1 x when the sto bit is set: 1. a stop is sent after the end of ack cycle of the current byte and bytecnt is updated. the sd bits will be set. refrate loop idle (reset, load tranconfig, slatable, data sta = 1) [1] ? 1 0 0 x x no action. ? 1 0 x 0 1 channel will go immediately to the inactive state and sd and fld bits will be set. [2] ? 1 0 x 1 x channel will go immediately to the inactive state and sd and fld bits will be set. [2] refrate loop active (reset, load, tranconfig, slatable, data, sta = 1) ? 1 0 x 0 0 no action. ? 1 0 x 0 1 stop at end of current frame. the sd and fld bits will be set. ? 1 0 x 1 x when the sto bit is set: 1. a stop is sent after the end of ack cycle of the current byte and bytecnt is updated. the sd and fld bits will be set. trigger loop idle (reset, load tranconfig, slatable, data, sta = 1) x 1 0 x x no action. x 1 x 0 1 stop at end of current frame. the sd and fld bits will be set. x 1 x 1 x when the sto bit is set: 1. a stop is sent after the end of ack cycle of the current byte and the bytecnt is updated. the sd and fld bits will be set. trigger loop active (reset, load tranconfig, slatable, data, sta = 1) x 1 x 0 0 no action. x 1 x 0 1 channel will go immediately to the inactive state and sd and fld bits will be set. [2] x 1 x 1 x channel will go immediately to the inactive state and sd and fld bits will be set. [2] pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 14 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.1.3 chstatus ? channel status register chstatus is an 8-bit read-only register that provides status information for the serial channel. all these status drive the int pin active low. to clea r the channel interrupt request, you must read the chstatus regist er. the be interrupt is cleared by reading the ctrlstatus register. after the chstatus register is cleared, only new errors or status updates will cause the chstatus bits to be set. [1] bits [5:1] always read as logic 0. fe - frame error bit: this bit indicates that the time required to send the sequence exceeds the refresh rate programmed in the refrate register or the time between trigger ticks. solving frame erro rs include programming longer refresh rates, speeding up the bus frequency, shortening the amount of bytes sent/received in the sequence, or increasing the time between trigger ticks. if the frame error is mask ed by the femsk, the device will continue to tran smit transactions until the end of the se quence without re-starting the sequence even if new triggers are detected. the total number of sequences transmitted will be the number stored in the framecnt register. once a complete sequence is transmitted, a new sequence will initiate when a subsequent trig ger appears. the fe flag will be held high and sequen ces will still be transmitted unless chstatus is read. if the frame error is unmasked, the sequence will be aborted at the next logical stopping point, a stop transmitted and an inte rrupt will be generated. the fe bit is set after the stop is detected on the bus. table 7. chstatus - channel and buffer status codes register bit description address: channel 2 = e1h. bit symbol description 7 sd sequence done. the sequence loaded in the buffer was sent and stop issued on the serial bus. 6 fld frame loop done. the framecnt val ue has been reached. a stop has been issued on the bus. 5:1 - reserved. 0 fe frame error detected. the time required to send the sequence exceeds refresh rate programmed to the refrate regist er or the time be tween trigger ticks. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 15 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.1.4 intmsk ? interrupt mask register through the intmsk register, there is the op tion to manage which states generate an interrupt, allowing more control from the host on the transaction. the interrupt mask applies to all transactions on the channel. a bi t set to 1 indicates that the mask is active. the intmsk register default is all interrupts are un-masked (00h). a. sequence fully executed within the pe riod programmed in refrate register this condition causes a frame error and the fe bit to be set. b. sequence exceeds period programmed in refrate register, femsk = 0 c. sequence exceeds period programmed in refrate register, femsk = 1 fig 3. frame error detection 002aaf247 sequence a sequence a sequence a 10 ms 10 ms 10 ms time 002aaf627 sequence b 10 ms 10 ms 10 ms time frame error detected, data not sent after fe 002aaf628 sequence c 10 ms 10 ms 10 ms time frame error detected, femsk = 1, data sent after fe sequence c table 8. intmsk - interrupt mask register bit description address: channel 0 = c2h; channel 1 = d2h; channel 2 = e2h. bit symbol description 7 sdmsk sequence done mask. the end of se quence interrupt will not be generated. 6 fldmsk frame loop done mask. a frame loop done interrupt will not be generated. the controller will enter the idle state. 5:1 - reserved 0 femsk frame error mask. a frame error interrupt will not be generated. remark: use caution and good judgem ent when using this mask. unexpected/erratic behavior may result in the slave devices. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 16 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.1.5 slatable ? slave address table register slatable is an 8-bit ? 64 register set that makes up a t able that stores the slave address for each transaction in the sequence. the table is loaded by using an auto-increment pointer that is not user-accessible. to reset the pointer, the aiptrrst bit must be set in the control register. the slave addresses in the slatable register are stored with a zero-based (n ? 1) index. the first slave addre ss occupies the 00h position. remark: slave address entries greater than the transaction count are not part of the sequence. tranconfig[0] cont ains the transaction count that will be included in the sequence. table 9. slatable - slave address table register bit description address: channel 2 = e3h. bit symbol description 7:1 slatable[7:1] slave address. 0 slatable[0] when 1, a read transaction w ill be ignored and a write transaction is requested. when 0, a write transaction is requested. table 10. example of slatable registers transaction slave address 00h 10h 01h 12h 02h 28h 03h 40h 04h 14h :: 3fh 36h pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 17 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.1.6 tranconfig ? transacti on configuration register the tranconfig register is an 8-bit ? 65 register set that makes up a table that contains the number of transa ctions that will be executed in a sequence and the number of data bytes involved in the transaction. the first byte of the register is the transact ion count register. the remaining 64 registers are the transaction length registers. remark: even if the transaction length (tranconfig[1:40h]) and the slatable([0:3fh]) are fully init ialized, only the specified number of transactions in the transaction count (tranconfig[0]) will be part of the sequence. if the transaction count is 0, th en there will be no activity on th e serial bus if the sta bit is set. in addition, there will be no interrupts generated or st atus updated. th e controller will simply reset the control.sta bit wit hout performing any transactions. if the transaction length is 0, a write transaction will send th e slave address plus write bit (sla+w) on the serial bus with no data bytes. 7.5.1.7 data ? i 2 c-bus data register data is an 8-bit read/write, auto-increment regi ster. it is the interface port to the channel buffer. when accessing the buffer, the host writes a byte of serial data to be transmitted at this location. the host can read from the data at any time and can only write to this 8-bit register while the channel is idle. the host can read or write data up to the amount of memory space allotted to the channel. the location at which the data is accessed is stored in the transel and tranofs register (both default at 00h). table 11. tranconfig, byte 0 - transaction configuration register bit description address: channel 2 = e4h. bit symbol description 7:0 number of transactions in the sequence. maximum is 40h. table 12. tranconfig, byte 1 to 40h - transactio n configuration regi ster bit description bit symbol description 7:0 number of bytes per transaction in the sequence. maximum is ffh. table 13. example of tranconfig register loaded register value description transaction count 10h 16 transactions = 16 slave addresses in the slatable transaction length 00h 0ah 10 byte transaction transaction length 01h 12h 18 byte transaction transaction length 02h 28h 40 byte transaction transaction length 03h 40h 64 byte transaction ::: transaction length 3fh 12h 18 byte transaction pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 18 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller to return to the data location pointed by the contents of the transel and tranofs register after read or write access to the data register, set the aiptrrst (auto-increment pointer reset) bit in the control register. to return to the first data register loca tion in the buffer set the transel to 00h. 7.5.1.8 transel ? transaction data buffer sel ect register the transel register is used to select the po inter to a specific transaction in the data buffer. this allows the user to update the data of a specific slave without having to re-write the entire data buffer. the value of this re gister is the slave address position in the slatable register. the transel register is zero-based (n ? 1) register. for example, if a change to the 22nd slave address data is required, the host would set the transel register to 15h. this register can be used in conjunction with the transofs register to access a specific by te in the data buffer. the host would then proceed to write the new data to the data r egister. the auto-increm ent feature continues to operate from this new position in the data register. setting transel to an uninitialized tr anconfig entry may cause a request to read/write data outside the data buffer. if this occurs, the be bit in the ctrlstatus register will be set to a logic 1. write data w ill be ignored and read data will be invalid. when a new transaction is selected by programming the transel registers, the transofs register will automat ically be reset to 00h. remark: when updating the data buffer, if the number of bytes to be updated or read exceeds the number of bytes that were specified in the tranco nfig register, the auto-increment will go over the transaction boundary into the next tran saction stored in the buffer. remark: to reset the data pointer, write 00h to the transel register. table 14. data - data register bit description address: channel 2 = e5h. bit symbol description 7:0 d[7:0] eight bits to be transmitted. a l ogic 1 in data corresponds to a high level on the i 2 c-bus. a logic 0 corresponds to a low level on the bus. table 15. transel - transaction data buffer select register bit description address: channel 2 = e6h. bit symbol description 7 - reserved. 6 - reserved. 5:0 transel[5:0] slave address position in the slatable. the maximum number is 3fh. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 19 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.1.9 tranofs ? transaction data buffer byte select register in conjunction with the transel register, the tranofs register is used to select the pointer to a specific byte in a transaction in the data buffer. this allows the user to read or re-write a specific data byte of a specific slave without having to read/re-write the entire data buffer. the tranofs register is zero-based (n ? 1), so the maximum bytes this register will point to is 256. for example, if the tenth byte in the 40th sl ave address data is required, the host would set the transel register to 27h and the tr ansofs register to 09h. the host would then proceed with a read to the data register. setting tranofs to a byte offset outside of the data buffer will cause the be bit in the ctrlstatus register will be set to a logic 1. write data will be ignored and read data will be invalid. remark: the number of bytes to be updated or read should not exceed the number of bytes that were specified in the tran config register. doing so will cause the auto-increment to go over the transaction boundary into the next transaction stored in the buffer. 7.5.1.10 bytecount ? transmitted an d received byte count register the bytecount register stores the number of bytes that have been sent. the count is continuously updated, therefore the bytecount is a real time reporting of transmitted and received bytes. this is a read-only regi ster. the bytecount includes only the bytes that have been acked in a write transaction. the bytecount register is cleared at the start of every sequence. 7.5.1.11 framecnt ? frame count register this register is a read/write register. the contents of this register holds the programmed value by the host and is not a real-time c ount of frames sent on the serial bus. if the framecnt is 00h, the sequence stored in the buffer will loop continuously. a stop will be sent at the end of each sequence. table 16. tranofs - transaction data buffe r byte select register bit description address: channel 2 = e7h. bit symbol description 7:0 tranofs[7:0] byte index for the specified transaction buffer in transel. table 17. bytecount, byte 0 - transaction configuration register bit description address: channel 2 = e8h. bit symbol description 7:0 bytecount[7:0] number of bytes sent per transaction in the sequence. maximum is ffh. table 18. framecnt - frame count register bit description address: channel 2 = e9h. bit symbol description 7:0 framecnt[7:0] bit 7 to bit 0 indicate the number of times buffered commands are to be re-transmitted. default is 01h. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 20 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller if the framecnt is 01h, it is defined as the default state and the sequence stored in the buffer will be sent once and a stop will be sent at the en d of the sequence. if the framecnt is greater than 01h, the sequence stored in the buffer will loop framecnt times and a stop will be sent at the end of each sequence. remark: the framecnt can only be set to loop on the sequence stored in the buffer. 7.5.1.12 refrate ? refresh rate register the refrate register defines the time period between each sequence start when refrate looping is enabled (framecnt ? 1, and te = 0). the refresh period defined by refrate should always be programmed to be greater than the time it takes for the se quence to be transferred on the i 2 c-bus. if the refrate values is too small, the fram e error (fe) bit will be set an d an interrupt will be requested. remark: if the framecnt is 1, then the re fresh rate function will be disabled. 7.5.1.13 sclper, sdadly ? clock rate registers the clock rate register for the ultra fast-mode channel is controlled by the sclper and sdadly registers. they define the data ra te for the serial bus of the pcu9661. the actual frequency on the serial bus is determined by t high (time where scl is high), t low (time where scl is low), t r (rise time), and t f (fall time) values. writing illegal values into sclper registers will cause the part to op erate at the maximu m channel frequency. for ufm mode, the clock is a fixed 50 % duty cycle defined by the sclper and t r and t f are system/application dependent. calculating clock settings for ultra fast mode (ufm): the clock period is defined as follows (50 % duty cycle): (1) table 19. refrate - refresh rate register bit description address: channel 2 = eah. bit symbol description 7:0 refrate[7:0] bit 7 to bit 0 indicate the sequence refresh period. the resolution is 100 ? s. the default value is 00h, the ti mer is disabled, and the sequences will be sent back-to-back if the framecnt is = 0 or framecnt is > 1. table 20. sclper - clock period register bit description (ultra fast mode) address: channel 2 = ebh. bit symbol description 7:0 l[7:0] eight bits defining the clock period (ultra fast mode). default 32 (20h). table 21. sdadly - sda delay register bit description (ultra fast mode) address: channel 2 = ech. bit symbol description 7:6 h[7:6] reserved. read only read back zero. 5:0 h[5:0] six bits defining the sda delay (ultra fast mode). default: 8 (08h). sclper min ?? 1 t pll freq ? ---------------------------- - = pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 21 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller the data will be delayed with respect to the falling edge of the clock as follows: (2) [1] the minimum allowable value that can be stored in sclper is 32. [2] the minimum allowable value that can be stored in sdadly is 2. the pcu9661 will force a 50 % duty cycle by shifting the cont ents of the sclper register right by 1. when the user writes the sclper register , the sdadly will be loa ded automatically with a value 1 4 the value of sclper (sclper register value right shifted twice). the user can then overwrite the sdadly register if desired. the order in which the registers should be wr itten is first the scl per, then the sdadly register to adjust the delay. the maximum value for sdadly is the preferred value to be loaded. table 22. sample clock period and allowable data delay frequency sclper [1] sdadly [2] 5.0 mhz 32 2 to 8 4.0 mhz 39 2 to 9 3.0 mhz 53 2 to 13 2.0 mhz 79 2 to 19 1.0 mhz 158 2 to 39 sdadly max ?? sclper 4 ---------------------- - = pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 22 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.1.14 mode ? i 2 c-bus mode register mode is a read/write register. it contains t he control bits that select the bus recovery options, and the correct timing parameters. timing paramete rs involved with ac[1:0] are t buf , t hd;sta , t su;sta , t su;sto , t high , t low . the auto recovery and bus recovery bits are contained in this register. they control the bus recovery sequence. remark: chen bit value must be changed only when the i 2 c-bus is idle. remark: the ac[1:0] are read-only bits. the ufm channel ac parameters are controlled internally. 7.5.1.15 preset ? i 2 c-bus channel parallel software reset register preset is an 8-bit write-only register. programming the preset register allows the user to reset the channel under software control. th e software reset is achieved by writing two consecutive bytes to this register. the first by te must be a5h while the second byte must be 5ah. the writes must be consecutive and the values must match a5h and 5ah. if this sequence is not followed as described, the reset is aborted. the preset resets state-machines , registers, and buffer poin ters to the default values, zeroes the tranconfig, slatable, bytecount, and data arrays of the respective channel and will not reset the enti re chip. the parallel bus rema ins active while a software reset is active. the user ca n read the preset register to determine when the reset has completed, preset returns all 1s when the re set is active and all 0s when complete. table 23. mode - i 2 c-bus mode register bit description address: channel 2 = edh. bit symbol description 7 chen channel enable bit. r/w. 0: channel is disabled, scl and sda high -impedance, usda and uscl driven high. all registers are accessible for setup and configuration, however a sequence cannot be started if the chen bit is 0 (sta cannot be set). 1 (default): channel is enabled. 6:2 - reserved. ufm channel 2 1:0 ac[1:0] i 2 c-bus mode selection to ensure proper timing parameters (see table 33 ). ac[1:0] = 00: reserved. ac[1:0] = 01: reserved. ac[1:0] = 10: reserved. ac[1:0] = 11 (default): ult ra fast-mode ac parameters selected. read-only bits. table 24. preset - i 2 c-bus channel parallel software reset register bit description address: channel 2 = efh. bit symbol description 7:0 preset[7:0] read/write r egister used during an i 2 c-bus channel parallel reset command. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 23 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.2 global registers 7.5.2.1 ctrlstatus ? controller status register the ctrlstatus register reports the status of the controller, including the interrupts generated by the parallel bus. there are three status bits. when ctrlstatus contains 00h, it indicates the idle state and therefore no serial interrupts are requested. the content of this register is continuously updated during the operation of the controller. bit 2 indicates the serial channel has an interrupt request pending. to clear the serial channel interrupt request, you must read th e chstatus register. bit 5 indicates if the serial channel is currently active or if it is in the idle state. remark: a global reset will reset all ch annels and configuration settings. be - buffer error bit: this bit indicates that a buffer error has been detected. for example, a buffer overflow due to the host pr ogramming too many byte s will set this bit. a software or hardware reset is necessary to recover from a buffer error. the buffer error may occur when a data locati on is being read or written to that has not previously been configured by the tranconfig register. the buffer error can occur on a parallel data write or read beyond the buffer capacity, or setting the transel and tranofs pointers beyond the buffer boundary. when the data register is loaded with data th at goes beyond the capacity of the buffer, the bytes that go over the buffer size will be ignored and a buffer error (be) will be generated. special case: the be interrupt is cleared by readi ng the ctrlstatus register. all other interrupts are cleared by reading the respective chstatus register. see ta b l e 7 for channel status. table 25. ctrlstatus - interrupt status register bit description address: f0h. bit symbol description 7 be buffer error. a buffer error such as overflow has been detected. 6 - reserved. 5 ch2act channel 2 is active. 4 - reserved. 3 - reserved. 2 ch2intp channel 2 interrupt pending. 1 - reserved. 0 - reserved. fig 4. pcu9661 status reporting logic 002aag270 sd fe fld ch2intp (ufm) pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 24 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.2.2 ctrlintmsk ? control interrupt mask register the ctrlintmsk masks all interrupts generated by the masked channel. this allows the host mcu to complete other operations before servicing the interrupt without being interrupted by the same channel. see ta b l e 8 for interrupt mask. 7.5.2.3 device_id ? device id the device_id register stores the bus controller part number so it can be identified on the parallel bus. table 26. ctrlintmsk - control interrupt mask register bit description address: f1h. bit symbol description 7 bemsk buffer error mask. a buffer error interrupt will not be generated. remark: use caution and good judgement when using this mask. unexpected/erratic behavior may result in the slave devices. 6:3 - reserved 2 ch2msk when this bit is set to 1, all interrupts for the channel will be masked and the int pin will not be pulled low. 1:0 - reserved fig 5. pcu9661 interrupt logic ch2msk ch2 interrupt sources and masks to int pin bemsk be sd sdmsk re remsk fe femsk fld fldmsk 002aag271 table 27. device_id - device id register bit description address: f6h. bit symbol description 7 u/a selects pcu or pca device. 1 = pcu96xx 0 = pca96xx 6:0 bcd bcd (binary coded decimal) code of the ending 2 digits for id. range is 00h to 79h. the code for the pcu9661 is e1h. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 25 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 7.5.2.4 ctrlpreset ? parallel software reset register ctrlpreset is an 8-bit write-only regist er. programming the ctrlpreset register allows the user to reset the pcu9661 under software control. the software reset is achieved by writing two consecutive bytes to this register. the first byte must be a5h while the second byte must be 5ah. the writes mu st be consecutive and the values must match a5h and 5ah. if this sequence is not follo wed as described, the reset is aborted. 7.5.2.5 ctrlrdy ? controller ready register ctrlrdy (address ffh) is an 8- bit read-only register. it indicates the internal state of the controller. when the register is ffh, the co ntroller is in the init ialization state. the initialization state will be entere d at power-up, after a hardware reset, or after a global software reset. the oscillator and the pll will be initialized only after a power-on reset (por), a hardware reset, or a global software reset (ctrlpreset). when the register is 00h, the controller is in the normal operating mode. access while the controller is initializing requires ce pin follow the rd pin transitions to update the state of the controller that is read back. after controller is ready, the ce pin can be held low while rd and wr pins transition. see figure 6 , figure 7 and figure 8 . table 28. ctrlpreset - para llel software reset re gister bit description address: f7h. bit symbol description 7:0 ctrlpreset[7:0] write-only register used during a device parallel reset command. table 29. ctrlrdy - controller ready register bit description address: ffh. bit symbol description 7:0 ctrlrdy[7:0] read-only register indicates the internal state of the controller. ffh indicates the controller is initializing, 00h indicates controller is in normal operating mode. fig 6. during initialization, ce must transition with rd at each read operation 002aag095 ce 00h ffh ffh initializing ready rd data pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 26 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 8. pcu9661 operation the pcu9661 is designed to efficiently transmit large amounts of data on a single master bus. there are three major components that compose the architecture of the i 2 c-bus controller that interact with each other to prov ide a high throughput and a high level of automation when it conducts transactions: ? slave address table: specifies the address of the slaves on the bus and the direction (write only). ? transaction configuration: specifies the size of the transaction. ? data buffer: contains the data to be transmitted from the slave. these three components are integrated in the pcu9661 to build a sequence. a sequence is a set of write transactions and the mini mum sequence size is one write transaction. several transactions can be stored in o ne sequence and be executed without the intervention of the host controller (cpu) through loop control and using the built-in refresh rate timers. the pcu9661 executes tr ansactions in the order they were loaded into the buffer without interrupting the host. once the end of a sequen ce is reached, the sequence done (sd) bit will be asserted in the chstatus register and the controller will reques t an interrupt, if sdmsk = 0. at this point, the host can rel oad the buffer with a new sequence or resend the one that is currently loaded in the buffer. fig 7. during normal operation, ce may remain low while rd transitions during multiple reads fig 8. during normal operation, ce may remain low while wr transitions during multiple writes 002aag096 ce address z address y address x rd data read address z read address y read address x addr 002aag097 ce data z data y data x wr data write address z write address y write address x addr pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 27 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller when a sequence is in progress, no interrupts are generated unless there is an error when a transaction is con ducted. the host will only rece ive an interr upt when the sequence is done. the pcu96 61 will behave as a master transmitter regard less of the direction bits specified in the slatable. the host has the ability to update the data buffer while the controller carries on the remaining transactions in the sequence. 8.1 sequence execution sequences can only be of one type: ? write transactions, where the pcu966 1 will behave as a master transmitter data transfers in one direction are shown in figure 9 . this figure contains the following abbreviations: s ? start condition sla ? 7-bit slave address w ? write bit (low level at sda) a ? not acknowledge bit (high level at sda) data ? 8-bit data byte p ? stop condition in figure 9 , circles are used to indicate when a bit is set in the chstatus register. a channel interrupt is not requested when chstatus = 00h and the int pin is not asserted when the interrupt is masked (see section 7.5.2.2 ). for a successful sequence execution, all th ree components mentioned above must exist in the memory and must be correctly set up. there are not safeguards against programming incorrect transaction sizes, data buffer lengths, or direction bits. if the transaction length is set to 00h, then only the slave addr ess with direction bit will be transmitted. once the host has configured the serial port and programmed the tranconfig (number of slaves and bytes per slave), the slatabl e (slave addresses), transel (transaction data buffer selection) and the tranofs (byte offset selection) and loaded the serial data into the data buffer, the sequen ce is ready to be transmitted. to send the sequence, the host will set the sta bit in the control register and the controller will immediately send a start on the serial bus. then, the transactions will be carried out in the order they appear in the slatable, each being separated by a restart command. if the interrupts are unmasked, the serial transfer will be conducted with out generating interrupts in between transactions. once all tr ansactions are successfully completed, the controller will generate a stop, the sequence done bit (sd) will be set in the chstatus and an interrup t will be generated. once all transactio ns are completed, the contro ller will generate a stop and the sequence done bit (sd) will be set in the chstatus and an interrupt will be generated. if the host wants to poll the p cu9661, it can mask all registers including the sd bit and read the ctrlstatus, chstatus, status2_[n], and/or the control registers to determine the state of the controller. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 28 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller example chstatus codes: 80h: sequence done with no errors c0h: frame loop and sequence done with no errors c1h: frame loop and sequence done with frame errors fig 9. pcu9661 i 2 c status codes a chstatus register, interrupt requested. interrupt goes low at the stop. data any number of data bytes and their associated acknowledge bits from master to slave status2_[n] register, no interrupt n 002aag272 sla 0 s w a data sla 0 w data data a s sla 1 w datan sla n 01h s s w datan p 80h 00h s 01h a a a a a c0h c1h a a xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 29 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller status and configuration registers are not shown. shaded areas are comments/indexes that are not user-accessible. fig 10. pcu9661 sequence block diagram; sample sequence loaded 002aag273 00h tranconfig - 01h 02h : 03h 3dh 3eh 3fh 01h 40h 05h 10h : 08h 10h 05h 08h transaction count transaction 0 length, 1 byte transaction 1 length, 5 bytes transaction 2 length, 16 bytes transaction 3 length, 8 bytes : transaction 61 length, 16 bytes transaction 62 length, 5 bytes transaction 63 length, 8 bytes 00h slatable 01h 02h : 03h 3dh 3eh 3fh 10h 11h 40h : e0h 20h 33h 20h slaw slaw slaw slaw : slaw slaw slaw the slave address plus transaction count, direction bit, the transaction length and the transaction data make up one complete serial bus transaction or sequence. data 00h 10h 00h 00h 00h 02h 55h transaction 0, data byte 0 transaction 1, data byte 0 transaction 1, data byte 1 transaction 1, data byte 2 transaction 1, data byte 4 transaction 2, data byte 0 transaction 2, data byte 1 : aah : transaction 2, data byte 15 :: 44h transaction 63, data byte 0 aah transaction 63, data byte 1 :: 55h transaction 63, data byte 7 :: :: :: :: unused memory space internal memory pointer a00h or f00h sequence write data memory space internal memory pointer 0000h the memory pointers are managed internally by the buffer controller. number of slave addresses to be included in a sequence 00h transaction 1, data byte 3 transaction length corresponding to each slave address in the slatable slave address plus direction bit pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 30 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 8.2 stopping a sequence if the host needs to stop the execution of a sequence, it should set the sto bit in the control register. fo r write transactions, the host will issue a stop after the acknowledge cycle of the current byte being tr ansferred on the serial bus. no interrupts will be generated and all the status registers will be up to date. the sequence done bit (sd) will be set to indicate to the host that the stop cond ition was comple ted and the bus is idle. the sequence done and the frame loop done will be se t if the channel is in loop mode (framecnt ? 1) and a sto or stoseq bit is set. if the host issues a stop (by setting the sto) in the middle of a sequence followed by a start (by setting the sta), then the cont roller will re-send the sequence from the beginning, not from the point where the sequence was last stopped. 8.3 looping a sequence a sequence can be set to automatically loop several times using the framecnt and one of the following: ? the refrate register. the refrate register contains the value of the refresh rate which is timing required between the star t of two sequences. the refresh rate is derived from the internal clock of the bus controller. if the refrate is programmed to 00h, the sequences will be looped back-to-back. ? trigger enable (te) bit. when te is set, the refresh rate is controlled by the external trigger input and the contents of the refr ate registers is ignored. there is no maximum timing requirement for the trigger interval. the framecnt register sets the number of times th e sequence will be repeated. a frame is defined as a sequence associated wit h its respective refresh rate. as described above, the frame refresh rate is determined by the refrate register or an external trigger source. during looping, there is no host intervention required and all status and error reporting remains active. the sd (sequence done) bit ca n be masked to avoid getting interrupted each time a frame is completed while the other error reporting bits remain unmasked. in this manner, normal transactions can run wit hout host intervention and errors will be reported at the stop of the current byte where the error occurred. once the framecnt values is reached, the fld bit in the chstatus register is set and no further transactions will be executed and th e channel will go to the idle state. the fld interrupt can be masked with the fldmsk bit in the ctrlintmsk register. the host can poll the ctrlstatus register to check if the channel is active (looping) or if it is idle. for indefinite or long term looping the host can do the following: 1. a sequence can be set to loop indefinitely by setting the framecnt register to 00h. each frame will be sent out following the refrate settings or the trigger input if the te bit is set. to end the loop mode, the host sets the sto or stoseq bits in the control register. 2. a frame will be sent out c ontinuously and back-to-back if framecnt and refrate are set to 00h. to end the loop mode, the hose sets the sto or stoseq bits in the control register. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 31 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 8.3.1 looping with refrate control when using the refrate register (te bit is 0) the refresh rate timing is controlled internally. once the sta bit is set, the st art command will be immediately sent on the serial bus followed by the sequence. thereafter, the controller will issue a start command followed by the stored sequence every time the refrate value is reached. it is important to program enough time in the refrate to allow a complete sequence to reach the sequence done state. if the refresh rate is not long enough, the frame error (fe) bit will be set and an interrupt will be ge nerated. the fe bit is maskable, however, masking the fe bit may yield undesired results on the serial interface. if the fe bit is masked, the loop mode will continue to operate and the fe flag will remain set. to exit the loop mode, the sto or th e stoseq bit should be set. 8.3.2 looping with trigger control the pcu9661 has one trigger input. the trigger enable (te) bit in the control register is used to control the use of external triggering. once enabled , the trigger will override the contents of the refrate register, and will st art triggering when the sta bit is set. therefore, a significant time delay can occur between setting the sta bit and the detection of a trigger. when a trigger edge is detected, the controller will issue a start command and the stored sequence will be tran sferred on the serial bus. the trigger will control the timing of the frame, therefore, eno ugh time should be allowed by the trigger to allow the sequence to reach the sequence done state. if a trigger edge is detected while a sequence is actively being transmitted on the bus, the frame error (fe) bit will be set and an interr upt will be generated. the fe bit is maskable, however, masking the fe bit may yield undesired results on the serial interface. if the fe bit is masked, the loop mode will continue to operate and the fe flag will remain set. the polarity of the trigger edge detect is controlled by the tp bit in the control register. to exit the trigger mode, the sto or the stoseq bit should be set. 8.4 power-on reset when power is applied to v dd , an internal power- on reset holds the pcu9661 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pcu9661 goes to the power-up initializatio n phase where the following operations are performed: 1. the oscillator and pll will be re-initialized. 2. internal register init ialization is performed. 3. the memory space will be zeroed out. the complete power-up initialization phase takes t rst to be performed. during this time, writes to the pcu9661 through the parallel po rt are ignored. howe ver, the parallel port can be read. this allows the device connected to the parallel port of the pcu9661 to poll the ctrlrdy register. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 32 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 8.5 global reset reset of the pcu9661 to its default state can be performed in 2 different ways: ? by holding the reset pin low for a minimum of t w(rst) . ? by using the parallel software reset sequence as described in figure 11 . the host must write to the ctrlpreset register of the target channel in two successive parallel bus writes to the bus controller. the first byte is a5h and the second byte is 5ah. the reset hardware pin and the global software reset function behave the same as the power-on reset. a comp lete power-up initia lization phase will be perf ormed as defined in section 8.4 . the reset pin has an internal pull-up resistor (through a series diode) to guarantee proper operation of the device. this pin should not be left floating and should always be driven. fig 11. parallel software reset sequence 002aag274 a[7:0] ctrlpreset register selected d[7:0] a5h data byte 1 5ah data byte 2 wr if d[7:0] a5h, following byte is ignored and reset is aborted. if d[7:0] 5ah, reset is aborted. if data 1 = a5h and data 2 = 5ah, pcu9661 is reset to its default state. internal global reset signal ce pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 33 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 8.6 channel reset in addition to the above chip reset options, each channel can be individually reset by programming the preset register for that ch annel as described in figure 12 . the channel will reset to its default power-up state. the host must write to the preset register of the target channel in two successi ve parallel bus writes to the bus controller. the first byte is a5h and the second byte is 5ah. 8.7 i 2 c-bus timing diagram figure 13 illustrates the typical timi ng diagram fo r the pcu9661. fig 12. i 2 c-bus channel parallel software reset sequence 002aag275 d[7:0] a5h data byte 1 5ah data byte 2 wr a[7:0] channel preset register selected if d[7:0] a5h, following byte is ignored and reset is aborted. if d[7:0] 5ah, reset is aborted. if data 1 = a5h and data 2 = 5ah, pcu9661 is reset to its default state. internal channel reset signal ce pcu9661 writes data to slave. (1) 7-bit address + w = 0 byte and number of bytes sent = value programmed in transaction length register in tranconfig register. fig 13. bus timing diag ram; write transactions n byte (1) nack uscl usda int start condition 7-bit address (1) w = 0 from master first byte (1) nack nack stop condition 002aag276 interrupt (after stop) pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 34 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 9. characteristics of the i 2 c-bus ? ultra fast-mode (ufm) the pcu9661 ufm bus is a 2-wire push-pull serial bus that operates from 50 khz to 5 mhz transmitting data in one direction. the ufm protocol is based on the i 2 c-bus protocol that consists of a start, slave add ress, command bit, 9th clock, and a stop bit. the command bit is a ?write? only, and the data bit on the 9th clock is driven high, ignoring the ack cycle due to the unidirectional nature of the bus. the 2-wire pull-pull drivers consists of a ufm clock (uscl) and data (usda), requiring external series resistors to allow proper line termination. the ufm bus is designed to be used in high performance single master multi-drop applications. the external resistors are chosen based upon the characteristic impedance of the ufm bus. for example, if the characteristic input impedance of the line is 175 ? , a series resistance of 175 ? can be used. since the output resistance of the driver is approximately 50 ? , the value of the series resist ance used would then be 125 ? . the final value of the resistance also depends upon the electrical length of the bus and the signal settling time required to meet the ufm ti ming characteristics. larger values result in longer time for the signal to settle to its final valid value. lower values can result in overshoot and ringing on the bus. careful consideration must be made in designing the i 2 c-bus routing and selecting the series resistance. 9.1 bit transfer one data bit is transferred during each cl ock pulse. the data on the usda line must remain stable during the high period of the cl ock pulse as changes in the data line at this time will be interpreted as control signals (see figure 15 ). fig 14. simplified schematic of uscl, usda outputs 002aaf143 r s , external uscl or usda pin v ss v dd(io) fig 15. ufm i 2 c-bus bit transfer 002aaf145 usda uscl p stop condition s start condition pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 35 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 9.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 16 ). 9.3 acknowledge (9th clock) the ufm bus functions as a transmitter only (unidirectional). the number of data bytes transferred between the start and the stop co nditions from transmitter to receiver is not limited. each byte of eight bits of real da ta is followed by a dummy bit which is a high level put on the bus by the transmitter, whic h also generates an associated clock pulse. since the ufm bus is unidirectional, a slave receiver shall not generate an acknowledge pulse. the slave uscl and usda pins are input only. fig 16. definition of start and stop conditions for ufm i 2 c-bus 002aaf145 usda uscl p stop condition s start condition fig 17. acknowledgement on the ufm i 2 c-bus 002aaf144 start condition 9 8 2 1 clock pulse for acknowledgement data output by transmitter scl from master master drives the line high on 9th clock cycle. slave never drives the usda line. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 36 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 10. jtag port the pcu9661 has a jtag ieee 1149.1 compliant port. all signals (tdi, tms, tck, trst and tdo) are accessible. only extest functions are enabled, for example to conduct board-level continuity tests. device deb ug/emulation functionality such as intest commands are not supported. the jtag port is used for boundary scan testing (i.e., opens/shorts) during pcb manufacturing. the following extest jtag instructions are supported: ? bypass ? extest ? idcode ? sample ? preload ? clamp ? highz if the jtag boundary scan is not being used, then the jtag pins must be held in the following states: ? tdi, tck, tms: v dd ? trst : v ss 11. application design-in information fig 18. application diagram using the 80c51 002aag277 pcu9661 80c51 decoder d0 to d7 ale ce rd wr int a0 a1 reset slave int reset address bus v dd v dd 8 v ss v dd(io) v dd v dd v ss slave uscl2 usda2 v dd(io) a2 a3 a4 a5 a6 a7 trig pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 37 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 11.1 specific applications the pcu9661 is a parallel bus to ufm i 2 c-bus controller that is designed to allow ?smart? devices to interface with ufm i 2 c-bus components, where the ?smart? device does not have an integrated ufm i 2 c-bus port and the designer does not want to ?bit-bang? the ufm i 2 c-bus port. the pcu9661 can also be used to add more ufm i 2 c-bus ports to ?smart? devices, provide a higher frequency serial bus, and avoid running multiple traces across the printed-circuit board. 11.2 add ufm i 2 c-bus port as shown in figure 19 , the pcu9661 converts 8-bits of parallel data into a single master capable i 2 c-bus port for microcontrollers, microp rocessors, custom asics, dsps, etc., that need to interface with ufm i 2 c-bus components. 11.3 add additional ufm i 2 c-bus ports the pcu9661 can be used to convert 8-bit parallel data into additional single master capable i 2 c-bus port as shown in figure 20 . it is used if the microcontroller, microprocessor, custom asic, ds p, etc., already have an i 2 c-bus port but need one or more additional ufm i 2 c-bus ports to interface with ufm i 2 c-bus components. fig 19. adding ufm i 2 c-bus port application microcontroller, microprocessor, or asic control signals 8 bits data pcu9661 002aag278 usda2 uscl2 fig 20. adding additional ufm i 2 c-bus ports application control signals 8 bits data pcu9661 002aag279 microcontroller, microprocessor, or asic usda2 uscl2 slave master i 2 c-bus pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 38 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 12. limiting values [1] 5.5 v steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 v steady stat e voltage tolerance on inputs and outputs when no supply voltage is present. 13. static characteristics table 30. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.3 +4.6 v v dd(io) input/output supply voltage power supply reference for i 2 c-bus i/o pins ? 0.3 +7.0 v v i input voltage parallel bus interface ? 0.3 +4.6 v i 2 c-bus pins [1] ? 0.3 +7.0 v i i input current any input ? 10 +10 ma i o output current any output ? 10 +10 ma i osh high-level short-circuit output current i/o d0 to d7 - 106 ma i osl low-level short-circuit output current i/o d0 to d7 - 110 ma p tot total power dissipation - 300 mw p/out power dissipation per output - 50 mw t stg storage temperature ? 65 +150 ?c t amb ambient temperature operating ? 40 +85 ?c table 31. static characteristics v dd = 3.0 v to 3.6 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supply v dd supply voltage monotonic supply during power-up and power-down with a ramp time (t ramp ): 5 ? s pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 40 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 14. dynamic characteristics [1] parameters are valid over sp ecified temperature and voltage range. [2] all voltage measurements are referenced to ground (v ss ). for testing, all inputs swing between 0 v and 3.0 v with a transition time of 5 ns maximum. all time measurements are referenced at input voltages of 1.5 v and output voltages shown in figure 21 and figure 23 . [3] test conditions for outputs: c l =50pf; r l = 500 ? , except open-drain outputs. test conditions for open-drain outputs: c l =50pf; r l =1k ? pull-up to v dd . [4] resetting the device while actively communicating on the bus may cause glitches or an errant stop condition. [5] upon reset, the full delay will be the sum of t rst and the rc time constant of the sda and scl bus. table 32. dynamic characteristics (3.3 volt) [1] [2] [3] v dd =3.3v ? 0.3 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit initialization timing t init(po) power-on initialization time v dd ? 3.0 v - - 650 ? s t init initialization time channel initialization time from channel software reset --70 ? s controller initialization time from por, reset , or global software reset inactive --650 ? s reset timing t w(rst) reset pulse width 4 - - ? s t rst reset time [4] [5] 1.5 - - ? s int timing t as(int) interrupt assert time - - 500 ns t das(int) interrupt de-assert time - - 100 ns trig timing t w(trig) trigger pulse width high or low 100 - - ns bus timing (see figure 21 and figure 23 ) t su(a) address set-up time to rd , wr low 0 - - ns t h(a) address hold time from rd , wr low 14 - - ns t su(ce_n) ce set-up time to rd , wr low 0 - - ns t h(ce_n) ce hold time from rd , wr low 0 - - ns t w(rdl) rd low pulse width 40 - - ns t w(wrl) wr low pulse width 40 - - ns t d(dv) data valid delay time after rd and ce low - - 45 ns t d(qz) data output float delay time after rd or ce high - - 7 ns t su(q) data output set-up time before wr high 5 - - ns t h(q) data output hold time after wr high 2 - - ns t w(rdh) rd high pulse width 40 - - ns t w(wrh) wr high pulse width 40 - - ns pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 41 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller fig 21. bus timing (read cycle) fig 22. parallel bus timing (write cycle) a0 to a7 ce rd d0 to d7 (read) 002aaf458 t su(a) t h(a) t su(ce_n) t h(ce_n) t w(rdl) t w(rdh) float float not valid valid t d(dv) t d(qz) a0 to a7 ce 002aaf459 t su(a) t h(a) t su(ce_n) t h(ce_n) wr valid t w(wrh) d0 to d7 (write) t su(q) t h(q) t w(wrl) pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 42 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller [1] t vd;dat = minimum time for sda data out to be valid following scl low. [2] typical rise/fall times for uf m signals is 25 ns measured from the 20 % level to the 80 % (rise time) or from the 80 % level to the 20 % level (fall time). v m =1.5v v x =v ol +0.2v v y =v oh ? 0.2 v v ol and v oh are typical output voltage drops that occur with the output load. fig 23. data timing 002aaf172 t d(qlz) t d(qhz) outputs floating outputs enabled outputs enabled dn output low-to-float float-to-low dn output high-to-float float-to-high rd, ce input v i v ol v oh v dd v m v m v x v y v m v ss v ss t d(qzl) t d(qzh) v m table 33. ufm i 2 c-bus frequency and timing specifications all the timing limits are valid within the operating supply voltage and ambient temperature range; v dd =2.5v ? 0.2 v and 3.3 v ? 0.3 v; t amb = ? 40 ? c to +85 ? c; and refer to v il and v ih with an input voltage of v ss to v dd . symbol parameter conditions ultra fast-mode i 2 c-bus unit min max f uscl uscl clock frequency 0 5000 khz t buf bus free time between a stop and start condition 0.08 - ? s t hd;sta hold time (repeated) start condition 0.05 - ? s t su;sta set-up time for a repeated start condition 0.05 - ? s t su;sto set-up time for stop condition 0.05 - ? s t hd;dat data hold time 10 - ns t vd;dat data valid time [1] 10 - ns t su;dat data set-up time 30 - ns t low low period of the uscl clock 0.05 - ? s t high high period of the uscl clock 0.05 - ? s t f fall time of both usda and uscl signals - [2] 50 ns t r rise time of both usda and uscl signals - [2] 50 ns pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 43 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller fig 24. definition of timing on the ufm i 2 c-bus usda2 uscl2 002aag280 t f s sr p s t hd;sta t low t r t su;dat t f t hd;dat t high t su;sta t hd;sta t su;sto t r t buf rise and fall times refer to v il and v ih . fig 25. ufm i 2 c-bus timing diagram uscl2 usda2 t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high 002aag281 protocol start condition (s) bit 7 msb bit 6 bit n bit 0 acknowledge (a) 1 /f uscl t r t vd;dat t su;sto stop condition (p) pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 44 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 15. test information test data are given in ta b l e 3 4 . r l = load resistance. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 26. test circuitry for switching times table 34. test data test conditions load s1 c l r l t d(dv) , t d(qz) dn outputs active low 50 pf 500 ? v dd ? 2 dn outputs active high 50 pf 500 ? open test data are given in ta b l e 3 5 . r l = load resistance. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 27. test circuitry for open-drain switching times table 35. test data test load s1 c l r l t as(int) 50 pf 1 k ? v dd t das(int) 50 pf 1 k ? v dd pulse generator v o c l 50 pf r l 500 002aac694 r t v i v dd dut r l 500 v dd 2 open v ss pulse generator v o c l 50 pf r l 1 k 002aac695 r t v i v dd dut v dd open v ss pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 45 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 16. package outline fig 28. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2 pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 46 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 17. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are: pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 47 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 18.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 29 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 3 6 and 37 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 29 . table 36. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 37. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 48 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 19. abbreviations msl: moisture sensitivity level fig 29. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 38. abbreviations acronym description asic application specific integrated circuit cdm charged-device model cpu central processing unit dsp digital signal processor esd electrostatic discharge fm+ fast-mode plus hbm human body model i 2 c-bus inter-integrated circuit bus i/o input/output led light emitting diode mcu microcontroller unit pcb printed-circuit board pll phase-locked loop smbus system management bus ufm ultra fast-mode pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 49 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 20. revision history table 39. revision history document id release date data sheet status change notice supersedes pcu9661 v.1 20110912 product data sheet - - pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 50 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 21.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 21.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. pcu9661 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 12 september 2011 51 of 52 nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 21.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors pcu9661 parallel bus to 1 channel ufm i 2 c-bus controller ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 12 september 2011 document identifier: pcu9661 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 internal oscillator and pll . . . . . . . . . . . . . . . . 6 7.3 buffer description . . . . . . . . . . . . . . . . . . . . . . . 6 7.3.1 buffer management assumptions . . . . . . . . . . . 7 7.3.2 buffer size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.4 error reporting and handling . . . . . . . . . . . . . . . 7 7.5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.5.1 channel registers . . . . . . . . . . . . . . . . . . . . . . 10 7.5.1.1 status2_[n] ? transa ction status registers 10 7.5.1.2 control ? control register . . . . . . . . . . . . 11 7.5.1.3 chstatus ? channel status register . . . . . 14 7.5.1.4 intmsk ? interrupt mask register. . . . . . . . . 15 7.5.1.5 slatable ? slave address table register . . 16 7.5.1.6 tranconfig ? tr ansaction configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5.1.7 data ? i 2 c-bus data register . . . . . . . . . . . . 17 7.5.1.8 transel ? transaction data buffer select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.5.1.9 tranofs ? transaction data buffer byte select register . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5.1.10 bytecount ? tr ansmitted and received byte count register . . . . . . . . . . . . . . . . . . . . . 19 7.5.1.11 framecnt ? frame c ount register . . . . . . . 19 7.5.1.12 refrate ? refresh rate register. . . . . . . . . 20 7.5.1.13 sclper, sdadly ? clock rate registers. . . 20 7.5.1.14 mode ? i 2 c-bus mode register . . . . . . . . . . 22 7.5.1.15 preset ? i 2 c-bus channel parallel software reset register. . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.5.2 global registers . . . . . . . . . . . . . . . . . . . . . . . 23 7.5.2.1 ctrlstatus ? controller status register . . 23 7.5.2.2 ctrlintmsk ? control interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5.2.3 device_id ? device id . . . . . . . . . . . . . . . . 24 7.5.2.4 ctrlpreset ? para llel software reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5.2.5 ctrlrdy ? controller ready register. . . . . . 25 8 pcu9661 operation . . . . . . . . . . . . . . . . . . . . . 26 8.1 sequence execution . . . . . . . . . . . . . . . . . . . 27 8.2 stopping a sequence . . . . . . . . . . . . . . . . . . . 30 8.3 looping a sequence. . . . . . . . . . . . . . . . . . . . 30 8.3.1 looping with refrate control . . . . . . . . . . . 31 8.3.2 looping with trigger control. . . . . . . . . . . . . . 31 8.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 31 8.5 global reset . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.6 channel reset. . . . . . . . . . . . . . . . . . . . . . . . . 33 8.7 i 2 c-bus timing diagram . . . . . . . . . . . . . . . . . 33 9 characteristics of the i 2 c-bus ? ultra fast-mode (ufm). . . . . . . . . . . . . . . . . . . . . . . 34 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 start and stop conditions. . . . . . . . . . . . . 35 9.3 acknowledge (9th clock) . . . . . . . . . . . . . . . . 35 10 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 application design-in information. . . . . . . . . 36 11.1 specific applications. . . . . . . . . . . . . . . . . . . . 37 11.2 add ufm i 2 c-bus port . . . . . . . . . . . . . . . . . . 37 11.3 add additional ufm i 2 c-bus ports . . . . . . . . . 37 12 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38 13 static characteristics . . . . . . . . . . . . . . . . . . . 38 14 dynamic characteristics. . . . . . . . . . . . . . . . . 40 15 test information . . . . . . . . . . . . . . . . . . . . . . . 44 16 package outline. . . . . . . . . . . . . . . . . . . . . . . . 45 17 handling information . . . . . . . . . . . . . . . . . . . 46 18 soldering of smd packages . . . . . . . . . . . . . . 46 18.1 introduction to soldering. . . . . . . . . . . . . . . . . 46 18.2 wave and reflow soldering. . . . . . . . . . . . . . . 46 18.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 46 18.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 47 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 48 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 49 21 legal information . . . . . . . . . . . . . . . . . . . . . . 50 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 50 21.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 21.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 50 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51 22 contact information . . . . . . . . . . . . . . . . . . . . 51 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 |
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