1 2153bs?bdc?08/03 features ? dual adc ? 8-bit resolution ? 1 gsps sampling rate per channel ? 2 gsps equivalent sampling rate with one channel (interlaced mode) ? 500 mvpp analog input (differential only) ? differential or single-ended 50 ? pecl/lvds compatible clock inputs ? lvds output format (100 ? ) ? 3-wire serial interface (16-bit data, 3-bit address): ? full or partial standby mode ? 1:2 or 1:1 selectable data output demultiplexer ? analog gain (1.5 db) digital control ? input clock selection ? analog input switch selection ? binary or gray logical outputs ? asynchronous data ready reset ? data ready delay adjustable on both channels ? interlacing functions: offset and gain (channel to channel) calibration digital fine sda (fine sampling delay adjust) on one channel ? internal static or dynamic built-in test (bit) ? very low input capacitance: 2 pf ? power supply: 3.3 v (analog), 3.3 v (digital), 2.25 v (output) ? lqfp144 ? temperature range: ? ?c? grade: 0c < t a < 70c ? ?i? grade: -20c < t a < 85c performance ? low power consumption: 1.4 w (typ) ? power consumption in standby mode: 60 mw ? 1.5 ghz full power input bandwidth (-3 db) ? sinad = 46 db typ (7.3 enob), thd = -60 db, sfdr = - 62 db at fs = 1 gsps, fin = 500 mhz ? 2-tone imd: -60 dbc min (499 mhz, 501 mhz) at 1 gsps ? dnl = 0.25 lsb typ, inl = 0.5 lsb typ ? channel to channel input offset error: 0.5 lsb ma x (after calibration) ? gain matching (channel to channel): 0.5 lsb max (after calibration) ? low bit error rate (2.10 -13 ) at 1 gsps application ? instrumentation ? satellite receiver ? direct rf down conversion ? wlan description ? the ad84ad001b is a monolithic low-power (1.4 w typ) dual 8-bit analog-to-digital converter, designed for digitizing in-phase (i) and quadrature (q) wide bandwidth analog signals at very high sampling rates of up to 1 gsps. the ability to directly interface i and q signals makes the ad84ad001b ideal for use in direct satellite demodulation applications or dual channel acquisition applications (instrumentation). ? the ad84ad001b uses an innovative architecture, including an on-chip sample and hold (s/h), and is manufactured with an advanced high-speed bicmos process. ? the on-chip 2 s/h have a well matched 1.5 ghz full power input bandwidth, providing excellent dynamic performance in undersampling app lications (high if digitizing). ? a 3-wire serial bus interface provides extra adj ustment (standby mode, input range, gray or binary coding). dual 8-bit 1 gsps adc AT84AD001b smart adc ? preliminary summary for more information please contact hotline-bdc@gfo.atmel.com
2 AT84AD001b [preliminary] 2153bs?bdc?08/03 functional description the AT84AD001b is a dual 8-bit 1gsps adc based on an advanced high-speed bicmos technology. each adc includes a front-end analog multiplexer followed by a sample and hold (s/h), and an 8-bit flash-like architecture core analog to digital converter. the output data is followed by a switchable 1:1 or 1:2 demultiplexer and lvds output buffers (100 w). two over-range bits are given for external gain control adjustment on each channel. a 3-wire serial interface (3-bit address, 16-bit data) is included to provide several adjustments: ? analog input range adjustment (1.5 db) with 8-bit data control using a 3-wire bus interface (step of 0.18 db) ? analog input switch: both adcs can convert the same analog input signal i or q ? gray or binary encoder output. output format: demux 1:2 or 1:1 with control output frequency on data ready output signal ? partial or full standby channel i or q ? clock selection: ? two independent clocks clki and clkq ? one master clock (clki) with same phase for channel i and q ? one master clock but with two phases (clki for channel i, clkib for channel q) ? isa: internal settling adjustment on channel i and q ? fisda: fine sampling delay adjustment on channel q ? adjustable data ready output delay on both channels ? test mode: decimation mode with a selectable factor (4, 8, 16, 32). bit error rate (between the 3 most significant bits), adc gain, offset and drda test setting. a calibration phase is provided to set the two dc offsets of channel i and q close to code 127.5 and calibrate the two gains to achieve a maximum difference of 0.5 lsb. the offset and gain error can also be set externally via the 3-wire serial interface. the ad84ad001b works in fully differential mode from analog inputs up to digital out- puts. the ad84ad001b features a full power input bandwidth of 1.5 ghz.
3 this is a summary document. a complete document is not available at this time. for more information, please contact your local atmel sales office AT84AD001b [preliminary] 2153bs?bdc?08/03 figure 1. simplified block diagram doiri, doirin doirq, doirqn clki clock buffer divider 2 to 32 drda i lvds clock buffer 2 clkio ddrb 16 doai, doain 8bit adc i demux 1:2 or 1:1 i lvds buffer i doiri input mux + vini s/h 16 dobi, dobin vinib 8 - 2 gain control i calibration gain/offset isa i demux control bit data clock ldn 3 wire serial interface 3wsi input switch gain control q calibration gain/offset isa q & fisda demux control mode 2 doirq lvds buffer q 8bit adc q demux 1:2 or 1:1 q + vinq s/h 16 doaq, doaqn vinqb - 8 16 dobq, dobqn clkq clock buffer divider 2 to 32 drda q lvds clock buffer 2 clkqo ddrb
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