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| dsp56003/005 24-bit digital signal processor user? manual motorola, inc. semiconductor products sector dsp division 6501 william cannon drive, west austin, texas 78735-8598 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
order this document by dsp56003um/ad motorola reserves the right to make changes without further notice to any products herein to im- prove reliability, function or design. motorola does not assume any liability arising out of the appli- cation or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. buyer agrees to notify motorola of any such intended end use whereupon motorola shall determine availability and suitability of its product or products for the use intended. motorola and m are registered trademarks of motorola, inc. motorola, inc. is an equal employment oppor- tunity /af?mative action employer. once ? is a trade mark of motorola, inc. ? motorola inc., 1994 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola table of contents iii table of contents paragraph page number title number section 1 introduction to the dsp56003/005 1.1 manual introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.1 related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.2 training. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.1.3 technical assistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.1.4 manual conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.1.5 manual organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.2 product use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.3 dsp56003/005 architectural overview . . . . . . . . . . . . . . . . 1-9 1.3.1 dsp56003/005 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.3.2 block diagram description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.3.2.1 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.3.2.2 address buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.3.2.3 data alu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.3.2.4 address generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.2.5 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.3.2.5.1 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.3.2.5.2 x data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.2.5.3 y data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.2.5.4 bootstrap rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.2.6 program control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.2.7 phase-locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.3.2.8 on-chip emulator (once ? ) port . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.3.2.9 input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.3.2.9.1 external memory interface (port a) . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.3.2.9.2 general purpose i/o (hi, sci, ssi, timer/event counter) . . . . . 1-20 1.3.2.9.3 host interface (hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.3.2.9.4 serial communication interface (sci) . . . . . . . . . . . . . . . . . . . . . 1-21 1.3.2.9.5 synchronous serial interface (ssi) . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.3.2.9.6 timer/event counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.3.2.9.7 pulse width modulators (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.3.2.9.8 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . iv table of contents motorola table of contents (continued) paragraph page number title number section 2 pin descriptions 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.1 port a address bus, data bus, and basic bus control. . . . . . . . . . . 2-5 2.2.1.1 address bus (a0?15) ?three-state, outputs . . . . . . . . . . . . . . .2-5 2.2.1.2 data bus (d0?23) ?three-state, bidirectional input/outputs . . . .2-5 2.2.1.3 program memory select (ps ) ?three-state, active low output . . .2-5 2.2.1.4 data memory select (ds ) ?three-state, active low output . . . . . .2-5 2.2.1.5 x/y select (x/y ) ?three-state output . . . . . . . . . . . . . . . . . . . . . .2-6 2.2.1.6 read enable (rd ) ?three-state, active low output . . . . . . . . . . . .2-6 2.2.1.7 write enable (wr ) ?three-state, active low output . . . . . . . . . . .2-6 2.2.1.8 external peripheral (extp ) ?active low output . . . . . . . . . . . . . .2-6 2.2.2 enhanced bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.2.1 bus needed (bn ) ?active low output ?dsp56003 only . . . . . .2-7 2.2.2.2 bus request (br ) ?active low input ?dsp56003 only . . . . . . .2-7 2.2.2.3 bus grant (bg ) ?active low output ?dsp56003 only . . . . . . . .2-8 2.2.2.4 bus strobe (bs ) ?active low output ?dsp56003 only . . . . . . .2-8 2.2.2.5 bus wait (wt ) ?active low input ?dsp56003 only . . . . . . . . . .2-8 2.2.3 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.3.1 host data bus (h0?7) ?bidirectional . . . . . . . . . . . . . . . . . . . . .2-9 2.2.3.2 host address (ha0?a2) ?input . . . . . . . . . . . . . . . . . . . . . . . . .2-9 2.2.3.3 host read/write (hr/w ) ?input* . . . . . . . . . . . . . . . . . . . . . . . . .2-9 2.2.3.4 host enable (hen ) ?active low input* . . . . . . . . . . . . . . . . . . . . .2-9 2.2.3.5 host request (hreq ) ?active low output* . . . . . . . . . . . . . . . . .2-9 2.2.3.6 host acknowledge (ha ck ) ?active low input* . . . . . . . . . . . . . . .2-10 2.2.4 serial communication interface (sci). . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.2.4.1 receive data (rxd) ?input* . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 2.2.4.2 transmit data (txd) ?output* . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10 2.2.4.3 sci serial clock (sclk) ?bidirectional . . . . . . . . . . . . . . . . . . . .2-11 2.2.5 synchronous serial interface (ssi) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.2.5.1 serial control 0 (sc0) ?bidirectional . . . . . . . . . . . . . . . . . . . . . .2-11 2.2.5.2 serial control 1 (sc1) ?bidirectional . . . . . . . . . . . . . . . . . . . . . .2-11 2.2.5.3 serial control 2 (sc2) ?bidirectional . . . . . . . . . . . . . . . . . . . . . .2-11 2.2.5.4 ssi serial clock (sck) ?bidirectional . . . . . . . . . . . . . . . . . . . . .2-11 2.2.5.5 ssi receive data (srd) ?input* . . . . . . . . . . . . . . . . . . . . . . . . .2-12 2.2.5.6 ssi transmit data (std) ?output* . . . . . . . . . . . . . . . . . . . . . . . .2-12 2.2.6 timer/event counter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.6.1 timer/event counter input/output (tio) ?bidirectional . . . . . . . .2-12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola table of contents v table of contents (continued) paragraph page number title number 2.2.7 pulse width modulator a (pwma) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.7.1 pulse width modulator a positive (pwap0 - pwap2) ? output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.2.7.2 pulse width modulator a negative (pwan0 - pwan2) ? output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.2.7.3 pulse width modulator a carrier (pwac0 - pwac2) ?input . . . 2-13 2.2.7.4 pulse width modulator a clock (pwaclk) ?input . . . . . . . . . . . 2-13 2.2.8 pulse width modulator b (pwmb) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.2.8.1 pulse width modulator b carrier (pwbc) ?input . . . . . . . . . . . . 2-14 2.2.8.2 pulse width modulator b output (pwb0 -pwb1 ) ? active low output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.2.8.3 pulse width modulator b clock (pwbclk) ?input . . . . . . . . . . . 2-14 2.2.9 on-chip emulation (once ? ) port . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.2.9.1 debug serial input/chip status 0 (dsi/os0) ?bidirectional . . . . 2-14 2.2.9.2 debug serial clock/chip status 1 (dsck/os1) ?bidirectional . . 2-15 2.2.9.3 debug serial output (dso) ?output . . . . . . . . . . . . . . . . . . . . . . 2-15 2.2.9.4 debug request (dr ) ?active low input . . . . . . . . . . . . . . . . . . . . 2-15 2.2.10 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.2.10.1 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.2.10.2 ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.2.11 interrupt and mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.2.11.1 mode select a/external interrupt request a (moda/irqa ) ? input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.2.11.2 mode select b/external interrupt request b (modb/irqb ) ? input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.2.11.3 mode select c/non-maskable interrupt request (modc/nmi ) ? edge triggered input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.2.11.4 external interrupt request c (irqc ) ?edge triggered input . . . . 2-19 2.2.11.5 external interrupt request d (irqd ) ?edge triggered input . . . . 2-19 2.2.11.6 reset (reset ) ?input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.2.12 clock, oscillator, and pll pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.2.12.1 output clock (ckout) ?output . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.2.12.2 ckout polarity control (ckp) ?input. ?dsp56003 only . . . . 2-20 2.2.12.3 external clock/crystal (extal) ?input . . . . . . . . . . . . . . . . . . . . 2-20 2.2.12.4 crystal (xtal) ?output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.2.12.5 pll filter capacitor (pcap) ?input . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.2.12.6 pll initialization (pinit) ?input . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.2.12.7 phase and frequency locked (plock) ?output ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . vi table of contents motorola table of contents (continued) paragraph page number title number section 3 memory, operating modes, and interrupts 3.1 memory introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.1.1 dsp56003/005 data and program memory . . . . . . . . . . . . . . . . . . . 3-3 3.1.1.1 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3 3.1.1.2 x data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4 3.1.1.3 y data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5 3.2 dsp56003/005 operating mode register (omr) . . . . . . . . . . 3-6 3.2.1 omr chip operating mode (mc, mb, ma) bits 4, 1, and 0 . . . . . . . 3-6 3.2.2 omr data rom enable (de) bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.3 omr internal y memory disable (yd) bit 3 . . . . . . . . . . . . . . . . . . . 3-7 3.2.4 omr chip operating mode (mc) bit 4 . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.5 omr reserved bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.6 omr stop delay (sd) bit 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.7 omr reserved bits 7?3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3 dsp56003/005 operating modes . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.1 single chip mode (mode 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.2 bootstrap from eprom at $c000 (mode 1) . . . . . . . . . . . . . . . . . . 3-9 3.3.3 normal expanded mode (mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.3.4 development mode (mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.3.5 reserved (mode 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.3.6 bootstrap from host (mode 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.3.7 bootstrap from sci (mode 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.3.8 bootstrap from eprom at $8000 (mode 7) . . . . . . . . . . . . . . . . . . . 3-12 3.4 dsp56003/005 interrupt priority register . . . . . . . . . . . . . 3-12 3.5 dsp56003/005 phase-locked loop (pll) configuration . . 3-13 section 4 external memory interface 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.4 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.5 bus control register (bcr). . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.6 bus strobe and wait pins ?dsp56003 only . . . . . . . . . . . . . 4-15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola table of contents vii table of contents (continued) paragraph page number title number 4.7 bus arbitration and shared memory ?dsp56003 only. . 4-16 4.7.1 bus arbitration using only br and bg with internal control ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.7.2 bus arbitration using bn , br , and bg with external control ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.7.3 arbitration using br and bg , and wt and bs with no overhead ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4.7.4 signaling using semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 section 5 host interface 5.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 general purpose i/o configuration . . . . . . . . . . . . . . . . . . 5-4 5.2.1 programming general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.2.2 port b general purpose i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 host interface (hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.1 host interface ?dsp cpu viewpoint. . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.2 programming model ?dsp cpu viewpoint. . . . . . . . . . . . . . . . . . . 5-12 5.3.2.1 host control register (hcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.3.2.1.1 hcr host receive interrupt enable (hrie) bit 0 . . . . . . . . . . . . 5-14 5.3.2.1.2 hcr host transmit interrupt enable (htie) bit 1 . . . . . . . . . . . . 5-14 5.3.2.1.3 hcr host command interrupt enable (hcie) bit 2 . . . . . . . . . . 5-14 5.3.2.1.4 hcr host flag 2 (hf2) bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.3.2.1.5 hcr host flag 3 (hf3) bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.2.1.6 hcr reserved bits 5, 6, and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.2.2 host status register (hsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.2.2.1 hsr host receive data full (hrdf) bit 0 . . . . . . . . . . . . . . . . . 5-15 5.3.2.2.2 hsr host transmit data empty (htde) bit 1 . . . . . . . . . . . . . . 5-15 5.3.2.2.3 hsr host command pending (hcp) bit 2 . . . . . . . . . . . . . . . . . 5-16 5.3.2.2.4 hsr host flag 0 (hf0) bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.2.2.5 hsr host flag 1 (hf1) bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.2.2.6 hsr reserved bits 5 and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.2.2.7 hsr dma status (dma) bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.2.3 host receive data register (hrx) . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.2.4 host transmit data register (htx) . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.2.5 register contents after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.2.6 host interface dsp cpu interrupts . . . . . . . . . . . . . . . . . . . . . . . . 5-18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . viii table of contents motorola table of contents (continued) paragraph page number title number 5.3.2.7 host port use considerations ?dsp side . . . . . . . . . . . . . . . . . . .5-18 5.3.3 host interface ?host processor viewpoint. . . . . . . . . . . . . . . . . . . . 5-19 5.3.3.1 programming model ?host processor viewpoint . . . . . . . . . . . . .5-20 5.3.3.2 interrupt control register (icr) . . . . . . . . . . . . . . . . . . . . . . . . . . .5-20 5.3.3.2.1 icr receive request enable (rreq) bit 0 . . . . . . . . . . . . . . . .5-22 5.3.3.2.2 icr transmit request enable (treq) bit 1 . . . . . . . . . . . . . . . .5-22 5.3.3.2.3 icr reserved bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 5.3.3.2.4 icr host flag 0 (hf0) bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 5.3.3.2.5 icr host flag 1 (hf1) bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23 5.3.3.2.6 icr host mode control (hm1 and hm0 bits) bits 5 and 6 . . . . . .5-23 5.3.3.2.7 icr initialize bit (init) bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-24 5.3.3.3 command vector register (cvr) . . . . . . . . . . . . . . . . . . . . . . . . .5-26 5.3.3.3.1 cvr host vector (hv) bits 0? . . . . . . . . . . . . . . . . . . . . . . . . . .5-26 5.3.3.3.2 cvr reserved bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27 5.3.3.3.3 cvr host command bit (hc) bit 7 . . . . . . . . . . . . . . . . . . . . . . .5-27 5.3.3.4 interrupt status register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-27 5.3.3.4.1 isr receive data register full (rxdf) bit 0 . . . . . . . . . . . . . . .5-27 5.3.3.4.2 isr transmit data register empty (txde) bit 1 . . . . . . . . . . . . .5-28 5.3.3.4.3 isr transmitter ready (trdy) bit 2 . . . . . . . . . . . . . . . . . . . . . .5-28 5.3.3.4.4 isr host flag 2 (hf2) bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-28 5.3.3.4.5 isr host flag 3 (hf3) bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-28 5.3.3.4.6 isr reserved bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-28 5.3.3.4.7 isr dma status (dma) bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 5.3.3.4.8 isr host request (hreq) bit 7 . . . . . . . . . . . . . . . . . . . . . . . . .5-29 5.3.3.5 interrupt vector register (ivr) . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-29 5.3.3.6 receive byte registers (rxh, rxm, rxl) . . . . . . . . . . . . . . . . . .5-29 5.3.3.7 transmit byte registers (txh, txm, txl) . . . . . . . . . . . . . . . . . .5-30 5.3.3.8 registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30 5.3.4 host interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.3.4.1 host data bus (h0-h7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-30 5.3.4.2 host address (ha0?a2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-31 5.3.4.3 host read/write (hr/w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 5.3.4.4 host enable (hen ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 5.3.4.5 host request (hreq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-32 5.3.4.6 host acknowledge (hack ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-33 5.3.5 servicing the host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.3.5.1 hi host processor data transfer . . . . . . . . . . . . . . . . . . . . . . . . . .5-34 5.3.5.2 hi interrupts host request (hreq ) . . . . . . . . . . . . . . . . . . . . . . . .5-34 5.3.5.3 polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-35 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola table of contents ix table of contents (continued) paragraph page number title number 5.3.5.4 servicing non-dma interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 5.3.5.5 servicing dma interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5.3.6 hi application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5.3.6.1 hi initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 5.3.6.2 polling/interrupt controlled data transfer . . . . . . . . . . . . . . . . . . . 5-38 5.3.6.2.1 host to dsp ?data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5.3.6.2.2 host to dsp ?command vector . . . . . . . . . . . . . . . . . . . . . . . . 5-43 5.3.6.2.3 host to dsp ?bootstrap loading using the hi . . . . . . . . . . . . . 5-50 5.3.6.2.4 dsp to host data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 5.3.6.3 dma data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 5.3.6.3.1 host to dsp internal processing . . . . . . . . . . . . . . . . . . . . . . . . 5-56 5.3.6.3.2 host to dsp dma procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58 5.3.6.3.3 dsp to host internal processing . . . . . . . . . . . . . . . . . . . . . . . . . 5-59 5.3.6.3.4 dsp to host dma procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60 5.3.6.4 example circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 5.3.6.5 host port use considerations ?host side . . . . . . . . . . . . . . . . . 5-63 section 6 serial communications interface 6.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 general-purpose i/o (port c) . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.1 programming general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2.2 port c general purpose i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.3 serial communication interface (sci). . . . . . . . . . . . . . . . . 6-10 6.3.1 sci i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.1.1 receive data (rxd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.1.2 transmit data (txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.1.3 sci serial clock (sclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.2 sci programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.3.2.1 sci control register (scr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.3.2.1.1 scr word select (wds0, wds1, wds2) bits 0, 1, and 2 . . . . 6-13 6.3.2.1.2 scr sci shift direction (ssftd) bit 3 . . . . . . . . . . . . . . . . . . . . 6-14 6.3.2.1.3 scr send break (sbk) bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.3.2.1.4 scr wakeup mode select (wake) bit 5 . . . . . . . . . . . . . . . . . . 6-17 6.3.2.1.5 scr receiver wakeup enable (rwu) bit 6 . . . . . . . . . . . . . . . . 6-17 6.3.2.1.6 scr wired-or mode select (woms) bit 7 . . . . . . . . . . . . . . . . 6-18 6.3.2.1.7 scr receiver enable (re) bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . x table of contents motorola table of contents (continued) paragraph page number title number 6.3.2.1.8 scr transmitter enable (te) bit 9 . . . . . . . . . . . . . . . . . . . . . . .6-18 6.3.2.1.9 scr idle line interrupt enable (ilie) bit 10 . . . . . . . . . . . . . . . .6-19 6.3.2.1.10 scr sci receive interrupt enable (rie) bit 11 . . . . . . . . . . . . .6-19 6.3.2.1.11 scr sci transmit interrupt enable (tie) bit 12 . . . . . . . . . . . . .6-20 6.3.2.1.12 scr timer interrupt enable (tmie) bit 13 . . . . . . . . . . . . . . . . .6-20 6.3.2.1.13 scr sci timer interrupt rate (stir) bit 14 . . . . . . . . . . . . . . . .6-20 6.3.2.1.14 scr sci clock polarity (sckp) bit 15 . . . . . . . . . . . . . . . . . . . .6-20 6.3.2.2 sci status register (ssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20 6.3.2.2.1 ssr transmitter empty (trne) bit 0 . . . . . . . . . . . . . . . . . . . . .6-21 6.3.2.2.2 ssr transmit data register empty (tdre) bit 1 . . . . . . . . . . . .6-21 6.3.2.2.3 ssr receive data register full (rdrf) bit 2 . . . . . . . . . . . . . .6-21 6.3.2.2.4 ssr idle line flag (idle) bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . .6-22 6.3.2.2.5 ssr overrun error flag (or) bit 4 . . . . . . . . . . . . . . . . . . . . . . .6-22 6.3.2.2.6 ssr parity error (pe) bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22 6.3.2.2.7 ssr framing error flag (fe) bit 6 . . . . . . . . . . . . . . . . . . . . . . .6-22 6.3.2.2.8 ssr received bit 8 address (r8) bit 7 . . . . . . . . . . . . . . . . . . . .6-22 6.3.2.3 sci clock control register (sccr) . . . . . . . . . . . . . . . . . . . . . . . .6-23 6.3.2.3.1 sccr clock divider (cd11?d0) bits 11? . . . . . . . . . . . . . . . .6-24 6.3.2.3.2 sccr clock out divider (cod) bit 12 . . . . . . . . . . . . . . . . . . . .6-24 6.3.2.3.3 sccr sci clock prescaler (scp) bit 13 . . . . . . . . . . . . . . . . . . .6-24 6.3.2.3.4 sccr receive clock mode source (rcm) bit 14 . . . . . . . . . . . .6-25 6.3.2.3.5 sccr transmit clock source (tcm) bit 15 . . . . . . . . . . . . . . . .6-25 6.3.2.4 sci data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26 6.3.2.4.1 sci receive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26 6.3.2.4.2 sci transmit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28 6.3.2.5 preamble, break, and data transmission priority . . . . . . . . . . . . .6-29 6.3.3 register contents after reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6.3.4 sci initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6.3.5 sci exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6.3.6 synchronous data mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36 6.3.7 asynchronous data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 6.3.7.1 asynchronous data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-44 6.3.7.2 asynchronous data transmission . . . . . . . . . . . . . . . . . . . . . . . . .6-44 6.3.8 multidrop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 6.3.8.1 transmitting data and address characters . . . . . . . . . . . . . . . . . .6-54 6.3.8.2 wired-or mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-54 6.3.8.3 idle line wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-54 6.3.8.4 address mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-58 6.3.8.5 multidrop example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-61 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola table of contents xi table of contents (continued) paragraph page number title number 6.3.9 sci timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-66 6.3.10 bootstrap loading through the sci (operating mode 6). . . . . . . . . 6-69 6.3.11 example circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70 section 7 synchronous serial interface 7.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 general-purpose i/o (port c) . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1 programming general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.2 port c general purpose i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.3 synchronous serial interface (ssi) . . . . . . . . . . . . . . . . . . 7-10 7.3.1 ssi data and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.3.1.1 serial transmit data pin (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.1.2 serial receive data pin (srd) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.3.1.3 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.3.1.4 serial control pin (sc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7.3.1.5 serial control pin (sc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.3.1.6 serial control pin (sc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7.3.2 ssi programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 7.3.2.1 ssi control register a (cra) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 7.3.2.1.1 cra prescale modulus select (pm7?m0) bits 0? . . . . . . . . . 7-17 7.3.2.1.2 cra frame rate divider control (dc4?c0) bits 8?2 . . . . . . 7-17 7.3.2.1.3 cra word length control (wl0, wl1) bits 13 and 14 . . . . . . . 7-21 7.3.2.1.4 cra prescaler range (psr) bit 15 . . . . . . . . . . . . . . . . . . . . . . 7-21 7.3.2.2 ssi control register b (crb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7.3.2.2.1 crb serial output flag 0 (of0) bit 0 . . . . . . . . . . . . . . . . . . . . . 7-22 7.3.2.2.2 crb serial output flag 1 (of1) bit 1 . . . . . . . . . . . . . . . . . . . . . 7-22 7.3.2.2.3 crb serial control 0 direction (scd0) bit 2 . . . . . . . . . . . . . . . 7-22 7.3.2.2.4 crb serial control 1 direction (scd1) bit 3 . . . . . . . . . . . . . . . 7-22 7.3.2.2.5 crb serial control 2 direction (scd2) bit 4 . . . . . . . . . . . . . . . 7-22 7.3.2.2.6 crb clock source direction (sckd) bit 5 . . . . . . . . . . . . . . . . . 7-24 7.3.2.2.7 crb shift direction (shfd) bit 6 . . . . . . . . . . . . . . . . . . . . . . . . 7-24 7.3.2.2.8 crb frame sync length (fsl0 and fsl1) bits 7 and 8 . . . . . . 7-24 7.3.2.2.9 crb sync/async (syn) bit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 7.3.2.2.10 crb gated clock control (gck) bit 10 . . . . . . . . . . . . . . . . . . . 7-25 7.3.2.2.11 crb ssi mode select (mod) bit 11 . . . . . . . . . . . . . . . . . . . . . . 7-25 7.3.2.2.12 crb ssi transmit enable (te) bit 12 . . . . . . . . . . . . . . . . . . . . 7-25 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xii table of contents motorola table of contents (continued) paragraph page number title number 7.3.2.2.13 crb ssi receive enable (re) bit 13 . . . . . . . . . . . . . . . . . . . . .7-26 7.3.2.2.14 crb ssi transmit interrupt enable (tie) bit 14 . . . . . . . . . . . . .7-26 7.3.2.2.15 crb ssi receive interrupt enable (rie) bit 15 . . . . . . . . . . . . .7-26 7.3.2.3 ssi status register (ssisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27 7.3.2.3.1 ssisr serial input flag 0 (if0) bit 0 . . . . . . . . . . . . . . . . . . . . . .7-27 7.3.2.3.2 ssisr serial input flag 1 (if1) bit 1 . . . . . . . . . . . . . . . . . . . . . .7-27 7.3.2.3.3 ssisr transmit frame sync flag (tfs) bit 2 . . . . . . . . . . . . . .7-27 7.3.2.3.4 ssisr receive frame sync flag (rfs) bit 3 . . . . . . . . . . . . . . .7-28 7.3.2.3.5 ssisr transmitter underrun error flag (tue) bit 4 . . . . . . . . . .7-29 7.3.2.3.6 ssisr receiver overrun error flag (roe) bit 5 . . . . . . . . . . . . .7-30 7.3.2.3.7 ssisr ssi transmit data register empty (tde) bit 6 . . . . . . . .7-30 7.3.2.3.8 ssisr ssi receive data register full (rdf) bit 7 . . . . . . . . . . .7-30 7.3.2.4 ssi receive shift register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-30 7.3.2.5 ssi receive data register (rx) . . . . . . . . . . . . . . . . . . . . . . . . . .7-32 7.3.2.6 ssi transmit shift register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-32 7.3.2.7 ssi transmit data register (tx) . . . . . . . . . . . . . . . . . . . . . . . . . .7-32 7.3.2.8 time slot register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-32 7.3.3 operational modes and pin definitions . . . . . . . . . . . . . . . . . . . . . . . 7-34 7.3.4 registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35 7.3.5 ssi initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 7.3.6 ssi exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 7.3.7 operating modes ?normal, network, and on-demand . . . . . . . . . . 7-44 7.3.7.1 data/operation formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-45 7.3.7.1.1 normal/network mode selection . . . . . . . . . . . . . . . . . . . . . . . . .7-45 7.3.7.1.2 continuous/gated clock selection . . . . . . . . . . . . . . . . . . . . . . .7-45 7.3.7.1.3 synchronous/asynchronous operating modes . . . . . . . . . . . . . .7-45 7.3.7.1.4 frame sync selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-55 7.3.7.1.5 shift direction selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-59 7.3.7.2 normal mode examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-59 7.3.7.2.1 normal mode transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-59 7.3.7.2.2 normal mode receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-65 7.3.7.3 network mode examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-67 7.3.7.3.1 network mode transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-70 7.3.7.3.2 network mode receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-76 7.3.7.4 on-demand mode examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-77 7.3.7.4.1 on-demand mode ?continuous clock . . . . . . . . . . . . . . . . . . . .7-80 7.3.7.4.2 on-demand mode ?gated clock . . . . . . . . . . . . . . . . . . . . . . . .7-80 7.3.8 flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-85 7.3.9 example circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-87 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola table of contents xiii table of contents (continued) paragraph page number title number section 8 timer/event counter 8.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2 timer/event counter block diagram . . . . . . . . . . . . . . . . . 8-3 8.3 timer count register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4 timer control/status register (tcsr). . . . . . . . . . . . . . . . 8-5 8.4.1 tcsr timer enable (te) bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.2 tcsr timer interrupt enable (tie) bit 1 . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.3 tcsr inverter (inv) bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.4 tcsr timer control (tc0-tc2) bits 3-5 . . . . . . . . . . . . . . . . . . . . . 8-6 8.4.5 tcsr general purpose i/o (gpio) bit 6 . . . . . . . . . . . . . . . . . . . . . 8-6 8.4.6 tcsr timer status (ts) bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.4.7 tcsr direction (dir) bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.4.8 tcsr data input (di) bit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.4.9 tcsr data output (do) bit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.4.10 tcsr reserved bits 11-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5 timer/event counter modes of operation . . . . . . . . . . . . 8-7 8.5.1 timer mode 0 (standard timer mode, internal clock, no timer output) . . . . . . . . 8-8 8.5.2 timer mode 1 (standard timer mode, internal clock, output pulse enabled) . . . . 8-10 8.5.3 timer mode 2 (standard timer mode, internal clock, output toggle enabled) . . . 8-12 8.5.4 timer mode 4 (pulse width measurement mode) . . . . . . . . . . . . . . 8-13 8.5.5 timer mode 5 (period measurement mode). . . . . . . . . . . . . . . . . . . 8-15 8.5.6 timer mode 6 (standard time counter mode, external clock) . . . . 8-17 8.5.7 timer mode 7 (standard timer mode, external clock) . . . . . . . . . . 8-19 8.6 timer/event counter behavior during wait and stop . 8-21 8.7 operating considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.8 software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.8.1 general purpose i/o input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.8.2 general purpose i/o output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.8.3 timer mode 0, input clock, gpio output, and no timer output . . . 8-22 8.8.4 pulse width measurement mode (timer mode 4) . . . . . . . . . . . . . . 8-23 8.8.5 period measurement mode (timer mode 5). . . . . . . . . . . . . . . . . . . 8-24 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xiv table of contents motorola table of contents (continued) paragraph page number title number section 9 pulse width modulators 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2 pulse width modulator internal architecture . . . . . . 9-3 9.2.1 pulse width modulator a (pwma) overview . . . . . . . . . . . . . . . . . . 9-4 9.2.1.1 pwma count registers pwma0, pwma1, and pwma2 . . . . . . .9-4 9.2.1.2 pwma clock and control logic . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6 9.2.2 pulse width modulator b (pwmb) overview . . . . . . . . . . . . . . . . . . 9-6 9.2.2.1 pwmb count registers pwmb0 and pwmb1 . . . . . . . . . . . . . . .9-6 9.2.2.2 pwmb clock and control logic . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7 9.3 pulse width modulator programming model . . . . . . . . . 9-8 9.3.1 pwman count registers ?pwacr0, pwacr1, and pwacr2 . . 9-8 9.3.2 pwman control/status register 0 ?pwacsr0. . . . . . . . . . . . . . . 9-8 9.3.2.1 pwman prescale (wap0-wap2) bits 0-2 . . . . . . . . . . . . . . . . . . .9-10 9.3.2.2 pwman clock source (wack) bit 3 . . . . . . . . . . . . . . . . . . . . . . .9-10 9.3.2.3 pwman data width (waw0-waw2) bits 4-6 . . . . . . . . . . . . . . . .9-10 9.3.2.4 pwman pwacsr0 reserved bits 7-9 . . . . . . . . . . . . . . . . . . . . .9-11 9.3.2.5 pwman status (was0-was2) bits 10-12 . . . . . . . . . . . . . . . . . . .9-11 9.3.2.6 pwman error (war0-war2) bits 13-15 . . . . . . . . . . . . . . . . . . . .9-11 9.3.3 pwma control/status register 1 (pwacsr1). . . . . . . . . . . . . . . . . 9-12 9.3.3.1 pwacsr1 pwman enable (waen) bits 0-2 . . . . . . . . . . . . . . . . .9-12 9.3.3.2 pwacsr1 pwman interrupt enable (wain) bits 3-5 . . . . . . . . . .9-12 9.3.3.3 pwacsr1 pwman carrier select (wacn) bits 6-8 . . . . . . . . . . .9-12 9.3.3.4 pwacsr1 pwman output polarity (waln) bits 9-11 . . . . . . . . .9-13 9.3.3.5 pwacsr1 reserved bits 12-14 . . . . . . . . . . . . . . . . . . . . . . . . . .9-13 9.3.3.6 pwacsr1 pwma error interrupt enable (waei) bit 15 . . . . . . . .9-13 9.3.4 pwmb count registers ?pwbcr0, pwbcr1 . . . . . . . . . . . . . . . 9-13 9.3.5 pwmb control/status register 0 ?pwbcsr0. . . . . . . . . . . . . . . . 9-13 9.3.5.1 pwbcsr0 pwmb prescale (wbp0- wbp2) bits 0-2 . . . . . . . . . .9-13 9.3.5.2 pwbcsr0 pwmb clock source (wbck) bit 3 . . . . . . . . . . . . . . .9-14 9.3.5.3 pwbcsr0 pwmb data width (wbw0-wbw2) bits 4-6 . . . . . . . .9-14 9.3.5.4 pwbcsr0 reserved bits 7-11 . . . . . . . . . . . . . . . . . . . . . . . . . . .9-15 9.3.5.5 pwbcsr0 pwmbn status (wbsn) bits 12-13 . . . . . . . . . . . . . . .9-15 9.3.5.6 pwbcsr0 pwmbn error (wbrn) bit 14-15 . . . . . . . . . . . . . . . . .9-15 9.3.6 pwmb control/status register 1 ?pwbcsr1. . . . . . . . . . . . . . . . 9-16 9.3.6.1 pwbcsr1 pwmbn enable (wben) bits 0-1 . . . . . . . . . . . . . . . . .9-16 9.3.6.2 pwbcsr1 pwmbn interrupt enable (wbin) bits 2-3 . . . . . . . . . .9-16 9.3.6.3 pwbcsr1 reserved bits 4-12 . . . . . . . . . . . . . . . . . . . . . . . . . . .9-16 9.3.6.4 pwbcsr1 pwmb carrier select (wbc) bit 13 . . . . . . . . . . . . . . .9-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola table of contents xv table of contents (continued) paragraph page number title number 9.3.6.5 pwbcsr1 pwmb open drain output (wbo) bit 14 . . . . . . . . . . 9-17 9.3.6.6 pwbcsr1 pwmb error interrupt enable (wbei) bit 15 . . . . . . . . 9-17 9.4 pulse width modulator functional description . . . . . 9-17 9.4.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.2 boundary conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 section 10 watchdog timer 10.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2 watchdog timer architecture . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2.1 watchdog timer count register (wcr) . . . . . . . . . . . . . . . . . . . . . 10-3 10.2.2 watchdog timer control/status register (wcsr) . . . . . . . . . . . . . . 10-4 10.2.2.1 wcsr watchdog timer prescale (wp0-wp2) bits 0-2 . . . . . . . . 10-5 10.2.2.2 wcsr watchdog timer status (ws) bit 3 . . . . . . . . . . . . . . . . . . . 10-5 10.2.2.3 wcsr watchdog timer interrupt enable (wie) bit 4 . . . . . . . . . . 10-5 10.2.2.4 wcsr watchdog timer enable (we) bit 5 . . . . . . . . . . . . . . . . . . 10-6 10.2.2.5 wcsr watchdog timer load (wld) bit 6 . . . . . . . . . . . . . . . . . . 10-6 10.2.2.6 wcsr watchdog timer debug (wdb) bit 7 . . . . . . . . . . . . . . . . . 10-6 10.2.2.7 wcsr reserved bits 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.3 watchdog timer functional description . . . . . . . . . . . . . 10-7 10.4 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . 10-8 appendix a bootstrap program and data rom listings a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.2 bootstrap program listing . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 a.3 arctangent table contents . . . . . . . . . . . . . . . . . . . . . . . . . a-7 a.4 sine table contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xvi table of contents motorola table of contents (continued) paragraph page number title number appendix b programming sheets b.1 peripheral addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . b-4 b.3 exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 b.4 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-6 b.5 central processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-11 b.6 gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-15 b.7 host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-17 b.8 sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-22 b.9 ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-25 b.10 timer/counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-28 b.11 pulse width modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-29 b.12 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-35 appendix c dsp56003 and dsp56005 differences c.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3 c.2 differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3 c.3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3 c.3.1 (2.2.2.1) bus needed (bn ) ? active low output ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . .c-3 c.3.2 (2.2.2.2) bus request (br ) ? active low input ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . .c-4 c.3.3 (2.2.2.3) bus grant (bg ) ? active low output ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . .c-7 c.3.4 (2.2.2.4) bus strobe (bs ) ? active low output ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . .c-7 c.3.5 (2.2.2.5) bus wait (wt ) ?active low input ?dsp56003 only . .c-8 c.3.6 (2.2.10.2) thermal ground (gnd) ?dsp56003 only . . . . . . . . .c-8 c.3.7 (2.2.11.6) reset (reset ) ?input . . . . . . . . . . . . . . . . . . . . . . . . .c-8 c.3.8 (2.2.12.2) ckout polarity control (ckp) input ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c-8 c.3.9 (2.2.12.7) phase and frequency locked (plock) ? output ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c-10 c.4 applications of the extra pins . . . . . . . . . . . . . . . . . . . . . . . c-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola table of contents xvii table of contents (continued) paragraph page number title number c.4.1 bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-10 c.4.2 external memory interface wait states . . . . . . . . . . . . . . . . . . . . . c-10 c.4.3 pll and clock signal applications . . . . . . . . . . . . . . . . . . . . . . . . c-11 c.5 (4.6) bus strobe and wait pins ?dsp56003 only . . . . . . . . c-11 c.6 (4.7) bus arbitration and shared memory ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-12 c.6.1 (4.7.1) bus arbitration using only br and bg with internal control ?dsp56003 only . . . . . . . . . . . . . . . . . . . . c-14 c.6.2 (4.7.2) bus arbitration using bn , br , and bg with external control ?dsp56003 only . . . . . . . . . . . . . . . . . . . c-16 c.6.3 (4.7.3) arbitration using br and bg , and wt and bs with no overhead ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . c-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola list of figures xix list of figures figure page number title number section 1 1-1 dsp56003/005 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1-2a dsp56003/005 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1-2b dsp56003/005 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 section 2 2-1 dsp56003/005 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 section 3 3-1a dsp56003/005 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-1b dsp56003/005 memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-2 omr format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-3 port a bootstrap circuit (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3-4 dsp56003/005 interrupt priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 section 4 4-1 external memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-2 external program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-3 external x and y data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-4 memory segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-5 external memory interface bootstrap rom with x and y ram . . . . . . . . . . 4-8 4-6 external memory interface bus operation with no wait states . . . . . . . . . . 4-9 4-7 external memory interface bus operation with two wait states . . . . . . . . . 4-10 4-8 bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4-9 mixed-speed expanded system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4-10 bus strobe/wait sequence ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . 4-15 4-11 bus request/bus grant sequence ?dsp56003 only . . . . . . . . . . . . . . . . 4-17 4-12 bus arbitration using only br and bg with internal control ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4-13 two dsps with external bus arbitration timing . . . . . . . . . . . . . . . . . . . . . . 4-19 4-14 bus arbitration using bn , br , and bg with external control ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4-15 bus arbitration using br and bg , and wt and bs with no overhead ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4-16 two dsps with external bus arbitration timing ?dsp56003 only . . . . . . 4-22 4-17 signaling using semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 section 5 5-1 port b interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5-2 parallel port b registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5-3 parallel port b pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xx list of figures motorola list of figures (continued) figure page number title number 5-4 port b i/o pin control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5-5 on-chip peripheral memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5-6 instructions to write/read parallel data with port b . . . . . . . . . . . . . . . . . . . 5-8 5-7 i/o port b configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-8 hi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5-9 host interface programming model ?dsp viewpoint . . . . . . . . . . . . . . . . . 5-13 5-10 host flag operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5-11 hsr?cr operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5-12 host processor programming model ?host side . . . . . . . . . . . . . . . . . . . . 5-21 5-13 hi register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5-14 command vector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5-15 host processor transfer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5-16 interrupt vector register read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 5-17 hi interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 5-18 dma transfer logic and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 5-19 hi initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 5-20 hi initialization ?dsp side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39 5-21a hi configuration ?host side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5-21b hi initialization ?host side, polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 5-21c hi initialization ?host side, interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . 5-41 5-21d hi initialization ?host side, dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 5-22 host mode and init bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 5-23 bits used for host-to-dsp transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 5-24 data transfer from host to dsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5-25 receive data from host ?main program . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 5-26 receive data from host interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 5-27 hi exception vector locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 5-28 host command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48 5-29 bootstrap using the hi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49 5-30 transmit/receive byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 5-31 bootstrap code fragment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 5-32 bits used for dsp to host transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52 5-33 data transfer from dsp to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53 5-34 main program ?transmit 24-bit data to host . . . . . . . . . . . . . . . . . . . . . . . 5-54 5-35 transmit to hi routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54 5-36 hi hardware ?dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 5-37 dma transfer and host interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 5-38 host-to-dsp dma procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57 5-39 host bits with treq and rreq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58 5-40 dsp to host dma procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-61 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola list of figures xxi list of figures (continued) figure page number title number 5-41 mc68hc11 to dsp56003/005 host interface . . . . . . . . . . . . . . . . . . . . . . . . 5-62 5-42 mc68000 to dsp56003/005 host interface . . . . . . . . . . . . . . . . . . . . . . . . . 5-63 5-43 multi-dsp network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64 section 6 6-1 port c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6-2 port c gpio control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6-3 port c gpio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6-4 port c i/o pin control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6-5 on-chip peripheral memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6-6 write/read parallel data with port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6-7 i/o port c configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6-8 sci programming model ?control and status registers . . . . . . . . . . . . . . . 6-12 6-9 sci programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6-10 serial formats (sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6-11 16x serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6-12 sci baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6-13 data packing and unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6-14 sci initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6-15 sci general initialization detail ?step 2 (sheet 1 of 2) . . . . . . . . . . . . . . . . 6-32 6-16 hi exception vector locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 6-17 synchronous master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 6-18 synchronous slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 6-19 synchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 6-20 sci synchronous transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 6-21 sci synchronous receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 6-22 asynchronous sci receiver initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 6-23 sci character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 6-24 sci character reception with exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 6-25 asynchronous sci transmitter initialization . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6-26 asynchronous sci character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6-27 transmitting marks and spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 6-28 sci asynchronous transmit/receive example (sheet 1 of 2) . . . . . . . . . . . 6-52 6-29 11-bit multidrop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 6-30 transmitting data and address characters . . . . . . . . . . . . . . . . . . . . . . . . . 6-56 6-31 wired-or mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57 6-32 idle line wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 6-33 address mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 6-34 multidrop transmit receive example (sheet 1 of 4) . . . . . . . . . . . . . . . . . . . 6-62 6-35 sci timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-67 6-36 sci timer example (sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-68 6-37 dsp56003/005 bootstrap example - mode 6 . . . . . . . . . . . . . . . . . . . . . . . . 6-70 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xxii list of figures motorola list of figures (continued) figure page number title number 6-38 bootstrap code fragment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-71 6-39 synchronous mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-72 6-40 multimaster system example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73 6-41 master-slave system example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73 section 7 7-1 port c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7-2 port c gpio control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7-3 port c gpio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7-4 port c i/o pin control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7-5 on-chip peripheral memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7-6 write/read parallel data with port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7-7 i/o port c configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7-8 ssi clock generator functional block diagram . . . . . . . . . . . . . . . . . . . . . . 7-13 7-9 ssi frame sync generator functional block diagram . . . . . . . . . . . . . . . . . 7-14 7-10 ssi programming model ?control and status registers . . . . . . . . . . . . . . 7-18 7-11 ssi programming model (sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7-12 serial control, direction bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 7-13 receive data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 7-14 transmit data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 7-15 ssi initialization block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 7-16 ssi cra initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 7-17 ssi crb initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39 7-18 ssi initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 7-19 hi exception vector locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42 7-20 ssi exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-43 7-21 crb mod bit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-46 7-22 normal mode, external frame sync (8 bit, 1 word in frame) . . . . . . . . . . . 7-47 7-23 network mode, external frame sync (8 bit, 2 words in frame) . . . . . . . . . 7-47 7-24 crb gck bit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-48 7-25 continuous clock timing diagram (8-bit example) . . . . . . . . . . . . . . . . . . . 7-49 7-26 internally generated clock timing (8-bit example) . . . . . . . . . . . . . . . . . . . 7-50 7-27 externally generated gated clock timing (8-bit example) . . . . . . . . . . . . . 7-51 7-28 synchronous communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-52 7-29 crb syn bit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-53 7-30 gated clock ?synchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54 7-31 gated clock ?asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54 7-32 continuous clock ?synchronous operation . . . . . . . . . . . . . . . . . . . . . . . . 7-54 7-33 continuous clock ?asynchronous operation . . . . . . . . . . . . . . . . . . . . . . . 7-54 7-34 crb fsl0 and fsl1 bit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-56 7-35 normal mode initialization for fls1=0 and fsl0=0 . . . . . . . . . . . . . . . . . . . 7-57 7-36 normal mode initialization for fsl1=1 and fsl0=0 . . . . . . . . . . . . . . . . . . . 7-58 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola list of figures xxiii list of figures (continued) figure page number title number 7-37 crb shfd bit operation (sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-60 7-38 normal mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-62 7-39 normal mode transmit example (sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . 7-64 7-40 normal mode receive example (sheet 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . 7-66 7-41 network mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-68 7-42 tdm network software flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-69 7-43 network mode initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-71 7-44 network mode transmit example program (sheet 1 of 2) . . . . . . . . . . . . . . 7-73 7-45 network mode receive example program (sheet 1 of 2) . . . . . . . . . . . . . . 7-75 7-46 on demand example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-78 7-47 on-demand data-driven network mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-79 7-48 clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-80 7-49 spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-81 7-50 on-demand mode example ?hardware configuration . . . . . . . . . . . . . . . 7-82 7-51 on-demand mode transmit example program (sheet 1 of 2) . . . . . . . . . . . 7-82 7-52 on-demand mode receive example program . . . . . . . . . . . . . . . . . . . . . . . 7-84 7-53 output flag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-86 7-54 output flag example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-87 7-55 output flag initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-88 7-56 input flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-89 7-57 ssi cascaded multi-dsp system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-89 7-58 ssi tdm parallel dsp network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-90 7-59 ssi tdm connected parallel processing array . . . . . . . . . . . . . . . . . . . . . . 7-91 7-60 ssi tdm serial/parallel processing array . . . . . . . . . . . . . . . . . . . . . . . . . . 7-92 7-61 ssi parallel processing ?nearest neighbor array . . . . . . . . . . . . . . . . . . . 7-93 7-62 ssi tdm bus dsp network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-94 7-63 ssi tdm master-slave dsp network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-95 section 8 8-1 timer/event counter module block diagram . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8-2 timer/event counter programming model . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8-3 mode 0 ?standard timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8-4 timer/event counter disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8-5 mode 1 ?standard timer mode, internal clock, output pulse enabled (inv=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8-6 mode 1 ?standard timer mode, internal clock, output pulse enabled (inv=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8-7 mode 2 ?standard timer mode, internal clock, output toggle enable . . . 8-12 8-8 mode 4 ?pulse width measurement mode (inv=0) . . . . . . . . . . . . . . . . . . 8-13 8-9 mode 4 ?io gates the internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8-10 mode 4 ?pulse width measurement mode (inv=1) . . . . . . . . . . . . . . . . . . 8-14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xxiv list of figures motorola list of figures (continued) figure page number title number 8-11 mode 5 ?period measurement mode (inv=0) . . . . . . . . . . . . . . . . . . . . . . 8-15 8-12 mode 5 ?period measurement mode (inv=1) . . . . . . . . . . . . . . . . . . . . . . 8-16 8-13 mode 6 ?standard time counter mode, external clock (inv=0) . . . . . . . 8-17 8-14 mode 6 ?standard timer mode, external clock (inv=1) . . . . . . . . . . . . . . 8-18 8-15 mode 7 ?standard timer mode, external clock (inv=0) . . . . . . . . . . . . . . 8-19 8-16 mode 7 ?standard timer mode, external clock (inv=1) . . . . . . . . . . . . . . 8-20 8-17 standard timer mode with simultaneous gpio program . . . . . . . . . . . . . . 8-22 8-18 input pulse width measurement program . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 8-19 input period measurement program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 section 9 9-1 pulse width modulator waveform controls . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9-2 dc motor control example using pulse width modulator a . . . . . . . . . . . . 9-4 9-3 pwma block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9-4 pwmb block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9-5 pwm programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9-6 pwma timing ?external clock, external carrier, positive data . . . . . . . . 9-18 9-7 pwma timing ?external clock, external carrier, error . . . . . . . . . . . . . . . 9-19 9-8 pwma timing ?external clock, external carrier, n=0 . . . . . . . . . . . . . . . 9-20 9-9 pwma timing ?internal clock, internal carrier width=w . . . . . . . . . . . . . . 9-21 9-10 pwma timing ?internal clock, internal carrier, n=$7fff, w=16 . . . . . . . 9-22 9-11 pwma timing ?internal clock, internal carrier, n=$8001, w=16 . . . . . . . 9-23 9-12 pwma timing ?internal clock, internal carrier, n=$8000, w=16 . . . . . . . 9-24 9-13 pwma timing ?internal clock, internal carrier, n=0, w=16 . . . . . . . . . . . 9-25 9-14 pwmb timing ?external clock, external carrier . . . . . . . . . . . . . . . . . . . . 9-26 section 10 10-1 16-bit timer module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-2 watchdog timer module programming model . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-3 watchdog timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10-4 watchdog timer disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 aappendix a a-1 dsp56003/005 bootstrap program listing (sheet 1 of 3) . . . . . . . . . . . . . . a-4 a-2 arc-tangent table contents listing (part 1 of 3) . . . . . . . . . . . . . . . . . . . . . . a-7 a-3 sine table contents (part 1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-10 bappendix b b-1 on-chip peripheral memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b-2 status register (sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-11 b-3 bus control register (bcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-11 b-4 interrupt priority register (ipr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-12 b-5 operating mode register (omr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-13 b-6 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-14 b-7 port b control register (pbc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola list of figures xxv list of figures (continued) figure page number title number b-8 port b data direction register (pbddr) . . . . . . . . . . . . . . . . . . . . . . . . . . . b-15 b-9 port b data register (pbd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-15 b-10 port c control register (pcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-16 b-11 port c data direction register (pcddr) . . . . . . . . . . . . . . . . . . . . . . . . . . . b-16 b-12 port c data register (pcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-16 b-13 port b control register (pbc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-17 b-14 host control register (hcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-17 b-15 host transmit data register (htx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-18 b-16 host receive data register (hrx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-18 b-17 host status register (hsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-18 b-18 command vector register (cvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-19 b-19 interrupt control register (icr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-19 b-20 interrupt status register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-20 b-21 interrupt vector register (ivr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-20 b-22 host receive byte registers (rxh/rxm/rxl) . . . . . . . . . . . . . . . . . . . . . . b-21 b-23 host transmit byte registers (txh/txm/txl) . . . . . . . . . . . . . . . . . . . . . . . b-21 b-24 port c control register (pcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-22 b-25 sci control register (scr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-22 b-26 sci clock control register (sccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-23 b-27 sci status register (ssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-23 b-28 sci receive data registers (srx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-24 b-29 sci transmit data registers (stx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-24 b-30 ssi control register (pcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-25 b-31 ssi control register a (cra) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-25 b-32 ssi control register b (crb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-26 b-33 ssi status register (ssisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-27 b-34 timer control/status register (tcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-28 b-35 timer count register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-28 b-36 pwma0 count register (pwacr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-29 b-37 pwma1 count register (pwacr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-29 b-38 pwma2 count register (pwacr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-29 b-39 pwma control/status register 0 (pwacsr0) . . . . . . . . . . . . . . . . . . . . . . . b-30 b-40 pwma control/status register 1 (pwacsr1) . . . . . . . . . . . . . . . . . . . . . . . b-31 b-41 pwmb0 count register 0 (pwbcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-32 b-42 pwmb1 count register 1 (pwbcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-32 b-43 pwmb control/status register 0 (pwbcsr0) . . . . . . . . . . . . . . . . . . . . . . . b-33 b-44 pwmb control and status register 1 (pwbcsr1) . . . . . . . . . . . . . . . . . . . b-34 b-45 watchdog timer control/status register (wcsr) . . . . . . . . . . . . . . . . . . . . b-35 b-46 watchdog timer count register (wcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-36 cappendix c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xxvi list of figures motorola list of figures (continued) figure page number title number c-1 (1-1) dsp56003/005 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-4 c-2 (2-1) dsp56003/005 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-6 c-3 (4-1) port a signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-9 c-4 (4-10) bus strobe/wait sequence ?dsp56003 only . . . . . . . . . . . . . . . . . c-12 c-5 (4-11) bus request/bus grant sequence ?dsp56003 only . . . . . . . . . . . c-14 c-6 (4-12) bus arbitration using only br and bg with internal control ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-15 c-7 (4-13) two dsps with external bus arbitration timing . . . . . . . . . . . . . . . . . c-16 c-8 (4-14) bus arbitration using bn , br , and bg with external control ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-17 c-9 (4-15) bus arbitration using br and bg , and wt and bs with no overhead ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-18 c-10 (4-16) two dsps with external bus arbitration timing ? dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables table page number title number motorola list of tables xxvii section 1section 1 1-1 documentation required for a complete description. . . . . . . . . . . . . . . . . . . . . 1-3 1-2 related motorola documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-3 high true / low true signal conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 section 2section 2 2-1 functional pin groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-2 program and data memory select encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-3 power and ground pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 section 3section 3 3-1 memory mode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-2 dsp56003/005 operating mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3-3 organization of eprom data contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-4 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-5 exception priorities within an ipl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 section 4section 4 4-1 program and data memory select encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4-2 wait state control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4-3 br and bg during wait ?dsp56003 only. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 section 5section 5 5-1 host registers after reset ?dsp cpu side . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5-2 hreq pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5-3 host mode bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5-4 hreq pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5-5 host registers after reset (host side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5-6 port b pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 section 6section 6 6-1 word formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6-2 sci registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 6-3a asynchronous sci bit rates for a 40-mhz crystal. . . . . . . . . . . . . . . . . . . . . . . 6-34 6-3b frequencies for exact asynchronous sci bit rates. . . . . . . . . . . . . . . . . . . . . . 6-34 6-4a synchronous sci bit rates for a 32.768-mhz crystal . . . . . . . . . . . . . . . . . . . . 6-35 6-4b frequencies for exact synchronous sci bit rates . . . . . . . . . . . . . . . . . . . . . . 6-35 section 7section 7 7-1 definition of sc0, sc1, sc2, and sck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7-2 ssi clock sources, inputs, and outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7-3 ssi operation: flag 0 and rx clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7-4 ssi operation: flag 1 and rx frame sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7-5 ssi operation: tx and rx frame sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . xxviii list of tables motorola list of tables (continued) table page number title number 7-6 number of bits/word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7-7 frame sync length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 7-8 mode and pin definition table ?gated clock . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 7-9 mode and pin definition table ?continuous clock . . . . . . . . . . . . . . . . . . . . . 7-35 7-10 ssi registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 7-11a ssi bit rates for a 40-mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 7-11b ssi bit rates for a 39.936-mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 7-12 crystal frequencies required for codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 7-13 ssi operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-44 section 8section 8 8-1 timer/event counter control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 section 9section 9 9-1 prescale factor bits wap0-wap2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9-2 data width bits waw0-waw2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9-3 prescale factor bits wbp0-wbp2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9-4 data width bits wbw2-wbw0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 section 10section 10 10-1 prescale factor bits wp0-wp2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 appendix a a-1 appendix b b-1 b-1 interrupt starting addresses and sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 b-2 exception priorities within an ipl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 b-3 instruction set summary ?sheet 1 of 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-6 c-4 c-5 (2-1) functional pin groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-5 c-6 (2-3) power and ground pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-7 c-7 (4-2) wait state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-11 c-8 (4-3) br and bg during wait ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . c-14 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 1 - 1 section 1 introduction to the dsp56003/005 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 1 - 2 introduction to the dsp56003/005 motorola paragraph number page number section 1.1 manual introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2 product use. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.3 dsp56003/005 architectural overview . . . . . . . . . . . . . . . . . 1-9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . manual introduction motorola introduction to the dsp56003/005 1 - 3 1.1 manual introduction this manual describes the dsp56003 and the dsp56005 24-bit digital signal processors, their memory, operating modes, and peripheral modules. all of the documentation listed in table 1-1 is required for a complete description of the dsp56003/005, and is necessary to properly design with the part. 1.1.1 related literature additional supporting literature discussing theory, algorithms, systems, and applica- tions of dsp or the dsp56003/005 is listed in table 1-2. documentation is available from a local motorola distributor or semiconductor sales office, or through these motorola lit- erature distribution centers: 1. usa: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. 2. europe: motorola ltd.; european literature center; 88 tanners drive, blakelands, milton keynes, mk14 5bp, great britain. 3. japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. 4. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbor center, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. table 1-1 documentation required for a complete description document name description order number dsp56000 family manual detailed description of the 56000-family architecture and the 24-bit core proces- sor and instruction set dsp56kfamum/ad dsp56003/005 user's manual detailed description of memory, peripherals, and interfaces dsp56003um/ad dsp56003/005 technical data sheet pin and package descrip- tions, and electrical and timing specifications dsp56005/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . manual introduction 1 - 4 introduction to the dsp56003/005 motorola table 1-2 related motorola documentation document name description order number motorola? 16-, 24-, and 32-bit digital signal pro- cessing families overview of all of the dsp product families br1105/d dsp56005 product brief product overview, block diagram, features dsp56005p/d dsp56000/001 ads bro- chure overview of the chip? application development system hardware br517/d dsp56000/001 c cross compiler product summary br541/d dsp56000clasx design-in software pack- age product summary. simulator, libraries, assembler, linker br526/d digital sine-wave syn- thesis application report. uses the dsp56001 look-up table apr1/d digital stereo 10-band graphic equalizer application report. includes code and circuitry; features the dsp56001 apr2/d fractional and integer arithmetic application report. includes code apr3/d implementation of fast fourier transforms application report. comprehen- sive fft algorithms and code for dsp56001, dsp56156, and dsp96002 apr4/d implementation of pid controllers application report. pwm using the sci timer and three phase output using modulo addressing apr5/d convolutional encoding and viterbi decoding with a v.32 modem trellis example application report. theory and code; features the dsp56001 apr6/d implementing iir/fir fil- ters application report. comprehen- sive example using the dsp56001 apr7/d full-duplex 32-kbit/s ccitt adpcm speech coding application report. features the dsp56001 apr9/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . manual introduction motorola introduction to the dsp56003/005 1 - 5 dsp56001 interface techniques and exam- ples application report. interfaces for pseudo static ram, dynamic ram, isa bus, host apr11/d twin codec expansion board for the dsp56000 ads application report. circuit, code, fir filter design for two voice band codecs connecting to the ssi apr12/d conference bridging in the digital telecommuni- cations environment application report. theory and code; features the dsp56001/002 apr14/d implementation of adap- tive controllers application report. adaptive con- trol using reference models; gener- alized predictive control; includes code apr15/d low cost controller for dsp56001 application report. circuit and code to connect two dsp56001s to an mc68008 apr402/d g.722 audio processing application report. theory and code using sb-adpcm apr404/d minimal logic dram interface application report. 1m x 4 80 ns dram, 1 pal, code apr405/d logarithmic/linear con- version routines application report. m-law and a- law companding routines for pcm mono-circuits ane408/d dr. bub bulletin board flyer. motorola's electronic bulle- tin board where free dsp software is available br297/d third party compendium brochures from companies selling hardware and software that sup- ports motorola dsps dsp3rdptypak/d university support pro- gram flyer. motorola's program support- ing universities in dsp research and education br382/d real time signal pro- cessing applications with motorola's dsp56000 family textbook by mohamed el- sharkawy; 398+ pages prentice-hall, 1990; isbn 0-13-767138-5 table 1-2 related motorola documentation document name description order number (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . manual introduction 1 - 6 introduction to the dsp56003/005 motorola 1.1.2 training both self-paced audio courses and instructor led class room courses are available for the motorola digital signal processors. a technical training catalog (order number br348/d) is available which describes these courses and gives the current training schedule and prices. information about these courses and registration is available by calling (602) 897- 3665. to register for toronto and ottawa classes, call (416) 497-8181. 1.1.3 technical assistance information and assistance for dsp applications is available through your local motorola field office. see your local telephone directory for telephone numbers. 1.1.4 manual conventions the following conventions are used in this manual: this manual describes both the dsp56003 and the dsp56005. the chip is identical in both of these dsps. however, the dsp56003 is in a larger package with more pins which provide more functions than the dsp56005. vertical bars in the margin of this manual have been used to flag portions of the text that describe these signals that apply only to the dsp56003. additionally, appendix c details in one place all of the differences between the two parts. overbars are used to indicate a signal that is active when pulled to ground (see table 1-3) e.g. the reset pin, reset , is active when pulled to ground. therefore, references to the reset pin will always have an overbar. the word ?ssert?(see table 1-3) means that a high true (active high) signal is pulled high to v cc or that a low true (active low) signal is pulled low to ground. the word ?eassert?(see table 1-3) means that a high true signal is pulled low to ground or that a low true signal is pulled high to v cc . the word ?eset?is used in three different contexts in this manual. there is a reset pin which is always written as ?eset ? there is a reset instruction which is always written as ?eset? and the word reset, used to refer to the reset function, is written in lower case with a leading capital letter as grammar dictates. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . manual introduction motorola introduction to the dsp56003/005 1 - 7 1.1.5 manual organization this manual includes the following sections: section 1 introduction introduces the manual and gives references to related literature provides a brief description of the blocks in the chip block diagram. detailed information on these blocks can be found in either the dsp56000 family manual or in this manual. section 2 pin descriptions presents the dsp56003/005 pin descriptions note that the dsp56003 is a version of the dsp56005 with extra functions. the additional signals on the dsp56003 are bus arbitration signals, a pll lock signal, and a pll clock output polarity control signal. section 3 memory, operating modes, and interrupts presents the details of the dsp56003/005 memory maps describes the interrupt vector locations describes operation of the interrupt priority register explains the various operating modes that affect the processor? program and data memories table 1-3 high true / low true signal conventions signal/symbol logic state signal state voltage pin true asserted ground pin false deasserted v cc pin true asserted v cc pin false deasserted ground notes: 1. pin is a generic term for any pin on the chip. 2 ground is an acceptable low voltage level. see the ap- propriate data sheet for the range of acceptable low volt- age levels (typically a ttl logic low). 3. v cc is an acceptable high voltage level. see the appro- priate data sheet for the range of acceptable high volt- age levels (typically a ttl logic high). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . manual introduction 1 - 8 introduction to the dsp56003/005 motorola section 4 external memory interface describes the external memory port, its registers, and its controls section 5 host interface describes operation, registers, and control of the parallel host interface (hi) and port b general purpose i/o section 6 serial communications interface describes the port c parallel i/o, the synchronous communication interface, its registers, and its controls section 7 synchronous serial interface describes the port c parallel i/o, the synchronous serial interface, its registers, and its controls section 8 timer and event counter describes the timer/event counter, its registers, and controls section 9 pulse width modulators describes the five pulse width modulators available on the dsp56003/005, its registers, and controls section 10 watchdog timer describes a timer that can interrupt the dsp56003/005 after a specified number of clocks, its registers, and controls appendix a bootstrap code and data rom listings provides the code used to bootstrap the dsp56003/005 and the listings for the sine table and arctangent table available in on- chip rom appendix b programming sheets provide a fast reference section for the instructions and registers used by the dsp56003/005. these sheets are intended to be copied and used while programming the registers. appendix c differences between the dsp56003 and dsp56005 provides a description of the specific differences between the two parts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . product use motorola introduction to the dsp56003/005 1 - 9 user? comments allows the reader to notify motorola of any errors or discrepancies discovered in this manual 1.2 product use the dsp56003/005 is a general purpose digital signal processor designed for control and embedded processor applications such as a disk drive controller. it is based on the dsp56002 in that is has the same core processor and peripherals (host interface, sci, ssi, and timer/event counter) but has two new peripherals and extra memory. a timer/event counter, pulse width modulators, and a watchdog timer provide the tools needed to design sophisticated yet cost effective control applications using the dsp56003/005. the timer/event counter provides a versatile tool for both monitoring signals and generating them. the five pulse width modulators provide a convenient means to generate signals and control motors. critical applications require a foolproof method of insuring proper dsp operation. the watchdog timer is a tool to detect some software and hardware failures and provide a failure recovery path by resetting the sys- tem or running a corrective program. the general purpose i/o pins provide up to 25 additional input or output signals that are individually controllable. while the dsp56003/005 has the power and ease of programming required for stand alone, embedded applications, the three communication ports (host interface, sci, and ssi) allow this dsp to be simply connected to almost any other electronic device for at- tached processor or distributed processing applications with little or no additional logic. 1.3 dsp56003/005 architectural overview the dsp56003 and dsp56005 are expanded versions of the dsp56002 and are members of the 24-bit 56000 family. they are composed of the 24-bit 56000 dsp core, memory, and unique set of peripheral modules. the 24-bit 56000 dsp core is composed of a data alu, an address generation unit, a program controller, an on-chip emulator (once port), and a pll-based clock oscillator. the dsp56000-family architecture, on which the dsp56003/005 is built, was designed to maximize throughput in data-intensive digital sig- nal processing applications. the result is a dual-natured, expandable architecture with sophisticated on-chip peripherals and general purpose i/o. it is dual-natured in that there are two independent, expandable data memory spaces, two address arithmetic units, and a data alu which has two accumulators and two shifter/limiters. the duality of the archi- tecture makes it easier to write software for dsp applications. for example, data is naturally partitioned into x and y spaces for graphics and image processing applications, into coeffi- cient and data spaces for filtering and transformations, and into real and imaginary spaces for performing complex arithmetic. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview 1 - 10 introduction to the dsp56003/005 motorola the following memory and peripheral modules are contained in the dsp56003/005: program ram memory module ?long and varied programs can be run from the 4608 words of 24-bit wide fully static program ram that resides on the dsp56003/005 bootstrap rom memory module ?bootstrap code runs at reset time from a 96- word on-chip rom to load the dsp? operating program. this rom does not oc- cupy any of the 64k program memory space and is not accessible by the user. data ram memory modules ?there are two on-chip data rams: 256 words of x ram and 256 words of y ram. these are general purpose memories that can be used for intermediate values, coefficients, stacks, queues, variables, etc. data rom memory modules ?there are two on-chip data roms. a 256 word arctangent table is located from x:100 to x:1ff and a 256 word sine table is lo- cated from y:100 to y:1ff. these tables are useful in calculating trigonometric functions in control operations. host interface module (hi) ?the 8-bit host interface module provides a fast, yet simple parallel interface to connect the dsp56003/005 to a host processor or bus. the host interface is identical to those found in the dsp56000, dsp56001, and dsp56002. serial communications interface peripheral module (sci) ?the sci peripher- al module provides a full-duplex asynchronous serial interface which allows the dsp56003/005 to communicate using standard universal asynchronous re- ceiver and transmitter (uart) protocols at bit rates up to clk/4, i.e. 12.5 mhz for a 50 mhz clock, which are commonly used in modems, terminals, micro- controllers, computer serial ports, etc. the sci is identical to those found in the dsp56000, dsp56001, and dsp56002. synchronous serial interface peripheral module (ssi) ?the ssi peripheral module is an extremely flexible, full-duplex synchronous serial interface. the ssi allows the dsp56003/005 to be used with standard codecs, other dsps, mi- croprocessors, and serial peripherals up to system clock/4; i.e. 12.5 mb/s for a 50 mhz clock. the ssi is identical to those found in the dsp56000, dsp56001, and dsp56002. timer/event counter peripheral module ?the 24-bit timer/event counter pe- ripheral module can be used to interrupt the dsp at set intervals, output a fixed or modulated pulse or square wave, measure pulse widths (rising to falling or falling to rising edges), and measure signal periods (rising to rising or falling to falling edges). the maximum resolution is 1 / 2 the dsp clock frequency, i.e. 40 ns for a 50 mhz clock. the timer/event counter is identical to the one found in the dsp56002. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview motorola introduction to the dsp56003/005 1 - 11 pulse width modulator peripheral module (pwm) ? the pwm module con- tains three 16-bit signed data pulse width modulators and two 16-bit positive fractional data pulse width modulators. these are very flexible devices useful in many applications such as disk drive motor control and head positioning, heater controls, lighting controls, etc. the maximum resolution is 1 / 2 the dsp clock frequency, i.e. 40 ns for a 50 mhz clock. watchdog timer peripheral module ? the 16-bit watchdog timer peripheral mod- ule generates a non-maskable interrupt if it is allowed to time out. this can be used to reset the dsp when either software or hardware stops responding normally. the maximum resolution is 1 / 4 the dsp clock frequency, i.e. 80 ns for a 50 mhz clock. 1.3.1 dsp56003/005 features 24-bit 56000 family central processing unit (cpu) features 25 million instructions per second (mips) at 50 mhz on-chip harvard architecture making parallel accesses to program and two data memories single-cycle 24 x 24 bit parallel multiply-accumulator highly parallel instruction set with unique dsp addressing modes zero overhead nested do loops fast auto-return interrupts operation with 24-bit data/16-bit address parallel interface to off-chip memory stop and wait low-power standby modes fully static logic, operation frequency down to dc low-power cmos design dsp56003/005 features 4608 x 24-bit program ram two 256 x 24-bit data ram two 256 x 24-bit data rom (arctangent and sine tables) full speed memory expansion port with 16-bit address and 24-bit data buses byte-wide host interface with dma support synchronous serial interface port asynchronous serial communication interface port up to 25 general purpose i/o pins 24-bit timer/event counter five pulse width modulators - three use two? complement, fractional data - two use positive fractional data watchdog timer on-chip emulator port (once port) for unobtrusive, full speed debugging f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview 1 - 12 introduction to the dsp56003/005 motorola pll based clocking with wide input frequency range, wide range frequen- cy multiplication (1 to 4096) and power saving clock divider (2 i , i=0,...,15) to reduce clock noise dsp56003 features the dsp56003 has the same features as the dsp56005 with the following additions: - external memory bus arbitration signals - pll lock signal - pll clock output polarity signal 1.3.2 block diagram description the major components of the dsp56003/005 are (see figure 1-1): dsp56000 family dsp engine data alu address generation unit program control unit data buses address buses memory modules program memory including bootstrap code x data memory y data memory peripheral modules external memory expansion port host interface serial communications interface synchronous serial interface timer/event counter pulse width modulators watchdog timer general purpose i/o (most unused peripheral pins can be assigned for general purpose input/output control) these components are depicted in figure 1-1 and described in the following paragraphs. the blocks shown in the expansion area in figure 1-1 are described in detail in this manual. the blocks shown in the 24-bit 56000 core area are described in detail in the dsp56000 family manual. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview motorola introduction to the dsp56003/005 1 - 13 1.3.2.1 data buses data movement on the chip occurs over four bidirectional 24-bit buses ?the x data bus (xdb), the y data bus (ydb), the program data bus (pdb), and the global data bus (gdb). certain instructions concatenate xdb and ydb to form a 48-bit data bus. data transfers between the data alu and the two data memories, x data memory and y data memory, occur over the xdb and ydb, respectively. these transfers can occur simultaneously on the chip, maximizing performance. all other data transfers such as i/o transfers to inter- nal peripherals occur over the gdb. instruction word pre-fetches take place over the pdb in parallel to data transfers. transfers between buses are accomplished through the inter- nal bus switch. external memory transfers occur through the external memory port (port a). a single transfer can occur through port a in a single instruction cycle and can be a program mem- ory, x memory, or y memory transfer. the appropriate address and data bus is directed to port a by the external address bus switch and external data bus switch. figure 1-1 dsp56003/005 block diagram data 24 control 10=56003 5=56005 address 16 data alu 24 x 24 + 56 ? 56-bit mac two 56-bit accumulators pll clock gen. gdb pdb xdb ydb internal data bus switch external data bus switch bus control pab xab yab address generation unit external address bus switch y data memory irq 5 16-bit bus 24-bit bus 24-bit 56000 dsp core program address generator program decode controller interrupt control program control unit watch- dog timer 4 56003= 5 56005= 3 once 24-bit timer/ event counter pulse width modul. (5) sync. serial (ssi) or i/o serial comm. (sci) or i/o host interface (hi) or i/o 14 6 3 15 1 256 24 ram 256 24 rom (arc-tangent) x data memory 256 24 ram 256 24 rom (sine) program memory 4608 24 ram 96 24 rom (boot) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview 1 - 14 introduction to the dsp56003/005 motorola 1.3.2.2 address buses addresses are specified for internal x data memory and y data memory on two unidirec- tional 16-bit buses ?the x address bus (xab) and the y address bus (yab). program memory addresses are specified on the 16-bit program address bus (pab). external memo- ry spaces are addressed via a single 16-bit unidirectional external address bus driven by a three input multiplexer that can select addressing from either the xab, yab, or pab. there is no processing delay ? if only one external memory space is accessed in an instruction. if two or three external memory spaces are accessed in a single instruction, there will be a one or two instruction cycle execution delay ? , respectively. a bus arbitrator controls external accesses. 1.3.2.3 data alu the data alu has been designed to be fast and yet provide the capability to process sig- nals having a wide dynamic range. special circuitry has been provided to facilitate handling data overflows and round-off errors. the data alu performs all of the arithmetic and logical operations on data operands. the data alu consists of four 24-bit input registers, two 48-bit accumulator registers, two 8-bit accumulator extension registers, an accumulator shifter, two data shifter/lim- iters, and a parallel single-cycle non-pipelined multiply-accumulator (mac). data alu operations use fractional two? complement arithmetic. data alu registers may be read or written over the xdb and ydb as 24- or 48-bit operands. the data alu is capable of performing any of the following operations in a single instruction cycle: multiplication, multiply-accumulate with positive or negative accumulation, convergent rounding, multiply-accumulation with positive or negative accumulation and convergent round- ing, addition, subtraction, a divide iteration, a normalization iteration, shifting, and logical operations. data alu source operands may be 24, 48, or in some cases 56 bits, and originate from data alu registers. the data alu destination is always one of the two 56-bit accumulators. the 24-bit data words provide 144 db of dynamic range. this is sufficient for most real world applications including higher level audio applications since the majority of analog to digital (a/d) and digital to analog (d/a) converters are 16 bits or less, and certainly not greater than 24 bits. the 56-bit accumulation internal to the data alu provides 336 db of internal dynamic range assuring no loss of precision due to intermediate processing. ? when using fast external memories f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview motorola introduction to the dsp56003/005 1 - 15 two data shifter/limiters provide special post-processing on data read from the alu ac- cumulator registers a and b and directed to the xdb or ydb. the data shifters are capable of shifting data one bit to the left or to the right as well as passing the data unshifted. each data shifter has a 24-bit output with overflow indication. the data shifters are controlled by scaling mode bits. these shifters permit dynamic scaling of fixed point data without modifying the program code by simply programming the scaling mode bits. this permits block floating-point algorithms to be implemented in a regular fashion. for example, fft routines can use this feature to selectively scale each butterfly pass. saturation arithmetic is accommodated to minimize errors due to overflow. overflow oc- curs when a source operand requires more bits for accurate representation that there are available in the destination. to minimize the error due to overflow, the maximum (or minimum if negative) value, i.e. ?imited? is written to the destination with an error flag. 1.3.2.4 address generation unit the address generation unit performs all address storage and effective address calcula- tions necessary to address data operands in memory. it implements three types of arithmetic to update addresses ?linear, modulo, and reverse carry. this unit operates in parallel with other chip resources to minimize address generation overhead. the address generation unit contains eight address registers (r0-r7, i.e. rn), eight offset registers (n0- n7, i.e. nn), and eight modifier registers (m0-m7, i.e. mn). the rn are 16-bit registers which may contain an address or data. each rn register may provide addresses to the xab, yab, and pab. the nn and mn registers are 16-bit registers which are normally used to control updating the rn registers but can be used for data. address generation unit registers may be read or written via the global data bus as 16-bit operands. the address generation unit has two modulo arithmetic units which can gen- erate two independent 16-bit addresses every instruction cycle for any two of the xab, yab, or pab. the address generation unit can directly address 65,536 (64k) locations on the xab, 65,536 locations on the yab, and 65,536 locations on the pab ?a total capability of 196,608 24-bit words. 1.3.2.5 memories the three independent memory spaces of the dsp56003/005 ?x data, y data, and pro- gram ?are shown in figure 1-1, figure 1-2a, and figure 1-2b. these memory spaces are configured by control bits in the operating mode register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview 1 - 16 introduction to the dsp56003/005 motorola 1.3.2.5.1 program memory on-chip program ram memory, consists of a 4608 location by 24-bit high speed ram which is enabled by bits in the omr. addresses are received from the program control logic (usually the program counter) over the pab. program memory may be written using movem instructions. the interrupt vectors for the on-chip resources are located in the bot- tom 128 locations of program memory. program memory may be expanded to 64k off-chip. program ram has many advantages. it provides a means to develop code efficiently. the programs can be changed dynamically, allowing efficient overlaying of dsp software al- gorithms. in this way the on-chip program ram operates as a fixed cache thereby minimizing contention with accesses to external data memory spaces. $e000 $ffff $0000 $11ff $ffff $0000 mode 0 mc:mb:ma=0:0:0 $ffff $11ff $0000 external program memory internal program ram reset mode 2 mc:mb:ma=0:1:0 external program memory internal program ram reset program memory space interrupt vectors $ffff $007f $0000 the mc:mb:ma bits in the omr determine the program memory and reset starting addresses mode 3 mc:mb:ma=0:1:1 external program memory internal p: ram internal reset internal p: ram external reset no internal p: ram external reset $01ff figure 1-2a dsp56003/005 memory maps $0000 interrupt vector map host commands illegal instruction timer/event counter pwm external (irqc , irqd ) host commands host interface nmi/watchdog timer sci timer sci ssi external (irqa , irqb ) swi trace stack error reset on-chip peripheral register map reserved interrupt priority bus control pll once port sci ssi host interface watchdog timer gp i/o timer pwm $ffff $ffc0 $ffd4 interrupts $007f interrupts $007f reset interrupts $007f $007e $003e $002c $0022 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview motorola introduction to the dsp56003/005 1 - 17 the bootstrap mode, described in appendix a, provides a convenient, low cost method to load the dsp56003/005 program ram with a program after power-on reset. it allows loading the program ram from a single, inexpensive eprom, or serially through the sci, or via the host interface using a host processor. external $ffff $0000 $ffc0 $ffff $0000 $01ff internal x rom arctan table internal x ram external x data memory on-chip peripherals external y data memory internal y rom sine-wave table internal y ram de = 1; yd = 0 $ffc0 $ffff $0000 $00ff internal x ram external x data memory on-chip peripherals external y data memory internal y ram data roms disabled de = 0; yd = 0 x data memory space y data memory space $ffff $0000 the de and yd bits in the omr determine the x and y data memory maps $00ff figure 1-2b dsp56003/005 memory maps external peripherals external peripherals external y data memory peripherals internal x ram on-chip peripherals external y data memory external peripherals de = 1; yd = 1 de = 0; yd = 1 $ffbf $ffff $0000 $ffc0 $01ff internal x rom arctan table internal x ram external x data memory on-chip peripherals $00ff $ffbf $ffc0 $ffff $0000 $00ff note: addresses $ffc0?ffff in x data memory are not available externally external x data memory x data rom enabled external y memory data roms disabled; external y memory data roms enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview 1 - 18 introduction to the dsp56003/005 motorola 1.3.2.5.2 x data memory on-chip x data ram is a 24-bit wide internal memory which occupies the lowest 256 lo- cations in x memory space. the on-chip x data rom can occupy locations 256 through 511 in x data memory space. the x data rom is factory programmed with arctangent ta- bles, useful in control applications. the on-chip peripheral registers occupy the top 64 locations. addresses are received from the xab, and data transfers to the data alu occur on the xdb. x memory may be expanded to the full 64k off-chip. 1.3.2.5.3 y data memory on-chip y data ram is a 24-bit wide internal memory which occupies the lowest 256 lo- cations in y memory space. the on-chip y data rom can occupy locations 256 through 511 in y data memory space. the y data rom is factory programmed with a full four quadrant sine table, useful for ffts, dfts, and wave form generation. it is recommended that any off-chip peripheral registers be mapped into the top 64 y-data memory locations (to take advantage of the movep instruction). addresses are received from the yab, and data transfers to the data alu occur on the ydb. y memory may be expanded to the full 64k off-chip. 1.3.2.5.4 bootstrap rom bootstrap rom is a 96 location by 24-bit factory programmed rom which is used to load the on-chip program ram with the desired code prior to normal operation. the boot- strap rom is not accessible by the user and is disabled in normal operating modes. 1.3.2.6 program control unit the program control unit performs instruction prefetch, instruction decoding, hardware do loop control, and exception processing. it contains six directly addressable registers ?the program counter (pc), loop address (la), loop counter (lc), status register (sr), operating mode register (omr), and stack pointer (sp). the program control unit also contains a 15 level by 32-bit system stack memory. the 16-bit pc can address 65,536 (64k) locations in program memory space. 1.3.2.7 phase-locked loop (pll) the pll allows the processor to operate at a high internal clock frequency using a low frequency clock input. lower frequency clock inputs reduce the overall electromagnetic interference generated by a system, and the ability to oscillate at different frequencies allows greater flexibility while reducing costs by eliminating the need for additional oscillators in a system. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview motorola introduction to the dsp56003/005 1 - 19 the pll performs frequency multiplication to allow the processor to use almost any available external system clock for full speed operation, while also supplying an output clock synchronized to the synthesized internal core clock. it also improves the synchro- nous timing of the processor? external memory port, significantly reducing the timing skew between extal and the internal chip phases. the pll is unusual in that it pro- vides a low power divider on its output, which can reduce or restore the chip operating frequency without losing the pll lock. 1.3.2.8 on-chip emulator (once ) port once port circuitry provides a sophisticated debugging tool that allows simple, inexpen- sive, and speed independent access to the processor? internal registers and peripherals. once port tells the application programmer the exact status of the registers, memory lo- cations, and buses, as well as storing the last five instructions that were executed. once port capabilities are accessible through a set of pins which are standard on most of the members of the dsp56000 processor families. 1.3.2.9 input/output a variety of system configurations are facilitated by the dsp56003/005 i/o structure. these configurations include multiple dsp56003/005 systems with or without a host pro- cessor, global bus systems with bus arbitration (dsp56003 only), and many serial configurations; all with minimal glue logic. each i/o interface has its own control, status, and double buffered data registers which are memory-mapped in the x-data memory space. each interface has several dedicated interrupt vector addresses and control bits to enable/disable interrupts (see figure 1-2a). these interrupt vector addresses minimize the overhead associated with servicing an interrupt by immediately executing the appro- priate service routine, sometimes without a context switch. each interrupt can be programmed to one of three maskable priority levels. specifically, the i/o structure consists of port a, ten peripherals, and up to 25 additional i/o pins as well as four general-purpose interrupt pins, irqa , irqb , irqc , and irqd . the 25 additional pins may be used as gpio pins or allocated to four of the ten on-chip periph- erals under software control. the ten peripherals provided on the dsp56003/005 are: one 8-bit parallel host interface (hi) ?15 gpio pins one serial communications interface (sci) ?three gpio pins one synchronous serial interface (ssi) ?six gpio pins one timer/event counter ?one gpio pins five pulse width modulators (pwms) ?no gpio pins one watchdog timer ?no pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview 1 - 20 introduction to the dsp56003/005 motorola 1.3.2.9.1 external memory interface (port a) the dsp56003/005 expansion port is designed to synchronously interface over a common 24-bit data bus with a wide variety of memory and peripheral devices such as high speed static rams, slower memory devices, and other dsps and mpus in master/slave config- urations. this capability is possible because the expansion bus timing is programmable. the expansion bus timing is controlled by a bus control register (bcr). the bcr controls the timing of the bus interface signals rd and wr , and the data lines. each of four mem- ory spaces x data, y data, program data, and i/o has its own 4-bit bcr which can be programmed for up to 15 wait states (one wait state is equal to a clock period or equiv- alently, one-half of an instruction cycle). in this way, external bus timing can be tailored to match the speed requirements of the different memory spaces. 1.3.2.9.2 general purpose i/o (hi, sci, ssi, timer/event counter) each host interface, sci, ssi, and timer/event counter pin may be programmed as a general purpose i/o pin or as a dedicated on-chip peripheral pin under software control. associated with each general purpose port is a data direction register which programs each pin as an input or output, and a data register for data i/o. these registers are read/write making the use of bit manipulation instructions extremely effective. 1.3.2.9.3 host interface (hi) the host interface is a byte-wide, full duplex parallel port which may be connected directly to the data bus of a host processor. the host processor may be any of a number of industry standard microcomputers or microprocessors, another dsp, or dma hardware. this host interface is identical to the ones on the dsp56001 and dsp56002. the host interface appears to the host processor as a memory mapped peripheral occupy- ing eight bytes in the host processor address space. separate transmit and receive data registers are double-buffered to allow the dsp56003/005 and host processor to transfer data efficiently at high speed. the host processor can use standard data move instructions and addressing modes to communicate with the host interface. handshake flags are pro- vided for polled or interrupt driven data transfers with the host processor or dma hardware may be used to transfer data without host processor intervention. one of the most innovative features of the host interface is the host command fea- ture. the host processor can issue vectored exception requests to the dsp56003/005 and may select any one of 128 dsp56003/005 exception routines to be executed. this flexibility allows the host programmer to execute up to 128 functions preprogrammed in the dsp56003/005. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview motorola introduction to the dsp56003/005 1 - 21 1.3.2.9.4 serial communication interface (sci) the sci provides an asynchronous, full-duplex port for serial communication to other dsps, microprocessors, or peripherals such as modems. this interface uses three dedi- cated pins ?transmit data (txd), receive data (rxd), and sci serial clock (sclk). it supports industry standard asynchronous bit rates up to clk/4, i.e. 12.5 mhz for a 50 mhz clock, and protocols as well as high speed (up to system clock/8; i.e. 6.25 mb/s for a 50 mhz clock) synchronous data transmission. the asynchronous protocols include a multidrop mode for master/slave operation. the serial communication interface con- sists of separate transmit and receive sections having operations which can be asynchronous with respect to each other. a programmable baud rate generator is in- cluded to generate the transmit and/or receive clocks. the baud rate generator can function as a general purpose timer when it is not being used by the sci peripheral. this serial communication interface is identical to the ones on the dsp56001 and dsp56002. 1.3.2.9.5 synchronous serial interface (ssi) the ssi is an extremely flexible, full-duplex serial interface which allows the dsp56003/005 to communicate with a variety of serial devices. these include industry standard codecs, other dsps, microprocessors, and peripherals. each of the following characteristics of the ssi can be independently defined: the number of bits per word (8, 12, 16, or 24), the protocol or mode (normal, network, or on-demand), the clock (up to system clock/4; i.e. 12.5 mb/s for a 50 mhz clock), and the transmit/receive synchroni- zation (word or bit length frame sync). the normal mode is typically used to interface with devices on a regular or periodic ba- sis. in this mode the ssi functions with one data word of i/o per frame. the network mode provides time slots in addition to a bit clock and frame synchroniza- tion pulse. the ssi functions with from 2 to 32 words of i/o per frame in the network mode. this mode is typically used in star or ring time division multiplex networks with other dsp56003/005s and/or codecs. the on-demand mode is a data driven mode. there are no time slots defined. this mode is intended to be used to interface to devices on a non-periodic basis. the clock can be pro- grammed to be continuous or gated. this synchronous serial interface is identical to the ones on the dsp56001 and dsp56002. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 architectural overview 1 - 22 introduction to the dsp56003/005 motorola 1.3.2.9.6 timer/event counter the timer/event counter can use internal or external clocking and has a resolution of clk/2. the counter is 24 bits long. it can also interrupt the processor after a number of events (clocks) specified by a user program, or it can signal an external device after count- ing internal events. the timer/event counter can be used as an external event counter, to measure external pulse width/signal periods, or to generate a timer pulse. this timer/event counter is identical to the one on the dsp56002. 1.3.2.9.7 pulse width modulators (pwm) there are a total of five pulse width modulators on the dsp56003/005. three of these use 9-bit to 16-bit signed two? complement fractional data and two use 9-bit to 16-bit positive fractional data. these modulators can be used to provide fixed pulse width signals. how- ever, there is a separate interrupt vector location for each of the five pwms which makes it easy to reprogram each pwm after every carrier cycle. very short pulse widths and high repetition rates are possible since the maximum pwm clock rate is 1/2 of the dsp core clock rate. 1.3.2.9.8 watchdog timer the watchdog timer uses the dsp core clock to run a count down timer. when that timer times out, the watchdog timer generates a non-maskable interrupt that uses the same vector address as the nmi exception vector. this timer can be used to detect a program that is caught in a loop or any other failure (software or hardware) that prevents the pro- gram from resetting the watchdog timer before it times out. the dsp can then either reset and reinitialize the system or run the appropriate error reporting/recovery program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 2 - 1 section 2 pin descriptions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 2 - 2 pin descriptions motorola paragraph number page number section 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola pin descriptions 2 - 3 2.1 introduction this section introduces pins associated with the dsp56003/005 (see figure 2-1). it divides the pins into their functional groups and explains the role each pin plays in the operation of the chip. it acts as a reference for following chapters which explain the chip? peripher- als in detail. 2.2 pin descriptions the dsp56003 is available in a 176 pin thin quad flat pack (tqfp), see the dsp56003/dsp56005 data sheet . the dsp56005 is available in a 144 tqfp. the pins are or- ganized into the functional groups indicated in table 2-1. the signals are discussed in the paragraphs that follow. functional group dsp56003 pins dsp56005 pins address bus 16 16 data bus 24 24 bus control 11 6 host interface (hi) 15 15 serial communications interface (sci) 3 3 synchronous serial interface (ssi) 6 6 timer/event counter 1 1 pulse width modulator a (pwma) 10 10 pulse width modulator b (pwmb) 4 4 on-chip emulation (once) port 4 4 power (v cc )1817 ground (gnd) 42 26 interrupt and mode control 6 6 phase-locked loop (pll) and clock 7 5 reserved 9 1 total number of pins 176 144 table 2-1 functional pin groupings f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2 - 4 pin descriptions motorola all unused inputs should have pull-up resistors for two reasons: figure 2-1 dsp56003/005 signals a0-a15 d0-d23 ds ps rd wr x/y br bg gndd v ccd gnda v cca gndc v ccc wt bs gndq v ccq extal xtal reset moda/irqa modb/irqb modc/nmi h0-h7 ha0-ha2 hr/w hen hreq hack gndh v cch rxd txd sclk v ccs gnds sc0-sc2 sck srd std dsck/os1 dsi/os0 dso dr interrupt/ mode control dsp56003/005 host serial synchronous pwap0 - pwap2 pwan0 - pwan2 ckout pulse width pwaclk pwac0 - pwac2 bn ckp v ccck gndck only tio timer/ event irqc irqd clock v ccp gndp pcap phase-locked plock pinit pwb0 , pwb1 pwbc pwbclk v ccw gndw counter oscillator extp modulator a (pwma0-2) pulse width modulator b (pwmb0-1) interface (hi) communication interface (sci) serial interface (ssi) loop (pll) on-chip emulator (once ) port dsp56003 dsp56003 only external bus control external address bus external data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions motorola pin descriptions 2 - 5 1. floating inputs draw excessive power 2. a floating input can cause erroneous operation for example, during reset, all signals are three-stated. without pull-up resistors, the br and wt signals may appear to be active, causing two or more memory chips to try to si- multaneously drive the external bus, which can damage the memory chips. a pull-up resistor in the 50k-ohm range should be sufficient. also, for future enhancements, all reserved, ?o connect?(nc), pins should be left unconnected. 2.2.1 port a address bus, data bus, and basic bus control the port a address and data bus signals control the access to external memory. these sig- nals are three-stated during reset unless noted otherwise, and may require pull-up resistors to minimize power consumption and to prevent erroneous operation. 2.2.1.1 address bus (a0?15) ?three-state, outputs a0-a15 specify the address for external program and data memory accesses. if there is no external bus activity, a0-a15 remain at their previous values. a0-a15 are three-stated during hardware reset. 2.2.1.2 data bus (d0?23) ?three-state, bidirectional input/outputs data for external memory i/o is presented on d0-d23. if there is no external bus activity, d0-d23 are three-stated. d0-d23 are also three-stated during hardware reset. 2.2.1.3 program memory select (ps ) ?three-state, active low output this output is asserted only when external program memory is referenced (see table 2-2). ps timing is the same as the a0-a15 address lines. if the external bus is not used during an instruction cycle, ps is driven high. ps is three-stated during hardware reset. 2.2.1.4 data memory select (ds ) ?three-state, active low output this three-state output is asserted only when external data memory is referenced (see table 2-2). if the external bus is not used during an instruction cycle, ds is driven high. ds is three-stated during hardware reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2 - 6 pin descriptions motorola 2.2.1.5 x/y select (x/y ) ?three-state output this three-state output selects which external data memory space (x or y) is referenced by ds (see table 2-2). x/y is three-stated during hardware reset. 2.2.1.6 read enable (rd ) ?three-state, active low output this output is asserted during external memory read cycles. when rd is asserted, the data bus pins d0-d23 become inputs, and an external device is enabled onto the data bus. when rd is deasserted, the external data is latched inside the dsp. when rd is asserted, it qualifies the a0-a15, ps and ds pins. rd can be connected directly to the oe pin of a static ram or rom. rd is three-stated during hardware reset. 2.2.1.7 write enable (wr ) ?three-state, active low output this output is asserted during external memory write cycles. when wr is asserted, the data bus pins d0-d23 become outputs, and the dsp puts data on the bus. when wr is deasserted, the external data is latched inside the external device. when wr is asserted, it qualifies the a0-a15, ps and ds pins. wr can be connected directly to the we pin of a static ram. wr is three-stated during hardware reset. 2.2.1.8 external peripheral (extp ) ?active low output the extp pin is an output asserted whenever the external y memory i/o space (y:$ffc0-$ffff) is accessed. this signal simplifies generating peripheral enable sig- nals. no additional circuitry is needed if only one external peripheral is used. for most applications, no more than one decode chip is needed and, as a result, decode delays are minimized. using the y memory i/o space allows the movep instruction to be used to send and to receive data. using the movep instruction may allow the entire i/o routine to fit in a fast interrupt. extp is three-stated during hardware reset. ps ds x/y external memory reference 1 1 1 no activity 1 0 1 x data memory on data bus 1 0 0 y data memory on data bus 0 1 1 program memory on data bus (not an exception) 0 1 0 external exception fetch: vector or vector +1 (development mode only) 0 0 x reserved 1 1 0 reserved table 2-2 program and data memory select encoding f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions motorola pin descriptions 2 - 7 2.2.2 enhanced bus control these additional bus control pins are only available on the dsp56003. they provide a means to connect additional bus masters which may be additional dsps, microproces- sors, direct memory access (dma) controllers, etc. through port a to the dsp56003. the bus control signals are three-stated during reset unless noted otherwise and require pull- up resistors to prevent erroneous operation. 2.2.2.1 bus needed (bn ) ?active low output ?dsp56003 only the bn output pin is asserted whenever the chip requires the external memory expansion port (port a). during instruction cycles where the external bus is not required, bn is deas- serted. if an external device has requested the bus by asserting the br input and the dsp has granted the bus (by asserting bg ), the dsp will continue processing as long as no ex- ternal accesses are required. if an external access is required and the chip is not the bus master, it will stop processing and remain in wait states until bus ownership is returned. if the bn pin is asserted when the chip is not the bus master, the chip? processing has stopped and the dsp is waiting to acquire bus ownership. an external arbiter may use this pin to help decide when to return bus ownership to the dsp. during hardware reset, bn is deasserted. note: the bn pin cannot be used as an early indication of imminent external bus access because it is valid later than the other bus control signal bs . 2.2.2.2 bus request (br ) ?active low input ?dsp56003 only the bus request br allows another device such as a processor or dma controller to be- come the master of the dsp external data bus d0-d23 and external address bus a0-a15. the dsp asserts bg after the br input is asserted. the dsp bus controller releases control of the external data bus d0-d23, address bus a0-a15 and bus control pins ps , ds , x/y , rd , and wr at the earliest time possible consistent with proper synchronization after the execution of the current instruction has been completed. these pins are then placed in the high impedance state and the bg pin is asserted. the dsp continues executing instruc- tions only if internal program and data memory resources are accessed. if the dsp requests the external bus while br input pin is asserted, the dsp bus controller inserts wait states until the external bus becomes available (br and bg deasserted). when br is deasserted, the dsp will again assume bus mastership. br is an input during reset. notes: 1. interrupts are not serviced when a dsp instruction is waiting for the bus controller. 2. br is prevented from interrupting the execution of a read/modify/write instruction. 3. to prevent erroneous operation, the br pin should be pulled up when it is not in use. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2 - 8 pin descriptions motorola 2.2.2.3 bus grant (bg ) ?active low output ?dsp56003 only this pin is asserted to acknowledge an external bus request. it indicates that the dsp has released control of the external address bus a0-a15, data bus d0-d23 and bus control pins ps , ds , x/y , extp , rd , and wr . the bg output is asserted in response to a br input. when the bg output is asserted, the external address bus a0-a15, data bus d0-d23 and bus con- trol pins are in the high impedance state. bg assertion may occur in the middle of an instruction which requires more than one external bus cycle for execution. note that bg as- sertion will not occur during indivisible read-modify-write instructions (bset, bclr, bchg). when br is deasserted, the bg output is deasserted and the dsp regains control of the external address bus, data bus, and bus control pins. this output is deasserted during hardware reset. 2.2.2.4 bus strobe (bs ) ?active low output ?dsp56003 only bus strobe is asserted at the start of a bus cycle and deasserted at the end of the bus cycle. this pin can be used as an ?arly bus start?signal by an address latch and as an ?arly bus end?signal by an external bus controller. it may also be used with the bus wait input, wt , to generate wait states, a feature which provides capabilities such as: connecting slower asynchronous devices to the dsp allowing devices with differing timing requirements to reside in the same memory space allowing a bus arbiter to provide a fast multiprocessor bus access providing an alternative to the wait and stop instructions to halt the dsp at a known program location and have a fast restart this output is deasserted during hardware reset. 2.2.2.5 bus wait (wt ) ?active low input ?dsp56003 only this input allows an external device to force the dsp to generate wait states for as long as wt is asserted. if wt is asserted while bs is asserted, wait states will be inserted into the current cycle. see the dsp56003/005 data sheet for timing details. wt is an input during reset. 2.2.3 host interface the following paragraphs discuss the host interface signals, which provide a convenient connection to another processor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions motorola pin descriptions 2 - 9 2.2.3.1 host data bus (h0?7) ? bidirectional this bidirectional data bus is used to transfer data between the host processor and the dsp. this bus is an input unless enabled by a host processor read. it is high impedance when hen is deasserted. h0-h7 may be programmed as port b general purpose parallel i/o pins called pb0-pb7 when the host interface (hi) is not being used. these pins are config- ured as gpio input pins during hardware reset. 2.2.3.2 host address (ha0?a2) input * these inputs provide the address selection for each hi register and must be stable when hen is asserted. ha0-ha2 may be programmed as port b general purpose parallel i/o pins called pb8-pb10 when the hi is not being used. these pins are configured as gpio input pins during hardware reset. 2.2.3.3 host read/write (hr/w ) input * this input selects the direction of data transfer for each host processor access. if hr/w is high and hen is asserted, h0-h7 are outputs, and dsp data is transferred to the host pro- cessor. if hr/w is low and hen is asserted, h0-h7 are inputs and host data is transferred to the dsp when hen is deasserted. when hen is asserted, hr/w must be stable. hr/w may be programmed as a general purpose i/o pin called pb11 when the hi is not being used. this pin is configured as a gpio input pin during hardware reset. 2.2.3.4 host enable (hen ) ? active low input * this input enables a data transfer on the host data bus. when hen is asserted and hr/w is high, h0-h7 becomes an output and dsp data may be latched by the host processor. when hen is asserted and hr/w is low, h0-h7 is an input and host data is latched in- side the dsp when hen is deasserted. normally a chip select signal derived from host address decoding and an enable clock is connected to the host enable. hen may be pro- grammed as a general purpose i/o pin called pb12 when the hi is not being used. this pin is configured as a gpio input pin during hardware reset. 2.2.3.5 host request (hreq ) ? active low output * this open-drain output signal is used by the dsp to request service from the host proces- sor. hreq may be connected to a host processor interrupt request pin, a dma controller transfer request pin, or a control input to external circuitry. hreq is asserted when an enabled request occurs in the hi. hreq is deasserted when the enabled request is cleared or masked, dma hack is asserted, or the dsp is reset. hreq may be programmed as a general purpose i/o pin (not open-drain) called pb13 when the hi is not being used. this pin is configured as a gpio input pin during hardware reset. * note that these pins can be inputs or outputs when programmed as general purpose i/o. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2 - 10 pin descriptions motorola 2.2.3.6 host acknowledge (hack ) ? active low input * this input has two functions: to provide a host acknowledge signal for dma transfers to control handshaking and to provide a host interrupt acknowledge compati- ble with mc68000 family processors if programmed as a host acknowledge signal, hack may be used as a data strobe for hi dma data transfers. if programmed as an mc68000 host interrupt acknowledge, hack enables the hi interrupt vector register (ivr) onto the host data bus h0-h7 if the host request hreq output is asserted. in this case, all other hi control pins are ignored and the hi state is not affected. hack may be programmed as a general purpose i/o pin called pb14 when the hi is not being used. for more details about the programming options for this pin, see section 5.3.4.6 ?host acknowledge (hack). this pin is configured as a gpio input pin during hardware reset. note: hack should always be pulled high when not in use. 2.2.4 serial communication interface (sci) the following signals relate to the sci. they are introduced briefly here and described in more detail in section 6 ? serial communications interface . 2.2.4.1 receive data (rxd) ? input * this input receives byte-oriented data and transfers the data to the sci receive shift reg- ister. input data is sampled on the positive or the negative edge of the receive clock, depending on how the sci control register is programmed. rxd may be programmed as a general-purpose i/o pin called pc0 when it is not being used as an sci pin. this pin is configured as a gpio input pin during hardware reset. 2.2.4.2 transmit data (txd) ? output * this output transmits serial data from the sci transmit shift register. data changes on the negative edge of the transmit clock. this output is stable on the positive or the negative edge of the transmit clock, depending on how the sci control register is programmed. txd may be programmed as a general-purpose i/o pin called pc1 when the sci txd function is not being used. this pin is configured as a gpio input pin during hardware reset. * note that these pins can be inputs or outputs when programmed as general purpose i/o. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions motorola pin descriptions 2 - 11 2.2.4.3 sci serial clock (sclk) ? bidirectional this bidirectional pin provides an input or output clock from which the transmit and/or receive baud rate is derived in the asynchronous mode, and from which data is trans- ferred in the synchronous mode. sclk may be programmed as a general-purpose i/o pin called pc2 when the sci sclk function is not being used. this pin is configured as a gpio input pin during hardware reset. 2.2.5 synchronous serial interface (ssi) the ssi pins sc0, sc1, sc2, sck, srd, and std are introduced briefly here and are described in more detail in section 7 ? synchronous serial interface . 2.2.5.1 serial control 0 (sc0) ? bidirectional this bidirectional pin? function is determined by whether the ssi is in synchronous or asynchronous mode. in synchronous mode, this pin is used for serial flag i/o. in asyn- chronous mode, this pin receives clock i/o. sc0 and sc1 are independent serial i/o flags but may be used together for multiple serial device selection. sc0 may be programmed as a general-purpose i/o pin called pc3 when the ssi sc0 function is not being used. this pin is configured as a gpio input pin during hardware reset. 2.2.5.2 serial control 1 (sc1) ? bidirectional the ssi uses this bidirectional pin to control flag or frame synchronization. this pin? function is determined by whether the ssi is in synchronous or asynchronous mode. in asynchronous mode, this pin is frame sync i/o. for synchronous mode with continuous clock, this pin is serial flag sc1 and operates like the sc0. sc0 and sc1 are independent serial i/o flags but may be used together for multiple serial device selection. sc1 may be programmed as a general-purpose i/o pin called pc4 when the ssi sc1 function is not being used. this pin is configured as a gpio input pin during hardware reset. 2.2.5.3 serial control 2 (sc2) ? bidirectional the ssi uses this bidirectional pin to control frame synchronization only. as with sc0 and sc1, its function is defined by the ssi operating mode. sc2 may be programmed as a gen- eral-purpose i/o pin called pc5 when the ssi sc2 function is not being used. this pin is configured as a gpio input pin during hardware reset. 2.2.5.4 ssi serial clock (sck) ? bidirectional this bidirectional pin provides the serial bit rate clock for the ssi when only one clock is be- ing used. sck may be programmed as a general-purpose i/o pin called pc6 when it is not needed as an ssi pin. this pin is configured as a gpio input pin during hardware reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2 - 12 pin descriptions motorola 2.2.5.5 ssi receive data (srd) ? input * this input pin receives serial data into the ssi receive shift register. srd may be pro- grammed as a general-purpose i/o pin called pc7 when the srd function is not being used. this pin is configured as a gpio input pin during hardware reset. 2.2.5.6 ssi transmit data (std) ? output * this output pin transmits serial data from the ssi transmit shift register. std may be pro- grammed as a general-purpose i/o pin called pc8 when the std function is not being used. this pin is configured as a gpio input pin during hardware reset. 2.2.6 timer/event counter pin the following pin is dedicated to the timer/event counter operation. 2.2.6.1 timer/event counter input/output (tio) ? bidirectional the tio pin provides an interface to the timer/event counter module. when the module functions as an external event counter or is used to measure an external pulse width/sig- nal period, the tio is used as an input. when the module functions as a timer, the tio is an output and the signal on the tio pin is the timer pulse. when not used by the timer module, the tio can act as a general purpose i/o pin. reset disables the tio pin and causes it to be three-stated. 2.2.7 pulse width modulator a (pwma) pulse width modulator a is a set of three 16-bit signed two? complement fractional data pulse width modulators and has 10 dedicated external pins. these pulse width modula- tors are independent of the pwmb modulators. 2.2.7.1 pulse width modulator a positive (pwap0 - pwap2) ?output these three pins are the positive outputs for the three pwma modulators (pwma0, pwma1, and pwma2). when a positive two? complement number is loaded in one of the three pwma count registers, an output signal will be generated on the respective pin (e.g., loading pwacr0 with a positive two? complement number will generate an out- put on pwap0). * note that these pins can be inputs or outputs when programmed as general purpose i/o. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions motorola pin descriptions 2 - 13 when a negative two? complement number is loaded in a pwma count register, pwap0-pwap2 will be at its inactive logic level (as defined by the polarity bits in the pwma control/status register 1). these pins are driven at their inactive logic level (as defined by the polarity bits in the control/status register 1) when the individual pwm modulator (pwma0, pwma1, or pwma2) is not enabled. during hardware reset, these pins are driven to a high logic level. 2.2.7.2 pulse width modulator a negative (pwan0 - pwan2) ?output these three pins are the negative outputs for the three pwma modulators (pwma0, pwma1, and pwma2). when a negative two? complement number is loaded in one of the three pwma count registers, an output signal will be generated on the respective pin (e.g. loading pwacr0 with a negative two? complement number will generate an out- put on pwan0). when a positive two? complement number is loaded in a pwma count register, the n-output (pwan0-pwan2) of this pwma block will be at its inactive logic level (as defined by the polarity bits in the pwma control/status register 1). these pins are driven at their inactive logic level (as defined by the polarity bits in the control/status register 1) when the individual pwm modulator (pwma0, pwma1, or pwma2) is not enabled. during hardware reset, these pins are driven to a high logic level. 2.2.7.3 pulse width modulator a carrier (pwac0 - pwac2) ?input these three pins are inputs that provide the external carrier signals for the three pwmas (pwma0, pwma1 and pwma2). when the carrier source for the respective pwma block is programmed to be external, the modulator starts operation at each rising edge of its carrier signal. while a pwma block is either disabled, or is enabled and programmed to operate with the internal carrier, its respective internal input buffer is disconnected from the pin and no external pull-up is necessary. 2.2.7.4 pulse width modulator a clock (pwaclk) ?input this input increments the prescaler which connects to the three pwma blocks and incre- ments the counter in each these blocks. if all of the pwma blocks are either disabled, or are programmed to use the internal clock, the internal input buffer is disconnected from the pin and no external pull-up is necessary. 2.2.8 pulse width modulator b (pwmb) pulse width modulator b is a pair 16-bit positive fractional data pulse width modulators and has four dedicated external pins. these two pulse width modulators are independent of the pwma modulators. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2 - 14 pin descriptions motorola 2.2.8.1 pulse width modulator b carrier (pwbc) ?input this pin is an input that provides the external carrier signals for the two pwmb blocks (pwmb0 and pwmb1). when the carrier source for these blocks is programmed to be external, these blocks start operation at each rising edge of this signal. while a pwmb block is either disabled, or is enabled and programmed to operate with the internal car- rier, its respective internal input buffer is disconnected from the pin and no external pull-up is necessary. 2.2.8.2 pulse width modulator b output (pwb0 -pwb1 ) ?active low output these two pins are the outputs for pulse width modulators pwmb0 and pwmb1. these pins are either open drain or driven at ttl levels depending on the programming of pwbcsr1 bit 14 (wbr0). these pins are also in the high-impedance state or in a high log- ic state (depending on the value of the bit wbo in pwbcsr1) when pwmb0 and pwmb1 are disabled. during hardware reset, these pins are in the high-impedance state. 2.2.8.3 pulse width modulator b clock (pwbclk) ?input this input increments the prescaler which increments the counter connected to the two pwmb blocks. while both pwmb blocks are disabled, the internal input buffer is discon- nected from the pin and no external pull-up is necessary. while the pwmb blocks are programmed to use the internal clock, the internal input buffer is disconnected from the pin and no external pull-up is necessary. 2.2.9 on-chip emulation (once ) port the following paragraphs describe the pins associated with the once port controller and its serial interface. 2.2.9.1 debug serial input/chip status 0 (dsi/os0) ? bidirectional the dsi/os0 pin, when an input, is the pin through which serial data or commands are provided to the once port controller. the data received on the dsi pin will be recognized only when the dsp has entered the debug mode of operation. data must have valid ttl logic levels before the serial clock falling edge. data is al ways shifted into the once serial port most significant bit (msb) first. when the dsp is not in the debug mode, the dsi/os0 pin provides information about the chip status if it is an output and used in conjunction with the os1 pin. when switching from output to input, the pin is three-stated. during hard- ware reset, this pin is defined as an output and it is driven low. note: to avoid possible glitches, an external pull-down resistor should be attached to this pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions motorola pin descriptions 2 - 15 2.2.9.2 debug serial clock/chip status 1 (dsck/os1) ? bidirectional the dsck/os1 pin, when an input, is the pin through which the serial clock is supplied to the once port. the serial clock provides pulses required to shift data into and out of the once serial port. data is clocked into the once port on the falling edge and is clocked out of the once serial port on the rising edge. if the dsck/os1 pin is an output and used in conjunction with the os0 pin, it provides information about the chip status when the dsp is not in the debug mode. the debug serial clock frequency must be no greater than 1 / 8 of the processor clock frequency. the pin is three-stated when it is changing from in- put to output. during hardware reset, this pin is defined as an output and is driven low. note: to avoid possible glitches, an external pull-down resistor should be attached to this pin. 2.2.9.3 debug serial output (dso) ? output the debug serial output provides the data contained in one of the once port controller registers as specified by the last command received from the command controller. the most significant bit (msb) of the data word is always shifted out of the once serial port first. data is clocked out of the once port serial port on the rising edge of dsck. the dso pin also provides acknowledge pulses to the external command controller. when the chip enters the debug mode, the dso pin will be pulsed low to indicate (ac- knowledge) that the once port is waiting for commands. after receiving a read command, the dso pin will be pulsed low to indicate that the requested data is available and the once port serial port is ready to receive clock pulses in order to deliver the data. after receiving a write command, the dso pin will be pulsed low to indicate that the once serial port is ready to receive the data to be written; after the data is written, anoth- er acknowledge pulse will be provided. during hardware reset and when idle, the dso pin is held high. 2.2.9.4 debug request (dr ) ? active low input the debug request input provides a means of entering the debug mode of operation. this pin, when asserted, will cause the dsp to finish the current instruction being executed, to save the instruction pipeline information, to enter the debug mode, and to wait for commands to be entered from the debug serial input line. while the dsp is in the debug mode, the user can reset the once port controller by asserting dr , waiting for an acknowledge from dso, and then deasserting dr . it may be necessary to reset the once port controller in cases where synchronization between the once port controller and external circuitry is lost. asserting dr when the dsp is in the wait or the stop state, and keeping it asserted until an acknowledge pulse in the dsp is produced, sends the dsp into the debug mode. after receiving the acknowledge, dr must be deasserted before sending f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2 - 16 pin descriptions motorola the first once port command. for more information, see section 10.6 ? methods of entering the debug mode in the dsp56000 family manual . 2.2.10 power and ground the power and ground pins are presented in the following paragraphs. there are ten sets of power and ground pins (see table 2-3). in accordance with good engineering practice, v cc should be bypassed to ground (as needed) by a 0.1 m f capacitor located as close as possible to the chip package. the two circuits where this bypassing is most important are the pll and the core processor internal logic circuits. refer to the pin assignments and lay- out practices section in the dsp56003/005 data sheet for additional information. table 2-3 power and ground pins function pin names dsp56003 dsp56005 v cc gnd v cc gnd v cc gnd address bus v cca gnda 3 5 3 5 data bus v ccd gndd 3 6 3 6 bus control v ccc gndc 1 1 1 1 host interface (hi) v cch gndh 2 4 2 4 port c (serial communications interface, synchronous serial interface) v ccs gnds 1 2 1 2 pulse width modulator (pwm) v ccw gndw 1 2 1 2 internal logic v ccq gndq 5 4 4 4 phase-locked loop (pll) v ccp gndp 1 1 1 1 clock v ccck gndck 1 1 1 1 thermal gnd 0 16 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions motorola pin descriptions 2 - 17 2.2.10.1 power these pins provide power to the circuits listed below. the voltage should be well regulated and the pin should be provided with an extremely low impedance path to the power rail. address bus output buffer power (v cca ) data bus output buffer power (v ccd ) bus control power (v ccc ) host interface power (v cch ) serial power (v ccs ) pwm power (v ccw ) internal logic power (v ccq ) ?core processor internal logic circuits pll circuit power (v ccp ) this pin supplies a quiet power source to the phase-locked loop (pll) to pro- vide greater frequency stability. the voltage should be well regulated and the pin should be provided with an extremely low impedance path to the power rail. v ccp should be bypassed to gndp by a 0.1 m f capacitor located as close as possible to the chip package. clock power (v ccck ) ?ckout circuitry 2.2.10.2 ground these pins provide grounds for the circuits listed below. the pins should be provided with an extremely low impedance path to ground. address bus output buffer ground (gnda) data bus output buffer ground (gndd) bus control ground (gndc) host interface ground (gndh) serial ground (gnds) ?sci, ssi, and their gpio circuits pwm ground (gndw) internal logic ground (gndq) ?core processor internal logic circuits pll circuit ground (gndp) this pin supplies a quiet ground source to the pll to provide greater frequency stability. the pin should be provided with an extremely low impedance path to ground. v ccp should be bypassed to gndp by a 0.1 m f capacitor located as close as possible to the chip package. clock ground (gndck) ?ckout circuitry thermal ground (gnd) ?dsp56003 only these pins provide a thermal enhancement (i.e. a heat sink) to the chip. the pins should be directly connected to the ground plane layer to help dissipate heat from the chip. this thermal connection is not necessary for operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2 - 18 pin descriptions motorola however, it will help keep the chip within the thermal specifications when thermal specification limits are otherwise being approached. 2.2.11 interrupt and mode control the interrupt and mode control pins select the chip? operating mode as it comes out of hardware reset and receive interrupt requests from external sources after reset. 2.2.11.1 mode select a/external interrupt request a (moda/irqa ) ? input this input pin has three functions: to work with the modb and modc pins to select the chip? initial operating mode to allow an external device to request a dsp interrupt after internal synchronization to turn on the internal clock generator when the dsp in the stop processing state, causing the chip to resume processing moda is read and internally latched in the dsp when the processor exits the reset state. moda, modb, and modc select the initial chip operating mode. several clock cycles after leaving the reset state, the moda pin changes to the external interrupt request irqa . the chip operating mode can be changed by software after reset. the irqa input is a synchronized external interrupt request. it may be programmed to be level sensitive or negative edge triggered. when the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqa will generate multiple interrupts also increases. while the dsp is in the stop processing state, asserting irqa gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. hardware reset causes this input to act as moda. 2.2.11.2 mode select b/external interrupt request b (modb/irqb ) ? input this input pin has two functions: to work with the moda and modc pins to select the chip? initial operating mode to allow an external device to request a dsp interrupt after internal synchronization modb is read and internally latched in the dsp when the processor exits the reset state. moda, modb, and modc select the initial chip operating mode. several clock cycles after leaving the reset state, the modb pin changes to the external interrupt request irqb . the chip operating mode can be changed by software after reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions motorola pin descriptions 2 - 19 the irqb input is a synchronized external interrupt request. it may be programmed to be level sensitive or negative edge triggered. when the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqb will generate multiple interrupts also increases. hardware reset causes this input to act as modb. 2.2.11.3 mode select c/non-maskable interrupt request (modc/nmi ) ? edge triggered input this input pin has two functions: to work with the moda and modb pins to select the chip? initial operating mode to allow an external device to request a dsp interrupt after internal synchronization modc is read and internally latched in the dsp when the processor exits the reset state. moda, modb, and modc select the initial chip operating mode. several clock cycles after leaving the reset state, the modc pin changes to the non-maskable interrupt re- quest, nmi . the chip operating mode can be changed by software after reset. the nmi input is a negative-edge triggered external interrupt request. this is a level 3 inter- rupt that can not be masked out. triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increas- es, the probability that noise on nmi will generate multiple interrupts also increases. hardware reset causes this input to act as modc. 2.2.11.4 external interrupt request c (irqc ) ? edge triggered input this negative edge triggered input allows an external device to request a dsp interrupt after internal synchronization. triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increas- es, the probability that noise on irqc will generate multiple interrupts also increases. 2.2.11.5 external interrupt request d (irqd ) ? edge triggered input this negative edge triggered input allows an external device to request a dsp interrupt after internal synchronization. triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increas- es, the probability that noise on irqd will generate multiple interrupts also increases. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions 2 - 20 pin descriptions motorola 2.2.11.6 reset (reset ) ? input this input is a direct hardware reset of the processor. when reset is asserted, the dsp is ini- tialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the moda, modb, and modc pins. the chip also samples the pinit pin and writes its status into the pen bit of the pll control register. on the dsp56003 only , the dsp samples the ckp pin to determine the polarity of the ckout signal. when the chip comes out of the reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the reset signal. however, the probability that noise on reset will generate multiple resets increases with increasing rise time of the reset signal. 2.2.12 clock, oscillator, and pll pins the following pins are dedicated to the pll, clock, and oscillator operation. 2.2.12.1 output clock (ckout) ? output this output pin provides a 50% (refer to the dsp56003/dsp56005 data sheet for absolute timings) duty cycle output clock synchronized to the internal processor clock when the pll is enabled and locked. when the pll is disabled, the output clock at ckout is de- rived from, and has the same frequency and duty cycle as, extal. note: if the pll is enabled and the multiplication factor is less than or equal to 4, then ckout is synchronized to extal. (for information on the dsp56003/005? pll multiplication factor, see section 3.6 ? pll multiplication factor in the dsp56000 family manual . 2.2.12.2 ckout polarity control (ckp) ? input. ?dsp56003 only this input pin defines the polarity of the ckout clock output. strapping ckp through a resistor to gnd will make the ckout polarity the same as the extal polarity. strap- ping ckp through a resistor to v cc will make the ckout polarity the inverse of the extal polarity. the ckout clock polarity is internally latched at the end of the hard- ware reset, so that any changes of the ckp pin logic state after deassertion of hardware reset will not affect the ckout clock polarity. 2.2.12.3 external clock/crystal (extal) ? input this pin may be used in one of two ways: driven from an external clock interface the internal crystal oscillator input to an external crystal circuit if the pll is enabled, this pin is internally connected to the on-chip pll. the pll can mul- tiply the frequency on the extal pin to generate the internal dsp clock. the pll output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin descriptions motorola pin descriptions 2 - 21 is divided by two to produce a four-phase instruction cycle clock, with the minimum in- struction time being two pll output clock periods. if the pll is disabled, extal is divided by two to produce the four-phase instruction cycle clock. 2.2.12.4 crystal (xtal) ? output this output connects the internal crystal oscillator output to an external crystal. if an ex- ternal clock is used, xtal should not be connected. it may be disabled through software control using the xtld bit in the pll control register. 2.2.12.5 pll filter capacitor (pcap) ? input this input is used to connect a high quality external capacitor needed for the pll filter. the capacitor should be as close as possible to the chip with heavy, short traces connect- ing one terminal of the capacitor to pcap and the other terminal to v ccp . the capacitor value is specified in the dsp56003/005 data sheet . 2.2.12.6 pll initialization (pinit) ? input during the assertion of hardware reset, the value at the pinit input pin is written into the pen bit of the pll control register. when high, the pen bit enables the pll by causing it to derive the internal clocks from the pll voltage controlled oscillator output. when the bit is clear, the pll is disabled and the chip? internal clocks are derived from the clock connected to the extal pin. after hardware reset is deasserted, the pinit pin is ignored. 2.2.12.7 phase and frequency locked (plock) ? output ?dsp56003 only this signal originates from the pll phase detector. the chip asserts plock when the pll is enabled and has locked on the proper phase and frequency of extal. plock is deasserted by the chip if the pll is enabled and has not locked on the proper phase and frequency. the processor is halted when plock is deasserted. plock is asserted if the pll is disabled. this signal is a reliable indicator of the pll lock state only after the chip has exited the hardware reset state. during hardware reset, the plock state is deter- mined by pinit and by the pll lock condition. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 3 - 1 section 3 memory, operating modes, and interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 3 - 2 memory, operating modes, and interrupts motorola paragraph number page number section 3.1 memory introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 dsp56003/005 operating mode register (omr) . . . . . . . . . . 3-6 3.3 dsp56003/005 operating modes . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4 dsp56003/005 interrupt priority register . . . . . . . . . . . . . 3-12 3.5 dsp56003/005 phase-locked loop (pll) configuration . . 3-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory introduction motorola memory, operating modes, and interrupts 3 - 3 3.1 memory introduction the dsp56003/005 memory can be partitioned in several ways to provide high-speed parallel operation and additional off-chip memory expansion. program and data memory are separate, and the data memory is, in turn, divided into two separate memory spaces, x and y. both the program and data memories can be expanded off-chip. there are also two on-chip data read-only memories (roms) that can overlay a portion of the x and y data memories, and a bootstrap rom that can overlay part of the program random-access memory (ram). the data memories are divided into two independent spaces to work with the two address arithmetic logic units (alus) to feed two operands simultaneously to the data alu. the dsp operating modes determine the memory maps for program and data memories and the start-up procedure when the dsp leaves the reset state. this section describes the dsp56003/005 operating mode register (omr), its operating modes and their associated memory maps, and discusses how to set and reset operating modes. this section also includes details of the interrupt vectors and priorities and describes the effect of a hardware reset on the pll multiplication factor. 3.1.1 dsp56003/005 data and program memory the dsp56003/005 has 4608 words of program ram, 96 words of bootstrap rom, 256 words of ram and 256 words of rom for each of the x and y internal data memories. the memory maps are shown in figure 3-1a and figure 3-1b. 3.1.1.1 program memory the dsp56003/005 has 4608 words of program ram and 96 words of factory-pro- grammed bootstrap rom. the bootstrap rom is programmed to perform the bootstrap operation from the memory expansion port (port a), from the host interface, or from the sci. the bootstrap rom pro- vides a convenient, low cost method of loading the program ram with a user program after power-on reset. the bootstrap rom activity is controlled by the ma, mb, and mc bits in the omr (see section 3.2 ?operating mode register (omr), for a complete explanation of the omr and the dsp56003/005? operating modes and memory maps). addresses are received from the program control logic (usually the program counter) over the pab. program memory may be written using the program memory (movem) instructions. the interrupt vectors are located in the bottom 128 locations ($0000-$007f) of program memory. program memory may be expanded to 64k off-chip. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory introduction 3 - 4 memory, operating modes, and interrupts motorola 3.1.1.2 x data memory the on-chip x data ram is a 24-bit-wide, internal static memory occupying the lowest 256 locations (0?55) in x memory space. the on-chip x data rom occupies locations 256?11 in the x data memory space and is controlled by the de bit in the omr. (see the explanation of the de bit in section 3.2.2 ?data rom enable (de) bit 2. also, see figure 3-1a.) the on-chip peripheral registers occupy the top 64 locations of the x data memory ($ffc0?ffff). the 16-bit addresses are received from the x address bus, and 24-bit data transfers to the data alu occur on the x data bus. the x memory may be expanded to 64k words off-chip. $e000 $ffff $0000 $11ff $ffff $0000 mode 0 mc:mb:ma=0:0:0 $ffff $11ff $0000 external program memory internal program- ram reset mode 2 mc:mb:ma=0:1:0 external program memory internal program ram reset program memory space interrupt vectors $ffff $007f $0000 the mc:mb:ma bits in the omr determine the program memory and reset starting addresses mode 3 mc:mb:ma=0:1:1 external program memory internal p: ram internal reset internal p: ram external reset no internal p: ram external reset $01ff figure 3-1a dsp56003/005 memory maps $0000 interrupt vector map host commands illegal instruction timer pwm external (irqc , irqd ) host commands host interface nmi/watchdog timer timer sci ssi external (irqa , irqb ) swi trace stack error reset on-chip peripheral register map reserved interrupt priority bus control pll once port sci ssi host interface watchdog timer gp i/o timer pwm $ffff $ffc0 $ffd4 interrupts $007f interrupts $007f reset interrupts $007f $007e $003e $002c $0022 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory introduction motorola memory, operating modes, and interrupts 3 - 5 3.1.1.3 y data memory the on-chip y data ram is a 24-bit-wide internal static memory occupying the lowest 256 loca- tions (0?55) in the y memory space. the on-chip y data rom occupies locations 256?11 in y data memory space and is controlled by the de and yd bits in the omr. (see the explanations of the de and yd bits in section 3.2.2 ?omr data rom enable (de) bit 2 and section 3.2.3 ?omr internal y memory disable bit (yd) bit 3, respectively. also, see figure 3-1a.) the 16-bit addresses are received from the y address bus, and 24-bit data transfers to the data alu occur on the y data bus. y memory may be expanded to 64k off-chip. note: the off-chip peripheral registers should be mapped into the top 64 locations ($ffc0 $ffff) to take advantage of the move peripheral data (movep) instruction. the extp pin indicates when these memory locations are being accessed and can be used to reduce the address decode logic required to generate chip enable signals. external $ffff $0000 $ffc0 $ffff $0000 $01ff internal x rom arctan table internal x ram external x data memory on-chip peripherals external y data memory internal y rom sine-wave table internal y ram de = 1; yd = 0 $ffc0 $ffff $0000 $00ff internal x ram external x data memory on-chip peripherals external y data memory internal y ram data roms disabled de = 0; yd = 0 x data memory space y data memory space $ffff $0000 the de and yd bits in the omr determine the x and y data memory maps $00ff figure 3-1b dsp56003/005 memory maps external peripherals external peripherals external y data memory peripherals internal x ram on-chip peripherals external y data memory external peripherals de = 1; yd = 1 de = 0; yd = 1 $ffbf $ffff $0000 $ffc0 $01ff internal x rom arctan table internal x ram external x data memory on-chip peripherals $00ff $ffbf $ffc0 $ffff $0000 $00ff note: addresses $ffc0?ffff in x data memory are not available externally external x data memory x data rom enabled external y memory data roms disabled; external y memory data roms enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 operating mode register (omr) 3 - 6 memory, operating modes, and interrupts motorola 3.2 dsp56003/005 operating mode register (omr) operating modes determine the memory maps for program and data memories, and the start-up procedure when the dsp leaves the reset state. the processor samples the mo- da, modb, and modc pins as it leaves the reset state, establishes the initial operating mode, and writes the operating mode information to the operating mode register. when the processor leaves the reset state, the moda and modb pins become general-purpose interrupt pins, irqa and irqb , respectively, and the modc pin becomes the non- maskable interrupt pin nmi . the omr is a 24-bit register (only six bits are defined) that controls the current operat- ing mode of the processor. it is located in the dsp56003/005? program control unit (described in section 5 of the dsp56000 family manual ). the omr bits are only affected by processor reset and by the andi, ori, movec, bset, bclr, and bchg instruc- tions, which directly reference the omr. the omr format for the dsp56003/005 is shown in figure 3-2. 3.2.1 omr chip operating mode (mc, mb, ma) bits 4, 1, and 0 the chip operating mode bits, mc, mb, and ma define the program memory maps and the operating mode of the dsp56003/005 (see table 3-2). on processor reset, mc, mb, and ma are loaded from the external mode select pins, modc, modb, and moda, re- spectively. after the dsp leaves the reset state, mc, mb, and ma can be changed under software control. 3.2.2 omr data rom enable (de) bit 2 the de bit enables the two, on-chip, 256 x 24 data roms located between addresses $0100?01ff in the x and y memory spaces (if the yd bit is set, y data memory accesses are external and do not access the internal data rom memory). when de is cleared, the $0100?01ff address space is part of the external x and y data spaces, and the on-chip data roms are disabled. hardware reset clears the de bit. * sd mc yd de mb ma 23 8 76543210 * operating modes a, b data rom enable internal y memory disable operating mode c (reserved) stop delay (reserved) * figure 3-2 omr format f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 operating mode register (omr) motorola memory, operating modes, and interrupts 3 - 7 3.2.3 omr internal y memory disable (yd) bit 3 bit 3 is defined as internal y memory disable (yd). when set, all y data memory address- es are considered to be external, disabling access to internal y data memory. when cleared, internal y data memory may be accessed according to the state of the de control bit. the content of the internal y data memory is not affected by the state of the yd bit. the yd bit is cleared during hardware reset. figure 3-1a shows a graphic representation of the de and yd bit effects on the x and y data memory maps. table 3-1 also compares the de and yd effects on the memory maps. 3.2.4 omr chip operating mode (mc) bit 4 the mc bit, together with bits ma and mb, define the program memory map and the operating mode of the chip. see paragraph 3.2.1 above for more information. 3.2.5 omr reserved bit 5 this bit is reserved for future expansion and will be read as zero during read operations. this bit should be written as zero for future compatibility. 3.2.6 omr stop delay (sd) bit 6 the sd bit determines the length of the clock stabilization delay that occurs when the pro- cessor leaves the stop processing state. if the stop delay bit is zero when the chip leaves the stop state, a 64k clock cycle delay is selected before continuing the stop instruction cycle and exiting the stop mode. this long delay period is long enough to allow the inter- nal clock to begin oscillating and to stabilize. when a stable external clock is used, setting the stop delay bit to one alows a shorter delay of only eight clock cycles for faster start-up of the dsp (see the dsp56003/005 data sheet for the actual timing values). table 3-1 memory mode bits de yd data memory 0 0 internal roms disabled and their addresses are part of external memory 0 1 internal x data rom is disabled and is part of external memory. internal y data ram and rom are disabled and are part of external memory f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 operating modes 3 - 8 memory, operating modes, and interrupts motorola 3.2.7 omr reserved bits 7?3 these bits are reserved for future expansion and will be read as zero during read opera- tions. these bits should be written as zero for future compatibility. 3.3 dsp56003/005 operating modes the user can set the chip operating mode through hardware by pulling the appropriate modc, modb, and moda pins high, and then asserting the reset pin. when the dsp leaves the reset state, it samples the mode pins and writes the results to the omr to set the initial operating mode. chip operating modes can also be changed using software to write the operating mode bits (mc, mb, ma) in the omr. changing operating modes does not reset the dsp. note: the user should disable interrupts immediately before changing the omr to pre- vent an interrupt from going to the wrong memory location. also, one no- operation (nop) instruction should be included after changing the omr to allow for remapping to occur. 3.3.1 single chip mode (mode 0) in the single-chip mode, all internal program and data ram memories are enabled (see figure 3-1a). a hardware reset causes the dsp to jump to internal program memory loca- tion $0000 and resume execution. the memory maps for mode 0 and mode 2 (see figure 3-1a and figure 3-1b) are identical. the difference between the two modes is that reset vec- tors to program memory location $0000 in mode 0 and vectors to location $e000 in mode 2. operating mode m c m b m a description 0 0 0 0 single-chip mode - p: ram enabled, reset at $0000 1 0 0 1 bootstrap from eprom at $c000, exit in mode 0 2 0 1 0 normal expanded mode - p: ram enabled, reset at $e000 3 0 1 1 development mode - p: ram disabled, reset at $0000 4 1 0 0 (reserved) 5 1 0 1 bootstrap from host, exit in mode 0 6 1 1 0 bootstrap from sci (external clock), exit in mode 0 7 1 1 1 bootstrap from eprom at $8000, exit in mode 0 table 3-2 dsp56003/005 operating mode summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 operating modes motorola memory, operating modes, and interrupts 3 - 9 3.3.2 bootstrap from eprom at $c000 (mode 1) the bootstrap mode allows the dsp to load a program from an inexpensive byte-wide rom into internal program memory during a power-on reset. on power-up, the wait- state generator adds 15 wait states to all external memory accesses (controlled by the bcr) so that slow memory can be used. the bootstrap program uses the bytes in three consecutive memory locations in the external rom to build a single word in internal pro- gram memory (see table 3-3). address of external byte-wide p memory p:$c000 p:$c001 p:$c002 p:$c5fd p:$c5fe p:$c5ff contents loaded to internal p: ram at: p:$0000 low byte p:$0000 mid byte p:$0000 high byte p:$01ff low byte p:$01ff mid byte p:$01ff high byte figure 3-3 port a bootstrap circuit (mode 1) dsp56003/005 11 8 ce a0-a10 d0-d7 27128 ps a0-a10 d0-d7 notes: 1. * these diodes must be schottky diodes. 2. all resistors are 15k w unless noted otherwise. 3. when in reset, irqa , irqb and nmi must be deasserted by external peripherals. moda/irqa reset modb/irqb mbd301 * +5 v from open collector buffer from reset function from open collector buffer br hack mbd301 * modc/nmi wt dr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 operating modes 3 - 10 memory, operating modes, and interrupts motorola in the bootstrap mode, the chip enables the bootstrap rom and executes the bootstrap program (the bootstrap program code is shown in appendix a). the bootstrap rom contains the bootstrap firmware program that performs initial loading of the dsp56003/005 program ram. written in dsp56003/005 assembly language, the pro- gram initializes the program ram by loading from an external byte-wide eprom starting at location p:$c000. the eprom is typically connected to the chip? address and data bus.the data contents of the eprom must be organized as shown in table 3-3. after loading the internal memory, the dsp switches to the single-chip mode (mode 0) and begins program execution at on-chip program memory location $0000. if the user selects mode 1 through hardware (moda, modb, modc pins), the following actions occur once the processor comes out of the reset state. 1. the control logic maps the bootstrap rom into the internal dsp program memory space starting at location $0000. 2. program execution begins at location $0000 in the bootstrap rom. the boot- strap rom program loads program ram from the external byte-wide eprom starting at p:$c000. address of external byte-wide memory : contents loaded to internal program ram at : p:$c000 p:$0000 low byte p:$c001 p:$0000 mid byte p:$c002 p:$0000 high byte p:$c5fd p:$01ff low byte p:$c5fe p:$01ff mid byte p:$c5ff p:$01ff high byte table 3-3 organization of eprom data contents f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 operating modes motorola memory, operating modes, and interrupts 3 - 11 3. the bootstrap rom program ends the bootstrap operation and begins execut- ing the user program. the processor enters mode 0 by writing to the omr. this action is timed to remove the bootstrap rom from the program memory map and re-enable read/write access to the program ram. the change to mode 0 is timed to allow the bootstrap program to execute a single-cycle in- struction (clear status register), then a jmp #<00, and begin execution of the user program at location $0000. the user can also get into the bootstrap mode (mode 1) through software by writing zero to mc and mb, and one to ma in the omr. this selection initiates a timed operation to map the bootstrap rom into the program address space (after a delay to allow execution of a single-cycle instruction), and then a jmp #<00 to begin the bootstrap process de- scribed previously in steps 1 through 4. this technique allows the user to reboot the system (with a different program, if desired). the code to enter the bootstrap mode is as follows: movep #0,x:$ffff ;disable interrupts. movec #1,omr ;the bootstrap rom is mapped ;into the lowest 96 locations ;in program memory. nop ;allow one cycle delay for the ;remapping. jmp <$0 ;begin bootstrap. the code disables interrupts before executing the bootstrap code. otherwise, an interrupt could cause the dsp to execute the bootstrap code out of sequence because the bootstrap program overlays the interrupt vectors. 3.3.3 normal expanded mode (mode 2) in this mode, the internal program ram is enabled and the hardware reset vectors to lo- cation $e000. (the memory maps for mode 0 and mode 2 are identical. the difference for mode 2 is that, after reset, the instruction at location $e000 is executed instead of the in- struction at $0000 ?see figure 3-1a and table 3-2). 3.3.4 development mode (mode 3) in this mode, the internal program ram is disabled and the hardware reset vector is set to location $0000. all references to program memory space are directed to external pro- gram memory. the reset vector points to location $0000. the memory map for this mode is shown in figure 3-1a and table 3-2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 interrupt priority register 3 - 12 memory, operating modes, and interrupts motorola 3.3.5 reserved (mode 4) this mode is reserved for future definition. if selected, it defaults to mode 5. 3.3.6 bootstrap from host (mode 5) in this mode, the bootstrap rom is enabled and the bootstrap program is executed. this is similar to mode 1 except that the bootstrap program loads internal program ram from the host port. note: there is a difference between modes 1 and 5 in the dsp56003/005 and mode 1 in the dsp56001. a dsp56001 program that reloads the internal program ram from the host port by setting mb:ma = 01 (assuming an external pull-up resistor on bit 23 of p:$c000) will not work as expected in the dsp56003/005. in the dsp56003/005, the program would trigger a bootstrap from the external eprom. the solution is to modify the dsp56001 program to set mc:mb:ma = 101. 3.3.7 bootstrap from sci (mode 6) in this mode, the bootstrap rom is enabled and the bootstrap program is executed. the internal and/or external program ram is loaded from the sci serial interface. the num- ber of program words to load and the starting address must be specified. the sci bootstrap code expects to receive three bytes specifying the number of program words, three bytes specifying the address from which to start loading the program words, and then three bytes for each program word to be loaded. the number of words, the starting address and the program words are received least significant byte first, followed by the mid-, and then by the most significant byte. after receiving the program words, program execution starts at the address where the first instruction was loaded. the sci is pro- grammed to work in asynchronous mode with 8 data bits, 1 stop bit, and no parity. the clock source is external and the clock frequency must be 16x the baud rate. after each byte is received, it is echoed back through the sci transmitter. 3.3.8 bootstrap from eprom at $8000 (mode 7) this mode is identical in operation to mode 1 except that the mode pins and/or bits must be set to mc:mb:ma = 111 and the eprom is loaded from memory location p: $8000. 3.4 dsp56003/005 interrupt priority register section 7 of the dsp56000 family manual describes interrupt (exception) processing in detail. it discusses interrupt sources, interrupt types, and interrupt priority levels (ipl). the figures and table in this section updates the information in the family manual to in- clude the specific information for the dsp56003/005. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 phase-locked loop (pll) configuration motorola memory, operating modes, and interrupts 3 - 13 interrupt priority levels for each on-chip peripheral device and for each external interrupt source can be programmed under software control by writing to the interrupt priority register. level 3 interrupts are nonmaskable, and interrupts of levels 0-2 are maskable. the dsp56003/005 interrupt priority register (ipr) configuration is shown in figure 3-4. the starting addresses of interrupt vectors in the dsp56003/005 are defined as shown in table 3-4, while the relative priorities of exceptions within the same ipl are defined as shown in table 3-5). 3.5 dsp56003/005 phase-locked loop (pll) configuration section 9 of the dsp56000 family manual discusses the details of the pll. the pll mul- tiplication factor and the clock applied to extal determine the frequency at which the voltage controlled oscillator (vco) will oscillate i.e. the output frequency of the pll. if the pll is used as the dsp internal clock (pctl pll enable bit = 1): the pll vco output is used directly as the internal dsp clock if the pctl chip clock source bit (csrc) is set the pll vco frequency is divided by the low power divider (lpd) and then used as the internal dsp clock if the csrc bit is cleared ssi ipl sci ipl timer ipl pwm ipl (reserved) ial1 ial0 ial2 ibl0 ibl1 ibl2 icl0 icl1 idl0 idl1 hpl0 hpl1 0 1110987654321 irqa mode irqb mode irqc ipl irqd ipl host ipl note: bits 20 to 23 are reserved, read as zero and should be written with zero for future compatibilit y . ssl1 ssl0 scl0 scl1 til0 til1 pwl0 pwl1 * * * * 12 23 22 21 20 19 18 17 16 15 14 13 figure 3-4 dsp56003/005 interrupt priority register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 phase-locked loop (pll) configuration 3 - 14 memory, operating modes, and interrupts motorola the dsp56003/005 pll multiplication factor is set to a logic one during hardware reset, which means that the multiplication factor bits mf0-mf11 in the pll control register (pctl) are set to $000.the dsp56003/005 lpd division factor bits in the pll control register (pctl) are cleared during hardware reset. interrupt starting address ipl interrupt source p:$0000 3 hardware reset p:$0002 3 stack error p:$0004 3 trace p:$0006 3 swi p:$0008 0 - 2 irqa p:$000a 0 - 2 irqb p:$000c 0 - 2 ssi receive data p:$000e 0 - 2 ssi receive data with exception status p:$0010 0 - 2 ssi transmit data p:$0012 0 - 2 ssi transmit data with exception status p:$0014 0 - 2 sci receive data p:$0016 0 - 2 sci receive data with exception status p:$0018 0 - 2 sci transmit data p:$001a 0 - 2 sci idle line p:$001c 0 - 2 sci timer p:$001e 3 nmi p:$0020 0 - 2 host receive data p:$0022 0 - 2 host transmit data p:$0024 0 - 2 host command (default) p:$0026 0 - 2 available for host command p:$0028 0 - 2 available for host command p:$002a 0 - 2 available for host command p:$002c 0 - 2 irqc p:$002e 0 - 2 irqd p:$0030 0 - 2 pwma0 p:$0032 0 - 2 pwma1 p:$0034 0 - 2 pwma2 p:$0036 0 - 2 pwmb0 p:$0038 0 - 2 pwmb1 p:$003a 0 - 2 pwm error p:$003c 0 - 2 timer/event counter p:$003e 3 illegal instruction p:$0040 0 - 2 available for host command p:$007e 0 - 2 available for host command table 3-4 interrupt vectors f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56003/005 phase-locked loop (pll) configuration motorola memory, operating modes, and interrupts 3 - 15 priority exception level 3 (nonmaskable) highest hardware reset illegal instruction nmi (external interrupt) stack error trace lowest swi levels 0, 1, 2 (maskable) highest irqa (external interrupt) irqb (external interrupt) irqc (external interrupt) irqd (external interrupt) host command interrupt host receive data interrupt host transmit data interrupt ssi rx data with exception interrupt ssi rx data interrupt ssi tx data with exception interrupt ssi tx data interrupt sci rx data with exception interrupt sci rx data interrupt sci tx data with exception interrupt sci tx data interrupt sci idle line interrupt sci timer interrupt timer/event counter interrupt pwm error pwma0 ready pwma1 ready pwma2 ready pwmb0 ready lowest pwmb1 ready table 3-5 exception priorities within an ipl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 4 - 1 section 4 external memory interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 4 - 2 external memory interface motorola paragraph number page number section 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.4 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.5 bus control register (bcr). . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.6 bus strobe and wait pins ?dsp56003 only . . . . . . . . . . . . . 4-15 4.7 bus arbitration and shared memory ?dsp56003 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola external memory interface 4 - 3 4.1 introduction the external memory interface (often refered to as port a) provides a versatile interface to external memory, allowing economical connection with fast memories/devices, slow memories/devices, and multiple bus master systems. the external memory interface has two power-reduction features. it can access internal memory spaces, toggling only the external memory signals that need to change, thereby eliminating unneeded switching current. also, if conditions allow the processor to oper- ate at a lower memory speed, wait states can be added to the external memory access to significantly reduce power while the processor accesses those memories. 4.2 interface the dsp56003/005 processor can access one or more of its memory sources (x data memory, y data memory, and program memory) while it executes an instruction. the memory sources may be either internal or external to the dsp. three address buses (xab, yab, and pab) and four data buses (xdb, ydb, pdb, and gdb) are available for internal memory accesses during one instruction cycle. the external memory interface? one address bus and one data bus are available for external memory accesses. if all memory sources are internal to the dsp, one or more of the three memory sources may be accessed in one instruction cycle (i.e., program memory access or program mem- ory access plus an x, y, xy, or l memory reference). however, when one or more of the memories are external to the chip, memory references may require additional instruction cycles because only one external memory access can occur per instruction cycle. if an instruction cycle requires more than one external access, the processor will make the accesses in the following priority: x memory, y memory, and program memory. it takes one instruction cycle for each external memory access ?i.e., one access can be executed in one instruction cycle, two accesses take two instruction cycles, etc. since the external data bus is only 24 bits wide, one xy or long external access will take two instruction cycles. the 16-bit address bus can sustain a rate of one memory access per instruction cycle (using no-wait-state memory which is discussed in section 4.4 wait states). figure 4-1 shows the external memory interface signals divided into their three func- tional groups: address bus signals (a0-a15), data bus signals (d0-d15), and bus control. the bus control signals can be subdivided into three additional groups: read/write con- trol (rd and wr ), address space selection (including program memory select (ps ), data memory select (ds ), external peripheral select (extp ), and x/y select) and bus access control (bn , br , bg , wt , bs ?dsp56003 only). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interface 4 - 4 external memory interface motorola external address bus switch external address bus a0 - a15 x address (xa) y address (ya) program address (pa) 16 - bit internal address buses 16 external data b u s switch external data b u s d0 - d23 x data (xd) y data (yd) program data (pd) 24 - bit internal data buses 24 global data (gd) external bus control logic bus control signals rd ? read enable wr ?write enable ps ?program memory select ds ?data memory select x/y ?x memory/y memory select extp ?external peripheral memory strobe bn ? bus needed br ?bus request bg ?bus grant wt ?bus wait bs ?bus strobe figure 4-1 external memory interface signals dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interface motorola external memory interface 4 - 5 the read/write controls can act as decoded read and write controls, or, as seen in figure 4-2, figure 4-3, and figure 4-4, the write signal can be used as the read/write control, and the read signal can be used as an output enable (or data enable) control for the memory. decoding in such a way simplifies connection to high-speed ran- dom-access memories (rams). the program memory select, data memory select, and x/y select can be considered additional address signals, which extend the directly addressable memory from 64k words to 192k words total. since external logic delay is large relative to ram timing margins, timing becomes more difficult as faster dsps are introduced. the separate read and write strobes used by the dsp56003/005 are mutually exclusive, with a guard time between them to avoid an instance where two data buffers are enabled simultaneously. other methods using exter- nal logic gates to generate the ram control inputs require either faster ram chips or external data buffers to avoid data bus buffer conflicts. figure 4-2 shows an example of external program memory. a typical implementation of this circuit would use three-byte-wide static memories and would not require any addi- tional logic. the ps signal is used as the program-memory chip-select signal to enable the program memory at the appropriate time. 16 rd wr ps ds x/y extp bn br bg wt bs 24 address bus a0 - a15 data b u s d0 - d23 dsp56003/005 bus control oe r/w cs address data program memory n x 24 bit words figure 4-2 external program space dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interface 4 - 6 external memory interface motorola figure 4-3 shows a similar circuit using the ds signal to enable two data memories and using the x/y signal to select between them. the three external memory spaces (pro- gram, x data, and y data) do not have to reside in separate physical memories; a single memory can be employed by using the ps , ds , and x/y signals as additional address lines to segment the memory into three spaces (see figure 4-4). table 4-1 shows how the ps , ds , and x/y signals are decoded. if the dsp is in the development mode, an exception fetch to any interrupt vector loca- tion will cause the x/y signal to go low when ps is asserted. this procedure is useful for debugging and for allowing external circuitry to track interrupt servicing. 16 rd wr ps ds x/y extp bn br bg wt bs 24 address bus a0 - a15 data b u s d0 - d23 dsp56003/005 bus control data data address address x data memory n x 24 bit words y data memory n x 24 bit words oe r/ w cs ce oe r/ w cs ce figure 4-3 external x and y data space dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interface motorola external memory interface 4 - 7 $2800 u3 u4 a11 a12 oe r/w cs a15 rd wr ps ds extp x/y bn br bg wt bs address bus a0 - a15 data b u s d0 - d23 dsp56003/005 bus control $3fff external program x and y memory 16 24 a0-a10 a13 a14 u1 ce a11 4k program memory $3000 $2fff 2k x data memory $27ff 2k y data memory $2000 24 bits u2 figure 4-4 memory segmentation dsp56003 only ps ds x/y external memory reference 1 1 1 no activity 1 0 1 x data memory on data bus 1 0 0 y data memory on data bus 0 1 1 program memory on data bus (not an exception) 0 1 0 external exception fetch: vector or vector +1 (development mode only) 0 0 x (reserved) 1 1 0 (reserved) table 4-1 program and data memory select encoding f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interface 4 - 8 external memory interface motorola figure 4-5 external memory interface bootstrap rom with x and y ram dsp56003/005 moda/irqa reset modb/irqb 24 8 mbd301 * +5 v from open collector buffer from reset function from open collector buffer a0-a10 d0-d7 a0-a9 a10 cs we oe rd ps x/y ds wr ce a0-a10 27128 d0-d23 11 10 2018-55 (3) d0-d23 br hack mbd301 * modc/nmi wt dr notes: 1. * these diodes must be schottky diodes. 2. all resistors are 15k w unless noted otherwise. 3. when in reset, irqa , irqb and nmi must be deasserted by external peripherals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing motorola external memory interface 4 - 9 figure 4-5 shows a system that uses internal program memory loaded from an external rom during power-up and splits the data memory space of a single memory bank into x: and y: memory spaces. although external program memory must be 24 bits, external data memory does not. of course, this is application specific. many systems use 16 or fewer bits for a/d and d/a conversion and, therefore, they may only need to store 16, 12, or even eight bits of data. the 24/56 bits of internal precision is usually sufficient for intermediate results. this is a cost saving feature which can reduce the number of exter- nal memory chips. 4.3 timing the external bus timing is defined by the operation of the address bus, data bus, and bus control pins. reads or writes by the dsp to the external data bus are syn- chronous with the dsp clock. the timing a, b, and c relative to the edges of an external clock (see figure 4-6 and figure 4-7) are provided in the dsp56003/005 data sheet . this timing is essential for designing synchronous multiprocessor sys- tems. figure 4-6 shows the external memory interface timing with no wait states (wait-state control is discussed in section 4.4). one instruction cycle equals two clock cycles or four clock phases. t0 t1 t2 t3 t0 t1 t2 t3 t0 t1 one instruction cycle one clock cycle internal clock phases address ps , ds , x/y a b c rd data i n wr data out read cycle write cycle figure 4-6 external memory interface bus operation with no wait states f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing 4 - 10 external memory interface motorola the clock phases, which are numbered t0 ?t3, are used for timing on the dsp. figure 4-7 shows the same timing with two wait states added to the external x: memory access. four tw clock phases have been added because one wait state adds two t phases and is equivalent to repeating the t2 and t2 clock phases. the write signal is also delayed from the t1 to the t2 state when one or more wait states are added to ease interfacing to the port. each external memory access requires the following procedure: 1. the external memory address is defined by the address bus (a0?15), and the memory reference selects (ps , ds , and x/y ). these signals change in the first phase (t0) of the bus cycle. since the memory reference select signals have the same timing as the address bus, they may be used as additional address lines. the address and memory reference signals are also used to generate chip- select signals for the appropriate memory chips. these chip-select signals change the memory chips from low-power standby mode to active mode and begin the read access time. this mode change allows slower memories to be used since the chip-select signals can be address based rather than read or write enable based. read and write enable do not become active until after the address is valid. see the timing diagrams in the dsp56003/005 data sheet for detailed timing information. t0 t1 t2 tw tw tw tw t3 t0 t1 one clock cycle internal clock phases address ps , ds , x/y a b c rd data i n wr data out read cycle write cycle one instruction cycle two wait states data latched here figure 4-7 external memory interface bus operation with two wait states f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing motorola external memory interface 4 - 11 2. when the address and memory reference signals are stable, the data transfer is enabled by read enable (rd ) or write enable (wr ). rd or wr is asserted to ?ualify?the address and memory reference signals as stable and to perform the read or write data transfer. rd and wr are asserted in the second phase of the bus cycle (if there are no wait states). read enable is typically connected to the output enable (oe ) of the memory chips and simply controls the output buffers of the chip-selected memory. write enable is connected to the write enable (we ) or write strobe (ws ) of the memory chips and is the pulse that strobes data into the selected memory. for a read operation, rd is asserted and wr remains deasserted. since write enable remains deasserted, a memory read operation is performed. the dsp data bus becomes an input, and the memory data bus becomes an output. for a write operation, wr is asserted and rd remains deasserted. since read enable remains deasserted, the mem- ory chip outputs remain in the high-impedance state even before write strobe is asserted. this state assures that the dsp and the chip-selected memory chips are not enabled onto the bus at the same time. the dsp data bus becomes an output, and the memory data bus becomes an input. 3. wait states are inserted into the bus cycle by a wait-state counter or by assert- ing wt . the wait-state counter is loaded from the bus control register. if the value loaded into the wait-state counter is zero, no wait states are inserted into the bus cycle, and rd and wr are asserted as shown in figure 4-6. if a value w 0 is loaded into the wait state counter, w wait states are inserted into the bus cycle. when wait states are inserted into an external write cycle, wr is delayed from t1 to t2. the timing for the case of two wait states (w=2) is shown in figure 4-7. 4. when rd or wr are deasserted at the start of t3 in a bus cycle, the data is latched in the destination device ?i.e., when rd is deasserted, the dsp latches the data internally; when wr is deasserted, the external memory latches the data on the positive-going edge. the address signals remain stable until the first phase of the next external bus cycle to minimize power dissipation. the memory reference signals (ps , ds , and x/y ) are deasserted (held high) during periods of no bus activity, and the data signals are three-stated. for read-mod- ify-write instructions such as bset, the address and memory reference signals remain active for the complete composite (i.e., two i cyc ) instruction cycle. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . wait states 4 - 12 external memory interface motorola 4.4 wait states the dsp56003/005 features two methods to allow the user to accommodate slow memory by changing the external memory interface bus timing. the first method uses the bus con- trol register (bcr), which allows a fixed number of wait states to be inserted in a given memory access to all locations in each of the four memory spaces: x, y, p, and i/o. the second method uses the bus strobe (bs ) and bus wait (wt ) facility (dsp56003 only), which allows an external device to insert an arbitrary number of wait states when accessing either a single location or multiple locations of external memory or i/o space. wait states are executed until the external device releases the dsp to finish the external memory cycle. 4.5 bus control register (bcr) the bcr determines the expansion bus timing by controlling the timing of the bus inter- face signals, rd and wr , and the data output lines. it is a memory mapped register located at x:$fffe. each of the memory spaces in figure 4-8 (x data, y data, program data, and i/o) has its own 4-bit bcr, which can be programmed for inserting up to 15 wait states (each wait state adds one-half instruction cycle to each memory access ?i.e., 20 ns for a 50 mhz clock). in this way, external bus timing can be tailored to match the speed requirements of the different memory spaces. on processor reset, the bcr is preset to all ones (15 wait states). this allows slow memory to be used for boot strapping. the bcr needs to be set appropriately for the memory being used or the processor will insert 15 wait states between each external memory fetch and cause the dsp to run slowly. figure 4-8 illustrates which of the four bcr nibbles affect which external memory space. all the internal peripheral devices are memory mapped, and their control registers reside between x:$ffc0 and x:$ffff. bcr contents wt (dsp56003 only) number of wait states generated 0 deasserted 0 0 asserted ?dsp56003 only 2 (minimum) > 0 deasserted equals value in bcr > 0 asserted ?dsp56003 only minimum equals 2 or value in bcr. maximum is determined by bcr or wt , whichever is larger. table 4-2 wait state control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus control register (bcr) motorola external memory interface 4 - 13 to load the bcr the way it is shown in figure 4-9, execute a ?ovep #$48ad, x:$fffe?instruction. or, change the individual bits in one of the four subregisters by using the bset and bclr instructions which are detailed in the dsp56000 family man- ual , section 6 and appendix a. figure 4-9 shows an example of mixing different memory speeds and memory-mapped peripherals in different address spaces. the internal memory uses no wait states, x: mem- ory uses two wait states, y: memory uses four wait states, p: memory uses five wait states, and the analog converters use 14 wait states. controlling five different devices at five dif- ferent speeds requires only one additional logic package. half the gates in that package are used to map the analog converters to the top 64 memory locations in y: memory. adding wait states to external memory accesses can substantially reduce power require- ments. consult the dsp56003/005 data sheet for specific power consumption requirements. bus control register $ffc0 $ffff $ffc0 $fffe $ffff x:$fffe 15 12 11 8 74 30 external x memory * external y memory * external p memory * external i/0 memory * external program memory internal program ram $ffff $200 0 external x data memory $200 $100 0 $200 $100 0 external y data memory external peripherals internal y rom internal y ram internal x rom internal x ram program memory space x data memory space y data memory space * zero to 15 wait states can be inserted into each external memory access. figure 4-8 bus control register on-chip peripherals f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus control register (bcr) 4 - 14 external memory interface motorola x:$fffe external i/0 memory external p memory external y memory external x memory 350 ns (13 wait states) a15 a15 x/y ds wr rd ps dsp56003/005 with a 40 mhz clock internal memory (0 wait states) 6242 - 15 d/a converter a/d converter cs wr dcs rd d a0 - a15 d0 - d23 cs cs we oe cs oe ce oe 6242 - 15 6242 - 15 2764 - 25 2764 - 25 2764 - 25 27256 - 30 27256 - 30 27256 - 30 8k x 24 x ram 150 ns (4 wait states) 8k x 24 y rom 250 ns (8 wait states) 32k x 24 p rom 300 ns (10 wait states) 0100 1000 1010 1101 15 12 11 8 74 30 external memory interface bus control register (bcr) figure 4-9 mixed-speed expanded system f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus strobe and wait pins ?dsp56003 only motorola external memory interface 4 - 15 4.6 bus strobe and wait pins ?dsp56003 only the ability to insert wait states using bs and wt allows devices with differing timing requirements to reside in the same memory space, allows a bus arbiter to provide a fast mul- tiprocessor bus access, and provides another means of halting the dsp at a known program location with a fast restart. the timing of the bs and wt pins is illustrated in figure 4-10. bs is asserted at the same time as the external address lines. bs can be used by external wait-state logic to establish the start of an external access. bs is deasserted in t3 of each external bus cycle, signaling that the current bus cycle will complete. since the wt signal is inter- nally synchronized, it can be asserted asynchronously with respect to the system clock. bus control t0 t1 t2 tw tw tw tw t3 t0 16 rd wr ps ds x/y extp wt bs 24 address bus a0 - a15 data b u s d0 - d23 dsp56003 t3 a0 - a15, d0 - d23, ps , ds , x/y , extp wt is sampled wt is sampled wt is sampled em sd 0 0 0 de mb ma 76 5 43210 set em = 1 operating mode register figure 4-10 bus strobe/wait sequence ?dsp56003 only dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus arbitration and shared memory ?dsp56003 only 4 - 16 external memory interface motorola the wt signal should only be asserted while bs is asserted. asserting wt while bs is deasserted will give indeterminate results. however, for the number of inserted wait states to be deterministic, wt timing must satisfy setup and hold timing with respect to the negative-going edge of extal. the setup and hold times are provided in the dsp56003/005 data sheet . the timing of wr is controlled by the bcr and is indepen- dent of wt . the minimum number of wait states that can be inserted using the wt pin is two. the bcr is still operative when using bs and wt and defines the minimum number of wait states that are inserted. table 4-2 summarizes the effect of the bcr and wt pin on the number of wait states generated. 4.7 bus arbitration and shared memory ?dsp56003 only the dsp56003 has five pins that control the external memory interface. they are bus needed (bn ), bus request (br ), bus grant (bg ), bus strobe (bs ) and bus wait (wt ) and they are described in section 2 ?dsp56003/005 pin descriptions. the bus control signals provide the means to connect additional bus masters (which may be additional dsps, microprocessors, direct memory access (dma) controllers, etc.) to the external memory interface bus. they work together to arbitrate and deter- mine what device gets access to the bus. if an external device has requested the external bus by asserting the br input, and the dsp has granted the bus by asserting bg , the dsp will continue to process as long as it requires no external bus accesses itself. if the dsp does require an external access but is not the bus master, it will stop processing and remain in wait states until it regains bus ownership. the bn pin will be asserted, and an external device may use bn to help ?rbitrate? or decide when to return bus ownership to the chip. four examples of bus arbitration will be described later in this section: bus arbitration using only br and bg with internal control bus arbitration using bn , br , and bg with external control bus arbitration using br , bg and wt , bs with no overhead signaling using semaphores. the br input allows an external device to request and be given control of the external bus while the dsp continues internal operations using internal memory spaces. this indepen- dent operation allows a bus controller to arbitrate a multiple bus-master system indepen- dent of operation of each dsp. (a bus master can issue addresses on the bus; a bus slave can respond to addresses on the bus. a single device can be both a master and a slave, but can only be one or the other at any given time.) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus arbitration and shared memory ?dsp56003 only motorola external memory interface 4 - 17 before br is asserted, all the external memory interface signals may be driven by the dsp. when br is asserted (see figure 4-11), the dsp will assert bg after the current external access cycle completes and will simultaneously three-state (high-impedance) the external memory interface signals (see the dsp56003/005 data sheet for exact timing of br and bg ). the bus is then available to whatever external device has bus mastership. the external device will return bus mastership to the dsp by deasserting br . after the dsp completes the current cycle (an internally executed instruction with or without wait states), bg will be deasserted. when bg is deasserted, the a0-a15, ps , ds , x/y , extp , and rd , wr lines will be driven. however, the data lines will remain in three-state. all signals are now ready for a normal external access. during the wait state (see section 7 in the dsp56000 family manual ), the br and bg circuits remain active. however, the port is inactive - the control signals are deasserted, the data signals are inputs, and the address signals remain as the last address read or written. when br is asserted, all signals are three-stated (high impedance). table 4-3 shows the status of br and bg during the wait state. dsp56003/005 bus master a0 - a15, d0 - d23, ps , ds , x/y , rd , wr br bg a different bus master dsp56003/005 bus master figure 4-11 bus request/bus grant sequence ?dsp56003 only s i g n a l before br while bg after br after return to n o rm a l state after first table 4-3 br and bg during wait ?dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus arbitration and shared memory ?dsp56003 only 4 - 18 external memory interface motorola 4.7.1 bus arbitration using only br and bg with internal control ? dsp56003 only perhaps the simplest example of a shared memory system using a dsp56003 is shown in figure 4-12. the bus arbitration is performed within the dsp#2 by using software. dsp#2 controls all bus operations by using i/o pin out2 to three-state its own external memory interface and by never accessing the external memory interface without first calling the subroutine that arbitrates the bus. when the dsp#2 needs to use external memory, it uses i/o pin out1 to request bus access and i/o pin in1 to read bus grant. dsp#1 does not need any extra code for bus arbitration since the br and bg hardware handles its bus arbitration automatically. the protocol for bus arbitration is as follows: at reset: dsp#2 sets out2=0 (br #2=0) and out1=1 (br #1=1), which gives dsp#1 access to the bus and suspends dsp#2 bus access. when dsp#2 wants control of the memory, the following steps are performed (see figure 4-13): 1. dsp# 2 sets out1=0 (br #1=0). 2. dsp# 2 waits for in1=0 (bg #1=0 and dsp#1 off the bus). 3. dsp#2 sets out2=1 (br #2=1 to let dsp#2 control the bus). 4. dsp#2 accesses the bus for block transfers, etc. at full speed. 5. to release the bus, dsp#2 sets out2=0 (br #2=0) after the last external access. 6. dsp#2 then sets out1=1 (br #1=1) to return control of the bus to dsp#1. 7. dsp#1 then acknowledges mastership by deasserting bg #1. 4.7.2 bus arbitration using bn , br , and bg with external control ? dsp56003 only the system shown in figure 4-14 can be implemented with external bus arbitration logic, which will save processing capacity on the dsps and can make bus access much faster at a cost of additional hardware. the bus arbitration logic takes control of the external bus by deasserting an enable signal (e1, e2, and e3) to all dsps, which will then acknowledge by granting the bus (bg =0). when a dsp (dsp#1 in figure 4-14) needs the bus, it will enter the wait state with bn asserted. if dsp#1 has highest priority of the pending bus requests, the arbitration logic grants the bus to dsp#1 by asserting e1 (e2 for dsp#2; e3 for dsp#3) to let the dsp know that it can have the bus. dsp#1 will then deassert bg to tell the arbiter it has taken control of the bus. when the dsp no longer needs to make an external access it will deassert bn and the arbiter deasserts e1, after which the dsp deasserts bg . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus arbitration and shared memory ?dsp56003 only motorola external memory interface 4 - 19 4.7.3 arbitration using br and bg , and wt and bs with no overhead ? br bg control a0 - a15 d0 - d23 br out2 out1 in1 control a0 - a15 d0 - d23 cad memory bank dsp56003/005 #1 dsp56003/005 #2 bus arbiter figure 4-12 bus arbitration using only br and bg with internal control ? dsp56003 only data transferred out1 1234567 in1 out2 figure 4-13 two dsps with external bus arbitration timing here f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus arbitration and shared memory ?dsp56003 only 4 - 20 external memory interface motorola dsp56003 only by using the circuit shown in figure 4-15, two dsps can share memory with hardware arbitration that requires no software on the part of the dsps. the protocol for bus arbi- tration in figure 4-15 is as follows: at reset assume dsp#1 is not making external accesses so that br of dsp#2 is deas- serted. hence, bg of dsp#2 is deasserted, which three-states the buffers, giving dsp#2 control of the memory. when dsp#1 wants control of the memory the following steps are performed (see figure 4-16): 16 system memory 32k x 24 x data ram 32k x 24 y data ram 32k x 24 program ram address data control address data control 24 5 adc adc adc dsp56003 #1 dsp56003 #2 dsp56003 #3 bg br bn bg br bn bg br bn bus arbitration logic with priority encoder a1 e1 br1 a2 e2 br2 a3 e3 br3 figure 4-14 bus arbitration using bn , br , and bg with external control ? dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus arbitration and shared memory ?dsp56003 only motorola external memory interface 4 - 21 1. dsp#1 makes an external access, thereby asserting bs , which asserts wt (causing dsp#1 to execute wait states in the current cycle) and asserts dsp#2 br (requesting that dsp#2 release the bus). 2. when dsp#2 finishes its present bus cycle, it three-states its bus drivers and asserts bg . asserting bg enables the three-state buffers, placing the dsp#1 signals on the memory bus. asserting bg also deasserts wt , which allows dsp#1 to finish its bus cycle. 3. when dsp#1? memory cycle is complete, it releases bs , which deasserts br . dsp#2 then deasserts bg , three-stating the buffers and allowing dsp#2 to access the memory bus. memory dac dsp #1 d0 - d23 a0 - a15 rd , wr , ds , ps , x/ y bs wt three-state buffer dir enable dsp #2 d0 - 23 a0 - a15 rd , wr , ds , ps , x/y bg br figure 4-15 bus arbitration using br and bg , and wt and bs with no overhead ? dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus arbitration and shared memory ?dsp56003 only 4 - 22 external memory interface motorola 4.7.4 signaling using semaphores figure 4-17 shows a more sophisticated shared memory system that uses external arbi- tration with both local external memory and shared memory. the four semaphores are bits in one of the words in each shared memory bank used by software to arbitrate mem- ory use. semaphores are commonly used to indicate that the contents of the semaphore? memory blocks are being used by one processor and are not available for use by another processor. typically, if the semaphore is cleared, the block is not allocated to a processor; if the semaphore is set, the block is allocated to a processor. without semaphores, one processor may try to use data while it is being changed by another processor, which may cause errors. this problem can occur in a shared memory system when separate test and set instructions are used to ?ock?a data block for use by a single processor. the correct procedure is to test the semaphore and then set the semaphore if it was clear to lock and gain exclusive use of the data block. the problem occurs when the second processor acquires the bus and tests the semaphore after the first processor tests the sema- phore but before the first processor can lock the data block. the incorrect sequence is: 1. the first processor tests the semaphore and sees that the block is available 2. the second processor then tests the bit and also sees that the block is available 3. both processors then set the bit to lock the data 4. both proceed to use the data on the assumption that the data cannot be changed by another processor bs wt br bg 12 3 figure 4-16 two dsps with external bus arbitration timing ?dsp56003 only data transferred between dsp#1 and memory here f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bus arbitration and shared memory ?dsp56003 only motorola external memory interface 4 - 23 the solution is that the dsp56k processor series has a group of instructions designed specifically to prevent this problem. they perform an indivisible read-modify-write operation and do not release the bus between the read and write (specifically, a0?15, ds , ps , and x/y do not change state). using a read-modify-write operation allows these instructions to test the semaphore and then to set, clear, or change the sema- phore without the possibility of another processor testing the semaphore before it is changed. the instructions are bit test and change (bchg), bit test and clear (bclr), and bit test and set (bset). (they are discussed in detail in the dsp56000 family manual .) the proper way to set the semaphore to gain exclusive access to a memory block is to use bset to test the semaphore and to set it to one. after the bit is set, the result of the test operation will reveal if the semaphore was clear before it was set by bset and if the memory block is available. if the bit was already set and the block is in use by another processor, the dsp must wait to access the memory block. address data and control buses address data and control buses semaphore 3 semaphore 2 semaphore 1 semaphore 0 1 1 0 0 bank 3 bank 2 bank 1 bank 0 dsp56003/005 processor or dma dsp56003/005 local memory processor local memory arbitration logic bus buffer bus buffer figure 4-17 signaling using semaphores f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 5 - 1 section 5 host interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 5 - 2 host interface motorola paragraph number page number section 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2 general purpose i/o configuration . . . . . . . . . . . . . . . . . . 5-4 5.3 host interface (hi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola host interface 5 - 3 5.1 introduction port b is a dual-purpose i/o port. it performs as 15 general-purpose i/o (gpio) pins, each configurable as output or input, to be used for device control. or, it can perform as an 8-bit bidirectional host interface (hi) (see figure 5-1), where it provides a convenient connection to another processor. this section describes both configurations, including examples of how to configure and use the port. this port b (gpio and host interface) is identical to the port b on the dsp56001 and dsp56002. external address switch external data switch bus control host/dma parallel interface sci interface ssi interface port a i/0 (47) port c i/0 (9) port b i/0 (15) a0 - a15 d0 - d23 ps ds x/y extp rd wr bn br bg wt bs pb0 - pb7 pb8 pb9 pb10 pb11 pb12 pb13 pb14 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 h0 - h7 ha0 ha1 ha2 hr/w hen hreq ha ck or pb14 rxd txd sclk sc0 sc1 sc2 sck srd std default function alternate function 8 8 24 16 figure 5-1 port b interface dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general purpose i/o configuration 5 - 4 host interface motorola 5.2 general purpose i/o configuration when it is configured as general-purpose i/o, port b acts as three memory-mapped registers (see figure 5-2) that control 15 i/o pins (see figure 5-3). they are the port b control register (pbc), port b data direction register (pbddr), and port b data register (pbd). reset configures port b as general-purpose i/o with all 15 pins as inputs by clearing both the control (pbc), and data direction (pbddr) registers (external circuitry connected to these pins may need pullups until the pins are configured for operation). there are three registers associated with each external pin. to select between general purpose i/o and the hi, set pbc bits 0 and 1 as shown in figure 5-2. use the pbddr to determine whether the corresponding bit in the pbd shall be an input pin (bit is set to zero) or an output pin (bit is set to one). if a pin is configured as a gpio input (as shown in figure 5-4) and the processor reads the pbd, the processor sees the logic level on the pin. if the processor writes to the pbd, the data is latched there, but does not appear on the pin because the buffer is in the high- impedance state. bc1 bc0 function 0 0 parallel i/o (reset condition) 0 1 host interface 1 0 host interface (with ha ck pin as gpio) 1 1 reserved 0000000000000000000000 bc 0 23 0 x:$ffe0 port b control register (pbc) bd 0 23 0 x:$ffe2 port b data direction register (pbddr) bdx data direction 0 input (reset condition) 1 output 000000000 bd 1 bd 2 bd 3 bd 4 bd 5 bd 6 bd 7 bd 8 bd 9 bd 11 bd 10 bd 12 bd 13 bd 14 pb 0 23 0 x:$ffe4 port b data register (pbd) 000000000 pb 1 pb 2 pb 3 pb 4 pb 5 pb 6 pb 7 pb 8 pb 9 pb 11 pb 10 pb 12 pb 13 pb 14 figure 5-2 parallel port b registers bc 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general purpose i/o configuration motorola host interface 5 - 5 if a pin is configured as a gpio output and the processor reads the pbd, the processor sees the contents of the pbd rather the logic level on the pin, which allows the pbd to be used as a general purpose 15-bit register. if the processor writes to the pbd, the data is latched there and appears on the pin during the following instruction cycle (see section 5.2.2 port b gen- eral purpose i/o timing ). if a pin is configured as a host pin, the port b gpio registers can be used to help in debugging the hi. if the pbddr bit for a given pin is cleared (configured as an input), the pbd will show the logic level on the pin, regardless of whether the hi function is using the pin as an input or an output. if the pbddr is set (configured as an output) for a given pin that is configured as a host pin, when the processor reads the pbd, it sees the contents of the pbd rather than the logic level on the pin - another case which allows the pbd to act as a general purpose register. note: the external host processor should be carefully synchronized to the dsp56003/005 to assure that the dsp and the external host will properly read status bits transmit- ted between them. there is more discussion of such port use considerations in sec- tions section 5.3.2.7 host port use considerations ?dsp side and section 5.3.6.5 host port use considerations ?host side . p o r t b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pb10 pb11 pb12 pb13 pb14 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bc0/bc1 bd0 bd1 bd2 bd3 bd4 bd5 bd6 bd7 bd8 bd9 bd10 bd11 bd12 bd13 bd14 enabled by bits in x:$ffe0 direction selected by x:$ffe2 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pb10 pb11 pb12 pb13 pb14 input/output data x:$ffe4 figure 5-3 parallel port b pinout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general purpose i/o configuration 5 - 6 host interface motorola 5.2.1 programming general purpose i/o port b is a memory-mapped peripheral as are all of the dsp56003/005 peripherals (see figure 5-5). the standard move instruction transfers data between port b and a register; as a result, move takes two instructions to perform a memory-to-memory data transfer and uses a temporary holding register. the movep instruction is specifically designed for i/o data transfer as shown in figure 5-6. although the movep instruction may take twice as long to execute as a move instruction, only one movep is required for a mem- ory-to-memory data transfer, and movep does not use a temporary register. using the movep instruction allows a fast interrupt to move data to/from a peripheral to memory and execute one other instruction or move the data to an absolute address. movep is the only memory-to-memory move instruction; however, one of the operands must be in the top 64 locations of either x: or y: memory. the bit-oriented instructions that use i/o short addressing (bchg, bclr, bset, btst, jclr, jsclr, jset, and jsset) can also be used to address individual bits for faster i/o processing. the digital signal processor (dsp) does not have a hardware data strobe to strobe data out of the gpio port. if a strobe is needed, it can be implemented using soft- ware to toggle one of the gpio pins. port registers hi input data bit hi data direction bit hi output data bit port input data bit port control register bit data direction register bit pin function 0 0 port input pin pin port b data (pbd) register bit data direction register (pbddr) bit port b control register (pbc) bit (gpio position) (input position) peripheral logic figure 5-4 port b i/o pin control logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general purpose i/o configuration motorola host interface 5 - 7 x:$ffff x:$fffe x:$fffd x:$fffc x:$fffb x:$fffa x:$fff9 x:$fff8 x:$fff7 x:$fff6 x:$fff5 x:$fff4 x:$fff3 x:$fff2 x:$fff1 x:$fff0 x:$ffef x:$ffee x:$ffed x:$ffec x:$ffeb x:$ffea x:$ffe9 x:$ffe8 x:$ffe7 x:$ffe6 x:$ffe5 x:$ffe4 x:$ffe3 x:$ffe2 x:$ffe1 x:$ffe0 x:$ffdf x:$ffde x:$ffdd x:$ffdc x:$ffdb x:$ffda x:$ffd9 x:$ffd8 x:$ffd7 x:$ffd6 x:$ffd5 x:$ffd4 interrupt priority register (ipr) port a ?bus control register (bcr) pll control register once port gdb register (reserved) (reserved) (reserved) (reserved) (reserved) sci hi - rec/xmit data register (srx/stx) sci mid - rec/xmit data register (srx/stx) sci low - rec/xmit data register (srx/stx) sci transmit data address register (stxa) sci control register (sccr) sci interface status register (ssr) sci interface control register (scr) ssi recieve/transmit data register (rx/tx) ssi status/time slot register (ssisr/tsr) ssi control register b (crb) ssi control register a (cra) host receive/transmit register (hrx/htx) (reserved) host status register (hsr) host control register (hcr) watchdog timer count register (wcr) watchdog timer control/status register (wcsr) port c ?data register (pcd) port b ?data register (pbd) port c ?data direction register (pcddr) port b ?data direction register (pbddr) port c ?control register (pcc) port b ?control register (pbc) timer count register (tcr) timer control/status register (tcsr) (reserved) pwma2 count register (pwacr2) pwma1 count register (pwacr1) pwma0 count register (pwacr0) pwma prescaler register (pwacsr0) pwma control and status register (pwacsr1) pwmb1 count register (pwbcr1) pwmb0 count register (pwbcr0) pwmb prescaler register (pwbcsr0) pwmb control and status register (pwbcsr1) x:$ffc0 reserved = read as random number; write as don? care. 23 16 15 8 7 0 figure 5-5 on-chip peripheral memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general purpose i/o configuration 5 - 8 host interface motorola figure 5-7 details the process of programming port b as gpio. normally, it is not good pro- gramming practice to activate a peripheral before programming it. however, reset activates the port b general-purpose i/o as all inputs; the alternative is to configure port b as an hi, which may not be desirable. in this case, it is probably better to insure that port b is initially configured for general-purpose i/o, and then configure the data direction and data registers. it may be better in some situations to program the data direction or the data registers first to prevent two devices from driving one signal. the order of steps 1, 2, and 3 in figure 5-7 is optional and can be changed as needed. 5.2.2 port b general purpose i/o timing general purpose data written to port b is synchronized to the central processing unit (cpu) but delayed by one instruction cycle. for example, the instruction move data15,x:portb data24,y:extern 1. writes 15 bits of data to the port b register, but the output pins do not change until the following instruction cycle 2. writes 24 bits of data to the external y memory, which appears on port a dur- ing t2 and t3 of the current instruction as a result, if it is desirable to synchronize port a and port b outputs, two instructions must be used: move data15,x:portb nop data24,y:extern the nop can be replaced by any instruction that allows parallel moves. inserting one or more ?ove data15,x:portb data24,y:extern?instructions between the first and second instruction effectively produces an external 39-bit write each instruction cycle with only one instruction cycle lost in setup time: . move #$0,x:$ffe0 ;select port b to be general-purpose i/o move #$7f00,x:$ffe2 ;select pins pb0?b7 to be inputs . ;and pins pb8?b14 to be outputs . movep #data_out,x:$ffe4 ;put bits 8?4 of ?ata_out?on pins ;pb8?b14 bits 0? are ignored movep x:$ffe4,#data_in ;put pb0?b7 in bits 0? of ?ata_in figure 5-6 instructions to write/read parallel data with port b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general purpose i/o configuration motorola host interface 5 - 9 move data15,x:portb move data15,x:portb data24,y:extern move data15,x:portb data24,y:extern : : move data15,x:portb data24,y:extern nop data24,y:extern one application of this technique is to create an extended address for port a by concate- nating the port a address bits (instead of data bits) to the port b general-purpose output bits. the port b general-purpose i/o register would then work as a base address register, allowing the address space to be extended from 64k words (16 bits) to two billion words (16 bits +15 bits = 31 bits). ************* bc 0 bd 0 bd 1 bd 2 bd 3 bd 4 bd 5 bd 6 bd 7 bd 8 bd 9 bd 10 bd 11 bd 12 bd 13 * * bd 14 pb 0 pb 1 pb 2 pb 3 pb 4 pb 5 pb 6 pb 7 pb 8 pb 9 pb 10 pb 11 pb 12 pb 13 * pb 14 step 1. acitivate port b for general - purpose i/o: set bits 0 and 1 to zero x:$ffe0 15 0 port b control register (pbc) x:$ffe2 port b data direction register (pbddr) 15 0 step 2. set individual pins to input or output: bdxx = 0 input or bdxx = 1 output 15 0 x:$ffe4 port b data register (pbd) *reserved; write as zero. step 3. write or read data: pbxx input if bdxx = 0 or pbxx output if bdxx = 1 figure 5-7 i/o port b configuration bc 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 10 host interface motorola port b uses the dsp cpu four-phase clock for its operation. therefore, if wait states are inserted in the dsp cpu timing, they also affect port b timing. the result is that ports a and b in the previous synchronization example will always stay synchronized, regardless of how many wait states are used. 5.3 host interface (hi) the hi is a byte-wide, full-duplex, double-buffered, parallel port which may be con- nected directly to the data bus of a host processor. the host processor may be any of a number of industry standard microcomputers or microprocessors, another dsp, or dma hardware because this interface looks like static memory. the hi is asynchronous and consists of two banks of registers ?one bank accessible to the host processor and a second bank accessible to the dsp cpu (see figure 5-8). a brief description of the hi features is presented in the following listing: speed 3.3 million word/sec interrupt driven data transfer rate (this is the maximum interrupt rate for the dsp56003/005 running at 40 mhz ?i.e., one interrupt every six instruction cycles.) signals (15 pins) h0?7 host data bus ha0-ha2 host address select hr/w host read/write control hen host transfer enable hreq host request hack host acknowledge interface ?dsp cpu side mapping: three x: memory locations data word: 24 bits transfer modes: dsp to host host to dsp host command handshaking protocols: software polled interrupt driven (fast or long interrupts) direct memory access instructions: memory-mapped registers allow the standard move instruction to be used. special movep instruction provides for i/o service capability using fast interrupts. bit addressing instructions simplify i/o service routines. i/o short addressing provides faster execution with fewer instruction words. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 11 interface ?host side mapping: eight consecutive memory locations memory-mapped peripheral for microprocessors, dma controllers, etc. data word: eight bits transfer modes: dsp to host host to dsp host command mixed 8-, 16-, and 24-bit data transfers handshaking protocols: software polled interrupt driven and compatible with mc68000 cycle stealing dma with initialization dedicated interrupts: separate interrupt vectors for each interrupt source special host commands force dsp cpu interrupts under host processor control, which are useful for: real-time production diagnostics debugging window for program development host control protocols and dma setup figure 5-8 is a block diagram showing the registers in the hi. these registers can be divided vertically down the middle into registers visible to the host processor on the left and registers visible to the dsp on the right. they can also be divided horizontally into control at the top, dsp-to-host data transfer in the middle (htx, rxh, rxm, and rxl), and host-to-dsp data transfer at the bottom (thx, txm, txl, and hrx). 5.3.1 host interface ?dsp cpu viewpoint the dsp cpu views the hi as a memory-mapped peripheral occupying three 24-bit words in data memory space. the dsp may use the hi as a normal memory-mapped peripheral, using either standard polled or interrupt programming techniques. separate transmit and receive data registers are double buffered to allow the dsp and host processor to efficiently transfer data at high speed. memory mapping allows dsp cpu communication with the hi registers to be accomplished using standard instructions and addressing modes. in addition, the movep instruction allows hi-to-memory and memory-to-hi data transfers without going through an intermediate register. both hardware and software reset disable the hi and change port b to general-purpose i/o with all pins designated as inputs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 12 host interface motorola 5.3.2 programming model ?dsp cpu viewpoint the hi has two programming models: one for the dsp programmer and one for the host pro- cessor programmer. in most cases, the notation used reflects the dsp perspective. the hi dsp programming model is shown in figure 5-9. there are three registers: a control register (hcr), a status register (hsr), and a data transmit/receive register (htx/hrx). these reg- isters can only be accessed by the dsp56003/005; they can not be accessed by the host processor. the hi host processor programming model is shown in figure 5-12. receive byte registers (read only) transmit byte registers (write only) interrupt control register (read/write) dsp cpu global data b u s $0 icr $1 cvr hcr hsr $2 isr $3 ivr control logic htx hrx $5 rxh $6 rxm $7 rxl $5 txh $6 txm $7 txl x:$ffe8 x:$ffe9 x:$ffeb x:$ffeb host control register (read/write) host status register (read only) host transmit data register (write only) host recieve data register (read only) command vector register (read/write) interrupt status register (read only) interrupt vector register (read/write) 24 24 24 8 host mpu data b u s h0 - h7 figure 5-8 hi block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 13 00 0 hf3 (0) hf2 (0) hcie (0) htie (0) hrie (0) x:$ffe8 70 dsp cpu hi flags host flag 3 host flag 2 interrupt enables host receive host transmit host command host control register (hcr) (read/write) 00 hf1 (0) hf0 (0) hcp (0) htde (1) hrdf (0) x:$ffe9 70 host hi flags host flag 1 host flag 0 host receive data full host transmit data empty host command pending host status register (hsr) (read only) dma (0) x:$ffeb x:$ffeb receive high byte receive middle byte receive low byte transmit high byte transmit middle byte transmit low byte host receive data register (hrx) (read only) host transmit data register (htx) (write only) 707070 23 16 15 8 7 0 note: the numbers in parentheses are reset values. figure 5-9 host interface programming model ?dsp viewpoint f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 14 host interface motorola the following paragraphs describe the purpose and operation of each bit in each reg- ister of the hi visible to the dsp cpu. the effects of the different types of reset on these registers are shown. a brief discussion of interrupts and operation of the dsp side of the hi complete the programming model from the dsp viewpoint. the pro- gramming model from the host viewpoint begins at section 5.3.3.1 programming model ?host processor viewpoint . 5.3.2.1 host control register (hcr) the hcr is an 8-bit read/write control register used by the dsp to control the hi inter- rupts and flags. the hcr cannot be accessed by the host processor. it occupies the low- order byte of the internal data bus; the high-order portion is zero filled. any reserved bits are read as zeros and should be programmed as zeros for future compatibility. (the bit manipulation instructions are useful for accessing the individual bits in the hcr.) the contents of the hcr are cleared on hardware or software reset. the control bits are described in the following paragraphs. 5.3.2.1.1 hcr host receive interrupt enable (hrie) bit 0 the hrie bit is used to enable a dsp interrupt when the host receive data full (hrdf) status bit in the host status register (hsr) is set. when hrie is cleared, hrdf interrupts are dis- abled. when hrie is set, a host receive data interrupt request will occur if hrdf is also set. hardware and software resets clear hrie. 5.3.2.1.2 hcr host transmit interrupt enable (htie) bit 1 the htie bit is used to enable a dsp interrupt when the host transmit data empty (htde) status bit in the hsr is set. when htie is cleared, htde interrupts are disabled. when htie is set, a host transmit data interrupt request will occur if htde is also set. hardware and software resets clear the htie. 5.3.2.1.3 hcr host command interrupt enable (hcie) bit 2 the hcie bit is used to enable a vectored dsp interrupt when the host command pending (hcp) status bit in the hsr is set. when hcie is cleared, hcp interrupts are disabled. when hcie is set, a host command interrupt request will occur if hcp is also set. the starting address of this interrupt is determined by the host vector (hv). hardware and software resets clear the hcie. 5.3.2.1.4 hcr host flag 2 (hf2) bit 3 the hf2 bit is used as a general-purpose flag for dsp-to-host communication. hf2 may be set or cleared by the dsp. hf2 is visible in the interrupt status register (isr) on the host pro- cessor side (see figure 5-10). hardware and software resets clear hf2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 15 5.3.2.1.5 hcr host flag 3 (hf3) bit 4 the hf3 bit is used as a general-purpose flag for dsp-to-host communication. hf3 may be set or cleared by the dsp. hf3 is visible in the isr on the host processor side (see figure 5-10). hardware and software resets clear hf3. note: there are four host flags: two used by the host to signal the dsp (hf0 and hf1) and two used by the dsp to signal the host processor (hf2 and hf3). they are gen- eral purpose flags and are not designated for any specific purpose. the host flags do not cause interrupts; they must be polled to see if they have changed. these flags can be used individually or as encoded pairs. see section 5.3.2.7 host port use considerations ?dsp side for additional information. an example of the use of host flags is the bootstrap loader, which is listed in appendix a. host flags are used to tell the bootstrap program whether or not to terminate early. 5.3.2.1.6 hcr reserved bits 5, 6, and 7 these unused bits are reserved for future expansion and should be written with zeros for upward compatibility. 5.3.2.2 host status register (hsr) the hsr is an 8-bit read-only status register used by the dsp to interrogate status and flags of the hi. it can not be directly accessed by the host processor. when the hsr is read to the internal data bus, the register contents occupy the low-order byte of the data bus; the high- order portion is zero filled. the status bits are described in the following paragraphs. 5.3.2.2.1 hsr host receive data full (hrdf) bit 0 the hrdf bit indicates that the host receive data register (hrx) contains data from the host processor. hrdf is set when data is transferred from the txh:txm:txl registers to the hrx register. hrdf is cleared when hrx is read by the dsp. hrdf can also be cleared by the host processor using the initialize function. hardware, software, individual, and stop resets clear hrdf. 5.3.2.2.2 hsr host transmit data empty (htde) bit 1 the htde bit indicates that the host transmit data register (htx) is empty and can be written by the dsp. htde is set when the htx register is transferred to the rxh:rxm:rxl registers. htde is cleared when htx is written by the dsp. htde can also be set by the host processor using the initialize function. hardware, software, individual, and stop sets htde. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 16 host interface motorola 5.3.2.2.3 hsr host command pending (hcp) bit 2 the hcp bit indicates that the host has set the hc bit and that a host command interrupt is pending. the hcp bit reflects the status of the hc bit in the command vector register (cvr). hc and hcp are cleared by the dsp exception hardware when the exception is taken. the host can clear hc, which also clears hcp. hardware, software, individual, and stop resets clear hcp. 5.3.2.2.4 hsr host flag 0 (hf0) bit 3 the hf0 bit in the hsr indicates the state of host flag 0 in the icr on the host processor side. hf0 can only be changed by the host processor (see figure 5-10). hardware, software, indi- vidual, and stop resets clear hf0. 5.3.2.2.5 hsr host flag 1 (hf1) bit 4 the hf1 bit in the hsr indicates the state of host flag 1 in the icr on the host processor side. hf1 can only be changed by the host processor (see figure 5-10). hardware, software, indi- vidual, and stop resets clear hf1. init hm1 hm0 hf1 hf0 0 treq rreq host to dsp56003/005 status flags 70 $0 host interrupt control register (icr) (read/write) dma 0 0 hf1 hf0 hcp htde hrdf 70 x:$ffe9 host status register (hsr) (read only) dsp56003/00 5 hreq dma 0 hf3 hf2 trdy txde rxdf dsp56003/005 to host status flags 70 $2 host interrupt status register (isr) (read only) 0 0 0 hf3 hf2 hcie htie hrie 70 x:$ffe8 host control register (hcr) (read/write) dsp56003/00 5 figure 5-10 host flag operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 17 5.3.2.2.6 hsr reserved bits 5 and 6 these status bits are reserved for future expansion and read as zero during dsp read operations. 5.3.2.2.7 hsr dma status (dma) bit 7 the dma bit indicates that the host processor has enabled the dma mode of the hi by set- ting hm1 or hm0 to one. when the dma bit is zero, it indicates that the dma mode is dis- abled by the hm0 and hm1 bits in the icr and that no dma operations are pending. when the dma bit is set, the dma mode has been enabled if one or more of the host mode bits have been set to one. the channel not in use can be used for polled or interrupt operation by the dsp. hardware, software, individual, and stop resets clear the dma bit. 5.3.2.3 host receive data register (hrx) the hrx register is used for host-to-dsp data transfers. the hrx register is viewed as a 24- bit read-only register by the dsp cpu. the hrx register is loaded with 24-bit data from the transmit data registers (txh:txm:txl) on the host processor side when both the transmit data register empty txde (host processor side) and dsp host receive data full (hrdf) bits are cleared. this transfer operation sets txde and hrdf. the hrx register contains valid data when the hrdf bit is set. reading hrx clears hrdf. the dsp may program the hrie bit to cause a host receive data interrupt when hrdf is set. resets do not affect hrx. 5.3.2.4 host transmit data register (htx) the htx register is used for dsp-to-host data transfers. the htx register is viewed as a 24-bit write-only register by the dsp cpu. writing the htx register clears htde. the dsp may program the htie bit to cause a host transmit data interrupt when htde is set. the htx register is transferred as 24-bit data to the receive byte registers (rxh:rxm:rxl) if both the htde bit (dsp cpu side) and receive data full (rxdf) status bits (host processor side) are cleared. this transfer operation sets rxdf and htde. data should not be written to the htx until htde is set to prevent the previous data from being overwritten. resets do not affect htx. 5.3.2.5 register contents after reset table 5-1 shows the results of four reset types on bits in each of the hi registers seen by the dsp cpu. the hardware reset (hw) is caused by the reset signal; the software reset (sw) is caused by executing the reset instruction; the individual reset (ir) is caused by clearing pbc register bits 0 and 1, and the stop reset (st) is caused by executing the stop instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 18 host interface motorola 5.3.2.6 host interface dsp cpu interrupts the hi may request interrupt service from either the dsp or the host processor. the dsp cpu interrupts are internal and do not require the use of an external interrupt pin (see figure 5-11). when the appropriate mask bit in the hcr is set, an interrupt condition caused by the host processor sets the appropriate bit in the hsr, which generates an interrupt request to the dsp cpu. the dsp acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine. the three possible interrupts are 1) receive data register full, 2) transmit data register empty, and 3) host command. the host command can access any interrupt vector in the interrupt vector table although it has a set of vectors reserved for host command use. the dsp interrupt service routine must read or write the appropriate hi reg- ister (clearing hrdf or htde, for example) to clear the interrupt. in the case of host command interrupts, the interrupt acknowledge from the program controller will clear the pending interrupt condition. 5.3.2.7 host port use considerations ?dsp side synchronization is a common problem when two asynchronous systems are connected, and careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. the considerations for proper operation on the dsp cpu side are discussed in the following paragraphs, and considerations for the host processor side are discussed in section 5.3.6.5 host port use considerations ?host side . register name register data reset type hw reset sw reset ir reset st reset hcr hf(3 - 2) 0 0 hcie 0 0 htie 0 0 hrie 0 0 hsr dma 0000 hf(1 - 0) 0000 hcp 0000 htde 1111 hrdf 0000 hrx hrx (23 - 0) htx htx (23 - 0) table 5-1 host registers after reset ?dsp cpu side f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 19 dma, hf1, hf0, hcp, htde, and hrdf status bits are set or cleared by the host processor side of the interface. these bits are individually synchronized to the dsp clock. the only system problem with reading status occurs if hf1 and hf0 are encoded as a pair because each of their four combinations (00, 01, 10, and 11) has significance. there is a small possibility that the dsp will read the status bits during the transition and receive ?1?or ?0?instead of ?1? the solution to this potential problem is to read the bits twice for consensus (see section 5.3.6.5 host port use considerations ?host side for additional information). 5.3.3 host interface ?host processor viewpoint the hi appears to the host processor as eight words of byte-wide static memory. the host may access the hi asynchronously by using polling techniques or interrupt-based tech- niques. separate transmit and receive data registers are double buffered to allow the dsp cpu and host processor to transfer data efficiently at high speed. the hi contains a rudi- mentary dma controller, which makes generating addresses (ha0?a2) for the tx/rx registers in the hi unnecessary. 70 0 0 0 hf3 hf2 hcie htie hrie mask hcr dma 0 0 hf1 hf2 hcp htde hrdf 70 x:$ffe9 x:$ffe8 dsp cpu interrupts recieve data full p:$0020 transmit data empty p:$0022 host command p:(2xhv t $0000 - $007e) reset t hv = $0012 in cvr hsr status figure 5-11 hsr?cr operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 20 host interface motorola 5.3.3.1 programming model ?host processor viewpoint the hi appears to the host processor as a memory-mapped peripheral occupying eight bytes in the host processor address space (see figure 5-12 and figure 5-13). these registers can be viewed as one control register (icr), one status register (isr), three data registers (rxh/txh, rxm/txm, and rxl/txl), and two vector registers (ivr and cvr). the cvr is a special command register that is used by the host processor to issue commands to the dsp. these reg- isters can be accessed only by the host processor; they can not be accessed by the dsp cpu. host processors may use standard host processor instructions (e.g., byte move) and address- ing modes to communicate with the hi registers. the hi registers are addressed so that 8-bit mc6801-type host processors can use 16-bit load (ldd) and store (std) instructions for data transfers. the 16-bit mc68000/mc68010 host processor can address the hi using the special movep instruction for word (16-bit) or long-word (32-bit) transfers. the 32-bit mc68020 host processor can use its dynamic bus sizing feature to address the hi using standard move word (16-bit), long-word (32-bit) or quad-word (64-bit) instructions. the hreq and hack handshake flags are provided for polled or interrupt-driven data transfers with the host pro- cessor. because the dsp interrupt response is sufficiently fast, most host microprocessors can load or store data at their maximum programmed i/o (non-dma) instruction rate without testing the handshake flags for each transfer. if the full handshake is not needed, the host pro- cessor can treat the dsp as fast memory, and data can be transferred between the host processor and the dsp at the fastest host processor data rate. dma hardware may be used with the handshake flags to transfer data without host processor intervention. one of the most innovative features of the host interface is the host command feature. with this feature, the host processor can issue vectored exception requests to the dsp56003/005. the host may select any one of 128 dsp56003/005 exception routines to be executed by writ- ing a vector address register in the hi. this flexibility allows the host programmer to execute up to 128 preprogrammed functions inside the dsp56003/005. for example, host exceptions can allow the host processor to read or write dsp56003/005 registers (x, y, or program mem- ory locations), force exception handlers (e.g., ssi, sci, irqa , irqb exception routines), and perform control and debugging operations if exception routines are implemented in the dsp56003/005 to perform these tasks. 5.3.3.2 interrupt control register (icr) the icr is an 8-bit read/write control register used by the host processor to control the hi interrupts and flags. icr cannot be accessed by the dsp cpu. icr is a read/write register, which allows the use of bit manipulation instructions on control register bits. the control bits are described in the following paragraphs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 21 hf1 (0) hf0 (0) 0 treq (0) rreq (0) $0 70 interrupt control register (icr) (read/write) interrupt vector number ($0f) 70 flags interrupt vector register (ivr) (read/write) 0 0 0 0 0 0 0 0 rxh receive high byte rxm receive middle byte not used txh transmit high byte txm transmit middle byte 70707070 note: the numbers in parentheses are reset values. hm1 (0) hm0 (0) init (0) modes 0 0 interrupt mode (dma off) 0 1 24-bit dma mode 1 0 16-bit dma mode 1 1 8-bit dma mode 0 host vector ($12) 75 0 command vector register (cvr) (read/write) hc (0) $1 hf3 (0) hf2 (0) 0 txde (1) rxdf (0) $2 70 interrupt status register (isr) (read only) status dma (0) hreq (0) flags trdy (1) $3 rxl receive low byte txl transmit low byte 31 $4 24 23 $5 16 15 $6 8 7 $7 0 receive byte registers (rxh:rxm:rxl) (read only) transmit byte registers (txh:txm:txl) (write only) figure 5-12 host processor programming model ?host side f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 22 host interface motorola 5.3.3.2.1 icr receive request enable (rreq) bit 0 the rreq bit is used to control the hreq pin for host receive data transfers. in interrupt mode (dma off), rreq is used to enable interrupt requests via the external host request (hreq ) pin when the receive data register full (rxdf) status bit in the isr is set. when rreq is cleared, rxdf interrupts are disabled. when rreq is set, the external hreq pin will be asserted if rxdf is set. in dma modes, rreq must be set or cleared by software to select the direction of dma trans- fers. setting rreq sets the direction of dma transfer to be dsp to host and enables the hreq pin to request data transfer. hardware, software, individual, and stop resets clear rreq. 5.3.3.2.2 icr transmit request enable (treq) bit 1 the treq bit is used to control the hreq pin for host transmit data transfers. in interrupt mode (dma off), treq is used to enable interrupt requests via the external hreq pin when the transmit data register empty (txde) status bit in the isr is set. when treq is cleared, txde interrupts are disabled. when treq is set, the external hreq pin will be asserted if txde is set. in dma modes, treq must be set or cleared by software to select the direction of dma trans- fers. setting treq sets the direction of dma transfer to be host to dsp and enables the hreq pin to request data transfer. hardware, software, individual, and stop resets clear treq. table 5-2 summarizes the effect of rreq and treq on the hreq pin. icr cvr isr ivr 0 0 0 0 0 0 0 0 rxh/txh rxm/txm rxl/txl interrupt control command vector interrupt status interrupt vector unused receive/transmit bytes host data bus h0 - h7 $0 $1 $2 $3 $4 $5 $6 $7 host address ha0 - ha2 figure 5-13 hi register map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 23 5.3.3.2.3 icr reserved bit 2 this bit, which is reserved and unused, reads as a logic zero. 5.3.3.2.4 icr host flag 0 (hf0) bit 3 the hf0 bit is used as a general-purpose flag for host-to-dsp communication. hf0 may be set or cleared by the host processor and cannot be changed by the dsp. hf0 is visible in the hsr on the dsp cpu side of the hi (see figure 5-10). hardware, software, individual, and stop resets clear hf0. 5.3.3.2.5 icr host flag 1 (hf1) bit 4 the hf1 bit is used as a general-purpose flag for host-to-dsp communication. hf1 may be set or cleared by the host processor and cannot be changed by the dsp. hardware, software, individual, and stop resets clear hf1. 5.3.3.2.6 icr host mode control (hm1 and hm0 bits) bits 5 and 6 the hm0 and hm1 bits select the transfer mode of the hi (see table 5-3). hm1 and hm0 enable the dma mode of operation or interrupt (non-dma) mode of operation. when both hm1 and hm0 are cleared, the dma mode is disabled, and the treq and rreq control bits are used for host processor interrupt control via the external hreq output pin. also, in the non-dma mode, the hack input pin is used for the mc68000 family vectored interrupt acknowledge input. treq rreq hreq pin interrupt mode 0 0 no interrupts (polling) 0 1 rxdf request (interrupt) 1 0 txde request (interrupt) 1 1 rxdf and txde request (interrupts) dma mode 0 0 no dma 0 1 dsp to host request (rx) 1 0 host to dsp request (tx) 1 1 unde?ed (illegal) table 5-2 hreq pin definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 24 host interface motorola when hm1 or hm0 are set, the dma mode is enabled, and the hreq pin is used to request dma transfers. when the dma mode is enabled, the treq and rreq bits select the direc- tion of dma transfers. the hack input pin is used as a dma transfer acknowledge input. if the dma direction is from dsp to host, the contents of the selected register are enabled onto the host data bus when hack is asserted. if the dma direction is from host to dsp, the selected register is written from the host data bus when hack is asserted. the size of the dma word to be transferred is determined by the dma control bits, hm0 and hm1. the hi register selected during a dma transfer is determined by a 2-bit address counter, which is preloaded with the value in hm1 and hm0. the address counter substitutes for the ha1 and ha0 bits of the hi during a dma transfer. the host address bit (ha2) is forced to one during each dma transfer. the address counter can be initialized with the init bit feature. after each dma transfer on the host data bus, the address counter is incremented to the next register. when the address counter reaches the highest register (rxl or txl), the address counter is not incremented but is loaded with the value in hm1 and hm0. this allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need for the dma controller to supply the ha2, ha1, and ha0 pins. for 16- or 24-bit data transfers, the dsp cpu interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate ?i.e., for every two or three host processor data transfers of one byte each, there is only one 24-bit dsp cpu interrupt. hardware, software, individual, and stop resets clear hm1 and hm0. 5.3.3.2.7 icr initialize bit (init) bit 7 the init bit is used by the host processor to force initialization of the hi hardware. initializa- tion consists of configuring the hi transmit and receive control bits and loading hm1 and hm0 into the internal dma address counter. loading hm1 and hm0 into the dma address counter causes the hi to begin transferring data on a word boundary rather than transferring only part of the first data word. hm1 hm0 mode 0 0 interrupt mode (dma off) 0 1 dma mode (24 bit) 1 0 dma mode (16 bit) 1 1 dma mode (8 bit) table 5-3 host mode bit definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 25 there are two methods of initialization: 1. allowing the dma address counter to be automatically set after transferring a word 2. setting the init bit, which sets the dma address counter. using the init bit to initialize the hi hardware may or may not be necessary, depending on the software design of the interface. the type of initialization done when the init bit is set depends on the state of treq and rreq in the hi. the init command, which is local to the hi, is designed to conveniently configure the hi into the desired data transfer mode. the commands are described in the following paragraphs and in table 5-4. the host sets the init bit, which causes the hi hard- ware to execute the init command. the interface hardware clears the init bit when the command has been executed. hardware, software, individual, and stop resets clear init. init execution always loads the dma address counter and clears the channel according to treq and rreq. init execution is not affected by hm1 and hm0. treq rreq after init execution transfer direction initialized interrupt mode (hm1 = 0, hm0 = 0) init execution 0 0 init = 0; address counter = 00 none 0 1 init = 0; rxdf = 0; htde = 1; address counter = 00 dsp to host 1 0 init = 0; txde = 1; hrdf = 0; address counter = 00 host to dsp 1 1 init = 0; rxdf = 0; htde = 1; txde = 1; hrdf = 0; address counter = 00 host to/from dsp dma mode (hm1 or hm0 = 1) init execution 0 0 init = 0; address counter = hm1, hm0 none 0 1 init = 0; rxdf = 0; htde = 1; address counter = hm1, hm0 dsp to host 1 0 init = 0; txde = 1; hrdf = 0; address counter = hm1, hm0 host to dsp 1 1 unde?ed (illegal) unde?ed table 5-4 hreq pin definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 26 host interface motorola the internal dma counter is incremented with each dma transfer (each hack pulse) until it reaches the last data register (rxl or txl). when the dma transfer is completed, the counter is loaded with the value of the hm1 and hm0 bits. when changing the size of the dma word (changing hm0 and hm1 in the icr), the dma counter is not automatically updated, and, as a result, the dma counter will point to the wrong data register immediately after hm1 and hm0 are changed. the init function must be used to preset the internal dma counter correctly. always set init after changing hm0 and hm1. however, the dma counter can not be initialized in the middle of a dma transfer. even though the init bit is set, the internal dma controller will wait until after completing the data transfer in progress before executing the initialization. 5.3.3.3 command vector register (cvr) the host processor uses the cvr to cause the dsp to execute a vectored interrupt. the host command feature is independent of the data transfer mechanisms in the hi. it can be used to cause any of the 128 possible interrupt routines in the dsp cpu to be executed. the com- mand vector register is shown in figure 5-14. 5.3.3.3.1 cvr host vector (hv) bits 0? the six hv bits select the host command exception address to be used by the host command exception logic. when the host command exception is recognized by the dsp interrupt con- trol logic, the starting address of the exception taken is 2 hv. the host can write hc and hv in the same write cycle, if desired. the host processor can select any of the 128 possible exception routine starting addresses in the dsp by writing the exception routine starting address divided by 2 into hv. this means that the host processor can force any of the existing exception handlers (ssi, sci, irqa, irqb, etc.) and can use any of the reserved or otherwise unused starting addresses provided they have been preprogrammed in the dsp. hv is set to $12 (vector location $0024) by hardware, software, individual, and stop resets. host vector reserved host command hv1 hv0 hv2 hv3 hv4 hv5 * hc 0 7654321 figure 5-14 command vector register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 27 caution the hv should not be used with a value of zero because the reset location is normally programmed with a jmp instruction. doing so will cause an improper fast interrupt. 5.3.3.3.2 cvr reserved bit 6 this bit is unused and read by the host processor as zero. 5.3.3.3.3 cvr host command bit (hc) bit 7 the hc bit is used by the host processor to handshake the execution of host command exceptions. normally, the host processor sets hc=1 to request the host command exception from the dsp. when the host command exception is acknowledged by the dsp, the hc bit is cleared by the hi hardware. the host processor can read the state of hc to determine when the host command has been accepted. the host processor may elect to clear the hc bit, can- celing the host command exception request at any time before it is accepted by the dsp cpu. caution the command exception might be recognized by the dsp and executed before it can be canceled by the host, even if the host clears the hc bit. setting hc causes host command pending (hcp) to be set in the hsr. the host can write hc and hv in the same write cycle if desired. hardware, software, individual, and stop resets clear hc. 5.3.3.4 interrupt status register (isr) the isr is an 8-bit read-only status register used by the host processor to interrogate the status and flags of the hi. the host processor can write this address without affecting the internal state of the hi, which is useful if the user desires to access all of the hi registers by stepping through the hi addresses. the isr can not be accessed by the dsp. the status bits are described in the following paragraphs. 5.3.3.4.1 isr receive data register full (rxdf) bit 0 the rxdf bit indicates that the receive byte registers (rxh, rxm, and rxl) contain data from the dsp cpu and may be read by the host processor. rxdf is set when the htx is transferred to the receive byte registers. rxdf is cleared when the receive data low (rxl) register is read by the host processor. rxl is normally the last byte of the receive byte regis- ters to be read by the host processor. rxdf can be cleared by the host processor using the ini- tialize function. rxdf may be used to assert the external hreq pin if the rreq bit is set. regardless of whether the rxdf interrupt is enabled, rxdf provides valid status so that polling techniques may be used by the host processor. hardware, software, individual, and stop resets clear rxdf. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 28 host interface motorola 5.3.3.4.2 isr transmit data register empty (txde) bit 1 the txde bit indicates that the transmit byte registers (txh, txm, and txl) are empty and can be written by the host processor. txde is set when the transmit byte registers are trans- ferred to the hrx register. txde is cleared when the transmit byte low (txl) register is written by the host processor. txl is normally the last byte of the transmit byte registers to be written by the host processor. txde can be set by the host processor using the initialize feature. txde may be used to assert the external hreq pin if the treq bit is set. regardless of whether the txde interrupt is enabled, txde provides valid status so that polling tech- niques may be used by the host processor. hardware, software, individual, and stop resets set txde. 5.3.3.4.3 isr transmitter ready (trdy) bit 2 the trdy status bit indicates that both the txh,txm,txl and the hrx registers are empty. trdy=txde hrdf when trdy is set to one, the data that the host processor writes to txh,txm, and txl will be immediately transferred to the dsp cpu side of the hi. this has many applications. for example, if the host processor issues a host command which causes the dsp cpu to read the hrx, the host processor can be guaranteed that the data it just transferred to the hi is what is being received by the dsp cpu. hardware, software, individual, and stop resets set trdy. 5.3.3.4.4 isr host flag 2 (hf2) bit 3 the hf2 bit in the isr indicates the state of host flag 2 in the hcr on the cpu side. hf2 can only be changed by the dsp (see figure 5-10). hf2 is cleared by a hardware or software reset. 5.3.3.4.5 isr host flag 3 (hf3) bit 4 the hf3 bit in the isr indicates the state of host flag 3 in the hcr on the cpu side. hf3 can only be changed by the dsp (see figure 5-10). hf3 is cleared by a hardware or software reset. 5.3.3.4.6 isr reserved bit 5 this status bit is reserved for future expansion and will read as zero during host processor read operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 29 5.3.3.4.7 isr dma status (dma) bit 6 the dma status bit indicates that the host processor has enabled the dma mode of the hi (hm1 or hm0=1). when the dma status bit is clear, it indicates that the dma mode is disabled (hm0=hm1=0) and no dma operations are pending. when dma is set, it indi- cates that the dma mode is enabled and the host processor should not use the active dma channel (rxh, rxm, rxl or txh, txm, txl depending on dma direction) to avoid conflicts with the dma data transfers. the channel not in use can be used for polled operation by the host and operates in the interrupt mode for internal dsp exceptions or polling. hardware, software, individual, and stop resets clear the dma status bit. 5.3.3.4.8 isr host request (hreq) bit 7 the hreq bit indicates the status of the external host request output pin (hreq ). when the hreq status bit is cleared, it indicates that the external hreq pin is deasserted and no host processor interrupts or dma transfers are being requested. when the hreq status bit is set, it indicates that the external hreq pin is asserted, indicating that the dsp is inter- rupting the host processor or that a dma transfer request is occurring. the hreq interrupt request may originate from either or both of two sources ?the receive byte registers are full or the transmit byte registers are empty. these conditions are indicated by the isr rxdf and txde status bits, respectively. if the interrupt source has been enabled by the associ- ated request enable bit in the icr, hreq will be set if one or more of the two enabled inter- rupt sources is set. hardware, software, individual, and stop resets clear hreq. 5.3.3.5 interrupt vector register (ivr) the ivr is an 8-bit read/write register which typically contains the exception vector number used with mc68000 family processor vectored interrupts. only the host processor can read and write this register. the contents of ivr are placed on the host data bus (h0?7) when both the hreq and hack pins are asserted and the dma mode is disabled. the contents of this register are initialized to $0f by a hardware or software reset, which corresponds to the uninitialized exception vector in the mc68000 family. 5.3.3.6 receive byte registers (rxh, rxm, rxl) the receive byte registers are viewed as three 8-bit read-only registers by the host pro- cessor. these registers are called receive high (rxh), receive middle (rxm), and receive low (rxl). these three registers receive data from the high byte, middle byte, and low byte, respectively, of the htx register and are selected by three external host address inputs (ha2, ha1, and ha0) during a host processor read operation or by an on-chip address counter in dma operations. the receive byte registers (at least rxl) contain valid data when the receive data register full (rxdf) bit is set. the host pro- cessor may program the rreq bit to assert the external hreq pin when rxdf is set. this informs the host processor or dma controller that the receive byte registers are full. these registers may be read in any order to transfer 8-, 16-, or 24-bit data. how- ever, reading rxl clears the receive data full rxdf bit. because reading rxl clears the rxdf status bit, it is normally the last register read during a 16- or 24-bit data transfer. reset does not affect rxh, rxm, or rxl. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 30 host interface motorola 5.3.3.7 transmit byte registers (txh, txm, txl) the transmit byte registers are viewed as three 8-bit write-only registers by the host processor. these registers are called transmit high (txh), transmit middle (txm), and transmit low (txl). these three registers send data to the high byte, middle byte and low byte, respec- tively, of the hrx register and are selected by three external host address inputs (ha2, ha1, and ha0) during a host processor write operation. data may be written into the transmit byte registers when the transmit data register empty (txde) bit is set. the host processor may pro- gram the treq bit to assert the external hreq pin when txde is set. this informs the host processor or dma controller that the transmit byte registers are empty. these registers may be written in any order to transfer 8-, 16-, or 24-bit data. however, writing txl clears the txde bit. because writing the txl register clears the txde status bit, txl is normally the last register written during a 16- or 24-bit data transfer. the transmit byte registers are transferred as 24-bit data to the hrx register when both txde and the hrdf bit are cleared. this transfer operation sets txde and hrdf. reset does not affect txh, txm, or txl. 5.3.3.8 registers after reset table 5-5 shows the result of four kinds of reset on bits in each of the hi registers seen by the host processor. the hardware reset is caused by asserting the reset pin; the software reset is caused by executing the reset instruction; the individual reset is caused by clearing the pbc register bit 0; and the stop reset is caused by executing the stop instruction. 5.3.4 host interface pins the 15 hi pins are described here for convenience. additional information, including timing, is given in the dsp56003/005 advanced information data sheet . 5.3.4.1 host data bus (h0-h7) this bidirectional data bus transfers data between the host processor and the dsp56003/005. it acts as an input unless hen is asserted and hr/w is high, making h0?7 become outputs and allowing the host processor to read dsp56003/005 data. it is high impedance when hen is deasserted. h0?7 can be programmed as general- purpose i/o pins (pb0?b7) when the host interface is not being used. these pins are configured as gpio input pins during hardware reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 31 5.3.4.2 host address (ha0?a2) these inputs provide the address selection for each host interface register. ha0?a2 can be programmed as general-purpose i/o pins (pb8?b10) when the host interface is not being used. these pins are configured as gpio input pins during hardware reset. register name register data reset type hw reset sw reset ir reset st reset icr init 0000 hm (1 - 0) 0000 treq 0000 rreq 0000 hf (1 - 0) 0000 cvr hc 0000 hv (5 - 0) $12 $12 $12 $12 isr hreq 0000 dma 0000 hf (3 - 2) 0 0 trdy 1111 txde 1111 rxdf 0000 ivr iv (7 - 0) $0f $0f rx rxh (23 - 16) rxm (15 - 8) rxl (7 - 0) tx txh (23 - 21) txm (15 - 8) txl (7 - 0) table 5-5 host registers after reset (host side) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 32 host interface motorola 5.3.4.3 host read/write (hr/w ) this input selects the direction of data transfer for each host processor access. if hr/w is high and hen is asserted, h0-h7 are outputs and dsp data is transferred to the host processor. if hr/w is low and hen is asserted, h0-h7 are inputs and host data is transferred to the dsp. hr/w is stable when hen is asserted. it can be programmed as a general-purpose i/o pin (pb11) when the host interface is not being used, and is configured as a gpio input pin during hardware reset. 5.3.4.4 host enable (hen ) this input enables a data transfer on the host data bus. when hen is asserted and hr/w is high, h0?7 become outputs and the host processor may read dsp56003/005 data. when hen is asserted and hr/w is low, h0?7 become inputs. when hen is deasserted, host data is latched inside the dsp. normally, a chip select signal derived from host address de- coding and an enable clock are used to generate hen . hen can be programmed as a general- purpose i/o pin (pb12) when the host interface is not being used, and is configured as a gpio input pin during hardware reset. 5.3.4.5 host request (hreq ) this open-drain output signal is used by the dsp56003/005 hi to request service from the host processor, dma controller, or a simple external controller. hreq may be connected to an interrupt request pin of a host processor, a transfer request of a dma controller or a control input of external circuitry. hreq is asserted when an enabled request occurs in the host inter- face. hreq is deasserted when the enabled request is cleared or masked, dma hack is asserted, or the dsp is reset. hreq may be programmed as a general purpose i/o pin (not open-drain) called pb13 when the hi is not being used. bc0 bc1 function 0 0 parallel i/o (reset condition) 0 1 host interface 1 0 host interface (ha ck is de?ed as general purpose i/o) 1 1 reserved table 5-6 port b pin definitions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 33 5.3.4.6 host acknowledge (hack ) the port b control register allows the user to program this input independently of the other host interface pins. when the port is defined for general purpose i/o, this input acts as a general purpose i/o pin called pb14. when the port is defined as the host interface, the user may manipulate the port b control register to program this input as either pb14, or as the hack pin. the table below shows the port b control register bit configurations. hack may act as a data strobe for hi dma data transfers (see figure 5-18). or, if hack is used as an mc68000 host interrupt acknowledge, it enables the hi interrupt vector register (ivr) on the host data bus h0-h7 if hreq is asserted (see figure 5-16). in this case, all other hi control pins are ignored and the state of the hi is not affected. note: hack should always be pulled high when it is not in use. 5.3.5 servicing the host interface the hi can be serviced by using one of the following protocols: 1. polling 2. interrupts, which can be either a. non-dma b. dma from the host processor viewpoint, the service consists of making a data transfer since this is the only way to reset the appropriate status bits. ha0 - ha2 hr/w hen h0 - h7 dsp56003/005 ha0 - ha2 hr/w hen h0 - h7 hreq ha ck write read data latched in hi 8 3 +5 v +5 v figure 5-15 host processor transfer timing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 34 host interface motorola 5.3.5.1 hi host processor data transfer the hi looks like static ram to the host processor. accordingly, in order to transfer data with the hi, the host processor: 1. asserts the hi address (ha0, ha1, ha2) to select the register to be read or written 2. asserts hr/w to select the direction of the data transfer 3. strobes the data transfer using hen . when data is being written to the hi by the host processor, the positive-going edge of hen latches the data in the hi register selected. when data is being read by the host processor, the negative-going edge of hen strobes the data onto the data bus h0-h7 figure 5-15 illustrates this process. the specified timing relationships are given in the dsp56003/005 advanced information data sheet . 5.3.5.2 hi interrupts host request (hreq ) the host processor interrupts are external and use the hreq pin. hreq is normally con- nected to the host processor maskable interrupt (ipl0, ipl1 or ipl2 in figure 5-16) input. the host processor acknowledges host interrupts by executing an interrupt service routine. 2. the host processor asserts ha ck with its interrupt acknowledge cycle. 1k 70 dsp56003/005 a1 - a31 fc0 - fc2 as ipl2 ipl1 ipl0 d0 - d7 hreq ha ck h0 - h7 ia ck logic $0f $3 +5 v interrupt vector number interrupt vector register (ivr) (read/write) mc68000 1. the dsp56003/005 aserts hreq to interrupt the host processor. 3. when hreq and ha ck are simultaneously asserted, the contents of the ivr are placed on the host data bus. ia ck interrupt vector register (ivr) figure 5-16 interrupt vector register read timing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 35 the most significant bit (hreq) of the isr may be tested by the host processor to determine if the dsp is the interrupting device and the two least significant bits (rxdf and txde) may be tested to determine the interrupt source (see figure 5-17). the host processor inter- rupt service routine must read or write the appropriate hi register to clear the interrupt. hreq is deasserted when1) the enabled request is cleared or masked, 2) dma hack is asserted, or 3) the dsp is reset. 5.3.5.3 polling in the polling mode of operation, the hreq pin is not connected to the host processor and hack must be deasserted to insure dma data or ivr data is not being output on h0-h7 when other registers are being polled. the host processor first performs a data read transfer to read the isr (see figure 5-17) to deter- mine, whether: 1. rxdf=1, signifying the receive data register is full and therefore a data read should be performed 2. txde=1, signifying the transmit data register is empty so that a data write can be performed 3. trdy=1, signifying the transmit data register is empty and that the receive data register on the dsp cpu side is also empty so that the data written by the host processor will be transferred directly to the dsp side 4. hf2 hf3 0, signifying an application-specific state within the dsp cpu has been reached, which requires action on the part of the host processor 5. dma=1, signifying the hi is currently being used for dma transfers. if dma transfers are possible in the system, deactivate hack prior to reading the isr so both dma data and the contents of isr are not simultaneously output on h0- h7 6. if hreq=1, the hreq pin has been asserted, and one of the previous five conditions exists generally, after the appropriate data transfer has been made, the corresponding status bit will toggle. if the host processor has issued a command to the dsp by writing the cvr and setting the hc bit, it can read the hc bit in the cvr to determine when the command has been accepted by the interrupt controller in the dsp? central processing module. when the command has been accepted for execution, the interrupt controller will reset the hc bit. 5.3.5.4 servicing non-dma interrupts when hm0=hm1=0 (non-dma) and hreq is connected to the host processor interrupt input, the hi can request service from the host processor by asserting hreq. in the non-dma mode, hreq will be asserted when txde=1 and/or rxdf=1 and the corresponding mask bit (treq or rreq, respectively) is set. this is depicted in figure 5-17. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 36 host interface motorola generally, servicing the interrupt starts with reading the isr, as described in the previous sec- tion on polling, to determine which dsp has generated the interrupt and why. when multiple dsps occur in a system, the hreq bit in the isr will normally be read first to determine the interrupting device. the host processor interrupt service routine must read or write the appropriate hi register to clear the interrupt. hreq is deasserted when the enabled request is cleared or masked. in the case where the host processor is a member of the mc680xx family, servicing the interrupt will start by asserting hreq to interrupt the processor (see figure 5-17). the host processor then acknowledges the interrupt by asserting hack . while hreq and hack are simultaneously asserted, the contents of the ivr are placed on the host data bus. this vector will tell the host processor which routine to use to service the hreq interrupt. the hreq pin is an open-drain output pin so that it can be wire-ored with the hreq pins from other dsp56003/005 processors in the system. when the dsp56003/005 generates an interrupt request, the host processor can poll the hreq bit in each of the isrs to determine which device generated the interrupt. 5.3.5.5 servicing dma interrupts when hm0 0 and/or hm1 0, hreq will be asserted to request a dma transfer. generally the hreq pin will be connected to the req input of a dma controller. 70 hreq dma 0 hf3 hf2 trdy txde rxdf status isr init hm1 hm0 hf1 hf0 0 treq rreq 70 $3 $2 icr mask exception source hreq asserted hreq figure 5-17 hi interrupt structure f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 37 the ha0-2, hen , and hr/w pins are not used during dma transfers; dma trans- fers only use the hreq and hack pins after the dma channel has been initialized. hack is used to strobe the data transfer as shown in figure 5-18 where an mc68440 is used as the dma controller. dma transfers to and from the hi are considered in more detail in section 5.3.6 hi application examples . 5.3.6 hi application examples the following paragraphs describe examples of initializing the hi, transferring data with the hi, bootstrapping via the hi, and performing dma transfers through the hi. dma a ck gated off fast interrupt to transfer 24-bit word high byte mc68440 irq a ck0 +5 v dsp56003/005 to irqb +5 v +5 v hreq ha ck req0 ci q d a0 a1 as o wn burst req0 ha ck high byte middle byte low byte 1 dma cycle = 8t = 4 dma clock cycles max. mc68440 clock = 10 mhz = > t = 50 ns figure 5-18 dma transfer logic and timing 8t f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 38 host interface motorola 5.3.6.1 hi initialization initializing the hi takes two steps (see figure 5-19). the first step is to initialize the dsp side of the hi, which requires that the options for interrupts and flags be selected and then the hi be selected (see figure 5-20). the second step is for the host processor to clear the hc bit by writing the cvr, select the data transfer method - polling, interrupts, or dma (see figure 5-21 (d) and figure 5-23), and write the ivr in the case of a mc680xx family host processor. figure 5-19 through figure 5-22 provide a general description of how to initialize the hi. later paragraphs in this section provide more detailed descriptions for specific examples. these subsections include some code fragments illustrating how to initialize and transfer data using the hi. 5.3.6.2 polling/interrupt controlled data transfer handshake flags are provided for polled or interrupt-driven data transfers. because the dsp interrupt response is sufficiently fast, most host microprocessors can load or store data at their maximum programmed i/o (non-dma) instruction rate without testing the handshake flags for each transfer. if the full handshake is not needed, the host processor can treat the dsp as fast memory, and data can be transferred between the host and dsp at the fastest host proces- sor rate. dma hardware may be used with the external host request and host acknowledge pins to transfer data at the maximum dsp interrupt rate. the basic data transfer process from the host processor? view (see figure 5-15) is for the host to: 1. assert hreq when the hi is ready to transfer data 2. assert hack if the interface is using hack 3. assert hr/w to select whether this operation will read or write a register 4. assert the hi address (ha2, ha1, and ha0) to select the register to be read or written 5. assert hen to enable the hi 6. when hen is deasserted, the data can be latched or read as appropriate if the timing requirements have been observed 7. hreq will be deasserted if the operation is complete step 1 the dsp cpu initializes the dsp side of the hi by writing: 1) hcr at x:$ffe8 and 2) pbc at x:$ffe0 step 2 the host procesor initializes the host side of the hi by writing: 1) icr at $0 and/or 2) cvr at $1 and/or 3) ivr at $3 figure 5-19 hi initialization flowchart f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 39 the previous transfer description is an overview. specific and exact information for the hi data transfers and their timing can be found in section 5.3.6.3 dma data transfer and in the dsp56003/005 data sheet . step 1 of host port configuration 1. enable/disable host receive data full interrupt enable interrupt: bit 0 = 1 disable interrupt: bit 0 = 0 2 , enable/disable host transmit data empty interrupt enable interrupt: bit 1 = 1 disable interrupt: bit 1 = 0 3. enable/disable host command pending interrupt enable interrupt: bit 2 = 1 disable interrupt: bit 2 = 0 4. set/clear host flag 2 (optional) enable flag: bit 3 = 1 disable flag: bit 3 = 0 5 . set/clear host flag 3 (optional) enable flag: bit 4 = 1 disable flag: bit 4 = 0 x:$ffe8 hf3 hf2 hcie htie hrie 765 43210 host control register (hcr) (read/write) 6 . select port b for host port operation: ************** bc 0 x:$ffe0 15 0 * reserved; write as zero. note: the host ?gs are general-purpose semaphores. they are not required for host port operation but may be used in some applications. *** figure 5-20 hi initialization ?dsp side bc 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 40 host interface motorola 5.3.6.2.1 host to dsp ?data transfer figure 5-23 shows the bits in the isr and icr registers used by the host processor and the bits in the hsr and hcr registers used by the dsp to transfer data from the host processor to the dsp. the registers shown are the status register and control register as they are seen by the host processor, and the status register and control register as they are seen by the dsp. only the registers used to transmit data from the host processor to the dsp are described. figure 5-24 illustrates the process of that data transfer. the steps in figure 5-24 can be summarized as follows: step 2 of host port configuration 1. clear host command bit (hc): bit 7 = 0 $1 765 0 hc hv 2. option 1: select host vector (hv) (optional since hv can be set any time before the host command is executed. dsp interrupt vector = the host vector multiplied by 2. default (upon dsp reset): hv = $12 t dsp interrupt vector $0024 * * reserved; write as zero. command vector register (cvr) (read/write) figure 5-21 (a) hi configuration ?host side init hm1 hm0 hf1 hf0 treq rreq $0 * reserved; write as zero. step 2 of host port configuration 2. option 2: select polling mode for host to dsp communication 76543210 initialize dsp and host port dma off bit 5 = 0 bit 6 = 0 optional disable interrupts bit 0 = 0 bit 1 = 0 interrupt control register (icr) (read/write) * figure 5-21 (b) hi initialization ?host side, polling mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 41 1. when the txde bit in the isr is set, it indicates that the hi is ready to receive a data byte from the host processor because the transmit byte registers (txh, txm, txl) are empty. 2. the host processor can poll as shown in this step. 3. alternatively, the host processor can use interrupts to determine the status of this bit. setting the treq bit in the icr causes the hreq pin to interrupt the host processor when txde is set. 4. once the txde bit is set, the host can write data to the hi. it does this by writ- ing three bytes to txh, txm, and txl, respectively, or two bytes to txm and txl, respectively, or one byte to txl. 5. writing data to txl clears txde in the isr. 6. from the dsp? viewpoint, the hrdf bit (when set) in the hsr indicates that data is waiting in the hi for the dsp. 7. when the dsp reads the hrx, the hrdf bit is automatically cleared and txde in the isr is set. init hm1 hm0 hf1 hf0 treq rreq $0 *reserved; write as zero. 76543210 initialize dsp initialize hi** bit 7 = 1 optional interrupt control register (icr) (read/write) dma off bit 5 = 0 bit 6 = 0 step 2 of host port configuration 2. option 3: select interrupt mode for enable receive data full interrupt bit 0 = 1 bit 1 = 0 enable transmit data empty interrupt bit 0 = 0 bit 1 = 1 dsp to host or host to dsp or dsp to host and host to dsp iv7 iv6 iv5 iv4 iv3 iv2 iv1 iv0 $3 76543210 interrupt vector register (ivr) (read/write) 2. option 4: load host interrupt vector if using the interrupt mode and the host processor requires an interrupt vector. **see figure 10 - 23. enable receive data full interrupt and transmit data empty interrupt bit 0 = 1 bit 1 = 1 * figure 5-21 (c) hi initialization ?host side, interrupt mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 42 host interface motorola 8. when txde=0 and hrdf=0, data is automatically transferred from tbr to hrx which sets hrdf. 9. the dsp can poll hrdf to see when data has arrived, or it can use interrupts. 10. if hrie (in the hcr) and hrdf are set, exception processing is started using interrupt vector p:$0020. the main program initializes the hi and then hangs in a wait loop while it allows inter- rupts to transfer data from the host processor to the dsp. the first three movep instructions enable the hi and configure the interrupts. the following move enables the interrupts (this should always be done after the interrupt programs and hardware are completely initialized) and prepares the dsp cpu to look for the host flag, hf0=1. the jclr instruction is a polling loop that looks for hf0=1, which indicates that the host processor is ready. when the host pro- cessor is ready to transfer data to the dsp, the dsp enables hrie in the hcr, which allows the interrupt routine to receive data from the host processor. the jump-to-self instruction that follows is for test purposes only, it can be replaced by any other code in normal operation. 16-bit dma bit 5 = 0 bit 6 = 1 init hm1 hm0 hf1 hf0 treq rreq $0 *reserved; write as zero. 76543210 initialize dsp initialize hi** bit 7 = 1 optional interrupt control register (icr) (read/write) dma off bit 5 = 1 bit 6 = 1 step 2 of host port configuration 2. option 5: select dma mode for enable receive data full interrupt bit 0 = 1 bit 1 = 0 enable transmit data empty interrupt bit 0 = 0 bit 1 = 1 dsp to host or host to dsp **see figure 5-23. 24-bit dma bit 5 = 1 bit 6 = 0 * or or figure 5-21 (d) hi initialization ?host side, dma mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 43 the receive routine in figure 5-26 was implemented as a long interrupt (the instruction at the interrupt vector location, which is not shown, is a jsr). since there is only one instruction, this could have been implemented as a fast interrupt. the movep instruction moves data from the hi to a buffer area in memory and increments the buffer pointer so that the next word received will be put in the next sequential location. 5.3.6.2.2 host to dsp ?command vector the host processor can cause three types of interrupts in the dsp (see figure 5-27). these are host receive data (p:$0020), host transmit data (p:$0022), and host command (p:$0024 - p:$007e). the host command (hc) can be used to control the dsp by forcing it to execute any of 45 subroutines that can be used to run tests, transfer data, process data, etc. in addi- tion, the hc can cause any of the other 19 interrupt routines in the dsp to be executed. treq rreq init execution 0 0 init = 0; address counter = 00 0 1 init = 0; rxdf = 0; htde = 1; address counter = 00 1 0 init = 0; txde = 1; hrdf = 0; address counter = 00 init hm1 hm0 hf1 hf0 0 treq rreq host sets init bit 70 interrupt control register (icr) (read/write) modes 0 0 interrupt mode (dma off) 0 1 24 bit dma mode 1 0 16 bit dma mode 1 1 8 bit dma mode reset condition interrupt mode (dma off) treq rreq init execution 0 0 init = 0; address counter = hm1, hm0 0 1 init = 0; rxdf = 0; htde = 1; address counter = hm1, hm0 1 0 init = 0; txde = 1; hrdf = 0; address counter = hm1, hm0 1 1 unde?ed (illegal) dma mode init is used by the host to force initialization of the hi hardware. the hi hardware automatically clears init when the command is executed. init is cleared by dsp reset. figure 5-22 host mode and init bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 44 host interface motorola the process to execute a hc (see figure 5-28) is as follows: 0 0 interrupt mode (dma off) 0 1 24 bit dma mode 1 0 16 bit dma mode 1 1 8 bit dma mode hreq dma 0 hf3 hf2 trdy txde rxdf $2 70 interrupt status register (isr) (read only) init hm1 hm0 hf1 hf0 0 treq rreq $0 70 modes host dsp56003/005 txde ?transmit data register empty 1 = indicates the transmit byte registers (txh, txm, txl) are empty. 0 = cleared by writing to txl; txde can be used to assert the hreq pin. trdy ?transmitter ready = txde ?hrdf 1 = both the transmit byte registers and the host receive data registers are empty. 0 = one or both registers are full. dma 0 0 hf1 hf0 hcp htde hrdf x:$ffe9 70 host status register (hsr) (read only) hrdf ?host receive data full 1 = the host receive register (hrx) contains data from the host processor. 0 = hrx is empty. dma ?ndicates the host processor has enabled the dma mode 1 = dma on. 0 = host mode. 0 0 0 hf3 hf2 hcie htie hrie 70 host control register (hcr) (read/write) hrie ?host receive interrupt enable enables interrupt at p:$0020 dsp interrupt is caused by hrdf = 1 1 = interrupt p:$0020 enabled. 0 = interrupt p:$0020 disabled. treq ?transmit request enable used to enable interrupts that come from txde to the host via the hreq pin. 1 = txde interrupts pass to hreq . 0 = txde interrupts are masked. figure 5-23 bits used for host-to-dsp transfer interrupt control register (icr) (read/write) x:$ffe8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 45 transfer hreq dma 0 hf3 hf2 trdy 1 rxdf $2 70 interrupt status register (isr) init 0 0 hf1 hf0 0 1 rreq $0 70 view from host view from dsp56003/005 1. when txde = 1, tdr is empty. 0 0 0 hf1 hf0 hcp htde 0 x:$ffe9 70 host status register (hsr) 0 0 0 hf3 hf2 hcie htie 1 x:$ffe8 70 host control register (hcr) txde transmit data register empty interrupt control register (icr) 2. host may poll txde. treq transmit request enable hm1 hm0 3. if treq = 1, then hreq pin is asserted to interrupt host. hreq pin 4. host writes data to transmit byte registers. 5. write to txl clears txde in isr. 6. if dsp56003/0052 has old data in hrx, then hrdf = 1. txh txm txl 70 $5 $6 last write $7 transmit byte registers (tbr) 7. when dsp56003/005 reads hrx, then hrdf = 0. 8. when txde = 0 and hrdf = 0, then transfer occurs. hrdf host receive data full dma high byte middle byte low byte x:$ffeb 23 0 host receive data register (hrx) 9. the transfer sets hrdf for the dsp56003/005 to poll. 10. if hrdf = 1 and interrupts are enabled, then exception processing begins. hrie host receive interrupt enable p:$0020 host receive data vector fast interrupt or long interrupt figure 5-24 data transfer from host to dsp f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 46 host interface motorola program memory space exception source exception starting address $0000 hardware reset $0002 stack error $0004 trace $0006 swi (software interrupt) $0008 irqa external hardware interrupt $000a irqb external hardware interrupt $000c ssi receive data $000e ssi receive data with exception status $0010 ssi transmit data $0012 ssi transmit data with exception status $0014 sci receive data $0016 sci receive data with exception status $0018 sci transmit data $001a sci idle line $001c sci timer $001e nmi /watchdog timer $0020 host receive data $0022 host transmit data $0024 host command (default) $0026 available for host command $0028 available for host command $002a available for host command $002c irqc $002e irqd $0030 pwma0 interrupt $0032 pwma1 interrupt $0034 pwma2 interrupt $0036 pwmb0 interrupt $0038 pwmb1 interrupt $003a pwm error $003c timer/event counter interrupt $003e illegal instruction $0040 available for host command $007e available for host command internal interrupts serial communications interface synchronous serial interface internal interrupts external interrupts internal interrupts two words per vector figure 5-27 hi exception vector locations external interrupts internal/external interrupts external interrupts internal interrupts watchdog timer host interface pulse width modulators interface timer/event counter interface host interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 47 $12 ?default 0 host vector (hv) 50 command vector register (cvr) view fr o m h o st view fr o m dsp56003 / 005 t h desired hv . dma 0 0 hf1 hf0 1 htde hrdf x:$ffe9 70 host status register (hsr) 0 0 0 hf3 hf2 1 htie hrie x:$ffe8 70 host control register (hcr) m and 3. hcp is set until exception is acknowledged. 4. host command is masked until hcie = 1. s t command exception is a cknowledged, the hc d by the host command logic. hc can be read as hcp host command pending exception vector table hcie host command interrupt enable p:$007e fast interrupt or long interrupt 0 host vector (hv) command vector register (cvr) h c ?host command (st atus) p:$0000 host command default vector p:$0024 available for host command exception vector address = hv x 2 50 available for host command p:$0026 p:$002a p:$0040 available for host command available for host command figure 5-28 host command f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 48 host interface motorola 1. the host processor writes the cvr with the desired hv (the hv is the dsp? interrupt vector (iv) location divided by two - i.e. if hv=$12, iv=$24). 2. the hc is then set. 3. the hcp bit in the hsr is set when hc is set. 4. if the hcie bit in the hcr has been set by the dsp, the hc exception processing will start. the hv is multiplied by 2 and the result is used by the dsp as the inter- rupt vector. 5. when the hc exception is acknowledged, the hc bit (and therefore the hcp bit) is cleared by the hc logic. hc can be read by the host processor as a status bit to determine when the command is accepted. similarly, the hcp bit can be read by the dsp cpu to determine if an hc is pending. to guarantee a stable interrupt vector, write hv only when hc is clear. the hc bit and hv can be written simultaneously. the host processor can clear the hc bit to cancel a host command at any time before the dsp exception is accepted. although the hv can be programmed to any exception vector, it is not recommended that hv=0 (reset) be used because it does not reset the dsp hardware. dma must be disabled to use the host exception. ; **************************************** ; main program... receive data from host ;**************************************** org p:$40 move #0,r0 move #3,m0 movep #1,x:pbc ;turn on host port movep #0,x:hcr ;turn off xmt and rcv interrupts movep #$0c00,x:ipr ;turn on host interrupt move #0,sr ;unmask interrupts jclr #3,x:hsr,* ;wait for hf0 (from host) set to 1 movep #$1,x:hgr ;enable host receive interrupt jmp * ;now wait for interrupt figure 5-25 receive data from host ?main program ; ************************************ ; receive from host interrupt routine ;************************************ rcv movep x:hrx,x:(r0)+;receive data. rti end figure 5-26 receive data from host interrupt routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 49 init hm1 hm0 hf1 hf0 0 treq rreq 70 host $0 interrupt control register (icr) (read/write) setting hf0 terminates bootstrap loading and starts execution at location p:$0000. host address contents loaded written to internal p: ram at: 4 (dummy) 5 p:$0000 high byte 6 p:$0000 mid byte 7 p:$0000 low byte 4 (dummy) 5 p:$01ff high byte 6 p:$01ff mid byte 7 p:$01ff low byte set hf0 for early termination * because the dsp56003/005 is so fast, host handshaking is generally not required. figure 5-29 bootstrap using the hi dsp56003/005 hr/w hen h0-h7 f32 f32 f32 f32 ls09 address decode 1k +5 v ha0-ha2 lds as dtack a1-a3 d0-d7 r/w a4-a23 8 3 mc68000 (12.5mhz) moda/irqa reset modb/irqb mdb301 * +5 v from open collector buffer from reset function from open collector buffer br hack modc/nmi wt dr notes: 1. * this diode must be a schottky diode. 2. all resistors are 15k w unless noted otherwise. 3. when in reset, irqa , irqb and nmi must be deasserted by external peripherals. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 50 host interface motorola 5.3.6.2.3 host to dsp ?bootstrap loading using the hi the circuit shown in figure 5-29 will cause the dsp to boot through the hi on power up. during the bootstrap program, the dsp looks at the modc, modb, and moda bits. if the bits are set at 101 respectively, the dsp will load from the hi. data is written by the host processor in a pattern of four bytes, with the high byte being a dummy and the low byte being the low byte of the dsp word (see figure 5-29 and figure 5-30). figure 5-30 shows how an 8-,16-, 24-, or 32-bit word in the host processor maps into the hi registers. the hi register at address $4 is not used and will read as zero. it is not necessary to use address $4, but since many host processors are 16- or 32-bit processors, address $4 will often be used as part of the 16- or 32-bit word. the low order byte (at $7) should always be written last since writing to it causes the hi to initiate the transfer of the word to the hrx. data is then transferred from the hrx to the dsp program memory. if the host processor needs to terminate the bootstrap loading before 4608 words have been down loaded, it can set the hf0 bit in the icr. the dsp will then terminate the down load and start exe- cuting at location p:$0000. since the dsp56003/005 is typically faster than the host proces- sor, hand shaking during the data transfer is normally not required. host data high middle low read - 00000000 write - xxxxxxxx host transmit/receive byte registers 70 host byte address 4 5 6 7 0 0 0 0 0 0 0 0 txh/rxh high byte txm/rxm middle byte txl/rxl low byte 31 24 23 16 15 8 7 0 8-bit transfer 16-bit transfer 24-bit transfer 32-bit transfer, ls 24 bits are significant access to low byte initiates transfer note: access low byte last figure 5-30 transmit/receive byte registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 51 the actual code used in the bootstrap program is given in appendix a . the portion of the code that loads from the hi is shown in figure 5-31. the bset instruction configures port b as the hi and the first jclr looks for a flag (hf0) to indicate an early termination of the down- load. the second jclr instruction causes the dsp to wait for a complete word to be received and then a movep moves the data from the hi to memory. 5.3.6.2.4 dsp to host data transfer data is transferred from the dsp to the host processor in a similar manner as from the host processor to the dsp. figure 5-32 shows the bits in the status registers (isr and hsr) and control registers (icr and hcr) used by the host processor and dsp cpu, respectively. the dsp cpu (see figure 5-33) can poll the htde bit in the hsr (1) to see when it can send data to the host, or it can use interrupts enabled by the htie bit in the hcr (2). if htie=1 and interrupts are enabled, exception processing begins at interrupt vector p:$0022 (3). the interrupt routine should write data to the htx (4), which will clear htde in the hsr. from the host? viewpoint, (5) reading the rxl clears rxdf in the isr. when rxdf=0 and htde=0 (6) the contents of the htx will be transferred to the receive byte registers (rxh:rxm:rxl). this transfer sets rxdf in the isr (7), which the host processor can poll to see if data is available or, if the rreq bit in the icr is set, the hi will interrupt the host processor with hreq (8). the code shown in figure 5-34 is essentially the same as the main program in figure 5-25 except that, since this code will transmit instead of receive data, the htie bit is set in the hcr instead of the hrie bit. ; this is the routine that loads from the host interface. ; mc:mb:ma=100 - reserved ; mc:mb:ma=101 - host hostld bset #0,x:pbc ; configure port b as host do b1,_loop3 ; load p_size instruction words _lbla jclr #3,x:hsr,_lblb ; if hf0=1, stop loading data. enddo ; must terminate the do loop jmp <_loop3 _lblb jclr #0,x:hsr,_lbla ; wait for hrdf to go high ;(meaning data is present). movep x:hrx,p:(r0)+ ; store 24-bit data in p memory _loop3 ; and go get another 24-bit word. ; finish bootstrap finish move #<0,r1 figure 5-31 bootstrap code fragment f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 52 host interface motorola host dsp56003/005 rxdf ? receive data register full 1 = indicates the recieve byte registers (rxh, rxm, rxl) contain data from the dsp. 0 = cleared by reading rxl. dma 0 0 hf1 hf0 hcp htde hrdf x:$ffe9 70 host status register (hsr) (read only) htde ?host transmit data empty 1 = htx is empty and can be written by dsp. 0 = htx is full. 0 0 0 hf3 hf2 hcie htie hrie x:$ffe8 70 host control register (hcr) (read/write) htie ?host transmit interrupt enable 1 = enable the dsp interrupt to p:$0022. 0 = disable the dsp interrupt to p:$0022. dsp interrupt is caused by htde = 1 init hm1 hm0 hf1 hf0 0 treq rreq $0 70 modes rreq ?eceive request enable (used to control the hreq pin) 1 = enable interrupt requests created by rxdf. 0 = disable interrupt requests. interrupt control register (hcr) (read/write) hreq dma 0 hf3 hf2 trdy txde rxdf $2 70 interrupt status register (isr) (read only) figure 5-32 bits used for dsp to host transfer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 53 view from host dma 0 0 hf1 hf0 hcp 1 hrdf x:$ffe9 70 host status register (hsr) 0 0 0 hf3 hf2 hcie 1 hrie x:$ffe8 70 host control register (hcr) 1. when htde = 1, then htx is empty. 2. dsp56003/005 may poll htde. 7. the transfer sets rxdf for the host to poll. htde host transmit data empty htie host transmit interrupt enable fast interrupt or long interrupt host transmit data vector p:$0022 5. read of rxl by host clears rxdf in isr. 6. when rxdf = 0 and htde = 0, then transfer occurs. rxh rxm rxl 70 $5 $6 last read $7 receive byte registers (rbr) hreq dma 0 hf3 hf2 trdy txde 1 $2 70 interrupt status register (isr) rxdf receive data full init hm1 hm0 hf1 hf0 0 treq 1 $0 70 interrupt control register (icr) rreq receive request enable 8. if rreq = 1, then hreq pin is asserted to interrupt host. hreq pin view from host 3. if htie = 1, and interrupts are enabled, then exception processing begins. 4. dsp56003/005 writes data to htx, which clears htde in hsr. high byte middle byte low byte x:$ffeb 23 0 host receive data register (hsr) figure 5-33 data transfer from dsp to host f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 54 host interface motorola the transmit routine used by the code in figure 5-34 is shown in figure 5-35. the interrupt vector contains a jsr, which makes it a long interrupt. the code sends a fixed test pattern ($123456) and then resets the hi for the next interrupt. ;**************************************** ; main program... transmit 24-bit data to host ;**************************************** org p:$40 movep #1,x:pbc ;turn on host port movep #$0c00,x:ipr ;turn on host interrupt movep #0,x:hcr ;turn off xmt and rcv interrupts move #0,sr ;unmask interrupts jclr #3,x:hsr,* ;wait for hf0 (from host) set to 1 and x0,a jeq loop movep #$2,x:hcr ;enable host transmit interrupt jmp * ;now wait for interrupt figure 5-34 main program ?transmit 24-bit data to host ; *********************************** ;transmit to host interrupt routine ;************************************ xmt movep #$123456,x:htx;test value to transmit movep #0,x:hcr;turn off xmt interrupt rti end figure 5-35 transmit to hi routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 55 5.3.6.3 dma data transfer the dma mode allows the transfer of 8-, 16- or 24-bit data through the dsp hi under the con- trol of an external dma controller. the hi provides the pipeline data registers and the synchronization logic between the two asynchronous processor systems. the dsp host excep- tions provide cycle-stealing data transfers with the dsp internal or external memory. this technique allows the dsp memory address to be generated using any of the dsp addressing modes and modifiers. queues and circular sample buffers are easily created for dma transfer regions. the host exceptions can be programmed as high priority fast or long exception ser- vice routines. the external dma controller provides the transfers between the dsp hi registers and the external dma memory. the external dma controller must provide the address to the external dma memory; however, the address of the selected hi register is pro- vided by a dma address counter in the hi. dma transfers can only be in one direction at a time; however, the host processor can access any of the registers not in use during the dma transfer by deasserting hack and using hen and ha0-ha2 to transfer data. the host can therefore transfer data in the other direction dur- ing the dma operation using polling techniques. +5 v dma controller transfer req uest transfer a ckno wledge dsp56003/005 host interface hreq ha ck internal address counter h0 - h7 1k memory r/w control address data characteristics of host dma mode the hreq pin is not available for host processor interrupts. treq and rreq select the direction of dma transfer. dma to dsp56003/005 dsp56003/005 to dma simultaneous bidirectional dma transfers are not permitted. host processor software polled transfers are permitted in the opposite direction of the dma transfer. 8-, 16-, or 24-bit transfers are supported. 16-, or 24-bit transfers reduce the dsp interrupt rate by a factor of 2 or 3, respectively. figure 5-36 hi hardware ?dma mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 56 host interface motorola 5.3.6.3.1 host to dsp internal processing the following procedure outlines the steps that the hi hardware takes to transfer dma data from the host data bus to dsp memory (see figure 5-36 and figure 5-37). 1. hi asserts the hreq pin when txde=1. 2. dma controller enables data on h0-h7 and asserts hack . 3. when hack is asserted, the hi deasserts hreq . 4. when the dma controller deasserts hack , the data on h0-h7 is latched into the txh, txm, txl registers. 5. if the byte register written was not txl (i.e., not $7) the dma address counter internal to the hi increments and hreq is again asserted. steps 2-5 are then repeated. 6. if txl ($7) was written, txde will be set to zero and the address counter in the hi will be loaded with the contents of hm1 and hm0. when txde=0, the contents of txh:txm:txl are transferred to hrx provided hrdf=0. after the transfer to hrx, txde will be set to one, and hreq will be asserted to start the transfer of another word from external memory to the hi. 7. when the transfer to hrx occurs within the hi, hrdf is set to one. assuming hrie=1, a host receive exception will be generated. the exception routine must read the hrx to clear hrdf. xfereq xfera ck dma controller hreq ha ck dsp56003/005 24-bit transfer (internal counter) 16-bit transfer (internal counter) 8-bit transfer (internal counter) h (01) m (10) m (10) m (10) m (10) m (10) h (01) l (11) l (11) l (11) l (11) l (11) l (11) l (11) l (11) l (11) l (11) l (11) host receive interrupt fast interrupt routine p:$0020 move x:$ffe8,a read hrx p:$0021 move a, y:(r7)+ ;and put into y memory figure 5-37 dma transfer and host interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 57 write icr host processor 1 0 1 hf1 hf0 0 1 0 $0 70 interrupt control register (icr) x:$ffe8 host control register (hcr) 4. assert hreq to start dma transfer. fast interrupt or long interrupt host receive data vector p:$0020 1. program dma controller. start address byte count transfer direction start dma channel txh txm txl txh txm txl txh txm txl 01 10 11 01 10 11 01 10 11 dsp56003/005 dma controller 2. initialize dsp56003/005 host inter- face. mode 24 bit dma host to dsp use init bit to: set txde clear hrdf 3. tell dsp56003/005 where to store data (i.e., program address register r7). enable interrupt hrie (can be done with a host command). 5. host is free to perform other tasks (i.e., dsp to host transfer on a polled basis). 8. terminate dma channel. 9. terminate dsp dma mode by clearing hm1, hm0, and treq. 6. dma controller performs writes. 7. dma controller interrupts host when transfers are done. init hm1 hm0 treq rreq 0 0 0 hf3 hf2 hcie htie 1 70 hrie hreq pin figure 5-38 host-to-dsp dma procedure f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 58 host interface motorola note: the transfer of data from the txh, txm, txl registers to the hrx register auto- matically loads the dma address counter from the hm1 and hm0 bits in the dma host to dsp mode. this dma address is used with the hi to place the re- ceived byte in the correct register (txh, txm, or txl) . figure 5-37 shows the differences between 24-, 16-, and 8-bit dma data transfers. the inter- rupt rate is three times faster for 8-bit data transfers than for 24-bit transfers. txl is always loaded last. 5.3.6.3.2 host to dsp dma procedure the following procedure outlines the typical steps that the host processor must take to setup and terminate a host-to-dsp dma transfer (see figure 5-38). hreq dma 0 hf3 hf2 trdy txde rxdf $2 70 interrupt status register (isr) (read only) 0 0 interrupt mode (dma off) 0 1 24 bit dma mode 1 0 16 bit dma mode 1 1 8 bit dma mode init hm1 hm0 hf1 hf0 0 treq rreq $0 70 modes dma 0 0 hf1 hf0 hcp htde hrdf x:$ffe9 70 host status register (hsr) (read only) treq rreq hreq pin 0 0 no interrupts (polling) 0 1 rxdf request (interrupt) 1 0 xde request (interrupt) 1 1 xdf and txde request (interrupts) interrupt control register (icr) (read/write) treq rreq hreq pin 0 0 no dma 0 1 dsp to host request (rx) 1 0 host to dsp request (tx) 1 1 unde?ed (illegal) interrupt mode (dma off) dma mode figure 5-39 host bits with treq and rreq reset condition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 59 1. set up the external dma controller (1) source address, byte count, direction, and other control registers. enable the dma controller channel. 2. initialize the hi (2) by writing the icr to select the word size (hm0 and hm1), to select the direction (treq=1, rreq=0), and to initialize the channel setting init=1 (see figure 5-39). 3. initialize the dsp? destination pointer (3) used in the dma exception handler (an address register, for example) and set hrie to enable the hrdf interrupt to the dsp cpu. this procedure can be done with a separate host command exception routine in the dsp. hreq will be asserted (4) immediately by the hi to begin the dma transfer. 4. perform other tasks (5) while the dma controller transfers data (6) until inter- rupted by the dma controller dma transfer complete interrupt (7). the dsp interrupt control register (icr), the interrupt status register (isr), and rxh, rxm, and rxl registers may be accessed at any time by the host processor but the txh, txm and txl registers may not be accessed until the dma mode is disabled. 5. terminate the dma controller channel (8) to disable dma transfers. 6. terminate the dsp hi dma mode (9) in the icr by clearing the hm1 and hm0 bits and clearing treq. the hreq will be active immediately after initialization is completed (depending on hard- ware) because the data direction is host to dsp and txh, txm, and txl registers are empty. when the host writes data to txh, txm, and txl, this data will be immediately transferred to hrx. if the dsp is due to work in interrupt mode, hrie must be enabled. 5.3.6.3.3 dsp to host internal processing the following procedure outlines the steps that the hi hardware takes to transfer dma data from dsp memory to the host data bus. 1. on the dsp side of the hi, a host transmit exception will be generated when htde=1 and htie=1. the exception routine must write htx, thereby setting htde=0. 2. if rxdf=0 and htde=0, the contents of htx will be automatically transferred to rxh:rxm:rxl, thereby setting rxdf=1 and htde=1. since htde=1 again on the initial transfer, a second host transmit exception will be generated imme- diately, and htx will be written, which will clear htde again. 3. when rxdf is set to one, the hi? internal dma address counter is loaded (from hm1 and hm0) and hreq is asserted. 4. the dma controller enables the data from the appropriate byte register onto h0-h7 by asserting hack . when hack is asserted, hreq is deasserted by the hi. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 60 host interface motorola 5. the dma controller latches the data presented on h0-h7 and deasserts hack . if the byte register read was not rxl (i.e., not $7), the hi? internal dma counter increments, and hreq is again asserted. steps 3, 4, and 5 are repeated until rxl is read. 6. if rxl was read, rxdf will be set to zero and, since htde=0, the contents of htx will be automatically transferred to rxh:rxm:rxl, and rxfd will be set to one. steps 3, 4, and 5 are repeated until rxl is read again. note: the transfer of data from the htx register to the rxh:rxm:rxl registers auto- matically loads the dma address counter from the hm1 and hm0 bits when in the dma dsp?ost mode. this dma address is used within the hi to place the ap- propriate byte on h0-h7. 5.3.6.3.4 dsp to host dma procedure the following procedure outlines the typical steps that the host processor must take to setup and terminate a dsp-to-host dma transfer (see figure 5-40). 1. set up the dma controller (1) destination address, byte count, direction, and other control registers. enable the dma controller channel. 2. initialize the hi (2) by writing the icr to select the word size (hm0 and hm1), the direction (treq=0, rreq=1), and setting init=1 (see figure 5-40 for additional information on these bits). 3. initialize the dsp? source pointer (3) used in the dma exception handler (an address register, for example), and set htie to enable the dsp host transmit interrupt. this could be done by the host processor with a host command exception routine. the dsp host transmit exception will be activated immediately after htie is set. the dsp cpu will move data to htx. the hi circuitry will transfer the contents of htx to rxh:rxm:rxl, setting rxdf which asserts hreq . asserting hreq (4) starts the dma transfer from rxh, rxm, and rxl to the host processor. 4. perform other tasks (5) while the dma controller transfers data (6) until inter- rupted by the dma controller dma complete interrupt (7). the dsp interrupt control register (icr), the interrupt status register (isr), and txh, txm, and txl may be accessed at any time by the host processor but the rxh, rxm and rxl registers may not be accessed until the dma mode is disabled. 5. terminate the dma controller channel (8) to disable dma transfers. 6. terminate the dsp hi dma mode (9) in the interrupt control register (icr) by clearing the hm1 and hm0 bits and clearing rreq. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 61 write icr host processor x:$ffe8 host control register (hcr) p:$007e fast interrupt or long interrupt p:$0000 host transmit data vector p:$0022 1. program dma controller. start address byte count transfer direction start dma channel rxh rxm rxl rxh rxm rxl rxh rxm rxl 01 10 11 01 10 11 01 10 11 dsp56003/005 dma controller 5. host is free to perform other tasks (i.e., dsp to host transfer on a polled basis). 8. terminate dma channel. 9. terminate dsp dma mode by clearing hm1, hm0, and treq. 7. dma controller interrupts host when transfers are done. 0 0 0 hf3 hf2 hcie 1 htie 70 hrie hreq 6. dma controller performs reads. 1 0 1 hf1 hf0 0 0 1 $0 70 interrupt control register (icr) init hm1 hm0 treq rreq 4. assert hreq to start dma transfer. 3. tell dsp56003/005. source pointer address enable htie (can be done with a host command). figure 5-40 dsp to host dma procedure 2. initialize dsp56003/005 host interface. mode 24 bit dma host to dsp use init bit to: clear txde set hrdf load dma counter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 62 host interface motorola 5.3.6.4 example circuits figure 5-41, figure 5-42, and figure 5-43 illustrate the simplicity of the hi. the mc68hc11 in figure 5-42 has a multiplexed address and data bus which requires that the address be latched. although the hack is not used in this circuit, it is pulled up. all unused input pins should be terminated to prevent erroneous signals. when determining whether a pin is an input, keep in mind that it may change during reset or while changing port b between general purpose i/o and hi functions. the mc68000 (see figure 5-42) can use a movep instruction with word and long-word data size to transfer multiple bytes. if an mc68020 or mc68030 is used, dynamic bus sizing can be used to transfer multiple bytes with any instruction. figure 5-43 is a high level block diagram of a system using a single host to control multi- ple dsps. in addition, the dsps use the ssi to network together the dsps and multiple codecs. this system, as shown with four dsps, can process 80 million instructions per sec- ond at 40 mhz and can be easily expanded if more processing power is needed. a0 - a2 +5 v dsp56003/005 mc68hc11 irq a8 - a15 e r/w as a0/d0 - a7/d7 ha ck (host acknowledge) hreq (host request) hen (host enable) hr/w (host read/write) ha0 - ha2 (host address) h0 - h7 (host data) address decode le address latch +5 v a3 - a7 use lda and sta for 8-bit transfers. use ldd and std for 16-bit transfers. figure 5-41 mc68hc11 to dsp56003/005 host interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 63 5.3.6.5 host port use considerations ?host side careful synchronization is required when reading multibit registers that are written by another asynchronous system. this is a common problem when two asynchronous systems are connected. the situation exists in the host port. the considerations for proper operation are discussed below. 1. unsynchronized reading of receive byte registers when reading receive byte registers, rxh, rxm, or rxl, the host program- mer should use interrupts or poll the rxdf flag which indicates that data is available. this assures that the data in the receive byte registers will be stable. 2. overwriting transmit byte registers the host programmer should not write to the transmit byte registers, txh, txm, or txl, unless the txde bit is set indicating that the transmit byte regis- ters are empty. this guarantees that the transmit byte registers will transfer valid data to the hrx register. +5 v dsp56003/005 mc68000 ipl0 - ipl2 a4 - a23 fc0 - fc2 lds as dt a ck berr r/w a1 - a3 d0 - d7 hreq hen ha ck hr/w ha0 - ha2 h0 - h7 address decode interrupt vector decode mc68000 ?use movep for multiple byte transfers. mc68020 or mc68030 ?any memory references will work due to dynamic bus sizing. interrupt encoder dt a ck timing generator figure 5-42 mc68000 to dsp56003/005 host interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 64 host interface motorola data address rd/wr req select flag 0 flag 1 clock frame sync serial data analog input host ssi dsp56003/005 host ssi dsp56003/005 host ssi dsp56003/005 host ssi dsp56003/005 host codec codec analog output analog input analog output req rd/wr address bus data b u s select select select rx tx rx tx rx tx rx figure 5-43 multi-dsp network example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) motorola host interface 5 - 65 3. synchronization of status bits from dsp to host hc, hreq, dma, hf3, hf2, trdy, txde, and rxdf status bits (refer to dsp56000/001 user? manual , i/o interface section, host/dma interface program- ming model for descriptions of these status bits) are set or cleared from inside the dsp and read by the host processor. the host can read these status bits very quickly without regard to the clock rate used by the dsp, but the possibility exists that the state of the bit could be changing during the read operation. this is generally not a system problem, since the bit will be read correctly in the next pass of any host poll- ing routine. however, if the host asserts the hen for t31 a ns, the status data is guaranteed to be stable. a minimum hen deassertion time of t32 ns is required to enable inter- nal updates of the host status bits. this minimum time applies only if the host processor is reading the status bits. this places a limit on the maximum polling rate for these bits. a potential problem exists when reading status bits hf3 and hf2 as an encoded pair. if the dsp changes hf3 and hf2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. if the combina- tion of hf3 and hf2 has significance, the host could read the wrong combination. solution: a. read the bits twice and check for consensus. b. assert hen access for t31 ns so that status bit transitions are stabilized. 4. overwriting the host vector the host programmer should change the host vector register only when the host command bit (hc) is clear. this change will guarantee that the dsp interrupt control logic will receive a stable vector. 5. cancelling a pending host command exception the host processor may elect to clear the hc bit to cancel the host command excep- tion request at any time before it is recognized by the dsp. because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the dsp may execute the host exception after the hc bit is cleared. for these reasons, the hv bits must not be changed at the same time the hc bit is cleared. 6. when using the hreq pin for handshaking, wait until hreq is asserted and then start writing/reading data using the hen pin or the hack pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host interface (hi) 5 - 66 host interface motorola when not using hreq for handshaking, poll the init bit in the icr to make sure it is cleared by the hardware (which means the init execution is completed). then, start writing/reading data. if using neither hreq for handshaking, nor polling the init bit, wait at least 6t after negation of hen that wrote icr, before writing/reading data. this wait ensures that the init is completed, because it needs 3t for synchronization (worst case) plus 3t for executing the init. 7. all unused input pins should be terminated. also, any pin that is temporarily not driven by an output during reset, when reprogramming a port or pin, when a bus is not driven, or at any other time, should be pulled up or down with a resistor. for example, the hen is capable of reacting to 2 ns noise spikes when it is not terminated. allowing hack to float may cause problems even though it is not needed in the circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 6 - 1 section 6 serial communications interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 6 - 2 serial communications interface motorola paragraph number page number section 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 general-purpose i/o (port c) . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3 serial communication interface (sci) . . . . . . . . . . . . . . . . . 6-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola serial communications interface 6 - 3 6.1 introduction port c is a triple-function i/o port with nine pins (see figure 6-1). three of the nine pins can be configured as general-purpose i/o or as the serial communication interface (sci) pins. the other six pins can also be configured as gpio, or they can be configured as the synchronous serial interface (ssi) pins. when configured as general-purpose i/o, port c can be used for device control. when the pins are configured as sci, port c provides a convenient connection to oth- er dsps, processors, codecs, digital-to-analog and analog-to-digital converters, and any of several transducers. this port c (gpio and sci) is identical to the one on the dsp56001 and dsp56002. external address switch external data switch bus control host/dma parallel interface sci interface ssi interface port a i/0 (47) port c i/0 (9) port b i/0 (15) a0 - a15 d0 - d23 ps ds x/y extp rd wr bn br bg wt bs pb0 - pb7 pb8 pb9 pb10 pb11 pb12 pb13 pb14 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 h0 - h7 ha0 ha1 ha2 hr/w hen hreq ha ck or pb14 rxd txd sclk sc0 sc1 sc2 sck srd std default function alternate function 8 8 24 16 figure 6-1 port c interface dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) 6 - 4 serial communications interface motorola 6.2 general-purpose i/o (port c) when it is configured as gpio, port c can be viewed as nine i/o pins (see figure 6-2), which are controlled by three memory-mapped registers. these registers are the port c control register (pcc), port c data direction register (pcddr), and port c data register (pcd) (see figure 6-3). reset configures port c as general-purpose i/o with all 9 pins as inputs by clearing both the control (pcc), and data direction (pcddr) registers (external circuitry connected to these pins may need pullups until the pins are configured for operation). there are three registers associated with each external pin. each port c pin may be individually programmed as a gen- eral-purpose i/o pin or as a dedicated on-chip peripheral pin under software control. pin se- lection between general-purpose i/o and sci or ssi is made by setting the appropriate pcc bit (memory location x:$ffe1) to zero for general-purpose i/o or to one for serial interface. the pcddr (memory location x:$ffe3) programs each pin corresponding to a bit in the pcd (memory location x:$ffe5) as an input pin (if pcddr=0) or as an output pin (if pcddr=1). if a pin is configured as a gpio input (as shown in figure 6-4) and the processor reads the pcd, the processor sees the logic level on the pin. if the processor writes to the pcd, the data is latched there, but does not appear on the pin because the buffer is in the high-impedance state. if a pin is configured as a gpio output and the processor reads the pcd, the processor sees the contents of the pcd rather the logic level on the pin, which allows the pcd to be used as a general purpose 15-bit register. if the processor writes to the pcd, the data is latched there and appears on the pin during the following instruction cycle (see section 6.2.2 ). p o r t c pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 cc0 cc1 cc2 cc3 cc4 cc5 cc6 cc7 cc8 cd0 cd1 cd2 cd3 cd4 cd5 cd6 cd7 cd8 enabled by bits in x:$ffe1 direction selected by x:$ffe3 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 input/output data register x:$ffe5 figure 6-2 port c gpio control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) motorola serial communications interface 6 - 5 if a pin is configured as a serial interface (sci or ssi) pin, the port c gpio registers can be used to help in debugging the serial interface. if the pcddr bit for a given pin is cleared (configured as an input), the pcd will show the logic level on the pin, regardless of whether the serial interface function is using the pin as an input or an output. if the pcddr is set (con?ured as an output) for a given serial interface pin, when the proces- sor reads the pcd, it sees the contents of the pcd rather than the logic level on the pin another case which allows the pcd to act as a general purpose register. 6.2.1 programming general purpose i/o port c and all the dsp56003/005 peripherals are memory mapped (see figure 6-5). the stan- dard move instruction transfers data between port c and a register; as a result, performing a memory-to-memory data transfer takes two move instructions and a register. the movep instruction is specifically designed for i/o data transfer as shown in figure 6-6. 000000000000000 cc 0 23 0 x:$ffe1 port c control register (pcc) ccx function 0 gpio 1 serial interface cd 0 23 0 x:$ffe3 port c data direction register (pcddr) cdx data direction 0 input 1 output 000000000000000 cd 1 cd 2 cd 3 cd 4 cd 5 cd 6 cd 7 cd 8 pd 0 23 0 x:$ffe5 port c data register (pcd) 000000000000000 pd 1 pd 2 pd 3 pd 4 pd 5 pd 6 pd 7 pd 8 cc 1 cc 2 cc 3 cc 4 cc 5 cc 6 cc 7 cc 8 std srd sck sc2 sc1 sc0 sclk txd rxd ssi sci note: hardware and software reset clears pcc and pcddr. figure 6-3 port c gpio registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) 6 - 6 serial communications interface motorola although the movep instruction may take twice as long to execute as a move instruc- tion, only one movep is required for a memory-to-memory data transfer, and movep does not use a temporary register. using the movep instruction allows a fast interrupt to move data to/from a peripheral to memory and execute one other instruction or to move the data to an absolute address. movep is the only memory-to-memory move in- struction; however, one of the operands must be in the top 64 locations of either x: or y: memory. the bit-oriented instructions which use i/o short addressing (bchg, bclr, bset, btst, jclr, jsclr, jset, and jsset) can also be used to address individual bits for faster i/o processing. the dsp does not have a hardware data strobe to strobe data out of the gpio port. if a data strobe is needed, it can be implemented using software to toggle one of the gpio pins. port registers input data bit data direction bit output data bit port input data bit port control register bit data direction register bit pin function 0 0 port input pin pin port c data (pcd) register bit data direction register (pcddr) port c control (pcc) register bit (gpio position) (input position) peripheral logic figure 6-4 port c i/o pin control logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) motorola serial communications interface 6 - 7 x:$ffff x:$fffe x:$fffd x:$fffc x:$fffb x:$fffa x:$fff9 x:$fff8 x:$fff7 x:$fff6 x:$fff5 x:$fff4 x:$fff3 x:$fff2 x:$fff1 x:$fff0 x:$ffef x:$ffee x:$ffed x:$ffec x:$ffeb x:$ffea x:$ffe9 x:$ffe8 x:$ffe7 x:$ffe6 x:$ffe5 x:$ffe4 x:$ffe3 x:$ffe2 x:$ffe1 x:$ffe0 x:$ffdf x:$ffde x:$ffdd x:$ffdc x:$ffdb x:$ffda x:$ffd9 x:$ffd8 x:$ffd7 x:$ffd6 x:$ffd5 x:$ffd4 interrupt priority register (ipr) port a ?bus control register (bcr) pll control register once port gdb register reserved reserved reserved reserved reserved sci hi - rec/xmit data register (srx/stx) sci mid - rec/xmit data register (srx/stx) sci low - rec/xmit data register (srx/stx) sci transmit data address register (stxa) sci control register (sccr) sci interface status register (ssr) sci interface control register (scr) ssi recieve/transmit data register (rx/tx) ssi status/time slot register (ssisr/tsr) ssi control register b (crb) ssi control register a (cra) host receive/transmit register (hrx/htx) reserved host status register (hsr) host control register (hcr) watchdog timer count register (wcr) watchdog timer control/status register (wcsr) port c ?data register (pcd) port b ?data register (pbd) port c ?data direction register (pcddr) port b ?data direction register (pbddr) port c ?control register (pcc) port b ?control register (pbc) timer count register (tcr) timer control/status register (tcsr) reserved pwma2 count register (pwacr2) pwma1 count register (pwacr1) pwma0 count register (pwacr0) pwma prescaler register (pwacsr0) pwma control and status register (pwacsr1) pwmb1 count register (pwbcr1) pwmb0 count register (pwbcr0) pwmb prescaler register (pwbcsr0) pwmb control and status register (pwbcsr1) x:$ffc0 reserved = read as random number; write as don? care. 23 16 15 8 7 0 figure 6-5 on-chip peripheral memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) 6 - 8 serial communications interface motorola figure 6-7 shows the process of programming port c as general-purpose i/o. normal- ly, it is not good programming practice to activate a peripheral before programming it. however, reset activates the port c general-purpose i/o as all inputs, and the alterna- tive is to configure the port as an sci and/or ssi, which may not be desirable. in this case, it is probably better to insure that port c is initially configured for general-purpose i/o and then configure the data direction and data registers. it may be better in some situations to program the data direction or the data registers first to prevent two devices from driving one signal. the order of steps 1, 2, and 3 in figure 6-7 is optional and can be changed as needed. 6.2.2 port c general purpose i/o timing parallel data written to port c is delayed by one instruction cycle. for example, the following instruction: move data9,x:portc data24,y:extern 1. writes nine bits of data to the port c register, but the output pins do not change until the following instruction cycle 2. writes 24 bits of data to the external y memory, which appears on port a dur- ing t2 and t3 of the current instruction as a result, if it is necessary to synchronize the port a and port c outputs, two instruc- tions must be used: move data9,x:portc nop data24,y:extern : : movep #$0,x:$ffe1 ;select port c to be general-purpose i/o movep #$01f0,x:$ffe3 ;select pins pc0?c3 to be inputs : ;and pins pc4?c8 to be outputs : movep #data_out,x:$ffe5 ;put bits 4? of ?ata_out?on pins ;pb4?b8 bits 0? are ignored. movep x:$ffe0,#data_in ;put pb0?b3 in bits 0? of ?ata_in figure 6-6 write/read parallel data with port c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) motorola serial communications interface 6 - 9 the nop can be replaced by any instruction that allows parallel moves. inserting one or more ?ove data15,x:portc data24,y:extern?instructions between the first and second instruction produces an external 33-bit write each instruction cycle with only one instruction cycle lost in setup time: move data9,x:portc move data9,x:portc data24,y:extern move data9,x:portc data24,y:extern : : move data9,x:portc data24,y:extern nop data24,y:extern cc 1 cd 0 cd 1 cd 2 cd 3 cd 4 cd 5 cd 6 cd 7 cd 8 pc 0 pc 1 pc 2 pc 3 pc 4 pc 5 pc 6 pc 7 pc 8 step 1. select each pin to be general-purpose i/o or an on-chip peripheral pin: ccx = 0 general- purpose i/o ccx = 1 on-chip peripheral x:$ffe1 80 port c control register (pcc) x:$ffe3 port c data direction register (pcddr) 80 step 2. set each general - purpose i/o pin (selected above) as input or output: cdx = 0 input pin or cdx = 1 output pin 80 x:$ffe5 port c data register (pcd) step 3. read/write general - purpose i/o pins: pcx = output data if selected for general - purpose i/o and output in steps 1 and 2. or pcx = input data if selected for general - purpose i/o and input in steps 1 and 2. cc 2 cc 3 cc 4 cc 5 cc 6 cc 7 cc 8 cc 0 figure 6-7 i/o port c configuration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 10 serial communications interface motorola one application of this technique is to create an extended address for port a by concate- nating the port a address bits (instead of data bits) to the port c general-purpose output bits. the port c general-purpose i/o register would then work as a base address register, allowing the address space to be extended from 64k words (16 bits) to 33.5 million words (16 bits+ 9 bits=25 bits). port c uses the dsp central processing unit (cpu) four-phase clock for its operation. therefore, if wait states are inserted in the dsp cpu timing, they also affect port c timing. as a result, port a and port c in the previous synchronization example will always stay synchronized, regardless of how many wait states are used. 6.3 serial communication interface (sci) the sci provides a full-duplex port for serial communication to other dsps, microproces- sors, or peripherals such as modems. the communication can be ttl-level signals or, with additional logic, rs232c, rs422, etc. this interface uses three dedicated pins: transmit data (txd), receive data (rxd), and sci serial clock (sclk). it supports industry-standard asynchronous bit rates and protocols as well as high-speed (up to 5 mbps for a 40-mhz clock) synchronous data transmission. the asynchronous protocols include a multidrop mode for master/slave operation with wakeup on idle line and wakeup on address bit capability. the sci consists of separate transmit and receive sections whose operations can be asyn- chronous with respect to each other. a programmable baud-rate generator provides the transmit and receive clocks. an enable vector and an interrupt vector have been included so that the baud-rate generator can function as a general-purpose timer when it is not be- ing used by the sci peripheral or when the interrupt timing is the same as that used by the sci. the following is a short list of sci features: ?three-pin interface: txd ?transmit data rxd ?receive data sclk ?serial clock ?781.25 kbps nrz asynchronous communications interface (50-mhz system clock) ?6.25 mbps synchronous serial mode (50-mhz system clock) ?multidrop mode for multiprocessor systems: two wakeup modes: idle line and address bit wired-or mode ?on-chip or external baud rate generation/interrupt timer ?four interrupt priority levels ?fast or long interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 11 6.3.1 sci i/o pins the three sci pins can be configured as either general-purpose i/o or as a specific sci pin. each pin is independent of the other two, so that if only txd is needed, rxd and sclk can be programmed for general-purpose i/o. however, at least one of the three pins must be selected as an sci pin to release the sci from reset. sci interrupts may be enabled by programming the sci control registers before any of the sci pins are programmed as sci functions. in this case, only one transmit interrupt can be generated because the transmit data register is empty. the timer and timer interrupt will operate as they do when one or more of the sci pins is programmed as an sci function. 6.3.1.1 receive data (rxd) this input receives byte-oriented serial data and transfers the data to the sci receive shift register. asynchronous input data is sampled on the positive edge of the receive clock (1 sclk) if sckp equals zero. see the dsp56003/005 data sheet for detailed tim- ing information. rxd may be programmed as a general-purpose i/o pin (pc0) when the sci rxd function is not being used. 6.3.1.2 transmit data (txd) this output transmits serial data from the sci transmit shift register. data changes on the negative edge of the asynchronous transmit clock (sclk) if sckp equals zero. this out- put is stable on the positive edge of the transmit clock. see the dsp56003/005 data sheet for detailed timing information. txd may be programmed as a general-purpose i/o pin (pc1) when the sci txd function is not being used. 6.3.1.3 sci serial clock (sclk) this bidirectional pin provides an input or output clock from which the transmit and/or receive baud rate is derived in the asynchronous mode and from which data is transferred in the synchronous mode. sclk may be programmed as a general-purpose i/o pin (pc2) when the sci sclk function is not being used. this pin may be programmed as pc2 when data is being transmitted on txd since, in the asynchronous mode, the clock need not be transmitted. there is no connection between programming the pc2 pin as sclk and data coming out the txd pin because sclk is independent of sci data i/o. 6.3.2 sci programming model the resources available in the sci are described before discussing specific examples of how the sci is used. the registers comprising the sci are shown in figure 6-8 and figure 6-9. these registers are the sci control register (scr), sci status register (ssr), sci clock control register (sccr), sci receive data registers (srx), sci transmit data registers (stx), and the sci transmit data address register (stxa). the sci programming model can be viewed as three types of registers: 1) control ?scr and sccr in figure 6-8; 2) sta- tus ?ssr in figure 6-8; and 3) data transfer ?srx, stx, and stxa in figure 6-9. the fol- lowing paragraphs describe each bit in the programming model. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 12 serial communications interface motorola x:$fff0 23 161514131211109876543210 0 sckp (0) stir (0) tmie tie rie ilie te re woms rwu wake sbk ssftd wds2 wds1 wds0 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) sci control register (scr) (read/write) sci clock polarity timer interrupt rate timer interrupt enable transmit interrupt enable receive interrupt enable idle line interrupt enable transmitter enable word select bits sci shift direction send break wakeup mode select receiver wakeup enable wired - or mode select receiver enable x:$fff1 23 876543210 0 r8 fe pe or idle rdrf tdre trne (0) (0) (0) (0) (0) (0) (1) (1) sci status register (ssr) (read only) received bit 8 framing error flag parity error flag overrun error flag transmitter empty transmitter data register empty receive data register full idle line flag x:$fff2 23 161514131211109876543210 0 tcm rcm scp cod cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) sci clock control register (sccr) (read/write) clock divider bits transmit clock source bit receive clock source bit clock prescaler clock output divider note: the number in parentheses is the condition of the bit after hardware reset. figure 6-8 sci programming model ?control and status registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 13 6.3.2.1 sci control register (scr) the scr is a 16-bit read/write register that controls the serial interface operation. each bit is described in the following paragraphs. 6.3.2.1.1 scr word select (wds0, wds1, wds2) bits 0, 1, and 2 the three word-select bits (wds0, wds1, wds2) select the format of the transmit and re- ceive data. the formats include three asynchronous, one multidrop asynchronous mode, and an 8-bit synchronous (shift register) mode. the asynchronous modes are compatible with most uart-type serial devices and support standard rs232c communication links. 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 srx srx srx sci recieve data register high (read only) sci recieve data register mid (read only) sci receive data register low (read only) rxd sci receive data shift register note: srx is the same register decoded at three different addresses. 23 16 15 8 7 0 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 stx stx stx sci transmit data register hig (write only) sci transmit data register mid (write only) sci transmit data register low (write only) txd sci transmitdata shift register notes: 1. bytes are masked on the ?. 2. stx is the same register decoded at three different addresses. stxa x:$fff3 sci transmitdata address register (write only) (a) receive data register (b) transmit data register figure 6-9 sci programming model f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 14 serial communications interface motorola the multidrop asynchronous modes are compatible with the mc68681 duart, the m68hc11 sci interface, and the intel 8051 serial interface. the synchronous data mode is essentially a high-speed shift register used for i/o expan- sion and stream-mode channel interfaces. a gated transmit and receive clock that is com- patible with the intel 8051 serial interface mode 0 accomplishes data synchronization. the word formats are shown in table 6-1 (also see figure 6-10 (a) and (b)). table 6-1 word formats when odd parity is selected, the transmitter will count the number of bits in the data word. if the total is not an odd number, the parity bit is made equal to one and thus pro- duces an odd number. if the receiver counts an even number of ones, an error in trans- mission has occurred. when even parity is selected, an even number must result from the calculation performed at both ends of the line or an error in transmission has occurred. the word-select bits are cleared by hardware and software reset. 6.3.2.1.2 scr sci shift direction (ssftd) bit 3 the sci data shift registers can be programmed to shift data in/out either lsb first if ssftd equals zero, or msb first if ssftd equals one. the parity and data type bits do not change position and remain adjacent to the stop bit. ssftd is cleared by hardware and software reset. wds2 wds1 wds0 word formats 0 0 0 8-bit synchronous data (shift register mode) 0 0 1 reserved 0 1 0 10-bit asynchronous (1 start, 8 data, 1 stop) 0 1 1 reserved 1 0 0 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop) 1 0 1 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop) 1 1 0 11-bit multidrop (1 start, 8 data, 1 data type, 1 stop) 1 1 1 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 15 mode 0 210 000 wds2 wds1 wds0 x:$fff0 8-bit synchronous data (shift register mode) tx (ssftd = 0) d0 d1 d2 d3 d4 d5 d6 d7 one byte from shift register mode 2 210 010 wds2 wds1 wds0 x:$fff0 10-bit asynchronous (1 start, 8 data, 1 stop) tx (ssftd = 0) d0 d1 d2 d3 d4 d5 d6 start bit d7 or data type stop bit mode 4 210 100 wds2 wds1 wds0 x:$fff0 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop) tx (ssftd = 0) d0 d1 d2 d3 d4 d5 d6 start bit d7 or data type stop bit even parity mode 5 210 101 wds2 wds1 wds0 x:$fff0 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop) tx (ssftd = 0) d0 d1 d2 d3 d4 d5 d6 start bit d7 or data type stop bit odd parity mode 6 210 110 wds2 wds1 wds0 x:$fff0 11-bit asynchronous multidrop (1 start, 8 data, 1 data type, 1 stop) tx (ssftd = 0) d0 d1 d2 d3 d4 d5 d6 start bit d7 stop bit data type data type: 1 = address byte 0 = data byte notes: 1. modes1, 3, and 7 are reserved. 2. d0 =lsb;d7 = msb 3. data is transmitted and received lsb ?st if ssftd = 0 or msb ?st if ssftd = 1. figure 6-10 serial formats (sheet 1 of 2) (a) ssftd = 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 16 serial communications interface motorola mode 0 210 000 wds2 wds1 wds0 x:$fff0 8-bit synchronous data (shift register mode) tx (ssftd = 1) d7 d6 d5 d4 d3 d2 d1 d0 one byte from shift register mode 2 210 010 wds2 wds1 wds0 x:$fff0 10-bit asynchronous (1 start, 8 data, 1 stop) tx (ssftd = 1) d6 d5 d4 d3 d2 d1 d0 start bit d7 or data type stop bit mode 4 210 100 wds2 wds1 wds0 x:$fff0 11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop) tx (ssftd = 1) start bit d7 or data type stop bit even parity mode 5 210 101 wds2 wds1 wds0 x:$fff0 11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop) tx (ssftd = 1) start bit d7 or data type stop bit odd parity mode 6 210 110 wds2 wds1 wds0 x:$fff0 11-bit asynchronous multidrop (1 start, 8 data, 1 data type, 1 stop) tx (ssftd = 1) start bit stop bit data type data type: 1 = address byte 0 = data byte notes: 1. modes 1, 3, and 7 are reserved. 2. d0 = lsb;d7 = msb 3. data is transmitted and received lsb ?st if ssftd = 0 or msb ?st if ssftd = 1. d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 (b) ssftd = 1 figure 6-10 serial formats (sheet 2 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 17 6.3.2.1.3 scr send break (sbk) bit 4 a break is an all-zero word frame ?a start bit zero, a character of all zeros (including any parity), and a stop bit zero: i.e., 10 or 11 zeros depending on the wds mode selected. if sbk is set and then cleared, the transmitter completes transmission of any data, sends 10 or 11 zeros, and reverts to idle or sending data. if sbk remains set, the transmitter will continually send whole frames of zeros (10 or 11 bits with no stop bit). at the completion of the break code, the transmitter sends at least one high bit before transmitting any data to guarantee recognition of a valid start bit. break can be used to signal an unusual con- dition, message, etc. by forcing a frame error, which is caused by a missing stop bit. hardware and software reset clear sbk. 6.3.2.1.4 scr wakeup mode select (wake) bit 5 when wake equals zero, an idle line wakeup is selected. in the idle line wakeup mode, the sci receiver is re-enabled by an idle string of at least 10 or 11 (depending on wds mode) consecutive ones. the transmitter? software must provide this idle string between consecutive messages. the idle string cannot occur within a valid message because each word frame contains a start bit that is a zero. when wake equals one, an address bit wakeup is selected. in the address bit wakeup mode, the sci receiver is re-enabled when the last (eighth or ninth) data bit received in a character (frame) is one. the ninth data bit is the address bit (r8) in the 11-bit multidrop mode; the eighth data bit is the address bit in the 10-bit asynchronous and 11-bit asyn- chronous with parity modes. thus, the received character is an address that has to be pro- cessed by all sleeping processors ?i.e., each processor has to compare the received char- acter with its own address and decide whether to receive or ignore all following charac- ters. wake is cleared by hardware and software reset. 6.3.2.1.5 scr receiver wakeup enable (rwu) bit 6 when rwu equals one and the sci is in an asynchronous mode, the wakeup function is enabled ?i.e., the sci is put to sleep waiting for a reason (defined by the wake bit) to wakeup. in the sleeping state, all receive flags, except idle, and interrupts are disabled. when the receiver wakes up, this bit is cleared by the wakeup hardware. the program- mer may also clear the rwu bit to wake up the receiver. rwu can be used by the programmer to ignore messages that are for other devices on a multidrop serial network. wakeup on idle line (wake=0) or wakeup on address bit (wake=1) must be chosen. 1. when wake equals zero and rwu equals one, the receiver will not respond to data on the data line until an idle line is detected. 2. when wake equals one and rwu equals one, the receiver will not respond to data on the data line until a data byte with bit 9 equal to one is detected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 18 serial communications interface motorola when the receiver wakes up, the rwu bit is cleared, and the first byte of data is received. if interrupts are enabled, the cpu will be interrupted, and the interrupt routine will read the message header to determine if the message is intended for this dsp. 1. if the message is for this dsp, the message will be received, and rwu will again be set to one to wait for the next message. 2. if the message is not for this dsp, the dsp will immediately set rwu to one. setting rwu to one causes the dsp to ignore the remainder of the message and wait for the next message. rwu is cleared by hardware and software reset. rwu is a don? care in the synchronous mode. 6.3.2.1.6 scr wired-or mode select (woms) bit 7 when the woms bit is set, the sci txd driver is programmed to function as an open- drain output and may be wired together with other txd pins in an appropriate bus con- figuration such as a master-slave multidrop configuration. an external pullup resistor is required on the bus. when the woms is cleared, the txd pin uses an active internal pul- lup. this bit is cleared by hardware and software reset. 6.3.2.1.7 scr receiver enable (re) bit 8 when re is set, the receiver is enabled. when re is cleared, the receiver is disabled, and data transfer is inhibited to the receive data register (srx) from the receive shift register. if re is cleared while a character is being received, the reception of the character will be completed before the receiver is disabled. re does not inhibit rdrf or receive interrupts. re is cleared by a hardware and software reset. 6.3.2.1.8 scr transmitter enable (te) bit 9 when te is set, the transmitter is enabled. when te is cleared, the transmitter will complete transmission of data in the sci transmit data shift register; then the serial output is forced high (idle). data present in the sci transmit data register (stx) will not be transmitted. stx may be written and tdre will be cleared, but the data will not be transferred into the shift register. te does not inhibit tdre or transmit interrupts. te is cleared by a hardware and software reset. setting te will cause the transmitter to send a preamble of 10 or 11 consecutive ones (de- pending on wds). this procedure gives the programmer a convenient way to ensure that the line goes idle before starting a new message. to force this separation of messages by the minimum idle line time, the following sequence is recommended: 1. write the last byte of the first message to stx 2. wait for tdre to go high, indicating the last byte has been transferred to the transmit shift register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 19 3. clear te and set te back to one. this queues an idle line preamble to immedi- ately follow the transmission of the last character of the message (including the stop bit) 4. write the first byte of the second message to stx in this sequence, if the first byte of the second message is not transferred to the stx prior to the finish of the preamble transmission, then the transmit data line will simply mark idle until stx is finally written. 6.3.2.1.9 scr idle line interrupt enable (ilie) bit 10 when ilie is set, the sci interrupt occurs when idle is set. when ilie is clear, the idle interrupt is disabled. ilie is cleared by hardware and software reset. an internal flag, the shift register idle interrupt (sriint) flag, is the interrupt request to the interrupt controller. sriint is not directly accessible to the user. when a valid start bit has been received, an idle interrupt will be generated if both idle (sci status register bit 3) and ilie equals one. the idle interrupt acknowledge from the interrupt controller clears this interrupt request. the idle interrupt will not be asserted again until at least one character has been received. the result is as follows: 1. the idle bit shows the real status of the receive line at all times. 2. idle interrupt is generated once for each idle state, no matter how long the idle state lasts. 6.3.2.1.10 scr sci receive interrupt enable (rie) bit 11 the rie bit is used to enable the sci receive data interrupt. if rie is cleared, receive inter- rupts are disabled, and the rdrf bit in the sci status register must be polled to determine if the receive data register is full. if both rie and rdrf are set, the sci will request an sci receive data interrupt from the interrupt controller. one of two possible receive data interrupts will be requested: 1. receive without exception will be requested if pe, fe, and or are all clear (i.e., a normal received character). 2. receive with exception will be requested if pe, fe, and or are not all clear (i.e., a received character with an error condition). rie is cleared by hardware and software reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 20 serial communications interface motorola 6.3.2.1.11 scr sci transmit interrupt enable (tie) bit 12 the tie bit is used to enable the sci transmit data interrupt. if tie is cleared, transmit data interrupts are disabled, and the transmit data register empty (tdre) bit in the sci status register must be polled to determine if the transmit data register is empty. if both tie and tdre are set, the sci will request an sci transmit data interrupt from the inter- rupt controller. tie is cleared by hardware and software reset. 6.3.2.1.12 scr timer interrupt enable (tmie) bit 13 the tmie bit is used to enable the sci timer interrupt. if tmie is set (enabled), the timer interrupt requests will be made to the interrupt controller at the rate set by the sci clock register. the timer interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt controller. this feature allows dsp programmers to use the sci baud clock generator as a simple periodic interrupt generator if the sci is not in use, if external clocks are used for the sci, or if periodic interrupts are needed at the sci baud rate. the sci internal clock is divided by 16 (to match the 1 sci baud rate) for timer interrupt gen- eration. this timer does not require that any sci pins be configured for sci use to operate. tmie is cleared by hardware and software reset. 6.3.2.1.13 scr sci timer interrupt rate (stir) bit 14 this bit controls a divide by 32 in the sci timer interrupt generator. when this bit is cleared, the divide by 32 is inserted in the chain. when the bit is set, the divide by 32 is bypassed, thereby increasing the timer resolution by 32 times. this bit is cleared by hard- ware and software reset. 6.3.2.1.14 scr sci clock polarity (sckp) bit 15 the clock polarity, sourced or received on the clock pin (sclk), can be inverted using this bit, eliminating the need for an external inverter. when bit 15 equals zero, the clock po- larity is positive; when bit 15 equals one, the clock polarity is negative. in the synchronous mode, positive polarity means that the clock is normally positive and transitions negative during data valid; whereas, negative polarity means that the clock is normally negative and transitions positive during valid data. in the asynchronous mode, positive polarity means that the rising edge of the clock occurs in the center of the period that data is valid; negative polarity means that the falling edge of the clock occurs during the center of the period that data is valid. sckp is cleared on hardware and software reset. 6.3.2.2 sci status register (ssr) the ssr is an 8-bit read-only register used by the dsp cpu to determine the status of the sci. when the ssr is read onto the internal data bus, the register contents occupy the low-order byte of the data bus and all high-order portions are zero filled. the status bits are described in the following paragraphs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 21 6.3.2.2.1 ssr transmitter empty (trne) bit 0 the trne flag is set when both the transmit shift register and data register are empty to indicate that there is no data in the transmitter. when trne is set, data written to one of the three stx locations or to the stxa will be transferred to the transmit shift register and be the first data transmitted. trne is cleared when tdre is cleared by writing data into the transmit data register (stx) or the transmit data address register (stxa), or when an idle, preamble, or break is transmitted. the purpose of this bit is to indicate that the trans- mitter is empty; therefore, the data written to stx or stxa will be transmitted next ?i.e., there is not a word in the transmit shift register presently being transmitted. this proce- dure is useful when initiating the transfer of a message (i.e., a string of characters). trne is set by the hardware, software, sci individual, and stop reset. 6.3.2.2.2 ssr transmit data register empty (tdre) bit 1 the tdre bit is set when the sci transmit data register is empty. when tdre is set, new data may be written to one of the sci transmit data registers (stx) or transmit data ad- dress register (stxa). tdre is cleared when the sci transmit data register is written. tdre is set by the hardware, software, sci individual, and stop reset. in the sci synchronous mode, when using the internal sci clock, there is a delay of up to 5.5 serial clock cycles between the time that stx is written until tdre is set, indicat- ing the data has been transferred from the stx to the transmit shift register. there is a two to four serial clock cycle delay between writing stx and loading the transmit shift register; in addition, tdre is set in the middle of transmitting the second bit. when using an external serial transmit clock, if the clock stops, the sci transmitter stops. tdre will not be set until the middle of the second bit transmitted after the external clock starts. gating the external clock off after the first bit has been transmitted will de- lay tdre indefinitely. in the sci asynchronous mode, the tdre flag is not set immediately after a word is trans- ferred from the stx or stxa to the transmit shift register nor when the word first begins to be shifted out. tdre is set two cycles of the 16 clock after the start bit ?i.e., two 16 clock cycles into to transmission time of the first data bit. 6.3.2.2.3 ssr receive data register full (rdrf) bit 2 the rdrf bit is set when a valid character is transferred to the sci receive data register from the sci receive shift register. rdrf is cleared when the sci receive data register is read or by the hardware, software, sci individual, and stop reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 22 serial communications interface motorola 6.3.2.2.4 ssr idle line flag (idle) bit 3 idle is set when 10 (or 11) consecutive ones are received. idle is cleared by a start-bit detection. the idle status bit represents the status of the receive line. the transition of idle from zero to one can cause an idle interrupt (ilie). idle is cleared by the hard- ware, software, sci individual, and stop reset. 6.3.2.2.5 ssr overrun error flag (or) bit 4 the or flag is set when a byte is ready to be transferred from the receive shift register to the receive data register (srx) that is already full (rdrf=1). the receive shift register data is not transferred to the srx. the or flag indicates that character(s) in the receive data stream may have been lost. the only valid data is located in the srx. or is cleared when the sci status register is read, followed by a read of srx. the or bit clears the fe and pe bits ?i.e., overrun error has higher priority than fe or pe. or is cleared by the hardware, software, sci individual, and stop reset. 6.3.2.2.6 ssr parity error (pe) bit 5 in the 11-bit asynchronous modes, the pe bit is set when an incorrect parity bit has been detected in the received character. it is set simultaneously with rdrf for the byte which contains the parity error ?i.e., when the received word is transferred to the srx. if pe is set, it does not inhibit further data transfer into the srx. pe is cleared when the sci status register is read, followed by a read of srx. pe is also cleared by the hardware, software, sci individual, or stop reset. in the 10-bit asynchronous mode, the 11-bit multidrop mode, and the 8-bit synchronous mode, the pe bit is always cleared since there is no par- ity bit in these modes. if the byte received causes both parity and overrun errors, the sci receiver will only recognize the overrun error. 6.3.2.2.7 ssr framing error flag (fe) bit 6 the fe bit is set in the asynchronous modes when no stop bit is detected in the data string received. fe and rdre are set simultaneously ?i.e., when the received word is trans- ferred to the srx. however, the fe flag inhibits further transfer of data into the srx until it is cleared. fe is cleared when the sci status register is read followed by reading the srx. the hardware, software, sci individual, and stop reset also clear fe. in the 8-bit syn- chronous mode, fe is always cleared. if the byte received causes both framing and over- run errors, the sci receiver will only recognize the overrun error. 6.3.2.2.8 ssr received bit 8 address (r8) bit 7 in the 11-bit asynchronous multidrop mode, the r8 bit is used to indicate whether the re- ceived byte is an address or data. r8 is not affected by reading the srx or status register. the hardware, software, sci individual, and stop reset clear r8. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 23 6.3.2.3 sci clock control register (sccr) the sccr is a 16-bit read/write register which controls the selection of the clock modes and baud rates for the transmit and receive sections of the sci interface. the control bits are described in the following paragraphs. the sccr is cleared by hardware reset. the basic points of the clock generator are as follows: 1. the sci core always uses a 16 internal clock in the asynchronous modes and always uses a 2 internal clock in the synchronous mode. the maximum internal clock available to the sci peripheral block is the oscillator frequency divided by 4. with a 40-mhz crystal, this gives a maximum data rate of 625 kbps for asynchonous data and 5 mbps for synchronous data. these maxi- mum rates are the same for internally or externally supplied clocks. 2. the 16 clock is necessary for the asynchronous modes to synchronize the sci to the incoming data (see figure 6-11). 3. for the asynchronous modes, the user must provide a 16 clock if he wishes to use an external baud rate generator (i.e., sclk input). 4. for the asynchronous modes, the user may select either 1 or 16 for the out- put clock when using internal tx and rx clocks (tcm=0 and rcm=0). 5. the transmit data on the txd pin changes on the negative edge of the 1 serial clock and is stable on the positive edge (sckp=0). for sckp equals one, the data changes on the positive edge and is stable on the negative edge. 6. the receive data on the rxd pin is sampled on the positive edge (if sckp=0) or on the negative edge (if sckp=1) of the 1 serial clock. rx, tx data (ssftd = 0) idle line start stop start 012 345 67 8 select 8-or 9-bit words x1 clock x16 clock (sckp = 0) figure 6-11 16x serial clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 24 serial communications interface motorola 7. for the asynchronous mode, the output clock is continuous. 8. for the synchronous mode, a 1 clock is used for the output or input baud rate. the maximum 1 clock is the crystal frequency divided by 8. 9. for the synchronous mode, the clock is gated. 10. for both the asynchronous and synchronous modes, the transmitter and receiver are synchronous with each other. 6.3.2.3.1 sccr clock divider (cd11?d0) bits 11? the clock divider bits (cd11?d0) are used to preset a 12-bit counter, which is dec- remented at the i cyc rate (crystal frequency divided by 2). the counter is not accessible to the user. when the counter reaches zero, it is reloaded from the clock divider bits. thus, a value of 0000 0000 0000 in cd11?d0 produces the maximum rate of i cyc , and a value of 0000 0000 0001 produces a rate of i cyc /2. the lowest rate available is i cyc /4096. figure 6-12 and figure 6-35 show the clock dividers. bits cd11?d0 are cleared by hardware and software reset. 6.3.2.3.2 sccr clock out divider (cod) bit 12 figure 6-12 and figure 6-35 show the clock divider circuit. the output divider is con- trolled by cod and the sci mode. if the sci mode is synchronous, the output divider is fixed at divide by 2; if the sci mode is asynchronous, and 1. if cod equals zero and sclk is an output (i.e., tcm and rcm=0), the sci clock is divided by 16 before being output to the sclk pin; thus, the sclk output is a 1 clock 2. if cod equals one and sclk is an output, the sci clock is fed directly out to the sclk pin; thus, the sclk output is a 16 baud clock the cod bit is cleared by hardware and software reset. 6.3.2.3.3 sccr sci clock prescaler (scp) bit 13 the sci scp bit selects a divide by 1 (scp=0) or divide by 8 (scp=1) prescaler for the clock divider. the output of the prescaler is further divided by 2 to form the sci clock. hardware and software reset clear scp. figure 6-12 and figure 6-35 show the clock divider diagram. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 25 6.3.2.3.4 sccr receive clock mode source (rcm) bit 14 rcm selects internal or external clock for the receiver (see figure 6-35). rcm equals zero selects the internal clock; rcm equals one selects the external clock from the sclk pin. hardware and software reset clear rcm. 6.3.2.3.5 sccr transmit clock source (tcm) bit 15 the tcm bit selects internal or external clock for the transmitter (see figure 6-35). tcm equals zero selects the internal clock; tcm equals one selects the external clock from the sclk pin. hardware and software reset clear tcm. tcm rcm tx clock rx clock sclk pin mode 0 0 internal internal output synchronous/asynchronous 0 1 internal external input asynchronous only 1 0 external internal input asynchronous only 1 1 external external input synchronous/asynchronous f osc divide by 2 12-bit counter prescaler: divide by 1 or 8 divide by 2 cd11 - cd0 scp internal clock divide by 16 timer interrupt (stmint) sci core logic uses divide by 16 for asynchronous uses divide by 2 for synchronous cod sckp if asynchronous divide by 1 or 16 if synchronous divide by 2 sckp = 0 + sckp = 1 - to sclk fo bps = 64 x (7(scp) + 1) x cd + 1) where: scp = 0 or 1 cd = 0 to $fff figure 6-12 sci baud rate generator stir f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 26 serial communications interface motorola 6.3.2.4 sci data registers the sci data registers are divided into two groups: receive and transmit. there are two receive registers ?a receive data register (srx) and a serial-to-parallel receive shift regis- ter. there are also two transmit registers ?a transmit data register (called either stx or stxa) and a parallel-to-serial transmit shift register. 6.3.2.4.1 sci receive register data words received on the rxd pin are shifted into the sci receive shift register. when the complete word has been received, the data portion of the word is transferred to the byte-wide srx. this process converts the serial data to parallel data and provides double buffering. double buffering provides flexibility and increased throughput since the pro- grammer can save the previous word while the current word is being received. the srx can be read at three locations: x:$fff4, x:$fff5, and x:$fff6 (see figure 6-13). when location x:$fff4 is read, the contents of the srx are placed in the lower byte of the data bus and the remaining bits on the data bus are written as zeros. similarly, when x:$fff5 is read, the contents of srx are placed in the middle byte of the bus, and when x:$fff6 is read, the contents of srx are placed in the high byte with the remaining bits zeroed. mapping srx as described allows three bytes to be efficiently packed into one 24-bit word by ?r?ing three data bytes read from the three addresses. the following code fragment requires that r0 initially points to x:$fff4, register a is initially cleared, and r3 points to a data buffer. the only programming trick is using bclr to test bit 1 of the packing pointer to see if it is pointing to x:$fff6 and clearing bit 1 to point to x:$fff4 if it had been pointing to x:$fff6. this procedure resets the packing pointer after receiv- ing three bytes. move x:(r0),x0 ;copy received data to temporary register bclr #$1,r0 ;test for last byte ;reset pointer if it is the last byte or x0,a ;pack the data into register a move (r0)+ ;and increment the packing pointer jcs flag ;jump to clean up routine if last byte rti ;else return until next byte is received flag move a,(r3)+ ;move the packed data to memory clr a ;prepare a for packing next three bytes rti ;return until the next byte is received f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 27 the length and format of the serial word is defined by the wds0, wds1, and wds2 control bits in the sci control register. in the synchronous modes, the start bit, the eight data bits with lsb first, the address/data indicator bit and/or the parity bit, and the stop bit are received in that order for ssftd equals zero (see figure 6-10 (a)). for ssftd equals one, the data bits are transmitted msb first (see figure 6-10(b)). the clock source is defined by the receive clock mode (rcm) select bit in the scr. in the synchronous mode, the synchronization is provided by gating the clock. in either mode, when a complete word has been clocked in, the contents of the shift register can be transferred to the srx and the flags; rdrf, fe, pe, and or are changed ap- propriately. because the operation of the sci receive shift register is transparent to the dsp, the contents of this register are not directly accessible to the programmer. 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 stx stx stx move x0, x:$fff6; transmit character ? move x0, x:$fff5; transmit character ? move x0, x:$fff4; transmit character ? note: stx is the same register decoded at three different addresses. x0 ? ? ? 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 srx srx srx move x0, x:$fff6; receive character ? move x0, x:$fff5; receive character ? move x0, x:$fff4; receive character ? note: srx is the same register decoded at three different addresses. x0 ? ? ? (a) unpacking (b) packing figure 6-13 data packing and unpacking f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 28 serial communications interface motorola 6.3.2.4.2 sci transmit registers the transmit data register is one byte-wide register mapped into four addresses: x:$fff3, x:$fff4, x:$fff5, and x:$fff6. in the asynchronous mode, when data is to be transmitted, x:$fff4, x:$fff5, and x:$fff6 are used, and the register is called stx. when x:$fff4 is written, the low byte on the data bus is transferred to the stx; when x:$fff5 is written, the middle byte is transferred to the stx; and when x:$fff6 is writ- ten, the high byte is transferred to the stx. this structure (see figure 6-9) makes it easy for the programmer to unpack the bytes in a 24-bit word for transmission. location x:$fff3 should be written in the 11-bit asynchronous multidrop mode when the data is an address and it is desired that the ninth bit (the address bit) be set. when x:$fff3 is written, the transmit data register is called stxa, and data from the low byte on the data bus is stored in stxa. the address data bit will be cleared in the 11-bit asynchro- nous multidrop mode when any of x:$fff4, x:$fff5, or x:$fff6 is written. when ei- ther stx or stxa is written, tdre is cleared. the transfer from either stx or stxa to the transmit shift register occurs automatical- ly, but not immediately, when the last bit from the previous word has been shifted out ?i.e., the transmit shift register is empty. like the receiver, the transmitter is double buffered. however, there will be a two to four serial clock cycle delay between when the data is transferred from either stx or stxa to the transmit shift register and when the first bit appears on the txd pin. (a serial clock cycle is the time required to trans- mit one data bit). the transmit shift register is not directly addressable, and a dedicat- ed flag for this register does not exist. because of this fact and the two to four cycle delay, two bytes cannot be written consecutively to stx or stxa without polling. the second byte will overwrite the first byte. the tdre flag should always be polled prior to writing stx or stxa to prevent overruns unless transmit interrupts have been en- abled. either stx or stxa is usually written as part of the interrupt service routine. of course, the interrupt will only be generated if tdre equals one. the transmit shift register is indirectly visible via the trne bit in the ssr. in the synchronous modes, data is synchronized with the transmit clock, which may have either an internal or external source as defined by the tcm bit in the sccr. the length and format of the serial word is defined by the wds0, wds1, and wds2 control bits in the scr. in the asynchronous modes, the start bit, the eight data bits (with the lsb first if ssftd=0 and the msb first if ssftd=1), the address/data indicator bit or parity bit, and the stop bit are transmitted in that order (see figure 6-10). the data to be transmitted can be written to any one of the three stx addresses. if sckp equals one and sshtd equals one, the sci synchronous mode is equivalent to the ssi op- eration in the 8-bit data on-demand mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 29 6.3.2.5 preamble, break, and data transmission priority it is possible that two or three transmission commands are set simultaneously: 1. a preamble (te was toggled) 2. a break (sbk was set or was toggled) 3. there is data for transmission (tdre=0) after the current character transmission, if two or more of these commands are set, the transmitter will execute them in the following priority: 1. preamble 2. break 3. data 6.3.3 register contents after reset there are four methods to reset the sci. hardware or software reset clears the port control register bits, which configure all i/o as general-purpose input. the sci will remain in the reset state while all sci pins are programmed as general-purpose i/o (cc2, cc1, and cc0=0); the sci will become active only when at least one of the sci i/o pins is pro- grammed as not general-purpose i/o. during program execution, the cc2, cc1, and cc0 bits may be cleared (individual re- set), which will cause the sci to stop serial activity and enter the reset state. all sci sta- tus bits will be set to their reset state; however, the contents of the interface control reg- ister are not affected, allowing the dsp program to reset the sci separately from the other internal peripherals. the stop instruction halts operation of the sci until the dsp is restarted, causing the ssr to be reset. no other sci registers are affected by the stop instruction. table 6-2 illus- trates how each type of reset affects each register in the sci. 6.3.4 sci initialization the correct way to initialize the sci is as follows: 1. hardware or software reset 2. program sci control registers 3. configure sci pins (at least one) as not general-purpose i/o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 30 serial communications interface motorola register bit bit mnemonic bit number reset type hw reset sw reset ir reset st reset sckp 15 0 0 stir 14 0 0 tmie 13 0 0 tie 12 0 0 rie 11 0 0 ilie 10 0 0 te 9 0 0 scr re 8 0 0 woms 7 0 0 rwu 6 0 0 wake 5 0 0 sbk 4 0 0 ssftd 3 0 0 wds (2?) 2? 0 0 r8 7 0 0 0 0 fe 6 0 0 0 0 pe 5 0 0 0 0 ssr or 4 0 0 0 0 idle 3 0 0 0 0 rdrf 2 0 0 0 0 tdre 1 1 1 1 1 trne 0 1 1 1 1 tcm 15 0 0 rcm 14 0 0 sccr scp 13 0 0 cod 12 0 0 cd (11?) 11? 0 0 srx srx (23?) 23?6, 15?, 7? stx stx (23?) 23? srsh srs (8?) 8? stsh sts (8?) 8? notes: srsh ?sci receive shift register, stsh ?sci transmit shift register hw ?hardware reset is caused by asserting the external reset pin. sw ?software reset is caused by executing the reset instruction. ir ?individual reset is caused by clearing pcc (bits 0?) (configured for general-purpose i/o). st ?stop reset is caused by executing the stop instruction. 1 ?the bit is set during the xx reset. 0 ?the bit is cleared during the xx reset. ??the bit is not changed during the xx reset. table 6-2 sci registers after reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 31 figure 6-14 and figure 6-15 show how to configure the bits in the sci registers. figure 6-14 is the basic initialization procedure showing which registers must be configured. 1. a hardware or software reset should be used to reset the sci and prevent it from doing anything unexpected while it is being programmed 2. both the sci interface control register and the clock control register must be con- figured for any operation using the sci 3. the pins to be used must then be selected to release the sci from reset 4. begin operation if interrupts are to be used, the pins must be selected, and interrupts must be enabled and unmasked before the sci will operate. the order does not matter; any one of these three requirements for interrupts can be used to finally enable the sci. figure 6-15 shows the meaning of the individual bits in the scr and sccr. the figures below do not assume that interrupts will be used; they recommend selecting the appro- priate pins to enable the sci. programs shown in figures figure 6-20, figure 6-21, figure 6-28, figure 6-34, and figure 6-36 control the sci by enabling and disabling interrupts. ei- ther method is acceptable. table 6-3 (a) through table 6-4 (b) provide the settings for common baud rates for the sci. the asynchronous sci baud rates show a baud rate error for the fixed oscillator frequency (see table 6-3 (a)). these small-percentage baud rate errors should allow most uarts to synchronize. the synchronous applications usually require exact frequencies, which re- quire that the crystal frequency be chosen carefully (see table 6-4 (a) and table 6-4 (b)). 1. perform hardware or software reset. 2. program sci control registers: a) sci interface control register ?x:$fff0 b) sci clock control register ?x:$fff2 3. configure at least one port c control bit as sci. 000000000000000 cc 0 23 0 x:$ffe1 port c control register (pcc) ccx function 0 gpio 1 serial interface cc 1 cc 2 cc 3 cc 4 cc 5 cc 6 cc 7 cc 8 sclk txd rxd sci 4. sci is now active. figure 6-14 sci initialization procedure f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 32 serial communications interface motorola x:$fff0 15141312111098 76543210 sckp stir tmie tie rie ilie te re woms rwu wake sbk ssftd wds2 wds1 wds0 sci interface control register (scr) (read/write) 000 = 8-bit synchronous data (shift register mode) 001 = reserved 010 = 10-bit asynchronous (1 start, 8 data, 1 stop) 011 = reserved 100 = 11-bit asynchronous (1 start, 8 data, even parity, 1 stop) 101 = 11-bit asynchronous (1 start, 8 data, odd parity, 1 stop) 110 = 11-bit multidrop (1 start, 8 data, even parity, 1 stop) 111 = reserved step 2a . select sci operation: for a basic configuration, set: sckp bit 15 = 0 stir bit 14 = 0 tmie bit 13 = 0 ilie bit 10 = 0 rwu bit 6 = 0 wake bit 5 = 0 sbk bit 4 = 0 ssftd bit 3 = 0 enable/disable transmit interrupt enable = 1 disable = 0 enable/disable receive interrupt enable = 1 disable = 0 enable/disable transmit data enable = 1 disable = 0 enable/disable receive data enable = 1 disable = 0 wired - or mode multidrop = 1 point to point = 0 figure 6-15 sci general initialization detail ?step 2 (sheet 1 of 2) step 2a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 33 x:$fff2 15141312111098 76543210 tcm scp cod cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 sci clock control register (sccr) (read/write) step 2b . select clock and data rate: set the clock divider bits (cd0 - cd11) according to tables 11 - 2 or 11 - 3. set the sci clock prescaler bit (scp, bit 13) according to tables 11 - 2 or 11 - 3. set transmit clock source external clock = 1 internal clock = 0 set receive clock source external clock = 1 internal clock = 0 set sci clock prescaler divide by 8 = 1 divide by 1 = 0 set clock out divider if sclk pin is an otuput and cod = 1 sclk output = 16 cod = 0 sclk output = 1 rcm figure 6-15 sci general initialization detail ?step 2 (sheet 2 of 2) step 2b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 34 serial communications interface motorola bit rate (bps) scp bit divider bits (cd0?d11) bit rate error, percent 625.0k 0 $000 0 56.0k 0 $00a +1.46 38.4k 0 $00f +1.72 19.2k 0 $020 -1.36 9600 0 $040 +0.16 8000 0 $04d +0.15 4800 0 $081 +0.15 2400 1 $020 -1.38 1200 1 $040 +0.08 600 1 $081 0 300 1 $103 0 bps = f 0 (64 x (7 x (scp) + 1) x (cd + 1)); f 0 = 40 mhz scp = 0 or 1 cd = 0 to $fff table 6-3 (a) asynchronous sci bit rates for a 40-mhz crystal bit rate (bps) scp bit divider bits (cd0?d11) crystal frequency 9600 0 $040 39,936,000 4800 0 $081 39,936,000 2400 0 $103 39,936,000 1200 0 $207 39,936,000 300 0 $822 39,993,000 9600 1 $007 39,321,600 4800 1 $00f 39,321,600 2400 1 $01f 39,321,600 1200 1 $040 39,360,000 300 1 $103 39,936,000 table 6-3 (b) frequencies for exact asynchronous sci bit rates f0 = bps x 64 x (7 x (scp) + 1) x (cd + 1)) scp = 0 or 1 cd = 0 to $fff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 35 an alternative to selecting the system clock to accommodate the sci requirements is to pro- vide an external clock to the sci. for example, a 2.048 mhz bit rate requires a cpu clock of 32.768 mhz. an application may need a 40 mhz cpu clock and an external clock for the sci. baud rate (bps) scp bit divider bits (cd0?d11) baud rate error, percent 4.096m 0 $000 0 128k 0 $01f 0 64k 0 $03f 0 56k 0 $048 -0.195 32k 0 $07f 0 16k 0 $0ff 0 8000 0 $1ff 0 4000 0 $3ff 0 2000 0 $7ff 0 1000 0 $fff 0 table 6-4 (a) synchronous sci bit rates for a 32.768-mhz crystal bps = f 0 (8 (7 x (scp) + 1) (cd + 1)); f 0 = 32.768 mhz scp = 0 or 1 cd = 0 to $fff bit rate (bps) scp bit divider bits (cd0?d11) crystal frequency 2.048m 0 $001 32.768 mhz 1.544m 0 $002 37.056 mhz 1.536m 0 $002 36.864 mhz table 6-4 (b) frequencies for exact synchronous sci bit rates f 0 = bps ? 8 (7 x (scp) + 1) (cd + 1) scp = 0 or 1 cd = 0 to $fff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 36 serial communications interface motorola 6.3.5 sci exceptions the sci can cause five different exceptions in the dsp (see figure 6-16). these exceptions are as follows: 1. sci receive data ?caused by receive data register full with no receive error conditions existing. this error-free interrupt may use a fast interrupt service routine for minimum overhead. this interrupt is enabled by scr bit 11 (rie). 2. sci receive data with exception status ?caused by receive data register full with a receiver error (parity, framing, or overrun error). the sci status register must be read to clear the receiver error flag. a long interrupt service routine should be used to handle the error condition. this interrupt is enabled by scr bit 11 (rie). 3. sci transmit data ?caused by transmit data register empty. this error-free interrupt may use a fast interrupt service routine for minimum overhead. this interrupt is enabled by scr bit 12 (tie). 4. sci idle line ?occurs when the receive line enters the idle state (10 or 11 bits of ones). this interrupt is latched and then automatically reset when the inter- rupt is accepted. this interrupt is enabled by scr bit 10 (ilie). 5. sci timer ?caused by the baud rate counter underflowing. this interrupt is automatically reset when the interrupt is accepted. this interrupt is enabled by scr bit 13 (tmie). 6.3.6 synchronous data mode the synchronous mode (wds=0, shift register mode) is designed to implement seri- al-to-parallel and parallel-to-serial conversions. this mode will directly interface to 8051/8096 synchronous (mode 0) buses as both a controller (master) or a peripheral (slave) and is compatible with the ssi mode if sckp equals one. in synchronous mode, the clock is always common to the transmit and receive shift registers. as a controller (synchronous master) shown in figure 6-17, the dsp puts out a clock on the sclk pin when data is present in the transmit shift register (a gated clock mode). the master mode is selected by choosing internal transmit and receive clocks (setting tcm and rcm=0). the example shows a 74hc165 parallel-to-serial shift register and 74hc164 serial-to-parallel shift register being used to convert eight bits of serial i/o to eight bits of parallel i/o. the load pulse latches eight bits into the 74hc165 and then sclk shifts the rxd data into the sci (these data bits are sample bits 0-7 in the timing diagram). at the same time, txd shifts data out (b0-b7) to the 74hc164. when using the internal clock, data is transmitted when the transmit shift register is full. data is valid on both edges of the output clock, which is com- patible with an 8051 microprocessor. received data is sampled in the middle of the clock low time if sckp equals zero or in the middle of the clock high time if sckp equals one. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 37 host interface program memory space exception source exception starting address $0000 hardware reset $0002 stack error $0004 trace $0006 swi (software interrupt) $0008 irqa external hardware interrupt $000a irqb external hardware interrupt $000c ssi receive data $000e ssi receive data with exception status $0010 ssi transmit data $0012 ssi transmit data with exception status $0014 sci receive data $0016 sci receive data with exception status $0018 sci transmit data $001a sci idle line $001c sci timer $001e nmi /watchdog timer $0020 host receive data $0022 host transmit data $0024 host command (default) $0026 available for host command $0028 available for host command $002a available for host command $002c irqc $002e irqd $0030 pwma0 interrupt $0032 pwma1 interrupt $0034 pwma2 interrupt $0036 pwmb0 interrupt $0038 pwmb1 interrupt $003a pwm error $003c timer/event counter interrupt $003e illegal instruction $0040 available for host command $007e available for host command internal interrupts serial communications interface synchronous serial interface internal interrupts external interrupts internal interrupts two words per vector figure 6-16 hi exception vector locations external interrupts internal/external interrupts external interrupts internal interrupts watchdog timer host interface pulse width modulators interface timer/event counter interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 38 serial communications interface motorola x:$fff0 15141312111098 76543210 sckp tmie tie rie ilie te re woms rwu wake sbk 0 0 0 0 sci control register (scr) (read/write) stir x:$fff2 15141312111098 76543210 0 scp cod cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 sci clock control register (sccr) (read/write) 0 tcm rcm clock output (scp = 0) b0 b1 b2 b3 b4 b5 b6 b7 transmit data (ssftd = 0) xxxxxx xx xx xx xx xx xx xx xxxxxxx receive data write stx 0 12345 6 7 sample example: shift register i/o dsp56003/005 rxd sclk txd 74hc165 d l clk q clk d q 74hc164 s/p 8 parallel inputs load pulse 8 parallel outputs ssftd wds2 wds1 wds0 figure 6-17 synchronous master f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 39 there is a window during which stx must be written with the next byte to be transmitted to prevent a gap between words. this window is from the time tdre goes high halfway into transmission of bit 1 until the middle of bit 6 (see figure 6-19(a)). as a peripheral (synchronous slave) shown in figure 6-18, the dsp accepts an input clock from the sclk pin. if sckp equals zero, data is clocked in on the rising edge of sclk, and data is clocked out on the falling edge of sclk. if sckp equals one, data is clocked in on the falling edge of sclk, and data is clocked out on the rising edge of sclk. the slave mode is selected by choosing external transmit and receive clocks (tcm and rcm=1). since there is no frame signal, if a clock is missed due to noise or any other rea- son, the receiver will lose synchronization with the data without any error signal being generated. detecting an error of this type can be done with an error detecting protocol or with external circuitry such as a watchdog timer. the simplest way to recover synchroni- zation is to reset the sci. the timing diagram in figure 6-18 shows transmit data in the normal driven mode. bit b7 is essentially one-half sci clock long (t sci /2 + 1.5 t extal ) the last data bit is truncated so that the pin is guaranteed to go to its reset state before the start of the next data word, thereby de- limiting data words. the 1.5 crystal clock cycles provide sufficient hold time to satisfy most external logic requirements. the example diagram requires that the woms bit be set in the scr to wired-or rxd and txd, which causes txd to be three-stated when not transmitting. collisions (two devices transmitting simultaneously) must be avoided with this circuit by us- ing a protocol such as alternating transmit and receive periods. in the example, the 8051 is the master device because it controls the clock. there is a window during which stx must be written with the next byte to be transmitted to prevent the current word from being retrans- mitted. this window is from the time tdre goes high, which is halfway into the transmission of bit 1, until the middle of bit 6 (see figure 6-19(b)). of course, this assumes the clock remains continuous ?i.e., there is a second word. if the clock stops, the sci stops. the dsp is initially configured according to the protocol to either receive data or transmit data. if the protocol determines that the next data transfer will be a dsp transmit, the dsp will configure the sci for transmit and load stx (or stxa). when the master starts sclk, data will be ready and waiting. if the protocol determines that the next data transfer will be a dsp receive, the dsp will configure the sci for receive and will either poll the sci or enable interrupts. this methodology allows multiple slave processors to use the same data line. selection of individual slave processors can be under protocol control or by multiplexing sclk. note: tcm=0, rcm=1 and tcm=1,rcm=0 are not allowed in the synchronous mode. the results are undefined. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 40 serial communications interface motorola x:$fff0 15141312111098 76543210 sckp tmie tie rie ilie te re woms rwu wake sbk 0 0 0 0 sci control register (scr) (read/write) stir x:$fff2 15141312111098 76543210 1 scp cod cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 sci clock control register (sccr) (read/write) 1 tcm rcm clock input (skp = 0) b0 b1 b2 b3 b4 b5 b6 b7 transmit data (ssftd = 0) xxxxxx xx xx xx xx xx xx xx xxxxxxx receive data write stx 0 12345 6 7 sample example: interface to synchronous microcomputer buses rxd txd sclk ssftd wds2 wds1 wds0 8051 or 8096 p3.0 p3.1 1.5 t cyc figure 6-18 synchronous slave dsp56003/005 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 41 serial clock (int) stx write range first word synchronous mode, internal clock (master) stx write range max 5.5 serial clock cycles stx write range for no gap between words 1 and 2 trde tdre 0 by stx write txd (trans- mit data) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 second word serial clock (ext) stx write range first word note: in external clock mode, if data 2 is written after the middle of bit 6 of data 1, then the previous data is retransmitted and data 2 is transmitted after the retransmission of data 1. synchronous mode, internal clock (slave) stx write range trde tdre 0 by stx write txd (trans- mit data) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 second word stx write range figure 6-19 synchronous timing (a) master (b) slave note: in internal clock mode, if data 2 is written after the middle of bit 6 of data 1, then a gap of at least two serial bits is inserted between word 1 and word 2. the gap is bigger as stx is written later. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 42 serial communications interface motorola the assembly program shown in figure 6-20 uses the sci synchronous mode to transmit only the low byte of the y data rom contents. the program sets the reset vector to run the program after a hardware reset, puts the movep instruction at the sci transmit in- terrupt vector location, sets the memory wait states to zero, and configures the memory pointers, operating mode register, and the ipr. the sci is then configured and the interrupts are unmasked, which starts the data transfer. the jump-to-self instruction (lab0 jmp lab0) is used to wait while interrupts transfer the data. the program shown in figure 6-21 is the program for receiving data from the program present- ed in figure 6-20. the program sets the reset vector to run the program after hardware reset, puts the movep instruction to store the data in a circular buffer starting at $100 at the sci re- ceive interrupt vector location, puts another movep instruction at the sci receive interrupt vec- tor location, sets the memory wait states to zero, and configures the memory pointers and ipr. the sci is then configured and the interrupts are unmasked, which starts the data transfer. the jump-to-self instruction (lab0 jmp lab0) is used to wait while interrupts transfer the data. org p:0 ;reset vector jmp $40 ; org p:$18 ;sci transmit interrupt vector movep y:(r0)+,x:$fff4 ;transmit low byte of data org p:$40 movep #0,x:$fffe ;clear bcr move #$100,r0 ;data rom start address move #$ff,m0 ;size of data rom - wraps around at $200 movec #6,omr ;change operating mode to enable data rom movep #$c000,x:$ffff ;interrupt priority register movep #$1200,x:$fff0 ;8-bit synchronous mode movep #7,x:$ffe1 ;port c control register ?enable sci movec #0,sr ;unmask interrupts lab0 jmp lab0 ;wait in loop for interrupts figure 6-20 sci synchronous transmit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 43 6.3.7 asynchronous data asynchronous data uses a data format with embedded word sync, which allows an unsynchro- nized data clock to be synchronized with the word if the clock rate and number of bits per word is known. thus, the clock can be generated by the receiver rather than requiring a separate clock signal. the transmitter and receiver both use an internal clock that is 16 the data rate to allow the sci to synchronize the data. the data format requires that each data byte have an additional start bit and stop bit. in addition, two of the word formats have a parity bit. the multidrop mode used when scis are on a common bus has an additional data type bit. the sci can operate in full-duplex or half-du- plex modes since the transmitter and receiver are independent. the sci transmitter and receiver can use either the internal clock (tcm=0 and/or rcm=0) or an external clock (tcm=1 and/or rcm=1) or a combination. if a combination is used, the transmitter and receiver can run at different data rates. org p:0 ;reset vector jmp $40 ; org p:$14 ;sci receive data vector movep x:$fff4,y:(r0)+ ;receive low byte of data nop ;fast interrupt response movep x:$fff1,x0 ;receive with exception. ;read status register movep x:$fff4,y:(r0)+ ;receive low byte of data org p:$40 movep #0,x:$fffe ;clear bcr move #$100,r0 ;data rom start address move #$ff,m0 ; size of data rom ?wraps around at $200 movep #$c000,x:$ffff ;interrupt priority register movep #$900,x:$fff0 ;8-bit synchronous mode receive only movep #$c000,x:$fff2 ;clock control register external clock movep #7,x:$ffe1 ;port c control register ?enable sci movec #0,sr ;unmask interrupts lab0 jmp lab0 ;wait in loop for interrupts figure 6-21 sci synchronous receive f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 44 serial communications interface motorola 6.3.7.1 asynchronous data reception figure 6-22 illustrates initializing the sci data receiver for asynchronous data. the first step (1) resets the sci to prevent the sci from transmitting or receiving data. step two (2) selects the desired operation by programming the scr. as a minimum, the word format (wds2, wds1, and wds0) must be selected, and (3) the receiver must be enabled (re=1). if (4) interrupts are to be used, set rie equals one. use table 6-3 (a) through table 6-4 (b) to set (5) the baud rate (scp and cd0?d11 in the sccr). once the sci is completely con- figured, it is enabled by (6) setting the rxd bit in the pcc. the receiver is continually sampling rdx at the 16 clock rate to find the idle-start-bit transition edge. when that edge is detected (1) the following eight or nine bits, depending on the mode, are clocked into the receive shift register (see figure 6-23). once a complete byte is received, (2) the character is latched into the srx, and rdrf is set as well as the error flags, or, pe, and fe. if (3) interrupts are enabled, an interrupt is generated. the interrupt service routine, which can be a fast interrupt or a long interrupt, (4) reads the received character. reading the srx (5) automatically clears rdfr in the ssr and makes the srx ready to receive another byte. if (1) an fe, pe, or or occurs while receiving data (see figure 6-24), (2) rdrf is set because a character has been received; fe, pe, or or is set in the ssr to indicate that an error was detected. either (3) the ssr can be polled by software to look for errors, or (4) interrupts can be used to execute an interrupt service routine. this interrupt is different from the normal receive interrupt and is caused only by receive errors. the long interrupt service routine should (5) read the ssr to determine what error was detected and then (6) read the srx to clear rdrf and all three error flags. 6.3.7.2 asynchronous data transmission figure 6-25 illustrates initializing the sci data transmitter for asynchronous data. the first step (1) resets the sci to prevent the sci from transmitting or receiving data. step two (2) selects the desired operation by programming the scr. as a minimum, the word for- mat (wds2, wds1, and wds0) must be selected, and (3) the transmitter must be enabled (te=1). if (4) interrupts are to be used, set tie equals one. use table 6-3 (a) through table 6-4 (b) to set (5) the baud rate (scp and cd0?d11 in the sccr). once the sci is com- pletely configured, it can be enabled by (6) setting the txd bit in the pcc. transmission begins with (7) a preamble of ones. if polling is used to transmit data (see figure 6-26), the polling routine can look at either tdre or trne to determine when to load another byte into stx. if tdre is used (1), one byte may be loaded into stx. if trne is used (2), two bytes may be loaded into stx if enough time is allowed for the first byte to begin transmission (see section 6.3.2.4.2 ). if interrupts are used (3), then an interrupt is generated when stx is empty. the interrupt routine, which can be a fast interrupt or a long interrupt, writes (4) one byte into stx. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 45 x:$fff0 15141312111098 76543210 sckp tmie tie 1 ilie te 1 woms rwu wake sbk ssftd wds2 wds1 wds0 sci control register (scr) (read/write) stir x:$fff2 15141312111098 76543210 tcm scp cod cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 sci control register (sccr) (read/write) rcm 1. hardware or software reset 2. program scr with desired mode and features. 3. turn on receiver (re = 1). 4. optionally enable receiver interrupts (rie = 1). rie re 5. set the baud rate by programming the sccr. ccx function 0 gpio 1 serial interface prescaler if scp = 1, then divide by 8 if scp = 0, then divide by 1 divide by 1 to 4096 6. set the rxd bit in pcc to enable the sci receiver system. x:$ffe1 23 98 76543210 cc8 cc7 cc6 cc5 cc4 cc3 cc2 cc1 1 port c control register (pcc) 0 sci rxd note: if re is cleared while a valid character is being received, the reception of the character will be completed before the receiver is disabled. figure 6-22 asynchronous sci receiver initialization f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 46 serial communications interface motorola r8 fe pe or idle 1 tdre trne 1. the receiver is idle until a character is received in the data shift register. rxd 2. transferring the received character into srx sets rdrf in the ssr. 76543210 rdrf x:$fff1 status register (ssr) (read only) 3. if rie = 1 in scr, then an interrupt is generated. sci receive data receive interrupt service routine p:$0014 interrupt vector table 4. the receive interrupt service routine reads the received character. 5. reading srx clears rdrf in the ssr. figure 6-23 sci character reception 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 srx srx srx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 47 r8 fe pe or idle 1 tdre trne 3. ssr can be polled by software. 4. if rie = 1 in scr, then an interrupt with error is generated. 1. a character is received with at least one of the following errors: framing error (fe = bit 6 in ssr parity error (pe = bit 5 in ssr) overrun error (or = bit 4 in ssr) rxd 2. this sets rdrf and set or, pe, or fe in ssr. 76543210 rdrf x:$fff1 sci status register (ssr) (read only) sci receive data receive with exception interrupt service routine p:$0016 interrupt vector table 5. read ssr serial string of bad data xxxxxxxx at least one bit set 76543210 r8 fe pe or idle 1 tdre trne rdrf x:$fff1 sci status register (ssr) (read only) rie interrupt with exception 6. read srx. this clears rdrf in the ssr and clears the or, pe, and fe flags. figure 6-24 sci character reception with exception 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 srx srx srx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 48 serial communications interface motorola x:$fff0 15141312111098 76543210 sckp tmie 1 rie ilie 1 re woms rwu wake sbk ssftd wds2 wds1 wds0 sci control register (scr) (read/write) stir 1. hardware or software reset 2. program scr with desired mode and features. 3. turn on transmitter (te = 1). 4. optionally enable transmitter interrupts (tie = 1). tie te 5. set the sci clock prescaler bit and the clock divider bits in the sccr. 6 . set the txd bit in pcc to enable the sci transmitter system. ccx function 0 gpio 1 serial interface 7. the transmitter will first broadcast a preamble of ones before beginning data transmission: 10 ones will be transmitted for the 10-bit asynchronous mode. 11 ones will be transmitted for the 11-bit asynchronous mode. x:$ffe1 23 9876543210 cc8 cc7 cc6 cc5 cc4 cc3 cc2 1 cc0 port c control register (pcc) 0 sci txd note: if te is cleared while transmitting a character, the transmission of the character will be completed before the transmitter is disabled. figure 6-25 asynchronous sci transmitter initialization f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 49 x:$fff1 15141312111098 76543210 0 000000r8fepeor idle rdrf 1 1 sci status register (ssr) (read/write) 0 1. when stx is empty, then tdre = 1. 2. when stx is empty and the transmit data shift register is empty then trne = 1. 3. if tie = 1 in scr and tdre = 1 in ssr, then an interrupt is generated. tdre 6 . the character in stx is copied into transmit data shift register. trne is cleared. tdre is set. go to step 2 . trne 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 stx stx stx sci transmit data p:$0018 interrupt vector table transmit interrupt service routine 4. store one character into stx (a) 5. this clears tdre in ssr. txd x:$fff3 stxa figure 6-26 asynchronous sci character transmission f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 50 serial communications interface motorola if multidrop mode is being used and this byte is an address, stxa should be used in- stead of stx. writing stx or stxa (5) clears tdre in the ssr. when the transmit data shift register is empty (6), the byte in stx (or stxa) is latched into the transmit data shift register, trne is cleared, and tdre is set. there is a provision to send a break or preamble. a break (space) consists of a period of zeros with no start or stop bits that is as long or longer than a character frame. a pre- amble (mark) is an inverted break. a preamble of 10 or 11 ones (depending on the word length selected by wds2, wds1, and wds0) can be sent with the following procedure (see figure 6-27). (1) write the last byte to stx and (2) wait for tdre equals one. this is the byte that will be transmitted immediately before the preamble. (3) clear te and then again set it to one. momentarily clearing te causes the output to go high for one character frame. if te remains cleared for a longer period, the output will remain high for an even number of character frames until te is set. (4) write the first byte to follow the preamble into srx before the preamble is complete and resume normal transmis- sion. sending a break follows the same procedure except that instead of clearing te, sbk is set in the scr to send breaks and then reset to resume normal data transmission. the example presented in figure 6-28 uses the sci in the asynchronous mode to transfer data into buffers. interrupts are used, allowing the dsp to perform other tasks while the data transfer is occurring. this program can be tested by connecting the sci transmit and receive pins. equates are used for convenience and readability. the program sets the reset vector to run the program after reset, puts a movep instruc- tion at the sci receive interrupt vector location, and puts a movep and bclr at the sci transmit interrupt vector location so that, after transmitting a byte, the transmitter is dis- abled until another byte is ready for transmission. the sci is initialized by setting the in- terrupt level, which configures the scr and sccr, and then is enabled by writing the pcc. the main program begins by enabling interrupts, which allows data to be received. data is transmitted by moving a byte of data to the transmit register and by enabling in- terrupts. the jump-to-self instruction (send jmp send) is used to wait while interrupts transfer the data. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 51 1234 5 67891012 91012 3456 78 910 sbk = 0 sbk = 1 sbk = 1 sbk = 1 sbk = 0 d0 d1 d2 d3 d4 d5 d6 d7 stop idle line st 1. write the last byte to stx. 2. wait for trde = 1. the last byte is now in the transmit shift register. 3. clear te and set back to one. this queues the preamble to follow the last byte. 4. write the first byte to follow the preamble into srx. x:$fff0 15141312111098 76543210 sckp tmie tie rie ilie te re woms rwu wake sbk ssftd wds2 wds1 wds0 sci interface control register (scr) (read/write) stir toggle (1 - 0 - 1) to send a character time of all ones (marks) toggle (0 - 1 - 0) to send a character time of all zeros (spaces) marks (ones) st01234 567stopst last character preamble of 10 ones first character spaces (zeros) d4 d5 d6 d7 stop stop st d0 d1 character ends before break begins. start of break break period is an exact multiple of character times. start of break first character after break a stop bit at the end of the break will be inserted before the next character starts figure 6-27 transmitting marks and spaces * 10 or 11 ones/zeros will be sent depending on the word length specified by wds2, wds1, wds0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 52 serial communications interface motorola ;***************************************************************** ; sci async with interrupts and single byte buffers * ;***************************************************************** ;************************************************* ; sci and other equates * ;************************************************* start equ $0040 ;start of program pcc equ $ffe1 ;port c control register scr equ $fff0 ;sci interface control register sccr equ $fff2 ;sci clock control register srx equ $fff4 ;sci receive register stx equ $fff4 ;sci transmit register bcr equ $fffe ;bus control register ipr equ $ffff ;interrupt priority register rxbuf equ $100 ;receive buffer txbuf equ $200 ;transmit buffer ;************************************************* ; reset vector * ;************************************************* org p:$0000 jmp start ;************************************************* ; sci receive interrupt vector * ;************************************************* org p:$0014 ;load the sci rx interrupt vectors movep x:srx,y:(r0)+ ;put the received byte in the receive ;buffer. this receive routine is ;implemented as a fast interrupt. ;************************************************* ; sci transmit interrupt vector * ;************************************************* org p:$0018 ;load the sci tx interrupt vectors movep x:(r3)+,x:stx ;transmit a byte and ;increment the pointer in the ;transmit buffer. bclr #12,x:scr ;disable transmit interrupts figure 6-28 sci asynchronous transmit/receive example (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 53 ;***************************************************************** ; initialize the sci port and rx, tx buffer pointers * ;***************************************************************** org p:start ;start the program at location $40 ori #$03,mr ;mask interrupts temporarily movep #$c000,x:ipr ;set interrupt priority to 2 movep #$0b02,x:scr ;disable tx, enable rx interrupts ;enable transmitter, receiver ;point to point ;10-bit asynchronous ;(1 start, 8 data, 1 stop) movep #$0022,x:sccr ;use internal tx, rx clocks ;9600 bps movep #>$03,x:pcc ;select pins txd and rxd for sci move rxbuf,r0 ;initialize the receive buffer move txbuf,r3 ;initialize the transmit buffer ;************************************************* ; main program * ;************************************************* andi #$fc,mr ;re-enable interrupts move #>$41,x:(r3) ;move a byte to the transmit buffer move r0,x:(r3) bset #12,x:scr ;and enable interrupts so it ;will be transmitted send jmp send ;normally something more useful ;would be put here. end ;end of example. figure 6-28 sci asynchronous transmit/receive example (sheet 2 of 2) 6.3.8 multidrop multidrop is a special case of asynchronous data transfer. the key difference is that a pro- tocol is used to allow networking transmitters and receivers on a single data-transmission line. interprocessor messages in a multidrop network typically begin with a destination address. all receivers check for an address match at the start of each message. receivers with no address match can ignore the remainder of the message and use a wakeup mode to enable the receiver at the start of the next message. receivers with an address match can receive the message and optionally transmit an acknowledgment to the sender. the particular message format and protocol used are determined by the user? software. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 54 serial communications interface motorola these message formats include point-to-point, bus, token-ring, and custom configura- tions. the sci multidrop network is compatible with other leading microprocessors. figure 6-29 shows a multidrop system with one master and n slaves. the multidrop mode is selected by setting wds2 equals one, wds1 equals one, and wds0 equals zero. one possible protocol is to have a preamble or idle line between messages, followed by an address and then a message. the idle line causes the slaves to wake up and compare the address with their own address. if the addresses match, the slave receives the mes- sage. if the addresses do not match, the slave ignores the message and goes back to sleep. it is also possible to generate an interrupt when an address is received, eliminating the need for idle time between consecutive messages and addresses. it is also possible for each slave to look for more than one address, which allows each slave to respond to indi- vidual messages as well as broadcast messages (e.g., a global reset). 6.3.8.1 transmitting data and address characters transmitting data and address when the multidrop mode is selected is shown in figure 6-30. the output sequence shown is idle line, data/address, and the next character. in both cases, an ??is being transmitted. to send data, te must be toggled to send the idle line, and then ??must be sent to stx. sending the ??to the stx sets the ninth bit in the frame to zero, which indicates that this frame contains data. if the ??is sent to stxa instead, the ninth bit in the frame is set to a one, which indicates that this frame contains an address. 6.3.8.2 wired-or mode building a multidrop bus network requires connecting multiple transmitters to a com- mon wire. the wired-or mode allows this to be done without damaging the transmitters when the transmitters are not in use. a protocol is still needed to prevent two transmitters from simultaneously driving the bus. the sci multidrop word format provides an ad- dress field to support this protocol. figure 6-31 shows a multidrop configuration using wired-or (set bit 7 of the scr). the protocol shown consists of an idle line between mes- sages; each message begins with an address character. the message can be any length, de- pending on the protocol. each processor in this system has one address that it responds to although each processor can be programmed to respond to more than one address. 6.3.8.3 idle line wakeup a wakeup mode frees a dsp from reading messages intended for other processors. the usual operational procedure is for each dsp to suspend sci reception (the dsp can con- tinue processing) until the beginning of a message. each dsp compares the address in the message header with the dsps address. if the addresses do not match, the sci again sus- pends reception until the next address. if the address matches, the dsp will read and pro- cess the message and then suspend reception until the next address. the idle line wakeup mode wakes up the sci to read a message before the first character arrives. this mode allows the message to be in any format. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 55 x:$fff0 15141312111098 76543210 sckp tmie tie rie ilie te re woms rwu wake sbk ssftd 1 1 0 sci control register (sccr) (read/write) stir wds2 wds1 wds0 header idle line address 1 long message for mpu 1 idle line rxd dsp56003/005 address 1 rxd dsp56003/005 address 2 rxd mc68hc11 address 3 rxd other serial device address n txd dsp56003/005 device receiving message receiver interrupt does header equal my address ? no receive rest of message; do not mask interrupts. yes exit devices ignoring messages receiver interrupt does header equal my address ? no yes ignore rest of message. disable receiver and its interrupts by setting rwu = 1. exit figure 6-29 11-bit multidrop mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 56 serial communications interface motorola st1 00000101stopst st1 000001 00stopst data next character 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 stx stx stx sci transmit data register high (write only) sci transmit data register mid (write ony) sci transmit data register low (write only) x:$fff3 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 stx stx stx txd txd stxa sci transmit data shift register 23 16 15 8 7 0 ? $41 01000001 data address sci transmit data shift register x:$fff3 stxa 23 16 15 8 7 0 idle line address next character idle line sci transmit data register (write only) ? figure 6-30 transmitting data and address characters f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 57 n0 n1 n2 n3 n4 n5 n6 n7 1 d0 d1 d2 d3 d4 d5 d6 d7 0 d0 d1 x:$fff0 15141312111098 76543210 sckp tmie tie rie ilie te re 1 rwu wake sbk ssftd 1 1 0 sci control register (scr) (read/write) stir woms wds2 wds1 wds0 dsp56003/005 sci port address 1 xmit rec dsp56003/005 sci port address 2 xmit rec other serial port address 3 xmit rec dsp56003/005 sci port address n-1 xmit rec dsp56003/005 sci port address n xmit rec a2 message a a3 message c a1 message b address character wakeup and/or interrupt idle idle line wakeup and/or interrupt first character second character third character address n first character of message d second character of message d indicates an address character indicates a data character 1k an message d figure 6-31 wired-or mode idle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 58 serial communications interface motorola figure 6-32 shows how to configure the sci to detect and respond to an idle line. the word format chosen (wds2, wds1, and wds0 in the scr) must be asynchronous. the wake bit must be clear to select idle line wakeup, and rwu must be set to put the sci to ?leep?and enable the wakeup function. rie should be set if interrupts are to be used to receive data. if processing must occur when the idle line is first detected, ilie should be set. the current message is followed by one or more data frames of ones (10 or 11 bits each, depending on which word format is used), which are detected as an idle line. if the word format is multidrop (an 11-bit code), after the 11 ones, the receiver determines the line is idle and (1) clears the rwu, enabling the receiver. the idle bit (2) and an internal flag sriint (3) are set, indicating the line is idle. the sci is now ready to receive messag- es; however, nothing more will happen until the next start bit unless (4) ilie is set. if ilie is set, an sci idle line interrupt will be recognized as pending. when the idle line interrupt is recognized (5), sriint is automatically cleared, and the sci waits for the first start bit of the next character. since rie was set, when the first character is received, an sci receive data interrupt (or sci receive data with exception status interrupt if an error is detected) will be recognized as pending. when the receiver has processed the message and is ready to wait for another idle line, rwu must be set to one again. 6.3.8.4 address mode wakeup the purpose and basic operational procedure for address mode wakeup is the same as idle line wakeup. the difference is that address mode wakeup re-enables the sci when the ninth bit in a character is set to one (if cleared, this bit marks a character as data; if set, an address). as a result, an idle line is not needed, which eliminates the dead time between messages. if the protocol is such that the address byte is not needed or is not wanted in the first byte of the message, a data byte can be written to stxa at the beginning of each mes- sage. it is not essential that the first byte of the message contain an address; it is essential that the start of a new message is indicated by setting the ninth bit to one using stxa. figure 6-33 shows how to configure the sci to detect and respond to an address character. the word format chosen (wds2, wds1, and wds0 in the scr) must be an asynchronous word format. the wake bit must be set to select address mode wakeup and rwu must be set to put the sci to ?leep?and enable the wakeup function. rie should be set if in- terrupts are to be used to receive data. (1) when an address character (ninth bit=1) is re- ceived, then r8 is set to one in the ssr, and rwu is cleared. clearing rwu re-enables the sci receiver. since (2) rie was set in this example, when the first character is received, an sci receive data interrupt (or sci receive data with exception status interrupt if an error is detected) will be recognized as pending. when the receiver is ready to wait for another address character, rwu must be set to one again. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 59 x:$fff0 15141312111098 76543210 sckp tmie tie 1 1 te re woms 1 0 sbk ssftd wds2 wds1 wds0 sci control register (scr) (read/write) stir rie ilie rwu wake 76543210 r8 fe pe or 1 rdrf tdre trne x:$fff1 sci status register (ssr) (read only) sci idle line p:$001a interrupt vector table a1 message a a2 message b line is idle for 10 or 11 stop bits 1. rwu is cleared; the receiver is enabled. 2. idle is set in ssr, indicating the line is idle. 3. an internal flag sriint is generated once each idle state, no matter how long it lasts. idle (sriint) 4. if ilie = 1 in scr, then an sci idle line interrupt is pending. 5. when idle line interrupt is accepted, sriint is automatically cleared. idle line interrupt service routine (fast or long) figure 6-32 idle line wakeup f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 60 serial communications interface motorola x:$fff0 15141312111098 76543210 sckp tmie tie 1 ilie te re woms 1 1 sbk ssftd wds2 wds1 wds0 sci control register (scr) (read/write) stir rie rwu wake 70 1 fe pe or 1 rdrf tdre trne x:$fff1 sci status register (ssr) (read only) sci receive data p:$0014 interrupt vector table a1 message a a2 message b 1. when address character is received, then r8 = 1 in ssr and rwu is cleared. the receiver wakes up. 2. if rie = 1 in scr, then an sci receive data interrupt is processed. receive data interrupt service routine (fast or long) a3 message c a4 message d r8 figure 6-33 address mode wakeup f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 61 6.3.8.5 multidrop example the program shown in figure 6-34 configures the sci as a multidrop master transmitter and slave receiver (using wakeup on address bit) that uses interrupts to transmit data from a circular buffer and to receive data into a different circular buffer. this program can be run with the i/o pins (rxd and txd) connected and with a pullup resistor for test purposes. the program starts by setting equates for convenience and clarity and then points the re- set vector to the start of the program. the receive and transmit interrupt vector locations have jsrs forming long interrupts because the multidrop protocol and circular buffers re- quire more than two instructions for maintenance. byte packing and unpacking are not used in this example. the srx and stx registers are equated to $fff4, causing only the lsb of the 24-bit dsp word to be used for sci data. the sci is then initialized as wired-or, multidrop, and using interrupts. the sci is enabled but the interrupts are masked, which prevents the sci from transmitting or receiving data at this time. the circular buffers used have two pointers. the first points to the first data byte; the sec- ond points to the last data byte. this configuration allows the transmit buffer to act as a first-in first-out (fifo) memory. the fifo can be loaded by a program and emptied by the sci in real time. as long as the number of data bytes never exceeds the buffer size, there will be no overflow or underflow of the buffer. registers m0-m3 must be loaded with the buffer size minus one to make pointer registers r0-r3 work as circular pointers. register n2 is used as a constant to clear the receive buffer empty flag. the main program starts by filling the transmit buffer with a data packet. when the trans- mit buffer is full, it calls the subroutine that transmits the slave? address and then jumps to self (send jmp send), allowing interrupts to transmit and receive the data. the receive subroutine first checks each byte to see if it is address or data. if it is an address, it compares the address with its own. if the addresses do not match, the sci is put back to sleep. if the addresses match, the sci is left awake, and control is returned to the main pro- gram. if the byte is data, it is placed in the receive buffer, and the receive buffer empty flag is cleared. although this flag is not used in this program, it can be used by another program as a simple test to see if data is available. using n2 as the constant $0 allows the flag to be cleared with a single-word instruction, which can be part of a fast interrupt. the transmit subroutine transmits a byte and then checks to see if the transmit buffer is empty. if the buffer is not empty, control is returned to the main program, and interrupts are allowed to continue emptying the buffer. if the buffer is empty, the transmit buffer emp- ty flag is set, the transmit interrupt is disabled, and control is returned to the main program. the wakeup subroutine transmits the slave? address by writing the address to the stxa register and by enabling the transmit interrupt to allow interrupts to empty the transmit buffer. control is then returned to the main program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 62 serial communications interface motorola ; **************************************************************** ; multidrop master/slave with interrupts and circular buffers * ;*************************************************************** ;************************************************* ; sci and other equates * ;************************************************* start equ $0040 ;start of program tx_buff equ $0010 ;transmit buffer location rx_buff equ $0020 ;receive buffer location b_size equ $000e ;transmit and receive buffer size ;(don? allow the tx buffer and rx ;buffers to overlap). tx_mty equ $0000 ;transmit buffer empty rx_mty equ $0001 ;receive buffer empty pcc equ $ffe1 ;port c control register scr equ $fff0 ;sci interface control register sccr equ $fff2 ;sci clock control register stxa equ $fff3 ;sci transmit address register srx equ $fff4 ;sci receive register stx equ $fff4 ;sci transmit register bcr equ $fffe ;bus control register ipr equ $ffff ;interrupt priority register ;************************************************* ; reset vector * ;************************************************* org p:$0000 jmp start ;************************************************* ; sci receive interrupt vector * ;************************************************* org p:$0014 ;load the sci rx interrupt vectors jsr rx ;jump to the receive routine that puts ;data packet in a circular buffer if it ;is forthis address. nop ;second word of fast interrupt not need ed figure 6-34 multidrop transmit receive example (sheet 1 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 63 org p:$0016 ;this interrupt occurs when data is ;received with errors. this example nop ;does not trap errors so this nop ;interrupt is not used. ;************************************************* ; sci transmit interrupt vector * ;************************************************* org p:$0018 ;load the sci tx interrupt vectors jsr tx ;transmit next byte in buffer nop ;************************************************* ; initialize the sci port * ;************************************************* org p:start ;start the program at location $40 ori #$03,mr ;mask interrupts temporarily movep #$c000,x:ipr ;set interrupt priority to 2 movep #$0be6,x:scr ;disable tx, enable rx interrupts ;enable transmitter and receiver, ;wired-or mode, rec. wakeup ;mode,11-bit multidrop (1 start, ;8 data,1 data type, 1 stop) movep #$0000,x:sccr ;use internal tx, rx clocks ;625k bps at 40 mhz movep #>$03,x:pcc ;select pins txd and rxd for sci ;************************************************** ;initialize interrupts, registers, etc. * ;************************************************** movep #$0,x:bcr ;no wait states move #tx_buff,r0 ;load start pointer of transmit buffer move #tx_buff,r1 ;load end pointer of transmit buffer move #rx_buff,r2 ;load start pointer of receive buffer move #rx_buff,r3 ;load end pointer of receive buffer move #>$41,r5 ;init data register... r5 contains ;the data that will be sent in this ;example; it is initialized to an ascii a. figure 6-34 multidrop transmit receive example (sheet 2 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 64 serial communications interface motorola move #b_size,m0 ;load transmit buffer size move #b_size,m1 ;load transmit buffer size move #b_size,m2 ;load receive buffer size move #b_size,m3 ;load receive buffer size move #>$1,n0 ;load receive address move #>$1,n1 ;load first slave address move #0,n2 ;load a constant (0) into n2 movep x:srx,x:(r0) ;clear receive register ;************************************************** ; main program * ;************************************************** andi #$fc,mr ;re-enable interrupts move (r1)+ ;temporarily increment the tail pointer ;build a packet loop move r1,a ;check to see if the tx buffer is full move (r1)- ;(fix tail pointer now that we?e used it) move r0,b ;by comparing the head and tail pointers cmp a,b ;of the circular transmit buffer. jeq snd_buf ;if equal, transmit completed packet move r5,x:(r1)+ ;if not, put next character in ;transmit buffer and move (r5)+ ;increment the pointers. move (r1)+ ;temporarily increment the tail ;pointer to test buffer again jmp loop snd_buf jsr wake_up ;wake up proper slave and send packet send jmp send ;and allow interrupts to drain ;the transmit buffer. figure 6-34 multidrop transmit receive example (sheet 3 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 65 ;********************************************************************** ; subroutine to read sci and store in buffer using a long interrupt * ;********************************************************************** rx jclr #7,x:$fff1,rx_data ;check if this is address or data. movep x:srx,a ;compare the received address move n1,b ;with the slave address. cmp a,b jeq end_rx ;if address ok, use interrupts to rx ;packet bset #6,x:$fff0 ;if not, go back to sleep jmp end_rx ;and return to previous program. rx_data movep x:srx,x:(r3)+ ;put data in buffer, move n2,x:rx_mty ;and clear the rx buffer empty flag end_rx rti ;return to previous program ;********************************************************************** ; subroutine to write buffer to sci using a long interrupt * ;********************************************************************** tx movep x:(r0)+,x:stx ;transmit a byte and increment the ;pointer move r0,a ;check to see if the tx buffer is ;empty move r1,b cmp a,b jne end_tx ;if not, return to main move #$000001,x0 ;if it is, set the tx buffer empty flag move x0,x:tx_mty bclr #12,x:scr ;disable transmit interrupts, and end_tx rti ;return to main ;********************************************************************** ; subroutine to wake up the addressed slave * ;********************************************************************** wake_up movep n1,x:stxa ;transmit slave address using stxa ;not stx bset #12,x:scr ;enable transmit interrupts to send ;packet awake rti end ;end of example. figure 6-34 multidrop transmit/receive example (sheet 4 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 66 serial communications interface motorola 6.3.9 sci timer the sci clock determines the data transmission rate and can also be used to establish a periodic interrupt that can act as an event timer or be used in any other timing function. figure 6-35 illustrates how the sci timer is programmed. bits cd11?d0, scp, and stir in the sccr work together to determine the time base. the crystal oscillator f osc is first divided by 2 and then divided by the number cd11?d0 in the sccr. the oscillator is then divided by 1 (if scp=0) or eight (if scp=1). this output is used as is if stir = 1 or, if stir = 0, it is divided by 2 and then by 16 before being used. if tmie in the scr = 1 when the periodic timeout occurs, the sci timer interrupt is recognized and pending. the sci timer interrupt is automatically cleared when the interrupt is serviced. this interrupt will occur every time the periodic timer times out. if only the timer function is being used (i.e., pc0, pc1, and pc2 pins have been programmed as gpio pins), the transmit interrupts should be turned off (tie=0). under individual reset, tdre will remain set and the timer will continuously generate interrupts. figure 6-35 shows that an external clock can be used for sci receive and/or transmit, which frees the sci timer to be programmed for a different interrupt rate. in addition, both the sci timer interrupt and the sci can use the internal time base if the sci receiver and/or transmitter require the same clock period as the sci timer. the program in figure 6-36 configures the sci to interrupt the dsp at fixed intervals. the program starts by setting equates for convenience and clarity and then points the reset vector to the start of the program. the sci timer interrupt vector location contains ?ove (r0)+? incrementing the contents of r0, which serves as an elapsed time counter. the timer initialization consists of enabling the sci timer interrupt, setting the sci baud rate counters for the desired interrupt rate, setting the interrupt mask, enabling the inter- rupt, and then enabling the sci state machine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 67 ;******************************************************************** 1 0 x:$fff2 1514131211109876543210 tcm scp cod cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 rcm sci control register (sccr) (read/write) sclk sci timer p:$001c interrupt vector table divide by 2 prescaler if scp = 1, then divide by 8 if scp = 0, then divide by 1 divide by 1 to 4096 divide by 2 f osc x:$fff0 1514131211109876543210 0 1 tie rie ilie te re woms rwu wake sbk 0 wds2 wds1 wds0 0 output divider if sync, then divide by 2 if async then: cod = 1, divide by 1 cod = 0, divide by 16 transmit control if async, then divide by 16 if sync then: master, divide by 2 slave, divide by 1 receive control if async, then divide by 16 if sync then: master, divide by 2 slave, divide by 1 periodic timer divide by 16 cod rcm tcm sckp sckp tcm transmit clock receive clock e x t e r n a l c l o c k i n t e r n a l c l o c k 1 0 sci control register (scr) (read/write) tmie 1. when periodic timeout occurs and tmie = 1 in scr, then an sci timer exception is taken. sci timer interrupt service routine (fast or long) 2. pending timer interrupt is automatically cleared when interrupt is serviced. figure 6-35 sci timer operation stir sckp ssftd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 68 serial communications interface motorola ; timer using sci timer interrupt * ;******************************************************************** ;************************************************* ; sci and other equates * ;************************************************* start equ $0040 ;start of program scr equ $fff0 ;sci control register sccr equ $fff2 ;sci clock control register ipr equ $ffff ;interrupt priority register ;************************************************* ; reset vector * ;************************************************* org p:$0000 jmp start ;************************************************* ; sci timer interrupt vector * ;************************************************* org p:$001c ;load the sci timer interrupt vectors move (r0)+ ;increment the timer interrupt counter nop ;this timer routine is implemented ;as a fast interrupt ;************************************************* ; initialize the sci port * ;************************************************* org p:start ;start the program at location $40 move #0,r0 ;initialize the timer interrupt counter movep #$2000,x:scr ;select the timer interrupt movep #$013f,x:sccr ;set the interrupt rate at 1 ms ;(arbitrarily chosen) ;interrupts/second = ;fosc/(64 x (7(scp)-+1) x (cd+1)) ;note that this is the same equation ;as for sci async baud rate figure 6-36 sci timer example (sheet 1 of 2) ;for 1 ms, scp=0, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 69 ;cd=0001 0011 1111. movep #$c000,x:ipr ;set the interrupt priority level ;application specific. andi #$fc,mr ;enable interrupts, set mr bits i1 and ;i0=0 end jmp end ;normally something more useful ;would be put here. end ;end of example. figure 6-36 sci timer example (sheet 2 of 2) 6.3.10 bootstrap loading through the sci (operating mode 6) when the dsp comes out of reset, it looks at the modc, modb, and moda pins and sets the corresponding mode bits in the omr. if the mode bits are set to 110 respec- tively, the dsp will load the program ram from the sci. figure 6-37 shows how the sci is con?ured for receiving this code and figure 6-37 shows the segment of bootstrap code that is used to load from the sci. the complete code used in the bootstrap program is given in appendix a. this program (1) con?ures the sci, (2) loads the program size, (3) loads the location where the program will begin loading in program memory, and (4) loads the program. first, the sci control register is set to $0302 (see figure 5-2) which enables the trans- mitter and receiver and con?ures the sci for 10 bits asynchronous with one start bit, 8 data bits, one stop bit, and no parity. next, the sci clock control register is set to $c000 which con?ures the sci to use external receive and transmit clocks on the sclk pin. this clock must be 16 times the serial data rate. the next step is to receive the program size and then the starting address to load the program. these two numbers are three bytes each loaded least signi?ant byte ?st. each byte will be echoed back as it is received. after both numbers are loaded, the pro- gram size is in a0 and the starting address is in a1. the program is then loaded one byte at a time, least signi?ant byte ?st. after loading the program, the operating mode is set to zero, the ccr is cleared, and the dsp begins execution with the ?st instruction that was loaded. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 70 serial communications interface motorola 6.3.11 example circuits the sci can be used in a number of configurations to connect multiple processors. the synchronous mode shown in figure 6-39 shows the dsp acting as a slave. the 8051 pro- vides the clock that clocks data in and out of the sci, which is possible because the sci shift register mode timing is compatible with the timing for 8051/8096 processors. trans- mit data is changed on the negative edge of the clock, and receive data is latched on the positive edge of the clock. a protocol must be used to prevent both processors from trans- mitting simultaneously. the dsp is also capable of being the master device. a multimaster system can be configured (see figure 6-40) using a single transmit/receive line, multidrop word format, and wired-or. the use of wired-or requires a pullup resis- tor as shown. a protocol must be used to prevent collisions. this scheme is physically the simplest multiple dsp interconnection because it uses only one wire and one resistor. dsp56003/005 moda/irqa reset modb/irqb mbd301 * +5 v from open collector buffer from reset function from open collector buffer br hack modc/nmi wt dr notes: 1. * these diodes must be schottky diodes. 2. all resistors are 15k w unless noted otherwise. 3. when in reset, irqa , irqb and nmi must be deasserted by external peripherals. sclk rxd txd 16xclk serial bootstrap loader (1 start, 8 data, 1 stop, lsb first) no parity, figure 6-37 dsp56003/005 bootstrap example - mode 6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 71 ; this is the routine that loads from the sci. ; mc:mb:ma=110 - external sci clock ; mc:mb:ma=111 - reserved org pl:$0d00,pl:$0d00 ; starting address of 2nd rom scild movep #$0302,x:scr ; configure sci control reg movep #$c000,x:sccr ; configure sci clock control reg movep #7,x:pcc ; configure sclk, txd and rxd _sci1 do #6,_loop6 ; get 3 bytes for number of ; program words and 3 bytes ; for the starting address jclr #2,x:ssr,* ; wait for rdrf to go high movep x:srxl,a2 ; put 8 bits in a2 jclr #1,x:ssr,* ; wait for tdre to go high movep a2,x:stxl ; echo the received byte rep #8 asr a _loop6 move a1,r0 ; starting address for load move a1,r1 ; save starting address do a0,_loop4 ; receive program words do #3,_loop5 jclr #2,x:ssr,* ; wait for rdrf to go high movep x:srxl,a2 ; put 8 bits in a2 jclr #1,x:ssr,* ; wait for tdre to go high movep a2,x:stxl ; echo the received byte rep #8 asr a _loop5 movem a1,p:(r0)+ ; store 24-bit result in p mem. _loop4 jmp finish+1 ; boot from sci done figure 6-38 bootstrap code fragment f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) 6 - 72 serial communications interface motorola the master-slave system shown in figure 6-41 is different in that it is full duplex. the clock pin is not required; thus, it is configured as a gpio pin. communication is asyn- chronous. the slave? transmitters must be wire-ored because more than one transmitter is on one line. the master? transmitter does not need to be wire-ored. clock input transmit data receive data 1.5 c cyc b0 b1 b2 b3 b4 b5 b6 b7 xxxxxx xx xx xx xx xx xx xx xxxxxxx sample 01234567 dsp56003/005 8051 rxd txd sclk p3.0 p3.1 figure 6-39 synchronous mode example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communication interface (sci) motorola serial communications interface 6 - 73 dsp56003/005 master txd rxd pc2 dsp56003/005 master txd rxd pc2 figure 6-40 multimaster system example mc68hc11 master rxd txd pc2 master receive master transmit dsp56003/005 slave rxd txd pc2 dsp56003/005 slave rxd txd pc2 dsp56003/005 slave rxd txd pc2 figure 6-41 master-slave system example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 7 - 1 section 7 synchronous serial interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 7 - 2 synchronous serial interface motorola paragraph number page number section 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 general-purpose i/o (port c) . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.3 synchronous serial interface (ssi) . . . . . . . . . . . . . . . . . . 7-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola synchronous serial interface 7 - 3 7.1 introduction port c is a triple-function i/o port with nine pins (see figure 7-1). three of the nine pins can be configured as general-purpose i/o or as the serial communication interface (sci) pins. the other six pins can also be configured as gpio, or they can be configured as the synchronous serial interface (ssi) pins. when configured as general-purpose i/o, port c can be used for device control. when the pins are configured as a ssi, port c provides a convenient connection to oth- er dsps, processors, codecs, digital-to-analog and analog-to-digital converters, and any of several transducers. this port c (ssi and gpio) is identical to the one on the dsp56001 and dsp56002. external address switch external data switch bus control host/dma parallel interface sci interface ssi interface port a i/0 (47) port c i/0 (9) port b i/0 (15) a0 - a15 d0 - d23 ps ds x/y extp rd wr bn br bg wt bs pb0 - pb7 pb8 pb9 pb10 pb11 pb12 pb13 pb14 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 h0 - h7 ha0 ha1 ha2 hr/w hen hreq ha ck or pb14 rxd txd sclk sc0 sc1 sc2 sck srd std default function alternate function 8 8 24 16 figure 7-1 port c interface dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) 7 - 4 synchronous serial interface motorola 7.2 general-purpose i/o (port c) when it is configured as gpio, port c can be viewed as nine i/o pins (see figure 7-2), which are controlled by three memory-mapped registers. these registers are the port c control register (pcc), port c data direction register (pcddr), and port c data register (pcd) (see figure 7-3). reset configures port c as general-purpose i/o with all 9 pins as inputs by clearing both the control (pcc), and data direction (pcddr) registers (external circuitry connected to these pins may need pullups until the pins are configured for operation). there are three registers associated with each external pin. each port c pin may be individually programmed as a gen- eral-purpose i/o pin or as a dedicated on-chip peripheral pin under software control. pin se- lection between general-purpose i/o and sci or ssi is made by setting the appropriate pcc bit (memory location x:$ffe1) to zero for general-purpose i/o or to one for serial interface. the pcddr (memory location x:$ffe3) programs each pin corresponding to a bit in the pcd (memory location x:$ffe5) as an input pin (if pcddr=0) or as an output pin (if pcddr=1). if a pin is configured as a gpio input (as shown in figure 7-4) and the processor reads the pcd, the processor sees the logic level on the pin. if the processor writes to the pcd, the data is latched there, but does not appear on the pin because the buffer is in the high-impedance state. if a pin is configured as a gpio output and the processor reads the pcd, the processor sees the contents of the pcd rather the logic level on the pin, which allows the pcd to be used as a general purpose 15-bit register. if the processor writes to the pcd, the data is latched there and appears on the pin during the following instruction cycle (see section 7.2.2 ). p o r t c pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 cc0 cc1 cc2 cc3 cc4 cc5 cc6 cc7 cc8 cd0 cd1 cd2 cd3 cd4 cd5 cd6 cd7 cd8 enabled by bits in x:$ffe1 direction selected by x:$ffe3 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 input/output data register x:$ffe5 figure 7-2 port c gpio control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) motorola synchronous serial interface 7 - 5 if a pin is configured as a serial interface (sci or ssi) pin, the port c gpio registers can be used to help in debugging the serial interface. if the pcddr bit for a given pin is cleared (configured as an input), the pcd will show the logic level on the pin, regardless of whether the serial interface function is using the pin as an input or an output. if the pcddr is set (con?ured as an output) for a given serial interface pin, when the proces- sor reads the pcd, it sees the contents of the pcd rather than the logic level on the pin another case which allows the pcd to act as a general purpose register. 7.2.1 programming general purpose i/o port c and all the dsp56003/005 peripherals are memory mapped (see figure 7-5). the standard move instruction transfers data between port c and a register; as a result, performing a mem- ory-to-memory data transfer takes two move instructions and a register. the movep instruc- tion is specifically designed for i/o data transfer as shown in figure 7-6. although the movep instruction may take twice as long to execute as a move instruction, only one movep is re- quired for a memory-to-memory data transfer, and movep does not use a temporary register. 000000000000000 cc 0 23 0 x:$ffe1 port c control register (pcc) ccx function 0 gpio 1 serial interface cd 0 23 0 x:$ffe3 port c data direction register (pcddr) cdx data direction 0 input 1 output 000000000000000 cd 1 cd 2 cd 3 cd 4 cd 5 cd 6 cd 7 cd 8 pd 0 23 0 x:$ffe5 port c data register (pcd) 000000000000000 pd 1 pd 2 pd 3 pd 4 pd 5 pd 6 pd 7 pd 8 cc 1 cc 2 cc 3 cc 4 cc 5 cc 6 cc 7 cc 8 std srd sck sc2 sc1 sc0 sclk txd rxd ssi sci note: hardware and software reset clears pcc and pcddr. figure 7-3 port c gpio registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) 7 - 6 synchronous serial interface motorola using the movep instruction allows a fast interrupt to move data to/from a peripheral to mem- ory and execute one other instruction or to move the data to an absolute address. movep is the only memory-to-memory move instruction; however, one of the operands must be in the top 64 locations of either x: or y: memory. the bit-oriented instructions which use i/o short address- ing (bchg, bclr, bset, btst, jclr, jsclr, jset, and jsset) can also be used to address in- dividual bits for faster i/o processing. the dsp does not have a hardware data strobe to strobe data out of the gpio port. if a data strobe is needed, it can be implemented using software to toggle one of the gpio pins. figure 7-7 shows the process of programming port c as general-purpose i/o. nor- mally, it is not good programming practice to activate a peripheral before program- ming it. however, reset activates the port c general-purpose i/o as all inputs, and the alternative is to configure the port as an sci and/or ssi, which may not be de- sirable. in this case, it is probably better to insure that port c is initially configured for general-purpose i/o and then configure the data direction and data registers. port registers input data bit data direction bit output data bit port input data bit port control register bit data direction register bit pin function 0 0 port input pin pin port c data (pcd) register bit data direction register (pcddr) port c control (pcc) register bit (gpio position) (input position) peripheral logic figure 7-4 port c i/o pin control logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) motorola synchronous serial interface 7 - 7 it may be better in some situations to program the data direction or the data regis- x:$ffff x:$fffe x:$fffd x:$fffc x:$fffb x:$fffa x:$fff9 x:$fff8 x:$fff7 x:$fff6 x:$fff5 x:$fff4 x:$fff3 x:$fff2 x:$fff1 x:$fff0 x:$ffef x:$ffee x:$ffed x:$ffec x:$ffeb x:$ffea x:$ffe9 x:$ffe8 x:$ffe7 x:$ffe6 x:$ffe5 x:$ffe4 x:$ffe3 x:$ffe2 x:$ffe1 x:$ffe0 x:$ffdf x:$ffde x:$ffdd x:$ffdc x:$ffdb x:$ffda x:$ffd9 x:$ffd8 x:$ffd7 x:$ffd6 x:$ffd5 x:$ffd4 interrupt priority register (ipr) port a ?bus control register (bcr) pll control register once port gdb register reserved reserved reserved reserved reserved sci hi - rec/xmit data register (srx/stx) sci mid - rec/xmit data register (srx/stx) sci low - rec/xmit data register (srx/stx) sci transmit data address register (stxa) sci control register (sccr) sci interface status register (ssr) sci interface control register (scr) ssi recieve/transmit data register (rx/tx) ssi status/time slot register (ssisr/tsr) ssi control register b (crb) ssi control register a (cra) host receive/transmit register (hrx/htx) reserved host status register (hsr) host control register (hcr) watchdog timer count register (wcr) watchdog timer control/status register (wcsr) port c ?data register (pcd) port b ?data register (pbd) port c ?data direction register (pcddr) port b ?data direction register (pbddr) port c ?control register (pcc) port b ?control register (pbc) timer count register (tcr) timer control/status register (tcsr) reserved pwma2 count register (pwacr2) pwma1 count register (pwacr1) pwma0 count register (pwacr0) pwma prescaler register (pwacsr0) pwma control and status register (pwacsr1) pwmb1 count register (pwbcr1) pwmb0 count register (pwbcr0) pwmb prescaler register (pwbcsr0) pwmb control and status register (pwbcsr1) x:$ffc0 reserved = read as random number; write as don? care. 23 16 15 8 7 0 figure 7-5 on-chip peripheral memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) 7 - 8 synchronous serial interface motorola ters first to prevent two devices from driving one signal. the order of steps 1, 2, and 3 in figure 7-7 is optional and can be changed as needed. 7.2.2 port c general purpose i/o timing parallel data written to port c is delayed by one instruction cycle. for example, the following instruction: move data9,x:portc data24,y:extern 1. writes nine bits of data to the port c register, but the output pins do not change until the following instruction cycle 2. writes 24 bits of data to the external y memory, which appears on port a dur- ing t2 and t3 of the current instruction as a result, if it is necessary to synchronize the port a and port c outputs, two instruc- tions must be used: move data9,x:portc nop data24,y:extern : : movep #$0,x:$ffe1 ;select port c to be general-purpose i/o movep #$01f0,x:$ffe3 ;select pins pc0?c3 to be inputs : ;and pins pc4?c8 to be outputs : movep #data_out,x:$ffe5 ;put bits 4? of ?ata_out?on pins ;pb4?b8 bits 0? are ignored. movep x:$ffe0,#data_in ;put pb0?b3 in bits 0? of ?ata_in figure 7-6 write/read parallel data with port c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general-purpose i/o (port c) motorola synchronous serial interface 7 - 9 the nop can be replaced by any instruction that allows parallel moves. inserting one or more ?ove data15,x:portc data24,y:extern?instructions between the first and second instruction produces an external 33-bit write each instruction cycle with only one instruction cycle lost in setup time: move data9,x:portc move data9,x:portc data24,y:extern move data9,x:portc data24,y:extern : : move data9,x:portc data24,y:extern nop data24,y:extern one application of this technique is to create an extended address for port a by concate- nating the port a address bits (instead of data bits) to the port c general-purpose output bits. the port c general-purpose i/o register would then work as a base address register, allowing the address space to be extended from 64k words (16 bits) to 33.5 million words (16 bits+ 9 bits=25 bits). cc 1 cd 0 cd 1 cd 2 cd 3 cd 4 cd 5 cd 6 cd 7 cd 8 pc 0 pc 1 pc 2 pc 3 pc 4 pc 5 pc 6 pc 7 pc 8 step 1. select each pin to be general-purpose i/o or an on-chip peripheral pin: ccx = 0 general- purpose i/o ccx = 1 on-chip peripheral x:$ffe1 80 port c control register (pcc) x:$ffe3 port c data direction register (pcddr) 80 step 2. set each general - purpose i/o pin (selected above) as input or output: cdx = 0 input pin or cdx = 1 output pin 80 x:$ffe5 port c data register (pcd) step 3. read/write general - purpose i/o pins: pcx = output data if selected for general - purpose i/o and output in steps 1 and 2. or pcx = input data if selected for general - purpose i/o and input in steps 1 and 2. cc 2 cc 3 cc 4 cc 5 cc 6 cc 7 cc 8 cc 0 figure 7-7 i/o port c configuration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 10 synchronous serial interface motorola port c uses the dsp central processing unit (cpu) four-phase clock for its operation. therefore, if wait states are inserted in the dsp cpu timing, they also affect port c timing. as a result, port a and port c in the previous synchronization example will always stay synchronized, regardless of how many wait states are used. 7.3 synchronous serial interface (ssi) the synchronous serial interface (ssi) provides a full-duplex serial port for serial commu- nication with a variety of serial devices including one or more industry-standard codecs, other dsps, microprocessors, and peripherals which implement the motorola spi. the user can independently define the following characteristics of the ssi: the number of bits per word, the protocol, the clock, and the transmit/receive synchronization. the user can select among three modes: normal, on-demand, and network. the normal mode is typically used to interface with devices on a regular or periodic basis. the da- ta-driven on-demand mode is intended to be used to communicate with devices on a non- periodic basis. the network mode provides time slots in addition to a bit clock and frame synchronization pulse. the ssi functions with a range of 2 to 32 words of i/o per frame in the network mode. this mode is typically used in star or ring time division multiplex networks with other dsp56k processors and/or codecs. the clock can be programmed to be continuous or gated. since the transmitter and receiver sections of the ssi are independent, they can be programmed to be synchronous (using a common clock) or asynchronous with respect to each other. the ssi requires up to six pins, depending on its operating mode. the most common mini- mum configuration is three pins: transmit data (std), receive data (srd) and clock (sck). the ssi consists of independent transmitter and receiver sections and a common ssi clock generator. three to six pins are required for operation, depending on the operat- ing mode selected. the following is a short list of ssi features: ?three-pin interface: txd ?transmit data rxd ?receive data sclk ?serial clock ?a 10 mbps at 40 mhz (f osc /4) serial interface ?double buffered f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 11 ?user programmable ?separate transmit and receive sections ?control and status bits ?interface to a variety of serial devices, including: codecs (usually without additional logic) mc145502 mc145503 mc145505 mc145402 (13-bit linear codec) mc145554 family of codecs mc145532 serial peripherals (a/d, d/a) most industry-standard a/d, d/a dsp56adc16 (16-bit linear a/d) dsp56k to dsp56k networks motorola spi peripherals and processors shift registers ?interface to time division multiplexed networks without additional logic ?six pins: std ssi transmit data srd ssi receive data sck ssi serial clock sc0 serial control 0 (defined by ssi mode) sc1 serial control 1 (defined by ssi mode) sc2 serial control 2 (defined by ssi mode) ?on-chip programmable functions include: clock ?continuous, gated, internal, external synchronization signals ?bit length and word length tx/rx timing ?synchronous, asynchronous operating modes ?normal, network, on-demand word length ?8, 12, 16, 24 bits serial clock and frame sync generator ?four interrupt vectors: receive receive with exception transmit transmit with exception f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 12 synchronous serial interface motorola this interface is descriptively named ?ynchronous?because all serial transfers are synchro- nized to a clock. additional synchronization signals are used to delineate the word frames. the normal mode of operation is used to transfer data at a periodic rate, but only one word per period. the network mode is similar in that it is also intended for periodic transfers; how- ever, it will support up to 32 words (time slots) per period. this mode can be used to build time division multiplexed (tdm) networks. in contrast, the on-demand mode is intended for nonperiodic transfers of data. this mode can be used to transfer data serially at high speed when the data becomes available. this mode offers a subset of the spi protocol. 7.3.1 ssi data and control pins the ssi has three dedicated i/o pins (see figure 7-1), which are used for transmit data (std), receive data (srd), and serial clock (sck), where sck may be used by both the transmitter and the receiver for synchronous data transfers or by the trans- mitter only for asynchronous data transfers. three other pins may also be used, de- pending on the mode selected; they are serial control pins sc0, sc1, and sc2. they may be programmed as ssi control pins in the port c control register. table 7-1 shows the definition of sc0, sc1, sc2, and sck in the various configurations. table 7-1 definition of sc0, sc1, sc2, and sck txc ?transmitter clock rxc ?receiver clock *xc ?transmitter/receiver clock (synchronous operation) fst ?transmitter frame sync ssi pin name (control bit name) asynchronous (syn=0) synchronous (syn=1) continuous clock (gck=0) gated clock (gck=1) continuous clock (gck=0) gated clock (gck=1) sc0=0 (in) rxc external rxc external input f0 input f0 sc0=1 (out) (scd0) rxc internal rxc internal output f0 output f0 sc1=0 (in) fsr external not used input f1 input f1 sc1=1 (out) (scd1) fsr internal fsr internal output f1 output f1 sc2=0 (in) fst external not used fs* external not used sc2=1 (out) (scd2) fst internal fst internal fs* internal fs* internal sck=0 (in) txc external txc external *xc external *xc external sck=1 (out (sckd) txc internal txc internal) *xc internal *xc internal fsr ?receiver frame sync fs* ?transmitter/receiver frame sync (synchronous operation) f0 ?flag 0 f1 ?flag 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 13 the following paragraphs describe the uses of these pins for each of the ssi oper- ating modes. figure 7-8 and figure 7-9 show the internal clock path connections in block diagram form. the receiver and transmitter clocks can be internal or external depending on the syn, scd0, and sckd bits in crb. 7.3.1.1 serial transmit data pin (std) std is used for transmitting data from the serial transmit shift register. std is an output when data is being transmitted. data changes on the positive edge of the bit clock. std goes to high impedance on the negative edge of the bit clock of the last data bit of the word (i.e., during the second half of the last data bit period) with external gated clock, re- gardless of the mode. with an internally generated bit clock, the std pin becomes high impedance after the last data bit has been transmitted for a full clock period, assuming another data word does not follow immediately. if a data word follows immediately, there will not be a high-impedance interval. codecs label the msb as bit 0; whereas, the dsp labels the lsb as bit 0. therefore, when us- ing a standard codec, the dsp msb (or codec bit 0) is shifted out first when shfd=0, and the dsp lsb (or codec bit 7) is shifted out first when shfd=1. std may be programmed as a general-purpose pin called pc8 when the ssi std function is not being used. flag0 out (sync mode) flag0 in (sync mode) sc0 sck scd0 sckd syn = 1 syn = 0 scd0 = 0 rclock tclock internal bit clock syn = 1 wl1, wl0 wl1, wl0 rx word length divider tx word length divider rx shift register tx shift register divide by 2 divide by 2 prescale divide by 1 or divide by 8 divider divide by 1 to divide by 256 f osc psr pm0 - pm7 rx word clock tx word clock syn = 0 scd0 = 1 figure 7-8 ssi clock generator functional block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 14 synchronous serial interface motorola frame sync transmit frame sync receive rx word clock tx word clock dc0 - dc4 dc0 - dc4 receiver frame rate divider transmitter frame rate divider receive control logic transmit control logic fsl0, fsl1 fsl0, fsl1 sync type sync type syn = 0 syn = 1 internal rx frame clock scd1 = 1 syn = 1 scd1 = 0 syn = 0 scd1 sc1 scd2 sc2 internal tx frame clock flag1 in (sync mode) flag1out (sync mode) figure 7-9 ssi frame sync generator functional block diagram table 7-2 ssi clock sources, inputs, and outputs ext ?external pin name int ?internal bit clock syn sckd scd0 r clock source rx clock out t clock source tx clock out asynchronous 0 0 0 ext, sc0 ext, sck 0 0 1 int sc0 ext, sck 0 1 0 ext, sc0 int sck 0 1 1 int sc0 int sck synchronous 1 0 0 ext, sck ext, sck 1 0 1 ext, sck ext, sck 1 1 0 int sck int sck 1 1 1 int sck int sck f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 15 7.3.1.2 serial receive data pin (srd) srd receives serial data and transfers the data to the ssi receive shift register. srd may be programmed as a general-purpose i/o pin called pc7 when the ssi srd function is not being used. data is sampled on the negative edge of the bit clock. 7.3.1.3 serial clock (sck) sck is a bidirectional pin providing the serial bit rate clock for the ssi interface. the sck is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes (see table 7-2). note: although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 8t (i.e., the system clock frequency must be at least four times the external ssi clock frequency). the ssi needs at least four dsp phases (dsp phase=t) inside each half of the serial clock. 7.3.1.4 serial control pin (sc0) the function of this pin is determined solely on the selection of either synchronous or asynchronous mode (see table 7-1 and table 7-2). for asynchronous mode, this pin will be used for the receive clock i/o. for synchronous mode, this pin is used for serial flag i/o. a typical application of flag i/o would be multiple device selection for addressing in codec systems. the direction of this pin is determined by the scd0 bit in the crb as described in table 7-3. when configured as an output, this pin will be either serial output flag 0, based on control bit of0 in crb, or a receive shift register clock output. when con- figured as an input, this pin may be used either as serial input flag 0, which will control status bit if0 in the ssisr, or as a receive shift register clock input. table 7-3 ssi operation: flag 0 and rx clock syn gck scd0 operation synchronous continuous input flag 0 input synchronous continuous output flag 0 output synchronous gated input flag 0 input synchronous gated output flag 0 output asynchronous continuous input rx clock ?external asynchronous continuous output rx clock ?internal asynchronous gated input rx clock ?external asynchronous gated output rx clock ?internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 16 synchronous serial interface motorola 7.3.1.5 serial control pin (sc1) the function of this pin is determined solely on the selection of either synchronous or asynchronous mode (see table 7-1 and table 7-4). in asynchronous mode (such as a single codec with asynchronous transmit and receive), this pin is the receiver frame sync i/o. for synchronous mode with continuous clock, this pin is serial flag sc1 and operates like the previously described sc0. sc0 and sc1 are independent serial i/o flags but may be used together for multiple serial device selection. sc0 and sc1 can be used unencoded to select up to two codecs or may be decoded externally to select up to four codecs. the di- rection of this pin is determined by the scd1 bit in the crb. when configured as an out- put, this pin will be either a serial output flag, based on control bit of1, or it will make the receive frame sync signal available. when configured as an input, this pin may be used as a serial input flag, which will control status bit if1 in the ssi status register, or as a receive frame sync from an external source for continuous clock mode. in the gated clock mode, external frame sync signals are not used. table 7-4 ssi operation: flag 1 and rx frame sync 7.3.1.6 serial control pin (sc2) this pin is used for frame sync i/o (see table 7-1 and table 7-5). sc2 is the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. the direction of this pin is determined by the scd2 bit in crb. when configured as an output, this pin is the internally generated frame sync signal. when configured as an input, this pin receives an external frame sync signal for the trans- mitter (and the receiver in synchronous operation). in the gated clock mode, external frame sync signals are not used. syn gck scd1 operation synchronous continuous input flag 1 input synchronous continuous output flag 1 output synchronous gated input flag 1 input synchronous gated output flag 1 output asynchronous continuous input rx frame sync ?external asynchronous continuous output rx frame sync ?internal asynchronous gated input asynchronous gated output rx frame sync ?internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 17 table 7-5 ssi operation: tx and rx frame sync 7.3.2 ssi programming model the ssi can be viewed as two control registers, one status register, a transmit register, a receive register, and special-purpose time slot register. these registers are illustrated in figure 7-10 and figure 7-11. the following paragraphs give detailed descriptions and op- erations of each of the bits in the ssi registers. the ssi registers are not prefaced with an ??(for serial) as are the sci registers. 7.3.2.1 ssi control register a (cra) cra is one of two 16-bit read/write control registers used to direct the operation of the ssi. the cra controls the ssi clock generator bit and frame sync rates, word length, and number of words per frame for the serial data. the high-order bits of cra are read as ze- ros by the dsp cpu. the cra control bits are described in the following paragraphs. 7.3.2.1.1 cra prescale modulus select (pm7?m0) bits 0? the pm0?m7 bits specify the divide ratio of the prescale divider in the ssi clock generator. a divide ratio from 1 to 256 (pm=0 to $ff) may be selected. the bit clock output is available at the transmit clock (sck) and/or the receive clock (sc0) pins of the dsp. the bit clock out- put is also available internally for use as the bit clock to shift the transmit and receive shift registers. careful choice of the crystal oscillator frequency and the prescaler modulus will allow the industry-standard codec master clock frequencies of 2.048 mhz, 1.544 mhz, and 1.536 mhz to be generated. hardware and software reset clear pm0?m7. 7.3.2.1.2 cra frame rate divider control (dc4?c0) bits 8?2 the dc4?c0 bits control the divide ratio for the programmable frame rate dividers used to generate the frame clocks (see figure 7-9). in network mode, this ratio may be interpret- ed as the number of words per frame minus one. in normal mode, this ratio determines the word transfer rate. the divide ratio may range from 1 to 32 (dc=00000 to 11111) for normal mode and 2 to 32 (dc=00001 to 11111) for network mode. syn gck scd2 operation synchronous continuous input tx and rx frame sync synchronous continuous output tx and rx frame sync synchronous gated input synchronous gated output tx and rx frame sync asynchronous continuous input tx frame sync ?external asynchronous continuous output tx frame sync ?internal asynchronous gated input asynchronous gated output tx frame sync ?internal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 18 synchronous serial interface motorola a divide ratio of one (dc=00000) in network mode is a special case (see section 7.3.7.4 ). x:$ffec 15141312111098 76543210 psr wl1 wl0 dc4 dc3 dc2 dc1 dc0 pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) ssi control register a (cra) (read/write) 7 65 432 10 x:$ffee ssi time slot register (tsr) (write) rdf tde roe tue rfs tfs if1 if0 (0) (1) (0) (0) (0) (0) (0) (0) x:$ffee ssi status register (ssisr) (read) x:$ffed 15141312111098 76543210 rie (0) re te mod gck syn fsl1 fsl0 shfd sckd scd2 scd1 scd0 of1 of0 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) ssi control register b (crb) (read/write) receive data register full transmit data register empty receiver overrun error flag input flags transmit frame sync receive frame sync transmitter underrun error flag tie (0) output flags serial control direction receive interrupt enable transmit interrupt enable receiver enable transmitter enable mode select (network/normal) shift direction frame sync length 0 (mixed bit/word) frame sync length (bit/word) sync/async control gated clock control reset value = $40 reset value = $0000 word-length control frame rate divider control prescale range prescale modulus select reset value = $0000 figure 7-10 ssi programming model ?control and status registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 19 in normal mode, a divide ratio of one (dc=00000) provides continuous periodic data srd x:$ffef 23 16 15 8 7 0 707070 receive high byte receive middle byte receive low byte serial receive data (rx) register (read only) serial receive shift register 23 16 15 8 7 0 707070 receive high byte receive middle byte receive low byte 24 bit wl1, wl0 24-bit data 0 0 0 16-bit data 12-bit data 8-bit data lsb lsb lsb lsb msb msb msb msb least significant zero fill notes: 1. data is received msb ?st if shfd = 0. 2. compatible with fractional format. 16 bit 12 bit 8 bit (a) receive registers for shfd = 0 std x:$ffef 23 16 15 8 7 0 707070 transmit high byte transmit middle byte transmit low byte serial transmit data (tx) register (write only) serial receive shift register serial transmit shift register 23 16 15 8 7 0 707070 transmit high byte transmit middle byte transmit low byte 24-bit data 0 0 0 16-bit data 12-bit data 8-bit data lsb lsb lsb lsb msb msb msb msb least significant zero fill notes: 1. data is sent msb ?st if shfd = 0. 2. compatible with fractional format. (b) transmit registers for shfd = 0 figure 7-11 ssi programming model (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 20 synchronous serial interface motorola srd x:$ffef 23 16 15 8 7 0 707070 receive high byte receive middle byte receive low byte serial receive data (rx) register (read only) serial receive shift register 23 16 15 8 7 0 707070 receive high byte receive middle byte receive low byte 24-bit data 0 0 0 16-bit data 12-bit data 8-bit data lsb lsb lsb lsb msb msb msb msb least significant zero fill notes: 1. data is received lsb ?st if shfd = 1. 2. compatible with fractional format. (c) receive registers for shfd = 1 std x:$ffef 23 16 15 8 7 0 707070 transmit high byte transmit middle byte transmit low byte serial transmit data (tx) register (read only) serial transmit/shift register 23 16 15 8 7 0 707070 transmit high byte transmit middle byte transmit low byte 24 bit wl1, wl0 24-bit data 0 0 0 16-bit data 12-bit data 8-bit data lsb lsb lsb lsb msb msb msb msb least significant zero fill notes: 1. data is received lsb ?st if shfd = 1. 2. compatible with fractional format. 16 bit 12 bit 8 bit (d) transmit registers for shfd = 1 figure 7-11 ssi programming model (sheet 2 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 21 word transfers. a bit-length sync (fsl1=1, fsl0=0) must be used in this case. hardware and software reset clear dc4?c0. 7.3.2.1.3 cra word length control (wl0, wl1) bits 13 and 14 the wl1 and wl0 bits are used to select the length of the data words being transferred via the ssi. word lengths of 8, 12, 16, or 24 bits may be selected according to table 7-6. these bits control the number of active clock transitions in the gated clock modes and con- trol the word length divider (see figure 7-8 and figure 7-9), which is part of the frame rate signal generator for continuous clock modes. the wl control bits also control the frame sync pulse length when fsl0 and fsl1 select a wl bit clock (see figure 7-8). hardware and software reset clear wl0 and wl1. 7.3.2.1.4 cra prescaler range (psr) bit 15 the psr controls a fixed divide-by-eight prescaler in series with the variable prescaler. this bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired (see figure 7-8). when psr is cleared, the fixed prescaler is bypassed. when psr is set, the fixed divide-by-eight prescaler is operational. this allows a 128-khz master clock to be generated for mc14550x series codecs. the maximum internally generated bit clock frequency is fosc/4, the minimum internally generated bit clock frequency is fosc/4/8/256=fosc/8192. hardware and software reset clear psr. 7.3.2.2 ssi control register b (crb) the crb is one of two 16-bit read/write control registers used to direct the operation of the ssi. crb controls the ssi multifunction pins, sc2, sc1, and sc0, which can be used as clock inputs or outputs, frame synchronization pins, or serial i/o flag pins. the serial output flag control bits and the direction control bits for the serial control pins are in the ssi crb. interrupt enable bits for each data register interrupt are provided in this control register. when read by the dsp, crb appears on the two low-order bytes of the 24-bit word, and the high-order byte reads as zeros. operating modes are also selected in this register. hardware table 7-6 number of bits/word wl1 wl0 number of bits/word 00 8 01 12 10 16 11 24 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 22 synchronous serial interface motorola and software reset clear all the bits in the crb. the relationships between the ssi pins (sc0, sc1, sc2, and sck) and some of the crb bits are summarized in tables table 7-1, table 7-9, and table 7-8. the ssi crb bits are described in the following paragraphs. 7.3.2.2.1 crb serial output flag 0 (of0) bit 0 when the ssi is in the synchronous clock mode and the serial control direction zero bit (scd0) is set, indicating that the sc0 pin is an output, then data present in of0 will be written to sc0 at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode. hardware and software reset clear of0. 7.3.2.2.2 crb serial output flag 1 (of1) bit 1 when the ssi is in the synchronous clock mode and the serial control direction one (scd1) bit is set, indicating that the sc1 pin is an output, then data present in of1 will be written to the sc1 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode (see section 7.3.7 ). the normal sequence for setting output flags when transmitting data is to poll tde (tx empty), to first write the flags, and then write the transmit data to the tx register. of0 and of1 are double buffered so that the flag states appear on the pins when the tx data is transferred to the transmit shift register (i.e., the flags are synchronous with the data). hardware and software reset clear of1. note: the optional serial output pins (sc0, sc1, and sc2) are controlled by the frame timing and are not affected by te or re. 7.3.2.2.3 crb serial control 0 direction (scd0) bit 2 scd0 controls the direction of the sc0 i/o line. when scd0 is cleared, sc0 is an input; when scd0 is set, sc0 is an output (see tables table 7-1 and table 7-2, and figure 7-12). hardware and software reset clear scd0. 7.3.2.2.4 crb serial control 1 direction (scd1) bit 3 scd1 controls the direction of the sc1 i/o line. when scd1 is cleared, sc1 is an input; when scd1 is set, sc1 is an output (see tables table 7-1 and table 7-2 and figure 7-12). hardware and software reset clear scd1. 7.3.2.2.5 crb serial control 2 direction (scd2) bit 4 scd2 controls the direction of the sc2 i/o line. when scd2 is cleared, sc2 is an input; when scd2 is set, sc2 is an output (see tables table 7-1 and table 7-2, and figure 7-12). hardware and software reset clear scd2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 23 x:$ffed 15141312111098 76543210 rie sckd scd2 scd1 scd0 (0) (0) (0) (0) ssi control register b (crb) (read/write) tie 1 = output 0 = input re te mod gck syn fsl1 fsl0 shfd of1 of0 p o r t c sc0 sc1 sc2 sck srd std scd0 scd1 scd2 sckd direction controlled by receive clock/flag 0 receive frame sync/flag 1 transmit frame sync/tx and rx frame sync transmit clock/tx and rx clock ssi receive data ssi transmit data basic function note: parentheses indicate reset condition. figure 7-12 serial control, direction bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 24 synchronous serial interface motorola 7.3.2.2.6 crb clock source direction (sckd) bit 5 sckd selects the source of the clock signal used to clock the transmit shift register in the asynchronous mode and both the transmit shift register and the receive shift register in the synchronous mode. when sckd is set, the internal clock source becomes the bit clock for the transmit shift register and word length divider and is the output on the sck pin. when sckd is cleared, the clock source is external; the internal clock generator is discon- nected from the sck pin, and an external clock source may drive this pin. hardware and software reset clear sckd. 7.3.2.2.7 crb shift direction (shfd) bit 6 this bit causes the transmit shift register to shift data out msb first when shfd equals zero or lsb first when shfd equals one. receive data is shifted in msb first when shfd equals zero or lsb first when shfd equals one. hardware reset and software reset clear shfd. 7.3.2.2.8 crb frame sync length (fsl0 and fsl1) bits 7 and 8 these bits select the type of frame sync to be generated or recognized (see table 7-7). if fsl1 equals zero and fsl0 equals zero, a word-length frame sync is selected for both tx and rx that is the length of the data word defined by bits wl1 and wl0. if fsl1 equals one and fsl0 equals zero, a 1-bit clock period frame sync is selected for both tx and rx. when fsl0 equals one, the tx and rx frame syncs are different lengths. hardware reset and software reset clear fsl0 and fsl1. table 7-7 frame sync length 7.3.2.2.9 crb sync/async (syn) bit 9 syn controls whether the receive and transmit functions of the ssi occur synchronously or asynchronously with respect to each other. when syn is cleared, asynchronous mode is chosen and separate clock and frame sync signals are used for the transmit and receive sec- tions. when syn is set, synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals. hardware reset and software reset clear syn. fsl1 fsl0 frame sync length 0 0 wl bit clock for both tx/rx 0 1 one-bit clock for tx and wl bit clock for rx 1 0 one-bit clock for both tx/rx 1 1 one-bit clock for rx and wl bit clock for tx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 25 7.3.2.2.10 crb gated clock control (gck) bit 10 gck is used to select between a continuously running data clock or a clock that runs only when there is data to be sent in the transmit shift register. when gck is cleared, a contin- uous clock is selected; when gck is set, the clock will be gated. hardware reset and soft- ware reset clear gck. note : for gated clock mode with externally generated bit clock, internally generated frame sync is not defined. 7.3.2.2.11 crb ssi mode select (mod) bit 11 mod selects the operational mode of the ssi. when mod is cleared, the normal mode is selected; when mod is set, the network mode is selected. in the normal mode, the frame rate divider determines the word transfer rate ?one word is transferred per frame sync during the frame sync time slot. in network mode, a word is (possibly) transferred every time slot. for more details, see section 7.3.3 . hardware and software reset clear mod. 7.3.2.2.12 crb ssi transmit enable (te) bit 12 te enables the transfer of data from tx to the transmit shift register. when te is set and a frame sync is detected, the transmit portion of the ssi is enabled for that frame. when te is cleared, the transmitter will be disabled after completing transmission of data cur- rently in the ssi transmit shift register. the serial output is three-stated, and any data present in tx will not be transmitted (i.e., data can be written to tx with te cleared; tde will be cleared, but data will not be transferred to the transmit shift register). the normal mode transmit enable sequence is to write data to tx or tsr before setting te. the normal transmit disable sequence is to clear te and tie after tde equals one. in the network mode, the operation of clearing te and setting it again will disable the transmitter after completing transmission of the current data word until the beginning of the next frame. during that time period, the std pin will remain in the high-impedance state. hardware reset and software reset clear te. the on-demand mode transmit enable sequence can be the same as the normal mode, or te can be left enabled. note : te does not inhibit tde or transmitter interrupts. te does not affect the generation of frame sync or output flags. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 26 synchronous serial interface motorola 7.3.2.2.13 crb ssi receive enable (re) bit 13 when re is set, the receive portion of the ssi is enabled. when this bit is cleared, the re- ceiver will be disabled by inhibiting data transfer into rx. if data is being received while this bit is cleared, the remainder of the word will be shifted in and transferred to the ssi receive data register. re must be set in the normal mode and on-demand mode to receive data. in network mode, the operation of clearing re and setting it again will disable the receiver after re- ception of the current data word until the beginning of the next data frame. hardware and software reset clear re. note: re does not inhibit rdf or receiver interrupts. re does not affect the generation of a frame sync. 7.3.2.2.14 crb ssi transmit interrupt enable (tie) bit 14 the dsp will be interrupted when tie and the tde flag in the ssi status register is set. (in network mode, the interrupt takes effect in the next frame synch, not in the next time slot.) when tie is cleared, this interrupt is disabled. however, the tde bit will always indicate the transmit data register empty condition even when the transmitter is disabled with the te bit. writing data to tx or tsr will clear tde, thus clearing the interrupt. hardware and software reset clear re. there are two transmit data interrupts that have separate interrupt vectors: 1. transmit data with exceptions ?this interrupt is generated on the following condition: tie=1, tde=1, and tue=1 2. transmit data without exceptions ?this interrupt is generated on the follow- ing condition: tie=1, tde=1, and tue=0 see section 7 ? processing states in the dsp56000 family manual for more in- formation on exceptions. 7.3.2.2.15 crb ssi receive interrupt enable (rie) bit 15 when rie is set, the dsp will be interrupted when rdf in the ssi status register is set. (in network mode, the interrupt takes effect in the next frame synch, not in the next time slot.) when rie is cleared, this interrupt is disabled. however, the rdf bit still indicates the receive data register full condition. reading the receive data register will clear rdf, thus clearing the pending interrupt. hardware and software reset clear rie. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 27 there are two receive data interrupts that have separate interrupt vectors: 1. receive data with exceptions ?this interrupt is generated on the following condition: rie=1, rdf=1, and roe=1 2. receive data without exceptions ?this interrupt is generated on the following condition: rie=1, rdf=1, and roe=0 see section 7 ? processing states in the dsp56000 family manual for more in- formation on exceptions. 7.3.2.3 ssi status register (ssisr) the ssisr is an 8-bit read-only status register used by the dsp to interrogate the status and serial input flags of the ssi. when the ssisr is read to the internal data bus, the reg- ister contents occupy the low-order byte of the data bus, and the high-order portion is zero filled. the status bits are described in the following paragraphs. 7.3.2.3.1 ssisr serial input flag 0 (if0) bit 0 the ssi latches data present on the sc0 pin during reception of the first received bit after frame sync is detected. if0 is updated with this data when the receive shift register is transferred into the receive data register. the if0 bit is enabled only when scd0 is cleared and syn is set, indicating that sc0 is an input and the synchronous mode is selected (see table 7-1); otherwise, if0 reads as a zero when it is not enabled. hardware, software, ssi individual, and stop reset clear if0. 7.3.2.3.2 ssisr serial input flag 1 (if1) bit 1 the ssi latches data present on the sc1 pin during reception of the first received bit after frame sync is detected. the if1 flag is updated with the data when the receiver shift reg- ister is transferred into the receive data register. the if1 bit is enabled only when scd1 is cleared and syn is set, indicating that sc1 is an input and the synchronous mode is se- lected (see table 7-1); otherwise, if1 reads as a zero when it is not enabled. hardware, software, ssi individual, and stop reset clear if1. 7.3.2.3.3 ssisr transmit frame sync flag (tfs) bit 2 when set, tfs indicates that a transmit frame sync occurred in the current time slot. tfs is set at the start of the first time slot in the frame and cleared during all other time slots. if word-wide transmit frame sync is selected (fsl0=fsl1), this indicates that the frame sync was high at least at the beginning of the time slot if external frame sync is selected, or high throughout the time slot if internal frame sync was selected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 28 synchronous serial interface motorola if bit-wide transmit frame sync is selected (fsl0 fsl1), this indicates that the frame sync (either internal or external) was high during the last tx clock bit period prior to the current time slot, and that the frame sync falling edge corresponds to the assertion of the first output data bit, as shown below. data written to the transmit data register during the time slot when tfs is set will be transmitted (in network mode) during the second time slot in the frame. tfs is useful in network mode to identify the start of the frame. this is illustrated in a typical trans- mit interrupt handler: movep x:(r4)+,x:ssitx jclr #2,x:ssisr,_notfs;1 = first timeslot ;do something jmp _done _notfs ;do something else _done note: in normal mode, tfs will always read as a one when transmitting data because there is only one time slot per frame ?the ?rame sync?time slot. tfs, which is cleared by hardware, software, ssi individual, or stop reset, is not affected by te. 7.3.2.3.4 ssisr receive frame sync flag (rfs) bit 3 when set, rfs indicates that a receive frame sync occurred during reception of the word in the serial receive data register. this indicates that the data word is from the first time slot in the frame. if word-wide receive frame sync is selected (fsl1=0), this indicates that the frame sync was high at least at the beginning of the timeslot. if bit-wide receive frame sync is selected (fsl1=1), this indicates that the frame sync (either internal or external) was high during the last bit period prior to the current timeslot, and that the frame sync falling edge corresponds to the assertion of the first output data bit, as shown below. time slot #1 time slot #2 time slot #3 tfs set here bit-length fs word-length fs tx shift clock time slots f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 29 when rfs is clear and a word is received, it indicates (only in network mode) that the frame sync did not occur during reception of that word. rfs is useful in network mode to identify the start of the frame. this feature is illustrated in a typical receive interrupt handler: movep x:ssirx,x:(r4)+ jclr #3,x:ssisr,_norfs;1 = first timeslot ;do something jmp _done _norfs ;do something else _done note: in normal mode, rfs will always read as a one when reading data because there is only one time slot per frame ?the ?rame sync?time slot. rfs, which is cleared by hardware, software, ssi individual, or stop reset, is not affected by re. 7.3.2.3.5 ssisr transmitter underrun error flag (tue) bit 4 tue is set when the serial transmit shift register is empty (no new data to be transmitted) and a transmit time slot occurs. when a transmit underrun error occurs, the previous data (which is still present in the tx) will be retransmitted. in the normal mode, there is only one transmit time slot per frame. in the network mode, there can be up to 32 transmit time slots per frame. tue does not cause any interrupts; however, tue does cause a change in the interrupt vector used for transmit interrupts so that a different interrupt handler may be used for a transmit underrun condition. if a transmit interrupt occurs with tue set, the transmit data with exception status interrupt will be generated; if a transmit interrupt occurs with tue clear, the transmit data without errors interrupt will be generated. hardware, software, ssi individual, and stop reset clear tue. tue is also cleared by reading the ssisr with tue set, followed by writing tx or tsr. time slot #1 time slot #2 time slot #3 rfs set here bit-length fs word-length fs rx shift clock time slots f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 30 synchronous serial interface motorola 7.3.2.3.6 ssisr receiver overrun error flag (roe) bit 5 this flag is set when the serial receive shift register is filled and ready to transfer to the receiver data register (rx) and rx is already full (i.e., rdf=1). the receiver shift register is not transferred to rx. roe does not cause any interrupts; however, roe does cause a change in the interrupt vector used for receive interrupts so that a different interrupt han- dler may be used for a receive error condition. if a receive interrupt occurs with roe set, the receive data with exception status interrupt will be generated; if a receive interrupt occurs with roe clear, the receive data without errors interrupt will be generated. hardware, software, ssi individual, and stop reset clear roe. roe is also cleared by read- ing the ssisr with roe set, followed by reading the rx. clearing re does not affect roe. 7.3.2.3.7 ssisr ssi transmit data register empty (tde) bit 6 this flag is set when the contents of the transmit data register are transferred to the trans- mit shift register; it is also set for a disabled time slot period in network mode (as if data were being transmitted after the tsr was written). thirdly, it can be set by the hardware, software, ssi individual, or stop reset. when set, tde indicates that data should be writ- ten to the tx or to the time slot register (tsr). tde is cleared when the dsp writes to the transmit data register or when the dsp writes to the tsr to disable transmission of the next time slot. if tie is set, a dsp transmit data interrupt request will be issued when tde is set. the vector of the interrupt will depend on the state of the transmitter underrun bit. 7.3.2.3.8 ssisr ssi receive data register full (rdf) bit 7 rdf is set when the contents of the receive shift register are transferred to the receive data register. rdf is cleared when the dsp reads the receive data register or cleared by hard- ware, software, ssi individual, or stop reset. if rie is set, a dsp receive data interrupt request will be issued when rdf is set. the vector of the interrupt request will depend on the state of the receiver overrun bit. 7.3.2.4 ssi receive shift register this 24-bit shift register receives the incoming data from the serial receive data pin. data is shifted in by the selected (internal/external) bit clock when the associated frame sync i/o (or gated clock) is asserted. data is assumed to be received msb first if shfd equals zero and lsb first if shfd equals one. data is transferred to the ssi receive data register after 8, 12, 16, or 24 bits have been shifted in, depending on the word-length control bits in the cra (see figure 7-13). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 31 16 bits 12 bits 8 bits srd gdb 23 16 15 12 11 8 7 0 rx 24 bits shfd = 0 receive shift register (a) shfd = 0 srd gdb 23 16 15 12 11 8 7 0 rx shfd = 1 receive shift register (b) shfd = 1 figure 7-13 receive data path f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 32 synchronous serial interface motorola 7.3.2.5 ssi receive data register (rx) rx is a 24-bit read-only register that accepts data from the receive shift register as it be- comes full. the data read will occupy the most significant portion of the receive data register (see figure 7-13). the unused bits (least significant portion) will read as zeros. the dsp is interrupted whenever rx becomes full if the associated interrupt is enabled. 7.3.2.6 ssi transmit shift register this 24-bit shift register contains the data being transmitted. data is shifted out to the se- rial transmit data pin by the selected (internal/external) bit clock when the associated frame sync i/o (or gated clock) is asserted. the number of bits shifted out before the shift register is considered empty and may be written to again can be 8, 12, 16, or 24 bits (de- termined by the word-length control bits in cra). the data to be transmitted occupies the most significant portion of the shift register. the unused portion of the register is ignored. data is shifted out of this register msb first if shfd equals zero and lsb first if shfd equals one (see figure 7-14). 7.3.2.7 ssi transmit data register (tx) tx is a 24-bit write-only register. data to be transmitted is written into this register and is automatically transferred to the transmit shift register. the data written (8, 12, 16, or 24 bits) should occupy the most significant portion of tx (see figure 7-14). the unused bits (least significant portion) of tx are don? care bits. the dsp is interrupted whenever tx becomes empty if the transmit data register empty interrupt has been enabled. 7.3.2.8 time slot register (tsr) tsr is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot. for the purposes of timing, tsr is a write-only register that behaves like an alternative transmit data register, except that, rather than transmit- ting data, the transmit data pin is in the high-impedance state for that time slot. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 33 std shfd = 0 12 11 gdb 23 16 15 8 7 0 tx transmit shift register 23 16 15 8 7 0 12 11 16 bit 12 bit 8 bit std gdb tx 24 bits shfd = 1 transmit shift register (a) shfd = 0 (b) shfd = 1 figure 7-14 transmit data path f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 34 synchronous serial interface motorola 7.3.3 operational modes and pin definitions table 7-9 and table 7-8 completely describe the ssi operational modes and pin definitions (table 7-1 is a simplified version of these tables). the operational modes are as follows: 1. continuous clock mode 1 ?normal with internal frame sync mode 2 ?network with internal frame sync mode 3 ?normal with external frame sync mode 4 ?network with external frame sync 2. gated clock mode 5 ?external gated clock mode 6 ?normal with internal gated clock mode 7 ?network with internal gated clock 3. special case (both gated and continuous clock) mode 8 ?on-demand mode (transmitter only) mode 9 ?receiver follows transmitter clocking control bits mode sc0 sc1 sc2 sck mod gclk syn scd2 scd1 scd0 sckd dc4- dc0 tx rx in out in out in out in out 0 1 0 x x 1 1 x 6 6 rxc ? fsr ? fst txc 0 1 1 x x x 1 x 6 6 f0 f0 f0 f1 ? fs* *xc 0 1 0 x x 1 0 x 5 6 rxc ? fsr ? ? txc 0 1 0 x x 0 0 x 5 5 rxc ? ? ? ? txc 0 1 1 x x x 0 x 5 5 f0 f0 f1 f1 ? ? *xc 1 1 0 x x 1 1 0 8 7 rxc ? fsr ? fst txc 1 1 0 x x 0 1 0 8 5 rxc ? ? ? fst txc 1 1 1 x x x 1 0 8 9 f0 f0 f1 f1 ? fs* *xc 0 1 0 x x 0 1 x 6 5 rxc ? ? ? fst txc table 7-8 mode and pin definition table ?gated clock dc4?c0=0 means that bits dc4=0, dc3=0, dc2=0, dc1=0, and dc0=0. txc ?transmitter clock rxc ?receiver clock *xc ?transmitter/receiver clock (synchronous operation) fst ?transmitter frame sync fsr ?receiver frame sync fs* ?transmitter/receiver frame sync (synchronous operation) f0 ?flag 0 f1 ?flag 1 ? ?undefined f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 35 7.3.4 registers after reset hardware or software reset clears the port control register bits, which configure all i/o as general-purpose input. the ssi will remain in reset while all ssi pins are programmed as general-purpose i/o (cc8?c3=0) and will become active only when at least one of the ssi i/o pins is programmed as not general-purpose i/o. table 7-10 shows how each type of reset affects each ssi register bit. control bits mode sc0 sc1 sc2 sck mod gclk syn scd2 scd1 scd0 sckd dc4- dc0 tx rx in out in out in out in out 0 0 0 1 1 x x x 1 1 rxc rxc fsr fst txc txc 0 0 1 1 x x x x 1 1 f0 f0 f1 f1 fs* *xc *xc 1 0 0 1 1 x x 1 2 2 rxc rxc fsr fst txc txc 1 0 1 1 x x x 1 2 2 f0 f0 f1 f1 fs* *xc *xc 0 0 0 0 1 x x x 3 1 rxc rxc fsr fst txc txc 0 0 0 1 0 x x x 1 3 rxc rxc fsr fst txc txc 0 0 0 0 0 x x x 3 3 rxc rxc fsr fst txc txc 0 0 1 0 x x x x 3 3 f0 f0 f1 f1 fs* *xc *xc 1 0 0 0 1 x x x 4 2 rxc rxc fsr fst txc txc 1 0 0 1 0 x x 1 2 4 rxc rxc fsr fst txc txc 1 0 0 0 0 x x x 4 4 rxc rxc fsr fst txc txc 1 0 1 0 x x x x 4 4 f0 f0 f1 f1 fs* *xc *xc 1 0 0 1 1 x x 0 8 2 rxc rxc fsr fst txc txc 1 0 1 1 x x x 0 8 9 f0 f0 f1 f1 fs* *xc *xc 1 0 0 1 0 x x 0 8 4 rxc rxc fsr fst txc txc dc4-dc0 = 0 means that bits dc4 = 0, dc3 = 0, dc2 = 0, dc1 = 0, and dc0 = 0 dc4-dc0 = 1 means that bits dc4-dc0 0 txc ?transmitter clock rxc ?receiver clock *xc ?transmitter/receiver clock (synchronous operation) fst ?transmitter frame sync fsr ?receiver frame sync fs* ?transmitter/receiver frame sync (synchronous operation) f0 ?flag 0 f1 ?flag 1 table 7-9 mode and pin definition table ?continuous clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 36 synchronous serial interface motorola register name register data bit number reset hw reset sw reset individual reset st reset cra psr 15 0 0 wl(2?) 13,14 0 0 dc(4?) 8?2 0 0 pm(7?) 0? 0 0 crb rie 15 0 0 tie 14 0 0 re 13 0 0 te 12 0 0 mod 11 0 0 gck 10 0 0 syn 9 0 0 fsl1 8 0 0 fsl0 7 0 0 shfd 6 0 0 sckd 5 0 0 scd(2?) 2? 0 0 of(1?) 0,1 0 0 ssisr rdf 7 0 0 0 0 tde 6 1 1 1 1 roe 5 0 0 0 0 tue 4 0 0 0 0 rfs 3 0 0 0 0 tfs 2 0 0 0 0 if(1?) 0,1 0 0 0 0 rdr rdr (23?) 23? tdr tdr (23?) 23? rsr rdr (23?) 23? tsr rdr (23?) 23? table 7-10 ssi registers after reset notes: 1. rsr ?ssi receive shift register 2. tsr ?ssi transmit shift register 3. hw ?hardware reset is caused by asserting the external pin reset . 4. sw ?software reset is caused by executing the reset instruction. 5. ir ?individual reset is caused by ssi peripheral pins (i.e., pcc(3?)) being configured as general-purpose i/o. 6. st ?stop reset is caused by executing the stop instructi on. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 37 7.3.5 ssi initialization the correct way to initialize the ssi is as follows: 1. hardware, software, ssi individual, or stop reset 2. program ssi control registers 3. configure ssi pins (at least one) as not general-purpose i/o during program execution, cc8?c3 may be cleared, causing the ssi to stop serial activ- ity and enter the individual reset state. all status bits of the interface will be set to their reset state; however, the contents of cra and crb are not affected. this procedure allows the dsp program to reset each interface separately from the other internal peripherals. the dsp program must use an ssi reset when changing the mod, gck, syn, sckd, scd2, scd1, or scd0 bits to ensure proper operation of the interface. figure 7-15 is a flowchart illustrating the three initialization steps previously listed. figure 7-16, figure 7-17, and figure 7-18 provide additional detail to the flowchart. figure 7-18 shows the six control bits in the pcc, which select the six ssi pins as either general-purpose i/o or as ssi pins. the std pin can only transmit data; the srd pin can only receive data. the other four pins can be inputs or outputs, depending on how they are programmed. this programming is accomplished by setting bits in cra and crb as shown in figure 7-12. the cra (see figure 7-16) sets the ssi bit rate clock with psr and pm0?m7, sets the word length with wl1 and wl0, and sets the number of words in a frame with dc0?c4. there is a special case where dc4?c0 equals zero (one word per frame). depending on whether the normal or network mode is selected (mod=0 or mod=1, respectively), either the continuous periodic data mode is selected, or the on-de- mand data driven mode is selected. the continuous periodic mode requires that fsl1 equals one and fsl0 equals zero. figure 7-17 shows the meaning of each individual bit in the crb. these bits should be set according to the application requirements. hardware or software rest program cra and crb select pins to be used port c control register figure 7-15 ssi initialization block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 38 synchronous serial interface motorola table 7-11 (a) and table 7-11 (b) provide a convenient listing of psr and pm0?m7 settings wl1 wl0 bits/word 00 8 01 12 x:$ffec 15141312111098 76543210 psr pm5 pm4 pm3 pm2 ssi control register a (cra) (read/write) wl1 wl0 dc4 dc3 dc2 dc1 dc0 pm7 pm6 pm1 pm0 x:$ffed 15141312111098 76543210 rie sckd scd2 scd1 scd0 ssi control register b (crb) (read/write) tie (see note 3) re te mod gck syn fsl1 fsl0 shfd of1 of0 prescaler if psr = 1, then divide by 8 if psr = 0, then divide by 1 divide by 2 ssi bit rate clock dc4-dc0 word transfer rate (see note 1) words/frame (see note 2) 0 0 0 0 0 continuous periodic (see note 3) on-demand data driven 0 0 0 0 1 2 2 0 0 0 1 0 3 3 0 0 0 1 1 4 4 divide by 2 f osc divide by 1 to 256 (see notes 1 and 2) notes: 1. normal ?mod = 0 2. network ?mod = 1 3. fsl1 = 1, fsl0 = 0 figure 7-16 ssi cra initialization procedure f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 39 15 14 13 12 10 rie sckd scd2 scd1 scd0 tie re te mod gck syn fsl1 fsl0 shfd of1 of0 11 10 9 8 7 6 5 4 3 2 frame sync length 1 0 = rx is word length 1 = rx is bit length sync/async control 0 = asynchronous 1 = synchronous gated clock control 0 = continuous clock 1 = gated clock ssi mode select 0 = normal 1 = network frame sync length 0 0 = rx and tx same length 1 = rx and tx different length shift direction 0 = msb first 1 = lsb first clock source direction 0 = input (external) 1 = output (internal) serial control direction bits 0 = input 1 = output transmit enable 0 = disable 1 = enable receive enable 0 = disable 1 = enable transmit interrupt enable 0 = disable 1 = enable receive interrupt enable 0 = disable 1 = enable output flag 1 if syn = 1, scd1 = 1 of1 sc1 pin output flag 0 if syn = 1, scd0 = 1 of0 sc0 pin figure 7-17 ssi crb initialization procedure f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 40 synchronous serial interface motorola for the common data communication rates and the highest rate possible for the ssi for the chosen crystal frequencies. the crystal frequency selected for table 7-11 (a) is the one used by the dsp56003/005ads board; the one selected for table 7-11 (b) is the closest one to 40 mhz that divides down to exactly 128 khz. if an exact baud rate is required, the crystal frequency may have to be selected. table 7-12 gives the psr and pm0?m7 settings in ad- dition to the required crystal frequency for three common telecommunication frequencies. 7.3.6 ssi exceptions the ssi can generate four different exceptions (see figure 7-19 and figure 7-20): 1. ssi receive data ?occurs when the receive interrupt is enabled, the receive data register is full, and no receive error conditions exist. reading rx clears the pending interrupt. this error-free interrupt can use a fast interrupt service routine for minimum overhead. 2. ssi receive data with exception status ?occurs when the receive interrupt is enabled, the receive data register is full, and a receiver overrun error has occurred. roe is cleared by first reading the ssisr and then reading rx. 23 0 000000000000000 cc cc cc cc cc cc cc cc cc 876543210 x:$ffe1 port c control register (pcc) std srd sck sc2 sc1 sc0 ccx function 0 gpio 1 serial interface p o r t c pc0 pc1 pc2 sc0 sc1 sc2 sck srd std serial control pin 0 serial control pin 1 serial control pin 2 serial clock pin serial receive data pin serial transmit data pin figure 7-18 ssi initialization procedure f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 41 3. ssi transmit data ?occurs when the transmit interrupt is enabled, the trans- bit rate (bps) psr pm 1000 1 $4e1 2000 1 $270 4000 1 $138 8000 1 $9b 16k 1 $4d 32k 1 $26 64k 0 $9b 128k 0 $4d 10m 0 $00 table 7-11 (a) ssi bit rates for a 40-mhz crystal bit rate (bps) psr pm 1000 1 $4df 2000 1 $26f 4000 1 $137 8000 1 $9b 16k 1 $4d 32k 1 $26 64k 0 $9b 128k 0 $4d 9.984m 0 $00 table 7-11 (b) ssi bit rates for a 39.936-mhz crystal bps = f osc (4 (7 (psr) +1) (pm + 1)) where f osc = 40 mhz psr = 0 or 1 pm = 0 to $fff bps = f osc (4 (7 (psr) +1) (pm + 1)) where f osc = 39.936 mhz psr = 0 or 1 pm = 0 to $fff bit rate (bps) psr pm crystal frequency 1.536m 0 $05 36.864 mhz 1.544m 0 $05 37.056 mhz 2.048m 0 $03 32.678 mhz table 7-12 crystal frequencies required for codecs bps = f osc (4 (7 (psr) +1) (pm + 1)) psr = 0 or 1 pm = 0 to $fff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 42 synchronous serial interface motorola mit data register is empty, and no transmitter error conditions exist. writing to host program memory space exception source exception starting address $0000 hardware reset $0002 stack error $0004 trace $0006 swi (software interrupt) $0008 irqa external hardware interrupt $000a irqb external hardware interrupt $000c ssi receive data $000e ssi receive data with exception status $0010 ssi transmit data $0012 ssi transmit data with exception status $0014 sci receive data $0016 sci receive data with exception status $0018 sci transmit data $001a sci idle line $001c sci timer $001e nmi /watchdog timer $0020 host receive data $0022 host transmit data $0024 host command (default) $0026 available for host command $0028 available for host command $002a available for host command $002c irqc $002e irqd $0030 pwma0 interrupt $0032 pwma1 interrupt $0034 pwma2 interrupt $0036 pwmb0 interrupt $0038 pwmb1 interrupt $003a pwm error $003c timer/event counter interrupt $003e illegal instruction $0040 available for host command $007e available for host command internal interrupts serial communications interface synchronous serial interface internal interrupts external interrupts internal interrupts two words per vector figure 7-19 hi exception vector locations external interrupts internal/external interrupts external interrupts internal interrupts watchdog timer host interface pulse width modulators interface timer/event counter interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 43 tx or the tsr will clear this interrupt. this error-free interrupt may use a fast ssi exception mask exception vector table 15 14 13 12 11 10 9 8 rie tie re te mod gck syn fsl1 x:$ffed ssi control register (crb) (read/write) ssi exception mask exception starting address $0000 $000c $000e $0010 $0012 ssi receive data ssi receive data with exceptions status ssi transmit data ssi transmit data with exception status 76543 2 10 rdf tde roe tue rfs tfs if1 if0 x:$fffe ssi status register (ssisr) (read only) ssi status bits receive interrupt service routine 1. interrupt is generated when rie = 1, rdf = 1, and roe = 0. 2. pending interrupt is cleared by reading rx. transmit interrupt service routine 1. interrupt is generated when tie = 1, tdf = 1, and tue = 0. 2. pending interrupt is cleared by writing to tx or tsr. transmit with exception status interrupt service routine 1. interrupt is generated when tie = 1, tdf = 1, and tue = 1. 2. tue is cleared by reading ssisr followed by: 3. writing to tx or tsr to clear pending interrupt. 4. application-specific code. figure 7-20 ssi exceptions 1. interrupt is generated when rie = 1, rdf = 1, and roe = 1. 2. roe is cleared by reading ssisr followed by: 3. reading rx to clear pending interrupt. 4. application-specific code. receive with exception status interrupt service routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 44 synchronous serial interface motorola interrupt service routine for minimum overhead. 4. ssi transmit data with exception status ?occurs when the transmit interrupt is enabled, the transmit data register is empty, and a transmitter underrun error has occurred. tue is cleared by first reading the ssisr and then writing to tx or the tsr to clear the pending interrupt. 7.3.7 operating modes ?normal, network, and on-demand the ssi has three basic operating modes and many data/operation formats. these modes can be programmed by several bits in the ssi control registers. table 7-13 lists the ssi op- erating modes and some of the typical applications in which they may be used. the data/operation formats are selected by choosing between gated and continuous clocks, synchronization of transmitter and receiver, selection of word or bit frame sync, and whether the lsb is transferred first or last. the following paragraphs describe how to select a particular data/operation format and describe examples of normal-mode and network-mode applications. the on-demand mode is selected as a special case of the net- work mode. the ssi can function as an spi master or spi slave, using additional logic for arbitration, which is required because the ssi interface does not perform spi master/slave arbitra- tion. an spi master device always uses an internally generated clock; whereas, an spi slave device always uses an external clock. 7.3.7.1 data/operation formats the data/operation formats available to the ssi are selected by setting or clearing control operating format serial clock tx, rx sections typical applications normal continuous asynchronous single asynchronous codec; stream-mode channel interface normal continuous synchronous multiple synchronous codecs normal gated asynchronous dsp-to-dsp; serial peripherals (a/d,d/a) normal gated synchronous spi-type devices; dsp to mcu network continuous asynchronous tdm networks network continuous synchronous tdm codec networks, tdm dsp networks on demand gated asynchronous parallel-to-serial and serial-to-parallel conversion on demand gated synchronous dsp to spi peripherals table 7-13 ssi operating modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 45 bits in the crb. these control bits are mod, gck, syn, fsl1, fsl0, and shfd. 7.3.7.1.1 normal/network mode selection selecting between the normal mode and network mode is accomplished by clearing or set- ting the mod bit in the crb (see figure 7-21). for normal mode, the ssi functions with one data word of i/o per frame (see figure 7-22). for the network mode, 2 to 32 data words of i/o may be used per frame. in either case, the transfers are periodic. the normal mode is typ- ically used to transfer data to/from a single device. network mode is typically used in time division multiplexed (tdm) networks of codecs or dsps with multiple words per frame (see figure 7-22, which shows two words in a frame with either word-length or bit-length frame sync). the frame sync shown in figure 7-21 is the word-length frame sync. a bit-length frame sync can be chosen by setting fsl1 and fsl0 for the configuration desired. 7.3.7.1.2 continuous/gated clock selection the tx and rx clocks may be programmed as either continuous or gated clock signals by the gck bit in the crb. a continuous tx and rx clock is required in applications such as com- municating with some codecs where the clock is used for more than just data transfer. a gat- ed clock, in which the clock only toggles while data is being transferred, is useful for many applications and is required for spi compatibility. the frame sync outputs may be used as a start conversion signal by some a/d and d/a devices. figure 7-23 illustrates the difference between continuous clock and gated clock systems. a separate frame-sync signal is required in continuous clock systems to delimit the active clock transitions. although the word-length frame sync is shown in figure 7-23, a bit-length frame sync can be used (see figure 7-24). in gated clock systems, frame syn- chronization is inherent in the clock signal; thus a separate sync signal is not required (see figure 7-25 and figure 7-26). the ssi can be programmed to generate frame sync out- puts in gated clock mode but does not use frame sync inputs. input flags (see figure 7-25 and figure 7-26) are latched on the negative edge of the first data bit of a frame. output flags are valid during the entire frame. 7.3.7.1.3 synchronous/asynchronous operating modes the transmit and receive sections of this interface may be synchronous or asynchronous i.e., the transmitter and receiver may use common clock and synchronization signals (syn- chronous operating mode, see figure 7-27) or they may have their own separate clock and sync signals (asynchronous operating mode). the syn bit in crb selects synchronous or asynchronous operation. since the ssi is designed to operate either synchronously or asyn- chronously, separate receive and transmit interrupts are provided. figure 7-28 illustrates the operation of the syn bit in the crb. when syn equals zero, the ssi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 46 synchronous serial interface motorola x:$ffed 15141312111098 76543210 rie sckd scd2 scd1 scd0 ssi control register b (crb) (read/write) tie re te mod gck syn fsl1 fsl0 shfd of1 of0 * * normal mod = 0 serial clock frame sync serial data data data transmitter interrupt and flags set receiver interrupt and flags set note: interrupts occur and data is transferred once per frame sync. * network mod = 1 serial clock frame sync transmitter interrupts and flags set receiver interrupt and flags set note: interrupts occur every time slot and a word may be transferred. figure 7-21 crb mod bit operation slot 1 slot 2 slot 3 slot 2 serial data slot 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 47 tx and rx clocks and frame sync sources are independent. if syn equals one, the ssi tx frame sync (fsl0 = 0, fsl1 = 0) frame sync (fsl0 = 0, fsl1 = 1) data out flags figure 7-22 normal mode, external frame sync (8 bit, 1 word in frame) slot 0 slot 1 slot 1 slot 0 frame sync (fsl0 = 0, fsl1 = 0) frame sync (fsl0 = 0, fsl1 = 1) flags data figure 7-22 network mode, external frame sync (8 bit, 2 words in frame) slot 0 slot 0 wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 48 synchronous serial interface motorola and rx clocks and frame sync come from the same source (either external or internal). x:$ffed 15141312111098 76543210 rie sckd scd2 scd1 scd0 ssi control register b (crb) (read/write) tie re te mod gck syn fsl1 fsl0 shfd of1 of0 * * continuous clock gck = 0 serial clock frame sync serial data data data note: frame sync is required to tell when data is present. serial clock serial data notes: 1. word synchronization is inherent in the serial clock signal. 2. frame sync generation is optional. data changes data stable * gated clock gck = 1 data changes data stable data data figure 7-23 crb gck bit operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 49 data clock and frame sync signals can be generated internally by the dsp or may be ob- 76543 2 10 76 54 3210 continuous clock notes: 1. for fsl1 = 0 the frame sync is latched and enables the std output buffer, but data may not be valid until the rising edge of the bit clock. 2. wl bit frame sync (fsl0 = 0, fsl1 = 0) is not de?ed for dc = 0 in continuous clock mode. 3. data and ?gs transition after external frame sync but not before the rising edge of the clock. 0 data out (for dc = 0, or network modes) data out (for dc > 0) data in latched input flags latched (dc = 0) (dc = 0) data not defined frame sync out: fsl0 = 0, fsl1 = 1 fsl0 = 0, fsl1 = 0 output flags frame sync in: fsl0 = 0, fsl1 = 1 fsl0 = 0, fsl1 = 0 data out for: fsl1 = 0, fsl0 = 0 output flags figure 7-24 continuous clock timing diagram (8-bit example) 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 50 synchronous serial interface motorola 76 54 3 2 10 76 54 3 2 10 gated clock output (dc>0) gated clock (dc = 0) data out (dc > 0) data in latched input flags latched (dc = 0) frame sync out: fsl0 = 0, fsl1 = 1 output flags (dc > 0) data out (dc = 0) frame sync out: fsl0 = 0, fsl1 = 0 output flags (dc = 0) 7 6 0 figure 7-25 internally generated clock timing (8-bit example) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 51 tained from external sources. if internally generated, the ssi clock generator is used to de- 76543 21 0 76543 21 0 gated clock input (dc>0) gated clock (dc = 0) data out (dc > 0) data in latched data out (dc = 0) 7 6 0 t dhgc 5 ns input flags latched notes: 1. output enabled on rising edge of ?st clock input. 2. output disabled on falling edge of last clock pulse. 3. t dhgc is guaranteed by circuit design. 4. frame syncs (in or out) are not de?ed for external gated clock mode. figure 7-26 externally generated gated clock timing (8-bit example) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 52 synchronous serial interface motorola rive bit clock and frame sync signals from the dsp internal system clock. the ssi clock generator consists of a selectable fixed prescaler and a programmable prescaler for bit rate clock generation and also a programmable frame-rate divider and a word-length di- vider for frame-rate sync-signal generation. figures figure 7-29 through figure 7-32 show the definitions of the ssi pins during each of the four main operating modes of the ssi i/o interface. figure 7-29 uses a gated clock (from either an external source or the internal clock), which means that frame sync is in- herent in the clock. since both the transmitter and receiver use the same clock (synchro- nous configuration), both use the sck pin. sc0 and sc1 are designated as flags or can be used as general purpose-parallel i/o. sc2 is not defined if it is an input; sc2 is the transmit and receive frame sync if it is an output. figure 7-30 shows a gated clock (from either an external source or the internal clock), which means that frame sync is inherent in the clock. since this configuration is asyn- chronous, sck is the transmitter clock pin (input or output) and sc0 is the receiver clock pin (input or output). sc1 and sc2 are designated as receive or transmit frame sync, re- spectively, if they are selected to be outputs; these bits are undefined if they are selected to be inputs. sc1 and sc2 can also be used as general-purpose parallel i/o. xmit data xmit data one frame word transfer fate (=3) 3 words per frame start of frame word word word word s erial clock frame sync t ransmit d ata transmitter empty internal interrupts and flags rec data rec data receive data receiver full internal interrupts and flags 3-state 3-state figure 7-27 synchronous communication f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 53 external frame sync sc1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rie sckd scd2 scd1 scd0 tie re te mod gck syn fsl1 fsl0 shfd of1 of0 ssi control register b (crb) (read/write) * *asynchronous syn = 0 transmitter clock frame sync receiver clock frame sync srd std sc2 external transmit frame sync external receive frame sync internal frame sync sc0 sck external transmit clock external receive clock internal clock ssi bit clock note: transmitter and receiver may have different clocks and frame syncs. * synchronous syn = 1 transmitter clock frame sync receiver clock frame sync srd std sc2 internal frame sync sck external clock internal clock ssi bit clock note: transmitter and receiver may have the same clock frame syncs. x:$ff figure 7-28 crb syn bit operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 54 synchronous serial interface motorola figure 7-31 shows a continuous clock (from either an external source or the internal clock), ssi pc8 pc7 pc6 pc3 pc4 pc5 sc0 sc1 sc2 std srd sck (txc and rxc) flag0 flag1 ? fst and fsr ssi pc8 pc7 pc6 pc3 pc4 pc5 sc0 sc1 sc2 std srd sck (txc) rxc ? ? fst fsr figure 7-29 gated clock ?synchronous operation figure 7-30 gated clock ?asynchronous operation std srd sck (txc and rxc) flag 0 flag 1 fsr and fst ssi pc8 pc7 pc6 pc3 pc4 pc5 sc0 sc1 sc2 figure 7-31 continuous clock ?synchronous operation std srd sck (txc) rxc fsr fst ssi pc8 pc7 pc6 pc3 pc4 pc5 sc0 sc1 sc2 figure 7-32 continuous clock ?asynchronous operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 55 which means that frame sync must be a separate signal. sc2 is used for frame sync, which can come from an internal or external source. since both the transmitter and receiver use the same clock (synchronous configuration), both use the sck pin. sc0 and sc1 are des- ignated as flags or can be used as general-purpose parallel i/o. figure 7-32 shows a continuous clock (from either an external source or the internal clock), which means that frame sync must be a separate signal. sc1 is used for the receive frame sync, and sc2 is used for the transmit frame sync. either frame sync can come from an internal or external source. since the transmitter and receiver use different clocks (asynchronous configuration), sck is used for the transmit clock, and sc0 is used for the receive clock. 7.3.7.1.4 frame sync selection the transmitter and receiver can operate totally independent of each other. the transmit- ter can have either a bit-long or word-long frame-sync signal format, and the receiver can have the same or opposite format. the selection is made by programming fsl0 and fsl1 in the crb as shown in figure 7-33. 1. if fsl1 equals zero (see figure 7-34), the rx frame sync is asserted during the entire data transfer period. this frame sync length is compatible with motor- ola codecs, spi serial peripherals, serial a/d and d/a converters, shift regis- ters, and telecommunication pcm serial i/o. 2. if fsl1 equals one (see figure 7-35), the rx frame sync pulses active for one bit clock immediately before the data transfer period. this frame sync length is compatible with intel and national components, codecs, and telecommunica- tion pcm serial i/o. the ability to mix frame sync lengths is useful in configuring systems in which data is re- ceived from one type device (e.g., codec) and transmitted to a different type device. fsl0 controls whether rx and tx have the same frame sync length (see figure 7-33). if fsl0 equals zero, rx and tx have the same frame sync length, which is selected by fsl1. if fsl0 equals one, rx and tx have different frame sync lengths, which are selected by fsl1. the ssi receiver looks for a receive frame sync leading edge only when the previous frame is completed. if the frame sync goes high before the frame is completed (or before the last bit of the frame is received in the case of a bit frame sync), the current frame sync will not be recognized, and the receiver will be internally disabled until the next frame sync. frames do not have to be adjacent ?i.e., a new frame sync does not have to imme- diately follow the previous frame. gaps of arbitrary periods can occur between frames. the transmitter will be three-stated during these gaps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 56 synchronous serial interface motorola data data serial clock rx, tx frame sync ssi control register b (crb) (read/write) * * * word length: fsl1 = 0, fsl0 = 0 rx, tx serial data note: frame sync occurs while data is valid. data data serial clock rx, tx frame sync * one bit: fsl1 = 1, fsl0 = 0 rx, tx serial data note: frame sync occurs for one bit time preceding the data. data data serial clock tx frame sync * mixed frame length: fsl1 = 0, fsl0 = 1 tx serial data rx frame sync data data rx serial data data data serial clock tx frame sync * mixed frame length: fsl1 = 1, fsl0 = 1 tx serial data rx frame sync data data rx serial data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rie sckd scd2 scd1 scd0 tie re te mod gck syn fsl1 fsl0 shfd of1 of0 x:$ffed figure 7-33 crb fsl0 and fsl1 bit operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 57 x:$ffec 15141312111098 76543210 psr pm5 pm4 pm3 pm2 ssi control register a (cra) (read/write) 0 000000pm7pm6 pm1pm0 x:$ffec 15141312111098 76543210 rie 1 1 scd1 scd0 tie re te 0 0 1 0 0 shfd of1 of0 wl1 wl0 dc4 dc3 dc2 dc1 dc0 8-bit word length 3 word frame rate mod ssi mode select 0 = normal gck gated clock control 0 = continuous clock syn sync/async control 1 = synchronous scd2 serial control 2 direction 1 = output sckd clock source direction 1 = output fsl0 frame sync length 0 = same lengths fsl1 frame sync length 0 = word clock dsp data dsp data serial clock frame sync transmit data internal interrupts and flags codec data receive data codec data internal interrupts and flags figure 7-34 normal mode initialization for fls1=0 and fsl0=0 ssi control register b (crb) (read/write) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 58 synchronous serial interface motorola x:$ffec 15141312111098 76543210 psr pm5 pm4 pm3 pm2 ssi control register a (cra) (read/write) 0 000000pm7pm6 pm1pm0 x:$ffed 15141312111098 76543210 rie 1 1 scd1 scd0 tie re te 0 0 1 1 0 shfd of1 of0 wl1 wl0 dc4 dc3 dc2 dc1 dc0 8-bit word length continuous periodic mod ssi mode select 0 = normal gck gated clock control 0 = continuous syn sync/async control 1 = synchronous scd2 serial control 2 direction 1 = output sckd clock source direction 1 = output fsl0 frame sync length 0 = different lengths fsl1 frame sync length 1 = wl clock for rx serial clock frame sync serial data ssi control register b (crb) (read/write) data 1 data 2 data 3 data 4 data 5 transmit and receive figure 7-35 normal mode initialization for fsl1=1 and fsl0=0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 59 7.3.7.1.5 shift direction selection some data formats, such as those used by codecs, specify msb first other data formats, such as the aes-ebu digital audio, specify lsb first. to interface with devices from both systems, the shift registers in the ssi are bidirectional. the msb/lsb selection is made by programming shfd in the crb. figure 7-36 illustrates the operation of the shfd bit in the crb. if shfd equals zero (see figure 7-36(a)), data is shifted into the receive shift register msb first and shifted out of the transmit shift register msb first. if shfd equals one (see figure 7-37(b)), data is shifted into the receive shift register lsb first and shifted out of the transmit shift register lsb first. 7.3.7.2 normal mode examples the normal ssi operating mode characteristically has one time slot per serial frame, and data is transferred every frame sync. when the ssi is not in the normal mode, it is in the network mode. the msb is transmitted first (shfd=0), with overrun and underrun errors detected by the ssi hardware. transmit flags are set when data is transferred from the transmit data register to the transmit shift register. the receive flags are set when data is transferred from the receive shift register to the receive data register. figure 7-38 shows an example of using the ssi to connect an mc15500 codec with a dsp56003/005. no glue logic is needed. the serial clock, which is generated internally by the dsp, provides the transmit and receive clocks (synchronous operation) for the codec. sc2 pro- vides all the necessary handshaking. data transfer begins when the frame sync is asserted. transmit data is clocked out and receive data is clocked in with the serial clock while the frame sync is asserted (word-length frame sync). at the end of the data transfer, dsp internal inter- rupts programmed to transfer data to/from will occur, and the ssisr will be updated. 7.3.7.2.1 normal mode transmit the conditions for data transmission from the ssi are as follows: 1. transmitter is enabled (te=1) 2. frame sync (or clock in gated clock mode) is active when these conditions occur in normal mode, the next data word will be transferred from tx to the transmit shift register, the tde flag will be set (transmitter empty), and the transmit in- terrupt will occur if tie equals one (transmit interrupt enabled.) the new data word will be transmitted immediately. the transmit data output (std) is three-stated, except during the data transmission period. the optional frame sync output, flag outputs, and clock outputs are not three-stated even if both re- ceiver and transmitter are disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 60 synchronous serial interface motorola x:$ffed 15141312111098 76543210 rie sckd scd2 scd1 scd0 tie re te mod gck syn fsl1 fsl0 shfd of1 of0 ssi control register b (crb) (read/write) srd x:$ffef 23 16 15 8 7 0 707070 receive high byte receive middle byte receive low byte serial receive data register (rx) (read only) serial receive shift register (rx) 23 16 15 8 7 0 707070 receive high byte receive middle byte receive low byte * 8 bit 12 bit 16 bit 24 bit std x:$ffef 23 16 15 8 7 0 707070 receive high byte receive middle byte receive low byte 23 16 15 8 7 0 707070 transmit high byte transmit middle byte transmit low byte serial receive data register (rx) (read only) serial transmit shift register (a) shfd = 0 figure 7-36 crb shfd bit operation (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 61 the optional output flags are always updated at the beginning of the frame, regardless of std x:$ffef 23 16 15 8 7 0 707070 transmit high byte transmit middle byte transmit low byte serial transmit data register (tx) (write only) serial receive shift register (rx) 23 16 15 8 7 0 707070 transmit high byte transmit middle byte transmit low byte 8 bit 12 bit 16 bit 24 bit srd x:$ffef 23 16 15 8 7 0 707070 receive high byte receive middle byte receive low byte 23 16 15 8 7 0 707070 receive high byte receive middle byte receive low byte serial receive data register (rx) (read only) serial transmit shift register (b) shfd=1 figure 7-37 crb shfd bit operation (sheet 2 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 62 synchronous serial interface motorola te. the state of the flag does not change for the entire frame. figure 6-39 is an example of transmitting data using the ssi in the normal mode with a continuous clock, a bit-length frame sync, and 16-bit data words. the purpose of the program is to interleave and transmit right and left channels in a compact disk player. four ssi pins are used: 1. sc0 is used as an output flag to indicate right-channel data (of0=1) or left-channel data (of0=0) 2. sc2 is tx and rx frame sync out 3. std is transmit data out 4. sck clocks the transmit data out equates are set for convenience and readability. test data is then put in the low x: mem- dsp data dsp data serial clock serial sync transmit data codec data receive data mc1550x codec filter dsp56003/005 tdd rdd tdc rdc tde rce msi tx1 rx0 srd std sck sc2 analog input analog output codec data figure 7-38 normal mode example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 63 ory locations. the transmit interrupt vector contains a jsr instruction (which forms a long interrupt). the data pointer and channel flag are initialized before initializing cra and crb. it is assumed that the dsp cpu and ssi have been previously reset. at this point, the ssi is ready to transmit except that the interrupt is masked because the mr was cleared on reset and port c is still configured as general-purpose i/o. unmask- ing the interrupt and enabling the ssi pins allows transmission to begin. a ?ump to self instruction causes the dsp to hang and wait for interrupts to transmit the data. when an interrupt occurs, a jsr instruction at the interrupt vector location causes the xmt routine to be executed. data is then moved to the tx register, and the data pointer is incremented. the flag is tested by the jset instruction and, if it is set, a jump to left occurs, and the code for the left channel is executed. if the flag is not set, the code for the right channel is exe- cuted. in either case, the channel flag in x0 and then the output flag are set to reflect the channel being transmitted. control is then returned to the main program, which will wait for the next interrupt. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 64 synchronous serial interface motorola ;************************************************* ; ssi and other i/o equates * ;************************************************* ipr equ $ffff cra equ $ffec crb equ $ffed pcc equ $ffe1 tx equ $ffef flg equ $0010 org x:0 dc $aaaa00;data to transmit. dc $333300 dc $cccc00 dc $f0f000 ;************************************************* ; interrupt vector * ;************************************************* org p:$0010 jsr xmt ;************************************************* ; main program * ;************************************************* org p:$40 move #0,r0 ;pointer to data buffer. move #3,m0 ;set modulus to 4. move #0,x0 ;initialize channel flag for ssi flag. move x0,x:flg ;start with right channel first. ;************************************************* ; initialize ssi port * ;************************************************* movep #$3000,x:ipr ;set interrupt priority register for ssi. movep #$401f,x:cra ;set continuous clock=5.12/32 mhz ;word length=16. movep #$5334,x:crb ;enable tie and te; make clock and ;frame sync outputs; frame ;sync=bit mode; synchronous mode; ;make sc0 an output. figure 7-39 normal mode transmit example (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 65 ;************************************************* ; init ssi interrupt * ;************************************************* andi #$fc,mr ;unmask interrupts. movep #$01f8,x:pcc ;turn on ssi port. jmp * ;wait for interrupt. ;************************************************* ; main interrupt routine * ;************************************************* xmt movep x:(r0);pl,x:tx ;move data to tx register. jset #0,x:flg,left ;check channel flag. right bclr #0,x:crb ;clear sc0 indicating right channel data move #>$01,x0 ;set channel flag to 1 for next data. move x0,x:flg rti left bset #0,x:crb ;set sc0 indicating left channel data. move #>$00,x0 ;clear channel flag for next data. move x0,x:flg rti end figure 6-39 normal mode transmit example (sheet 2 of 2) 7.3.7.2.2 normal mode receive if the receiver is enabled, a data word will be clocked in each time the frame sync signal is generated (internal) or detected (external). after receiving the data word, it will be transferred from the ssi receive shift register to the receive data register (rx), rdf will be set (receiver full), and the receive interrupt will occur if it is enabled (rie=1). the dsp program has to read the data from rx before a new data word is transferred from the receive shift register; otherwise, the receiver overrun error will be set (roe=1). figure 7-40 illustrates the program that receives the data transmitted by the program shown in figure 6-39. using the flag to identify the channel, the receive program receives the right- and left-channel data and separates the data into a right data buffer and a left data buffer. the program shown in figure 7-40 begins by setting equates and then using a jsr instruction at the receive interrupt vector location to form a long interrupt. the main program starts by initializing pointers to the right and left data buffers. the ipr, cra, and crb are then initialized. the clock divider bits in the cra do not have to be set since an external receive clock is specified (sckd=0). pin sc0 is specified as an input flag (syn=1, scd0=0); pin sc2 is specified as tx and rx frame sync (syn=1, scd2=0). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 66 synchronous serial interface motorola the ssi port is then enabled and interrupts are unmasked, which allows the ssi port to begin data reception. a jump-to-self instruction is then used to hang the processor and allow interrupts to receive the data. normally, the processor would execute useful in- structions while waiting for the receive interrupts. when an interrupt occurs, the jsr in- struction at the interrupt vector location transfers control to the rcv subroutine. the in- put flag is tested, and data is put in the left or right data buffer depending on the results of the test. the rti instruction then returns control to the main program, which will wait for the next interrupt. ;************************************************* ; ssi and other i/o equates * ;************************************************* ipr equ $ffff ssisr equ $ffee cra equ $ffec crb equ $ffed pcc equ $ffe1 rx equ $ffef flg equ $0010 ;************************************************* ; interrupt vector * ;************************************************* org p:$000c jsr rcv ;************************************************* ; main program * ;************************************************* org p:$40 move #0,r0 ;pointer to memory buffer for move #$08,r1 ;received data. note data will be move #1,m0 ;split between two buffers which are move #1,m1 ;modulus 2. figure 7-40 normal mode receive example (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 67 ;************************************************* ; initialize ssi port * ;************************************************* movep #$3000,x:ipr ;set interrupt priority register ;for ssi. movep #$4000,x:cra ;set word length = 16 bits. movep #$a300,x:crb ;enable rie and re; synchronous ;mode with bit frame sync; ;clock and frame sync are ;external; sc0 is an output. ;************************************************* ; init ssi interrupt * ;************************************************* andi #$fc,mr ;unmask interrupts. movep #$01f8,x:pcc ;turn on ssi port. jmp * ;wait for interrupt. ;************************************************* ; main interrupt routine * ;************************************************* rcv jset #0,x:ssisr, right ;test sco flag. left movep x:rx,x:(ro)+ ;if sco clear, receive data rti ;into left buffer (r0). right movep x:rx,x:(r1)+ ;if sco set, receive data rti ;into right buffer (r1). end figure 7-40 normal mode receive example (sheet 2 of 2) 7.3.7.3 network mode examples the network mode, the typical mode in which the dsp would interface to a tdm codec network or a network of dsps, is compatible with bell and ccitt pcm data/operation formats. the dsp may be a master device (see figure 7-41) that controls its own private network or a slave device that is connected to an existing tdm network, occupying one or more time slots. the key characteristic of the network mode is that each time slot (data word time) is identified by an interrupt or by polling status bits, which allows the option of ignoring the time slot or transmitting data during the time slot. the receiver operates in the same manner except that data is always being shifted into the receive shift register and transferred to the rx. the dsp reads the receive data register and uses or discards the contents. overrun and underrun errors are detected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 68 synchronous serial interface motorola the frame sync signal indicates the beginning of a new data frame. each data frame is divided into time slots; transmission or reception can occur in each time slot (rather than in just the frame sync time slot as in normal mode). the frame rate dividers (controlled by dc4, dc3, dc2, dc1, and dc0) control the number of time slots per frame from 2 to 32. time-slot assign- ment is totally under software control. devices can transmit on multiple time slots, receive multiple time slots, and the time-slot assignment can be changed dynamically. a simplified flowchart showing operation of the network mode is shown in figure 7-42. two counters are used to track the current transmit and receive time slots. slot counter one (slotct1) is used to track the transmit time slot; slot counter two (slotct2) is used for receive. when the transmitter is empty, it generates an interrupt; a test is then made to see if it is the beginning of a frame. if it is the beginning of a frame, slotct1 is cleared to start counting the time slots. if it is not the beginning of a frame, slotct1 is increment- ed. the next test checks to see if the ssi should transmit during this time slot. if it is time to transmit, data is written to the tx; otherwise, dummy data is written to the tsr, which prevents a transmit underrun error from occurring and three-states the std pin. the dsp can then return to what it was doing before the interrupt and wait for the next interrupt to occur. slotct1 should reflect the data in the shift registers to coincide with tfs. soft- ware must recognize that the data being written to tx will be transmitted in time slot slotct1 plus one. the receiver operates in a similar manner. when the receiver is full, an interrupt is generated, and a test is made to see if this is the beginning of a frame. if it is the beginning of a frame, slotct2 is cleared to start counting the time slots. if it is not the beginning of a frame, slotct2 is incremented. the next test checks to see if the data received is intended for this dsp. if the current time slot is the one assigned to the dsp receiver, the data is kept; otherwise, the data is discarded, and the dsp can then return to what it was doing before the interrupt. dsp56003/005 master time slot 1 std srd sck sc2 dsp56003/005 slave 1 time slot 2 std srd sck sc2 dsp56003/005 slave 2 time slot 3 std srd sck sc2 dsp56003/005 slave 3 time slot 4 std srd sck sc2 master transmit master receive master clock master sync figure 7-41 network mode example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 69 slotct2 should reflect the data in the receive shift register to coincide with the rfs transmitter empty interrupt test for frame sync tfs = 1? clear slot number slotct1 increment slot number slotct1 = slotct1 + 1 my turn to transmit? slotct1 = myslot? write data to tx write dummy data to tsr exit yes no no yes receiver full interrupt test for frame sync rfs = 1? clear slot number slotct2 = 0 increment slot number slotct2 = slotct2 + 1 is data for me? slotct2 = myslot? keep data discard data exit yes no no yes read data from rx figure 7-42 tdm network software flowchart f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 70 synchronous serial interface motorola flag. software must recognize that the data being read from rx is for time slot slotct2 minus two. initializing the network mode is accomplished by setting the bits in cra and crb as fol- lows (see figure 7-43): 1. the word length must be selected by setting wl1 and wl0. in this example, an 8-bit word length was chosen (wl1=0 and wl0=0). 2. the number of time slots is selected by setting dc4?c0. four time slots were chosen for this example (dc4?c0=$03). 3. the serial clock rate must be selected by setting psr and pm7?m0 (see table 7-11 (a), table 7-11 (b), and table 7-12). 4. re and te must be set to activate the transmitter and receiver. if interrupts are to be used, rie and tie should be set. rie and tie are usually set after everything else is configured and the dsp is ready to receive interrupts. 5. the network mode must be selected (mod=1). 6. a continuous clock is selected in this example by setting gck=0. 7. although it is not required for the network mode, synchronous clock control was selected (syn=1). 8. the frame sync length was chosen in this example as word length (fsl1=0) for both transmit and receive frame sync (fsl0=0). any other combinations could have been selected, depending on the application. 9. control bits shfd, sckd, scd2, scd1, scd0, and the flag bits (of1 and of0) should be set as needed for the application. 7.3.7.3.1 network mode transmit when te is set, the transmitter will be enabled only after detection of a new data frame sync. this procedure allows the ssi to synchronize to the network timing. normal startup sequence for transmission in the first time slot is to write the data to be transmitted to tx, which clears the tde flag. then set te and tie to enable the transmit- ter on the next frame sync and to enable transmit interrupts. alternatively, the dsp programmer may decide not to transmit in the first time slot by writing any data to the time slot register (tsr). this will clear the tde flag just as if data were going to be transmitted, but the std pin will remain in the high-impedance state for the first time slot. the programmer then sets te and tie. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 71 serial data 4 frame sync x:$ffec 15141312111098 76543210 psr pm5 pm4 pm3 pm2 0 000011pm7pm6 pm1pm0 wl1 wl0 dc4 dc3 dc2 dc1 dc0 8-bit word length four time slots ssi control register a (cra) (read/write) x:$ffed 15141312111098 76543210 rie sckd scd2 scd1 scd0 tie re te 1 0 1 0 0 shfd of1 of0 mod ssi mode select 1 = network gck gated clock control 0 = continuous clock syn sync/async control 1 = synchronous scd2 serial control 2 direction 1 = output (master) 0 = input (slave) sckd clock source direction 1 = output (master) 0 = input (slave) fls0 frame sync length 0 0 =tx, rx sync same length fsl1 frame sync length 1 0 = word width ssi control register b (crb) (read/write) serial clock slot 1 slot 4 slot 3 slot 2 slot 1 s internal tx flags and interrupts internal rx flags and interrupts 76 54 32 10 rdf tde roe tue rfs tfs if1 if0 ** ** ** * * x:$ffee x:$ffee ssi status register (sr) (read) ssi time slot register b (tsr) (write) figure 7-43 network mode initialization f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 72 synchronous serial interface motorola when the frame sync is detected (or generated), the first data word will be transferred from tx to the transmit shift register and will be shifted out (transmitted). tx being emp- ty will cause tde to be set, which will cause a transmitter interrupt. software can poll tde or use interrupts to reload the tx register with new data for the next time slot. soft- ware can also write to tsr to prevent transmitting in the next time slot. failing to reload tx (or writing to the tsr) before the transmit shift register is finished shifting (empty) will cause a transmitter underrun. the tue error bit will be set, causing the previous data to be retransmitted. the operation of clearing te and setting it again will disable the transmitter after comple- tion of transmission of the current data word until the beginning of the next frame sync pe- riod. during that time, the std pin will be three-stated. when it is time to disable the trans- mitter, te should be cleared after tde is set to ensure that all pending data is transmitted. the optional output flags are updated every time slot regardless of te. to summarize, the network mode transmitter generates interrupts every time slot and re- quires the dsp program to respond to each time slot. these responses can be: 1. write data register with data to enable transmission in the next time slot 2. write the time slot register to disable transmission in the next time slot 3. do nothing ?transmit underrun will occur the at beginning of the next time slot, and the previous data will be transmitted figure 7-44 differs from the program shown in figure 6-39 only in that it uses the net- work mode to transmit only right-channel data. a time slot is assigned for the left-chan- nel data, which could be inserted by another dsp using the network mode. in the ?ni- tialize ssi port?section of the program, two words per frame are selected using cra, and the network mode is selected by setting mod to one in the crb. the main interrupt routine, which waits to move the data to tx, only transmits data if the current time slot is for the right channel. if the current time slot is for the left channel, the tsr is written, which three-states the output to allow another dsp to transmit the left channel during the time slot. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 73 ;************************************************* ; ssi and other i/o equates * ;************************************************* ipr equ $ffff cra equ $ffec crb equ $ffed pcc equ $ffe1 tx equ $ffef tsr equ $ffee flg equ $0010 org x:0 dc $aaaa00 ;data to transmit. dc $333300 dc $cccc00 dc $f0f000 ;************************************************* ; interrupt vector * ;************************************************* org p:$0010 jsr xmt ;************************************************* ; main program * ;************************************************* org p:$40 move #0,r0 ;pointer to data buffer. move #3,m0 ;set modulus to 4. move #0,x0 ;initialize user flag for ssi flag. move x0,x:flg ;start with the right channel. figure 7-44 network mode transmit example program (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 74 synchronous serial interface motorola ;************************************************* ; initialize ssi port * ;************************************************* movep #$3000,x:ipr ;set interrupt priority register ;for ssi. movep #$411f,x:cra ;set continuous clock=5.12/32 mhz ;word length=16. movep #$5b34,x:crb ;enable tie and te; make clock and ;frame sync outputs; frame ;sync=bit mode; synchronous mode; ;make sc0 an output. ;************************************************* ; init ssi interrupt * ;************************************************* andi #$fc,mr ;unmask interrupts. movep #$01f8,x:pcc ;turn on ssi port. jmp * ;wait for interrupt. ;************************************************* ; main interrupt routine * ;************************************************* xmt jset #0,x:flg,left ;check user flag. right bclr #0,x:crb ;clear sc0 indicating right channel data movep x:(r0)+,x:tx move data to tx register. move #>$01,x0 ;set user flag to 1 move x0,x:flg ;for next data. rti left bset #0,x:crb ;set sc0 indicating left channel data. movep x0,x:tsr ;write to tsr register. move #>$00,x0 ;clear user flag move x0,x:flg ;for next data. rti end figure 7-44 network mode transmit example program (sheet 2 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 75 ;************************************************* ; ssi and other i/o equates * ;************************************************* ipr equ $ffff ssisr equ $ffee cra equ $ffec crb equ $ffed pcc equ $ffe1 rx equ $ffef ;************************************************* ; interrupt vector * ;************************************************* org p:$000c jsr rcv ;************************************************* ; main program * ;************************************************* org p:$40 move #0,r0 ;pointer to memory buffer for move #$08,r1 ;received data. note data will be move #3,m0 ;split between two buffers which are move #3,m1 ;modulus 4. ;************************************************* ; initialize ssi port * ;************************************************* movep #$3000,x:ipr ;set interrupt priority register ;for ssi. movep #$4100,x:cra ;set word length = 16 bits. movep #$ab00,x:crb ;enable rie and re; synchronous ;mode with bit frame sync; ;clock and frame sync are ;external; sc0 is an input. figure 7-45 network mode receive example program (sheet 1 of 2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 76 synchronous serial interface motorola ;************************************************* ; init ssi interrupt * ;************************************************* andi #$fc,mr ;unmask interrupts. movep #$01f8,x:pcc ;turn on ssi port. jmp * ;wait for interrupt. ;************************************************* ; main interrupt routine * ;************************************************* rcv jset #0,x:ssisr, right;test sco flag. left movep x:rx,x:(ro)+ ;if sco clear, receive data rti ;into left buffer (r0). right movep x:rx,x:(r1)+ ;if sco set, receive data rti ;into right buffer (r1). end figure 7-45 network mode receive example program (sheet 2 of 2) 7.3.7.3.2 network mode receive the receive enable will occur only after detection of a new data frame with re set. the first data word is shifted into the receive shift register and is transferred to the rx, which sets rdf if a frame sync was received (i.e., this is the start of a new frame). setting rdf will cause a receive interrupt to occur if the receiver interrupt is enabled (rie=1). the second data word (second time slot in the frame) begins shifting in immediately after the transfer of the first data word to the rx. the dsp program has to read the data from rx (which clears rdf) before the second data word is completely received (ready to transfer to rx), or a receive overrun error will occur (roe=1), and the data in the receiver shift register will not be transferred and will be lost. if re is cleared and set again by the dsp program, the receiver will be disabled after re- ceiving the current time slot in progress until the next frame sync (first time slot). this mechanism allows the dsp programmer to ignore data in the last portion of a data frame. note: the optional frame sync output and clock output signals are not affected, even if the transmitter and/or receiver are disabled. te and re do not disable bit clock and frame sync generation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 77 to summarize, the network mode receiver receives every time slot data word unless the receiver is disabled. an interrupt can occur after the reception of each data word, or the programmer can poll rdf. the dsp program response can be 1. read rx and use the data 2. read rx and ignore the data 3. do nothing ?the receiver overrun exception will occur at the end of the cur- rent time slot 4. toggle re to disable the receiver until the next frame, and read rx to clear rdf figure 7-45 is essentially the same program shown in figure 7-40 except that this program uses the network mode to receive only right-channel data. in the ?nitialize ssi port?sec- tion of the program, two words per frame are selected using the dc bits in the cra, and the network mode is selected by setting mod to one in the crb. if the program in figure 7-44 is used to transmit to the program in figure 7-45, the correct data will appear in the data buffer for the right channel, but the buffer for the left channel will probably contain $000000 or $ffffff, depending on whether the transmitter output was high or low when tsr was written and whether the output was three-stated. 7.3.7.4 on-demand mode examples a divide ratio of one (dc=00000) in the network mode is defined as the on-demand mode of the ssi because it is the only data-driven mode of the ssi ?i.e., data is transferred when- ever data is present (see figure 7-46 and figure 7-47). std and sck from dsp1 are con- nected to dsp2 ?srd and sc0, respectively. sc0 is used as an input clock pin in this ap- plication. receive data and receive data clock are separate from the transmit signals. on-demand data transfers are nonperiodic, and no time slots are defined. when there is a clock in the gated clock mode, data is transferred. although they are not necessarily needed, frame sync and flags are generated when data is transferred. transmitter under- runs (tue) are impossible in this mode and are therefore disabled. in the on-demand transmit mode, two additional ssi clock cycles are automatically inserted between each data word transmitted. this procedure guarantees that frame sync will be low between every transmitted data word or that the clock will not be continuous between two consec- utive words in the gated clock mode. the on-demand mode is similar to the sci shift reg- ister mode with ssftd equals one and sckp equals one. the receiver should be config- ured to receive the bit clock and, if continuous clock is used, to receive an external frame sync. therefore, for all full-duplex communication in on-demand mode, the asynchro- nous mode should be used. the on-demand mode is spi compatible. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 78 synchronous serial interface motorola initializing the on-demand mode for the example illustrated in figure 7-47 is accom- plished by setting the bits in cra and crb as follows: 1. the word length must be selected by setting wl1 and wl0. in this example, a 24-bit word length was chosen (wl1=1 and wl0=1). 2. the on-demand mode is selected by clearing dc4?c0. 3. the serial clock rate must be selected by setting psr and pm7?m0 (see table 7-11 (a), table 7-11 (b), and table 7-12). 4. re and te must be set to activate the transmitter and receiver. if interrupts are to be used, rie and tie should be set. rie and tie are usually set after every- thing else is configured and the dsp is ready to receive interrupts. 5. the network mode must be selected (mod=1). 6. a gated clock (gck=1) is selected in this example. a continuous clock exam- ple is shown in figure 7-44. 7. asynchronous clock control was selected (syn=0) in this example. 8. since gated clock is used, the frame sync is not necessary. fsl1 and fsl0 can be ignored. 9. sckd must be an output (sckd=1). 10. scd0 must be an input (scd0=0). 11. control bit shfd should be set as needed for the application. pins sc1 and sc2 are undefined in this mode (see table 7-8) and should be programmed as general-purpose i/o pins. dsp56003/005 dsp1 std sck srd sc0 dsp56003/005 dsp2 srd sco std sck figure 7-46 on demand example f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 79 24-bit data from dsp1 to dsp2 two ssi bit clocks (min.) 24-bit data from dsp2 to dsp1 dsp2 to dsp1 transmit data x:$ffec 15141312111098 76543210 psr pm5 pm4 pm3 pm2 1 100000pm7pm6 pm1pm0 wl1 wl0 dc4 dc3 dc2 dc1 dc0 24-bit word length on-demand ssi control register a (cra) (read/write) x:$ffed 15141312111098 76543210 rie 1 scd2 scd1 0 tie re te 1 1 0 fsl1 fsl0 shfd of1 of0 mod ssi mode select 1 = network gck gated clock control 1=gated cl0ck syn sync/async control 0 = asynchronous scd0 serial control 2 direction 0 = input sckd clock source direction 1 = output ssi control register b (crb) (read/write) transmit clock figure 7-47 on-demand data-driven network mode receive data receive clock note: two ssi bit clock times are automatically inserted between each data word. this guarantees frame sync will be low between every data word transmitted and the clock will not be continuous for two consecutive data words. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 80 synchronous serial interface motorola 7.3.7.4.1 on-demand mode ?continuous clock this special case will not generate a periodic frame sync. a frame sync pulse will be gen- erated only when data is available to transmit (see figure 7-48(a)). the frame sync signal indicates the first time slot in the frame. the on-demand mode requires that the transmit frame sync be internal (output) and the receive frame sync be external (input). therefore, for simplex operation, the synchronous mode could be used; however, for full-duplex op- eration, the asynchronous mode must be used. data transmission that is data driven is en- abled by writing data into tx. although the ssi is double buffered, only one word can be written to tx, even if the transmit shift register is empty. the receive and transmit inter- rupts function as usual using tde and rdf; however, transmit and receive underruns are impossible for on-demand transmission and are disabled. this mode is useful for inter- facing to codecs requiring a continuous clock. 7.3.7.4.2 on-demand mode ?gated clock gated clock mode (see figure 7-48(b)) is defined for on-demand mode, but the gated clock mode is considered a frame sync source; therefore, in gated clock mode, the transmit clock must be internal (output) and the receive clock must be external (input). for ondemand mode, with internal (output) synchronous gated clock, output clock is enabled for the transmitter and receiver when tx data is transferred to the transmit data shift register. data data serial clock frame sync (a) continuous serial data data changes data stable serial clock data data serial data (b) gated figure 7-48 clock modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 81 this spi master operating mode is shown in figure 7-49. word sync is inherent in the clock signal, and the operation format must provide frame synchronization. figure 7-50 is the block diagram for the program presented in figure 7-51. this program contains a transmit test program that was written as a scoping loop (providing a repeti- tive sync) using the on-demand, gated, synchronous mode with no interrupts (polling) to transmit data to the program shown in figure 7-52. the program also demonstrates using gpio pins as general-purpose control lines. pc3 is used as an external strobe or enable for hardware such as an a/d converter. the transmit program sets equates for convenience and readability. test data is then writ- ten to x: memory, and the data pointer is initialized. setting m0 to two makes the buffer cir- cular (modulo 3), which saves the step of resetting the pointer each loop. pc3 is configured as a general-purpose output for use as a scope sync, and cra and crb are then initialized. setting the pcc bits begins ssi operation; however, no data will be transmitted until data is written to tx. pc3 is set high at the beginning of data transmission; data is then moved to tx to begin transmission. a jclr instruction is then used to form a wait loop until tde equals one and the ssi is ready for another data word to be transmitted. two more data words are transmitted in this fashion (this is an arbitrary number chosen for this test loop). an additional wait is included to make sure that the frame sync has gone low before pc3 is cleared, indicating on the scope that transmission is complete. a wait of 100 nops is imple- mented by using the rep instruction before starting the loop again. dsp1 master slave dsp2 shift register shift register spi clock generator figure 7-49 spi configuration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 82 synchronous serial interface motorola ;************************************************* ; ssi and other i/o equates * ;************************************************* cra equ $ffec crb equ $ffed pcc equ $ffe1 pcd equ $ffe5 ssisr equ $ffee tx equ $ffef pcddr equ $ffe3 org x:0 dc $aa0000 ;data to transmit. dc $330000 dc $f00000 ;************************************************* ; main program * ;************************************************* org p:$40 move #0,r0 ;pointer to data buffer move #2,m0 ;length off buffer is 3 figure 7-51 on-demand mode transmit example program (sheet 1 of 2) dsp56003/005 pc3 sc2 std sck dsp56003/005 srd sck 15k w figure 7-50 on-demand mode example ?hardware configuration f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 83 movep #$08,x:pcddr ;sc0 (pc3) as general purpose output. movep #$001f,x:cra ;set word length=8, clk=5.12/32 mhz movep #$1e30,x:crb ;enable transmitter, mode=on- demand, ;gated clock on, synchronous mode, ;word frame sync selected, frame ;sync and clock are internal and ;output to port pins. movep #$1f0,x:pcc ;set pcc for ssi and loop0 bset #3,x:pcd ;set pc3 high (this is example enable ;or strobe for an external device :such as an adc). movep x:(r0);pl,x:tx ;move data to tx register tde1 jclr #6,x:ssisr,tde1 ;wait for tde (transmit data register ;empty) to go high. movep x:(r0);pl,x:tx ;move next data to tx. tde2 jclr #6,x:ssisr,tde2 ;wait for tde to go high. movep x:(r0);pl,x:tx ;move data to tx. tde3 jclr #6,x:ssisr,tde3 ;wait for tde=1. fsc jset #5,x:pcd,fsc ;wait for frame sync to go low. note: ;state of frame sync is directly ;determined by reading pc5. bclr #3,x:pcd ;set pc3 lo (example external enable). ;anything goes here (i.e., any processing) rep #100 nop jmp loop0 ;continue sequence forever. end figure 7-51 on-demand mode transmit example program (sheet 2 of 2) figure 7-52 is the receive program for the scoping loop program presented in figure 7-51. the receive program also uses the on-demand, gated, synchronous mode with no inter- rupts (polling). initialization for the receiver is slightly different than for the transmitter. in crb, re is set rather than te, and sckd and scd2 are inputs rather than outputs. after initialization, a jclr instruction is used to wait for a data word to be received (rdf=1). when a word is received, it is put into the circular buffer and loops to wait for another data word. the data in the circular buffer will be overwritten after three words are received (does not matter in this application). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 84 synchronous serial interface motorola ;************************************************* ; ssi and other i/o equates * ;************************************************* cra equ $ffec crb equ $ffed pcc equ $ffe1 pcd equ $ffe5 ssisr equ $ffee rx equ $ffef pcddr equ $ffe3 ;************************************************* ; main program * ;************************************************* org p:$40 move #0,r0 ;pointer to data buffer move #2,m0 ;length of buffer is 3 movep #$001f,x:cra ;set word length=8, clk=5.12/32 mhz movep #$1e30,x:crb ;enable receiver, mode=on-demand, ;gated clock on, synchronous mode, ;word frame sync selected, frame ;sync and clock are external. movep #$1f0,x:pcc ;set pcc for ssi loop rdf1 jclr #7,x:ssisr,rdf1 ;wait for rdf (receive data register ;full) go to high. movep x:rx,x:(r0)+ ;read data from rx into memory. jmp loop ;continue sequence forever. end figure 7-52 on-demand mode receive example program f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 85 7.3.8 flags two ssi pins (sc1 and sc0) are available in the synchronous mode for use as serial i/o flags. the control bits (of1 and of0) and status bits (if1 and if0) are double buffered to/from sc1 and sc0. double buffering the flags keeps them in sync with tx and rx. the direction of sc1 and sc0 is controlled by scd1 and scd0 in crb. figure 7-53 shows the flag timing for a network mode example. initially, neither tie nor te is set, and the flag outputs are the last flag output value. when tie is set, a tde inter- rupt occurs (the transmitter does not have to be enabled for this interrupt to occur). data (d1) is written to tx, which clears tde, and the transmitter is enabled by software. when the frame sync occurs, data (d1) is transferred to the transmit shift register, setting tde. data (d1) is shifted out during the first word time, and the output flags are updated. these flags will remain stable until the next frame sync. the tde interrupt is then ser- viced by writing data (d2) to tx, clearing tde. after the tsr completes transmission, the transmit pin is three-stated until the next frame sync figure 7-54 shows a speaker phone example that uses a dsp56003/005 and two codecs. no additional logic is required to connect the codecs to the dsp. the two serial output flags in this example (of1 and of0) are used as chip selects to enable the appropriate co- dec for i/o. this procedure allows the transmit lines to be ored together. the appropri- ate output flag pin changes at the same time as the first bit of the transmit word and re- mains stable until the next transmit word (see figure 7-55). applications include seri- al-device chip selects, implementing multidrop protocols, generating bell pcm signaling frame syncs, and outputting status information. initializing the flags (see figure 7-55) is accomplished by setting syn, scd1, and scd0. no other control bits affect the flags. the synchronous control bit must be set (syn=1) to select the sc1 and sc0 pins as flags. scd1 and scd0 select whether sc1 and sc0 are in- puts or outputs (input=0, output=1). the other bits selected in figure 7-55 are chosen for the speaker phone example in figure 7-54. in this example, the codecs require that the ssi be set for normal mode (mod=0) with a gated clock (gck=1) out (sckd=1). serial input flags, if1 and if0, are latched at the same time as the first bit is sampled in the receive data word (see figure 7-56). since the input was latched, the signal on the input flag pin can change without affecting the input flag until the first bit of the next receive data word. to initialize sc1 or sc0 as input flags, the synchronous control bit in crb must be set to one (syn=1) and scd1 set to zero for pin sc1, and scd0 must be set to zero for pin sc0. the input flags are bits 1 and 0 in the ssisr (at x:$ffee). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 86 synchronous serial interface motorola frame sync start tie te tde interrupts d1 d2 d3 load tsr d1 d2 data wo r d d1 d2 word time time slot * f1 f2 output flags notes: 1. fn = ?gs associated with dn data. 2. output ?gs are double buffered with transmit data. 3. output ?gs change when data is transferred from tx to the transmit data shift register. 4. initial ?g outputs (*) = last ?g output value. 5. data and ?gs transition after external frame sync but not before rising edge of clock. figure 7-53 output flag timing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 87 7.3.9 example circuits the dsp-to-dsp serial network shown in figure 7-57 uses no additional logic chips for the network connection. all serial data is synchronized to the data source (all serial clocks and serial syncs are common). this basic configuration is useful for decimation and data reduc- tion when more processing power is needed than one dsp can provide. cascading dsps in this manner is useful in several network topologies including star and ring networks. tdm networks are useful to reduce the wiring needed for connecting multiple pro- cessors. a tdm parallel topology, such as the one shown in figure 7-58, is useful for interpolating filters. serial data can be received simultaneously by all dsps, process- ing can occur in parallel, and the results are then multiplexed to a single serial data out line. this configuration can be cascaded and/or looped back on itself as needed to fit a particular application (see figure 7-59). the serial and parallel configurations can be combined to form the array processor shown in figure 7-60. a nearest neigh- bor array, which is applicable to matrix relaxation processing, is shown in figure 7-61. mc15500 codec filter 1 tdd rdd tdc rdc tde rce msi txi rxo mc15500 codec filter 2 tdd rdd tdc rdc tde rce msi txi rxo dsp5002 srd std sck sc0 sc1 microphone speaker phone line input phone line output output flag 1 output flag 0 of0 of1 speaker phone figure 7-54 output flag example note: sc0 and sc1 are output flag 0 and 1 used to software select either filter 1 or 2. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 88 synchronous serial interface motorola to simplify the drawing, only the center dsp is connected in this illustration. in use, transmit clock 15141312111098 76543210 rie 1 scd2 1 1 tie re te 0 1 1 fsl1 fsl0 shfd of1 of0 mod ssi mode select 0 = normal gck gated clock control 1 = gated clock syn sync/async control 1 = synchronous sckd clock source direction 1 = output scd1 and scd0 serial control 1 and 0 direction 1 = output 0 1 = filter 1 1 0 = filter 2 transmit data b7 b6 b5 b4 b3 b2 b1 b0 output flag valid output flag of0 and lf1 are clocked out on the rising edge of the transmit clock. output flags are always valid until the next word transmitted. figure 7-55 output flag initialization f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 89 all dsps would have four three-state buffers connected to their std pin. the flags receive clock receive data b7 b6 b5 b4 b3 b2 b1 b0 76 5 43 2 10 rdf tde roe tue rfs tfs if1 if0 x:$ffee ssi status register (ssisr) (read) input flags sample input flag figure 7-56 input flags data in dsp56003/005 srd std sck sc2 serial clock serial sync dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 data out figure 7-57 ssi cascaded multi-dsp system f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 90 synchronous serial interface motorola (sc0 and sc1) on the control master operate the three-state buffers, which control the dsp56003/005 srd std sck sc2 serial clock serial sync dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 serial data i n serial data out figure 7-58 ssi tdm parallel dsp network f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 91 direction that data is transferred in the matrix (north, south, east, or west). dsp56003/005 srd std sck sc2 frame sync serial clock dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 figure 7-59 ssi tdm connected parallel processing array f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 92 synchronous serial interface motorola the bus architecture shown in figure 7-62 allows data to be transferred between any two serial sync serial clock dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 serial in serial out figure 7-60 ssi tdm serial/parallel processing array dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 93 dsps. however, the bus must be arbitrated by hardware or a software protocol to prevent collisions. the master/slave configuration shown in figure 7-63 also allows data to be transferred between any two dsps but simplifies network control. dsp56003/005 srd sc0 sc1 std sck sc2 frame sync serial clock dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 dsp56003/005 srd std sck sc2 figure 7-61 ssi parallel processing ?nearest neighbor array f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) 7 - 94 synchronous serial interface motorola dsp56003/005 std srd sck sc2 serial data bus serial clock dsp56003/005 std srd sck sc2 dsp56003/005 std srd sck sc2 dsp56003/005 std srd sck sc2 serial sync figure 7-62 ssi tdm bus dsp network f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) motorola synchronous serial interface 7 - 95 dsp56003/005 master std srd sck sc2 sc1 sc0 dsp56003/005 slave 1 std srd sck sc2 sc1 sc0 dsp56003/005 slave 2 std srd sck sc2 sc1 sc0 dsp56003/005 slave 3 std srd sck sc2 sc1 sc0 master transmit master receive master clock master sync flag 1 flag 0 note: flags can specify data types: control, address, and data. figure 7-63 ssi tdm master-slave dsp network f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 8 - 1 section 8 timer/event counter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 8 - 2 timer/event counter motorola paragraph number page number section 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2 timer/event counter block diagram . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3 timer count register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4 timer control/status register (tcsr) . . . . . . . . . . . . . . . . . . . . 8-5 8.5 timer/event counter modes of operation . . . . . . . . . . . . . . . . 8-7 8.6 timer/event counter behavior during wait and stop . . . . . 8-21 8.7 operating considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.8 software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola timer/event counter 8 - 3 8.1 introduction this section describes the timer/event counter module. the timer can use internal or ex- ternal clocking and can interrupt the processor after a number of events (clocks) specified by a user program, or it can signal an external device after counting internal events. this timer/event counter is identical to the one on the dsp56002. the timer connects to the external world through the bidirectional tio pin. when tio is used as input, the module is functioning as an external event counter or is measuring ex- ternal pulse width/signal period. when tio is used as output, the module is functioning as a timer and tio becomes the timer pulse. when the tio pin is not used by the timer module it can be used as a general purpose i/o (gpio) pin. note : when the timer is disabled, the tio pin becomes three-stated. the tio pin should be pulled up or down to prevent undesired spikes from occurring when enabling it for use as a clock source when it is three-stated. 8.2 timer/event counter block diagram figure 8-1 shows a block diagram of the timer module. it includes a 24-bit read-write tim- er control and status register (tcsr), a 24-bit read-write timer count register (tcr), a 24-bit counter, and logic for clock selection and interrupt generation. 24-bit timer count gdb 24 24 24-bit timer control/ status register (tcsr) 24 24 timer interrupt clock select clk/2 tio 3 figure 8-1 timer/event counter module block diagram 24-bit counter register (tcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer count register (tcr) 8 - 4 timer/event counter motorola the dsp56003/005 views the timer as a memory-mapped peripheral occupying two 24- bit words in the x data memory space, and may use it as a normal memory-mapped pe- ripheral by using standard polled or interrupt programming techniques.the programming model is shown in figure 8-2. 8.3 timer count register (tcr) the 24-bit read-write tcr contains the value (specified by the user program) to be loaded into the counter when the timer is enabled (te=1), or when the counter has been decre- mented to zero and a new event occurs. if the tcr is loaded with n, the counter will be reloaded after (n+1) events. if the timer is disabled (te=0) and the user program writes to the tcr, the value is stored there but will not be loaded into the counter until the timer becomes enabled. when the timer is enabled (te=1) and the user program writes to the tcr, the value is stored there and will be loaded into the counter after the counter has been decremented to zero and a new event occurs. * do di dir ts g pi o tc2 tc1 tc0 inv tie te 0 timer control/status register (tcsr) address x:$ffde * - reserved, read as zero, should be written with zero for future compatibility 23 0 read/write timer count register (tcr) address x:$ffdf 23 figure 8-2 timer/event counter programming model ********** * * (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (1) read/write timer enable timer interrupt enable inverter timer control bits general purpose i0 timer status direction bit data input data output reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer control/status register (tcsr) motorola timer/event counter 8 - 5 in timer modes 4 and 5, however, the tcr will be loaded with the current value of the counter on the appropriate edge of the tio input signal (rather than with a value speci- fied by the user program). the value loaded to the tcr represents the width or the period of the signal coming in on the tio pin, depending on the timer mode. see sections 8.5.4 and 8.5.5 for detailed descriptions of timer modes 4 and 5. 8.4 timer control/status register (tcsr) the 24-bit read/write tcsr controls the timer and verifies its status. the tcsr can be ac- cessed by normal move instructions and by bit manipulation instructions. the control and status bits are described in the following paragraphs. 8.4.1 tcsr timer enable (te) bit 0 the te bit enables or disables the timer. setting the te bit (te=1) will enable the timer, and the counter will be loaded with the value contained in the tcr and will start decre- menting at each incoming event. clearing the te bit will disable the timer. hardware reset and software reset (reset instruction) clear te. 8.4.2 tcsr timer interrupt enable (tie) bit 1 the tie bit enables the timer interrupts after the counter reaches zero and a new event occurs. if tcr is loaded with n, an interrupt will occur after (n+1) events. setting tie (tie=1) will enable the interrupts.when the bit is cleared (tie=0) the inter- rupts are disabled. hardware and software resets clear tie. 8.4.3 tcsr inverter (inv) bit 2 the inv bit affects the polarity of the external signal coming in on the tio input and the polarity of the output pulse generated on the tio output. if tio is programmed as an input and inv=0, the 0-to-1 transitions on the tio input pin will decrement the counter. if inv=1, the 1-to-0 transitions on the tio input pin will dec- rement the counter. if tio is programmed as output and inv=1, the pulse generated by the timer will be in- verted before it goes to the tio output pin. if inv=0, the pulse is unaffected. in timer mode 4 (see section 8.5.4 timer mode 4 (pulse width measurement mode) ), the inv bit determines whether the high pulse or the low pulse is measured to determine input pulse width. in timer mode 5 (see section 8.5.5 timer mode 5 (period measure- ment mode) ), the inv bit determines whether the period is measured between leading or trailing edges. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer control/status register (tcsr) 8 - 6 timer/event counter motorola in gpio mode, the inv bit determines whether the data read from or written to the tio pin shall be inverted (inv=1) or not (inv=0). inv is cleared by hardware and software resets. note: because of its affect on signal polarity, and on how gpio data is read and written, the status of the inv bit is crucial to the timer? function. change it only when the timer is disabled (te=0). 8.4.4 tcsr timer control (tc0-tc2) bits 3-5 the three tc bits control the source of the timer clock, the behavior of the tio pin, and the timer mode of operation. table 8-1 summarizes the functionality of the tc bits. the timer control bits are cleared by hardware reset and software reset (reset instruction). note 1: if the clock is external, the counter will be decremented by the transitions on the tio pin. the dsp synchronizes the external clock to its own internal clock. the external clock? frequency should be lower than the maximum internal frequen- cy divided by 4 (clk/4). note 2: the tc2-tc0 bits should be changed only when te=0 (timer disabled) to ensure proper functionality. * - the gpio function is enabled only if tc2-tc0 are all 0 (zero) and the gpio bit is set. 8.4.5 tcsr general purpose i/o (gpio) bit 6 if the gpio bit is set (gpio=1) and if tc2-tc0 are all zeros, the tio pin operates as a gen- eral purpose i/o pin, whose direction is determined by the dir bit. if gpio=0 the general purpose i/o function is disabled. gpio is cleared by hardware and software resets. table 8-1 timer/event counter control bits tc2 tc1 tc0 tio clock mode 0 0 0 gpio* internal timer (mode 0) 0 0 1 output internal timer pulse (mode 1) 0 1 0 output internal timer toggle (mode 2) 0 1 1 reserved - do not use 1 0 0 input internal input width (mode 4) 1 0 1 input internal input period (mode 5) 1 1 0 input external standard time counter (mode 6) 1 1 1 input external event counter (mode 7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation motorola timer/event counter 8 - 7 note: the case where tc2-tc0 are not all zero and gpio=1 is undefined and should not be used. 8.4.6 tcsr timer status (ts) bit 7 when the ts bit is set, it indicates that the counter has been decremented to zero. the ts bit is cleared when the tcsr is read. the bit is also cleared when the timer interrupt is serviced (timer interrupt acknowledge). ts is cleared by hardware and software resets. 8.4.7 tcsr direction (dir) bit 8 the dir bit determines the behavior of the tio pin when tio acts as general purpose i/o. when dir=0, the tio pin acts as an input. when dir=1, the tio pin acts as an out- put. dir is cleared by hardware and software resets. note: the tio pin can act as a general purpose i/o pin only when tc2-tc0 are all zero and the gpio bit is set. if one of tc2, tc1 or tc0 is not 0, the gpio function is dis- abled and the dir bit has no effect. 8.4.8 tcsr data input (di) bit 9 when the tio pin acts as a general purpose i/o input pin (tc2-tc0 are all zero and dir=0), the contents of the di bit will reflect the value the tio pin. however, if the inv bit is set, the data in di will be inverted. when gpio mode is disabled or it is enabled in output mode (dir=1), the di bit reflects the value of the tio pin, again depending on the status of the inv bit. di is set by hardware and software resets. 8.4.9 tcsr data output (do) bit 10 when the tio pin acts as a general purpose i/o output pin (tc2-tc0 are all zero and dir=1), writing to the do bit writes the data to the tio pin. however, if the inv bit is set, the data written to the tio pin will be inverted. when gpio mode is disabled, writing to the do bit will have no effect. do is cleared by hardware and software resets. 8.4.10 tcsr reserved bits 11-23 these reserved bits are read as zero and should be written with zero for future compatibility. 8.5 timer/event counter modes of operation this section gives the details of each of the timer modes of operation. table 8-1 on page 8-6 summarizes the items which determine the timer mode, including the configuration of the timer control bits, the function of the tio pin, and the clock source. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation 8 - 8 timer/event counter motorola 8.5.1 timer mode 0 (standard timer mode, internal clock, no timer output) timer mode 0 is defined by tcsr bits tc2-tc0 equal to 000. with the timer enabled (te=1), the counter is loaded with the value contained by the tcr. the counter is decremented by a clock derived from the internal dsp clock, divided by two (clk/2). during the clock cycle following the point where the counter reaches 0, the ts bit is set and, if the tie bit is set, the timer generates an interrupt. the counter is re- loaded with the value contained by the tcr, and the entire process is repeated until the timer is disabled (te=0). figure 8-3 illustrates mode 0 with the timer enabled. figure 8-4 illustrates the events with the timer disabled. note: it is recommended that the gpio input function of mode 0 only be activated with the timer disabled. if the processor attempts to read the di bit to determine the gpio pin direction, it must read the entire tcsr register, which would clear the ts bit and, thus, clear a pending timer interrupt. te tcr write preload (n) n counter n 0 n ts first event last event n-1 clock (clk/2) interrupt figure 8-3 mode 0 ?standard timer mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation motorola timer/event counter 8 - 9 te tcr preload (n) n counter n-k n-k-1 n ts first event n-k-1 stop counting n-1 clock (clk/2) interrupt figure 8-4 timer/event counter disable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation 8 - 10 timer/event counter motorola 8.5.2 timer mode 1 (standard timer mode, internal clock, output pulse enabled) timer mode 1 is defined by tc2-tc0 equal to 001. with the timer enabled (te=1), the counter is loaded with the value contained by the tcr. the counter is decremented by a clock derived from the dsp? internal clock, divided by two (clk/2). during the clock cy- cle following the point where the counter reaches 0, the ts bit is set and, if the tie bit is set, the timer generates an interrupt. a pulse with a two clock cycle width and whose polarity is determined by the inv bit, will be put out on the tio pin. the counter is reloaded with the value contained by the tcr. the entire process is repeated until the timer is disabled (te=0). figure 8-5 illustrates timer mode 1 when inv=0, and figure 8-6 illustrates timer mode 1 when inv=1. te tcr write preload (n) n counter n 0 n interrupt first event last event n-1 tio new event 2xclk n-1 clock (clk/2) figure 8-5 mode 1 ?standard timer mode, internal clock, output pulse enabled (inv=0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation motorola timer/event counter 8 - 11 te tcr write preload (n) n counter n 0 n interrupt first event last event n-1 tio new event 2xclk n-1 clock (clk/2) figure 8-6 mode 1 ?standard timer mode, internal clock, output pulse enabled (inv=1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation 8 - 12 timer/event counter motorola 8.5.3 timer mode 2 (standard timer mode, internal clock, output toggle enabled) timer mode 2 is defined by tc2-tc0 equal to 010. with the timer enabled (te=1), the counter is loaded with the value contained by the tcr. the counter is decremented by a clock derived from the dsp? internal clock, divided by two (clk/2). during the clock cycle following the point where the counter reaches 0, the ts bit in tcsr is set and, if the tie is set, an interrupt is generated.the counter is reloaded with the value contained by the tcr and the entire process is repeated until the timer is disabled (te=0). each time the counter reaches 0, the tio output pin will be toggled. the inv bit determines the po- larity of the tio output. figure 8-7 illustrates timer mode 2. te tcr last event n counter n 0 n interrupt first event last event n-1 tio new event n-1 0 clock (clk/2) figure 8-7 mode 2 ?standard timer mode, internal clock, output toggle enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation motorola timer/event counter 8 - 13 8.5.4 timer mode 4 (pulse width measurement mode) timer mode 4 is defined by tc2-tc0 equal to 100. in this mode, tio acts as a gating signal for the dsp? internal clock (see figure 8-9). with the timer enabled (te=1), the counter is driven by a clock derived from the dsp? internal clock divided by two (clk/2). the counter is loaded with 0 by the first transition occurring on the tio input pin and starts incrementing. when the first edge of opposite polarity occurs on tio, the counter stops, the ts bit in tcsr is set and, if tie is set, an interrupt is generated. the contents of the counter is loaded into the tcr. the user? program can read the tcr, which now represents the width of the tio pulse. the process is repeated until the timer is disabled (te=0).the inv bit determines whether the counting is enabled when tio is high (inv=0) or when tio is low (inv=1). figure 8-8 illustrates timer mode 4 when inv=0 and figure 8-10 illustrates timer mode 4 with inv=1. te tcr start event clock counter 0 n-1 n interrupt 1 tio start event 0 stop event n figure 8-8 mode 4 ?pulse width measurement mode (inv=0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation 8 - 14 timer/event counter motorola figure 8-9 mode 4 ?io gates the internal clock tio clk/2 inv=1 inv=0 24-bit counter cntr te tcr start event clock xxx counter 0 n-1 n interrupt 1 tio start event 0 yyy stop event n figure 8-10 mode 4 ?pulse width measurement mode (inv=1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation motorola timer/event counter 8 - 15 8.5.5 timer mode 5 (period measurement mode) timer mode 5 is defined by tc2-tc0 equal to 101. in timer mode 5, the counter is driven by a clock derived from the dsp? internal clock divided by 2 (clk/2). with the timer en- abled (te=1), the counter is loaded with the value contained by the tcr and starts incrementing. on each transition of the same polarity that occurs on tio, the ts bit in tcsr is set and, if tie is set, an interrupt is generated. the contents of the counter are loaded into the tcr. the user? program can read the tcr and subtract consecutive val- ues of the counter to determine the distance between tio edges. the counter is not stopped and it continues to increment. the inv bit determines whether the period is mea- sured between 0-to-1 transitions of tio (inv=0), or between 1-to-0 transitions of tio (inv=1). figure 8-11 illustrates timer mode 5 when inv=0, and figure 8-12 illustrates this mode with inv=1. te tcr periodic event (first event) clock n counter n n+1 n+2 interrupt tio periodic event m-1 m m m+1 m+2 n + 1 figure 8-11 mode 5 ?period measurement mode (inv=0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation 8 - 16 timer/event counter motorola te tcr periodic event (first event) clock n counter n n+1 n+2 interrupt tio periodic event m-1 m m m+1 m+2 n + 1 figure 8-12 mode 5 ?period measurement mode (inv=1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation motorola timer/event counter 8 - 17 8.5.6 timer mode 6 (standard time counter mode, external clock) time mode 6 is defined by tc2-tc0 equal to 110. with the timer enabled (te=1) the counter is loaded with the 1? complement of the value contained by the tcr. the counter is incremented by the transitions on the incoming signal on the tio input pin. after each increment, the counter value is loaded into the tcr. thus, reading the tcr will give the value of the counter at any given moment. at the transition following the point where the counter reaches 0, the ts bit in tcsr is set and, if the tie is set, an interrupt is generat- ed.the counter will wrap around and the process is repeated until the timer is disabled (te=0). the inv bit determines whether 0-to-1 transitions (inv=0) or 1-to-0 transitions (inv=1) will increment the counter. figure 8-13 illustrates timer mode 6 when inv=0. figure 8-14 illustrates timer mode 6 when inv=1. te tcr write preload (n) tio (event) n counter n ffffff 0 interrupt first event last event n+1 n+1 ffffff 0 figure 8-13 mode 6 ?standard time counter mode, external clock (inv=0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation 8 - 18 timer/event counter motorola te tcr write preload (n) tio (event) counte r n ffffff 0 interrupt first event last event n+1 n n+1 ffffff 0 figure 8-14 mode 6 ?standard timer mode, external clock (inv=1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation motorola timer/event counter 8 - 19 8.5.7 timer mode 7 (standard timer mode, external clock) timer mode 7 is defined by tc2-tc0 equal to 111. with the timer enabled (te=1), the counter is loaded with the value contained by the tcr. the counter is decremented by the transitions of the signal coming in on the tio input pin. at the transition that occurs after the counter has reached 0, the ts bit in tcsr is set and, if the tie is set, the timer generates an interrupt. the counter is reloaded with the value contained by the tcr, and the entire process is repeated until the timer is disabled (te=0). the inv bit determines whether 0-to-1 transitions (inv=0) or 1-to-0 transitions (inv=1) will decrement the counter. figure 8-15 illustrates timer mode 7 when inv=0, and figure 8-16 illustrates timer mode 7 when inv=1. te tcr write preload (n) tio (event) n counter n 0 n interrupt first event last event n-1 figure 8-15 mode 7 ?standard timer mode, external clock (inv=0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter modes of operation 8 - 20 timer/event counter motorola te tcr write preload (n) tio (event) n counter n 0 n interrupt first event last event n-1 figure 8-16 mode 7 ?standard timer mode, external clock (inv=1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/event counter behavior during wait and stop motorola timer/event counter 8 - 21 8.6 timer/event counter behavior during wait and stop during the execution of the wait instruction, the timer clocks are active and the timer activity continues undisturbed. if the timer interrupt is enabled when the final event oc- curs, an interrupt will be generated and serviced. it is recommended that the timer be disabled before executing the stop instruction be- cause during the execution of the stop instruction, the timer clocks are disabled and the timer activity will be stopped. if, for example, the tio pin is used as input, the changes that occur while in stop will be ignored. 8.7 operating considerations the value 0 for the timer count register (tcr) is considered a boundary case and affects the behavior of the timer under the following conditions: if the tcr is loaded with 0, and the counter contained a non-zero value before the tcr was loaded, then after the timer is enabled, it will count 2 24 events, generate an inter- rupt, and then generate an interrupt for every new event. if the tcr is loaded with 0, and the counter contained a zero value prior to loading, then after the timer is enabled, it will generate an interrupt for every event. if the tcr is loaded with 0 after the timer has been enabled, the timer will be loaded with 0 when the current count is completed and then generate an interrupt for every new event. 8.8 software examples 8.8.1 general purpose i/o input the following routine can be used to read the tio input pin: movep #$000040,x:tcsr ;clear tc2-tc0, set gpio and ;clear inv for gpio input here jset #di,x:tcsr,here ;spin here until tio is set 8.8.2 general purpose i/o output the following routine can be used to write the tio output pin: movep #$000140,x:tcsr ;clear tc2-tc0, set gpio and ;set dir for gpio output, set tio to 0 bset #do,x:tcsr ;set tio to 1 nop nop bclr #do,x:tcsr ;set tio to 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . software examples 8 - 22 timer/event counter motorola this routine generates a pulse on the tio pin with the duration equal to 8 clk (assuming no wait states, no external bus conflict, etc.). 8.8.3 timer mode 0, input clock, gpio output, and no timer output the following program (see figure 8-17) illustrates the standard timer mode with simul- taneous gpio. the timer is used to activate an internal task after 65536 clocks; at the end of the task the tio pin is toggled to signal end of task. org p:$3c ;this is timer interrupt vector address jsr task ;go and execute task (long interrupt) org p:main_body movep #$000042,x:tcsr ;enable timer interrupts and ;enable gpio (input!) and set ;do =0 to have stable data bset #dir,x:tcsr ;change dir to output ;(clean 0, no spikes) movep #$00ffff,x:tcr ;load 64k -1 into the counter bset #ipl,x:ipr ;enable ipl for timer andi #$cf,mr ;remove interrupt masking ;in status register bset #te,x:tcsr ; timer enable ...... ; application program ..... task ..... ; task instructions .... end_of_task bset #do,x:tcsr ;set tio to signal end of task bclr #do,x:tcsr ;clear tio rti ;return to main program figure 8-17 standard timer mode with simultaneous gpio program f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . software examples motorola timer/event counter 8 - 23 8.8.4 pulse width measurement mode (timer mode 4) the following program (see figure 8-18) illustrates the use of the timer module for input pulse width measurement. the width is measured in this example for the low active pe- riod of the input pulse on the tio pin and is stored in a table (in multiples of the chip operating clock divided by 2). org x:$100 ;define buffer in x memory internal pulse_width ds $100 ;measure up to 256 pulses org p:$3c ;this is timer interrupt ;vector address movep x:tcr,x:(r0)+ ;store width value in table nop ;second word of the short interrupt ... org p:main_body ... move #pulse_width,r0 ;r0 points to start of table move #$ff,m0 ;modulo 100 to wrap around on ;end of table movep #$000026,x:tcsr ;enable timer interrupts, ;mode 4 and set inv to ;measure the low active pulse bset #ipl,x:ipr ;enable ipl for timer andi #$cf,mr ;remove interrupt masking in ;status register bset #te,x:tcsr ;timer enable ... ; do other tasks ... figure 8-18 input pulse width measurement program f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . software examples 8 - 24 timer/event counter motorola 8.8.5 period measurement mode (timer mode 5) the following program (see figure 8-19) illustrates the use of the timer module for input pe- riod measurement. the period is measured in this example between 0 to 1 transitions of the input signal on tio and is stored in a table (in multiples of the chip operating clock divided by 2). org x:$100 ;define buffer in x memory internal period ds $100 ;measure up to 256 pulses temp ds $1 ;temporary storage org p:$3c ;this is timer interrupt vector address jsr measure ;long interrupt to measure period .... org p:main_body ..... move #0,x:temp ;clear temporary storage move #period,r0 ;r0 points to start of table move #$ff,m0 ;modulo 100 to wrap around on end of table movep #$00002a,x:tcsr ;enable timer interrupts, mode 5 bset #ipl,x:ipr ;enable ipl for timer andi #$cf,mr ;remove interrupt masking in ;status register bset #te,x:tcsr ;timer enable ...... ; do other tasks ..... measure movep x:tcr,a ;read new counter value move x:temp,x0 ;retrieve former read value ;(initially zero) sub x0,a a,x:temp ;compute delta (i.e. new -old) ;and store the ;new read value in temp move a,x:(r0)+ ;store period value in table rti figure 8-19 input period measurement program f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 9 - 1 section 9 pulse width modulators f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 9 - 2 pulse width modulators motorola paragraph number page number section 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2 pulse width modulator internal architecture. . . . . . . 9-3 9.3 pulse width modulator programming model . . . . . . . . . 9-8 9.4 pulse width modulator functional description . . . . . . 9-17 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola pulse width modulators 9 - 3 9.1 introduction the pulse width modulator (pwm) module uses two different blocks: the pwma block, which is a 16-bit signed data pulse width modulator the pwmb block, which is a 16-bit positive fractional data pulse width modulator. the pulse width modulator module consists of three pwma blocks, two pwmb blocks, as well as their associated pins and clock prescaler blocks. the following is a list of the pwma features: programmable width from 9-bit to 16-bit signed two? complement fractional data internal or external clock internal or external carrier maximum clock rate equal to 1/2 of the dsp core clock rate four interrupt vectors the following is list of the pwmb features: programmable width from 9-bit to 16-bit positive fractional data internal or external clock internal or external carrier maximum clock rate equal to 1/2 of the dsp core clock rate three interrupt vectors 9.2 pulse width modulator internal architecture the pulse width modulator module includes three pwma blocks and two pwmb blocks. the 56kcore views each block as a memory mapped peripheral occupying one 16-bit word in the x data memory space and four additional 16-bit words (two of them shared by all of the pwma blocks and the other two shared by all of the pwmb blocks). the 56kcore may use the pulse width modulator as a normal memory mapped periph- eral using standard polled or interrupt programming techniques. count register carrier pulse width modulator output prescaler output figure 9-1 pulse width modulator waveform controls f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator internal architecture 9 - 4 pulse width modulators motorola pulses from the pwmn blocks are generated in the following way (see figure 9-1): 1. either an external or internal carrier controls the period of the pwmn output i.e. from rising edge to rising edge 2. the count register (pwacrn or pwbcrn) is loaded with a number that will determine the pulse width i.e. from rising edge to falling edge 3. selection of the clock source and the number loaded into the prescaler determine the resolution of the pulse 9.2.1 pulse width modulator a (pwma) overview figure 9-3 shows the internal architecture of pwma. 9.2.1.1 pwma count registers pwma0, pwma1, and pwma2 each one of the pwma0, pwma1, and pwma2 blocks consists of: one 16-bit count register (pwacrn) one 16-bit buffer register (pwabufn) one 15-bit counter (pwacnn) one comparator control logic which is responsible for generating the output pulses on the pwm pins, the interrupts, and the status bits if the pwman count register (pwacrn) is loaded with two? complement fractional data from the 56kcore through the global data bus, then beginning at the rising edge of the carrier signal: this data will be transferred to the register buffer pwabufn the 15-bit counter pwacnn will start incrementing the pwapn or pwann signal (according to the sign of the data ?pwabufn(23)) will be asserted pwan1 pwap1 figure 9-2 dc motor control example using pulse width modulator a pwap1 pwan1 s 1 s 2 s 3 s 4 l l (motor) i l +v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator internal architecture motorola pulse width modulators 9 - 5 when the comparator detects equality between the pwabufn and the pwacnn val- ue, the output signal (pwapn or pwann) is deasserted (see figure 9-6 through figure 9-6 for relative timing of the above events). figure 9-1 shows a motor con- trolled by the pwap1 and pwan1 pins. when a positive number is loaded into pwacn1, the pwap1 pin is driven closing switches s 1 and s 4 and creating a positive load current i 1 . as the number in pwacn1 decreases to zero, the driving force de- creases to zero. when a negative number is loaded into pwacn1, the pwa output switches to pwan1 turning on switches s 2 and s 3 , creating a negative i l and thus driving the motor in the opposite direction. pwacr0 15-bit counter control logic pwap0 pwan0 pwac0 pwacr1 15-bit counter control logic pwap1 pwan1 pwac1 pwacr2 15-bit counter control logic pwap2 pwan2 pwac2 pwaclk clk/2 7-bit prescaler select pwacsr0 global data bus pwacsr1 interrupts interrupts interrupts external pin pwma0 pwma1 pwma2 comparator and comparator and comparator and pwabuf0 pwabuf1 pwabuf2 control logic (pwacn0) (pwacn1) (pwacn2) clock and control logic 24 16 16 16 15 15 15 figure 9-3 pwma block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator internal architecture 9 - 6 pulse width modulators motorola since fractional signed data representation is used, if less than 16-bit data is used, this data will be loaded as left-aligned in the pwma count register (pwacrn). if, for exam- ple, the data width is 15-bit (i.e. 14-bit plus sign bit), then the bits waw2:waw1:waw0 in the pwacsr0 should be written by the programmer with the value 0:0:1 and the com- parator will compare only the bits 22 through 9 of pwabufn with the bits 0 through 13 of the pwacnn. 9.2.1.2 pwma clock and control logic the clock used to increment the pwma0, pwma1, and pwma2 counters may be: external, received through the pwaclk pin; in this case, the external clock is internally synchronized to the internal clock and enters the prescaler. its frequency must be lower than the internal 56kcore clock frequency divided by 2 (clk/2). the maximum external clock frequency is given in the dsp56003/005 data sheet. internal, derived from the 56kcore clock, after prescaling; the maximum clock rate for the counters is one half of the 56kcore clock (clk/2) if the carrier signal is programmed as internal, then the internal signal which is equivalent to the ?arrier signal rising edge?occurs in the following cases: when the counter wraps around (e.g. when pwacnn increments from $7fff to 0) when this pwman module is enabled (waen=1) after having been previously cleared (waen=0) if less than 16-bit fractional data is used, the counter wraps around according to the data width; e.g. if the data width is 15 (i.e. 14-bits plus sign bit), then the counter wraps around after it reaches $3fff). the ?idth?of the counter is programmable allowing a width be- tween 9 and 16 bits (i.e. the counter may wrap around when reaching a value from $ff to $7fff, according to the value of the bits waw(2:0) in pwacsr0). 9.2.2 pulse width modulator b (pwmb) overview figure 9-4 shows the internal architecture of pwmb 9.2.2.1 pwmb count registers pwmb0 and pwmb1 each one of the pwmb0 and pwmb1 blocks consists of: one 16-bit count register (pwbcrn) one 16-bit buffer register (pwbbufn) one comparator control logic which is responsible for generating the output pulses on the pwm pins, the interrupts and the status bits f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator internal architecture motorola pulse width modulators 9 - 7 if the pwmbn count register (pwbcrn) is loaded with positive fractional data from the 56kcore through the global data bus, then beginning at the rising edge of the carrier signal: this data will be transferred to the register buffer pwbbufn the pwbn signal will be asserted the 15-bit counter pwbcn will start incrementing when the comparator detects equality between the pwbbufn and the pwbcn value, the output signal (pwbn) is deasserted (see figure 9-3). since a fractional positive data representation is used, if less than 16-bit data is used, this data will be loaded as left-aligned in the pwmb count register (pwbcrn). if, for example, the data width is 15-bit (i.e. 14-bit plus sign bit), then the bits wbw2:wbw1:wbw0 in pwbcsr0 should be written by the programmer with the value 0:0:1 and the comparator will compare only the bits 22 through 9 of pwbbufn with the bits 0 through 13 of the pwbcn. 9.2.2.2 pwmb clock and control logic the clock which increments the counters of pwmb0 and pwmb1 (see figure 9-4) may be: external, received through the pwbclk pin; in this case, the external clock is internally synchronized to the internal clock and enters the prescaler. its frequency must be lower than the internal 56kcore clock frequency divided by 2 (clk/2). the maximum external clock frequency is given in the dsp56003/005 data sheet. internal, derived from the 56kcore clock after prescaling; the maximum clock rate for the counters is one half of the 56kcore clock (clk/2) if the carrier signal is programmed as internal, then the internal signal which is equivalent to the ?arrier signal rising edge?occurs in the following cases: when the counter wraps around (e.g. when pwbcn increments from $7fff to 0) when this pwmbn module is enabled (wben=1) after having been previously cleared (wben=0) while the second pwmbk module is disabled; if the second pwmbk module is enabled, then the next ?arrier signal rising edge?occurs when the counter wraps around (e.g. when pwbcn increments from $7fff to 0 ?see figure 9-4) if less than 16-bit fractional data is used, the counter should wrap around according to the data width; e.g. if the data width is 15 (i.e. 14-bit plus sign bit), then the counter should wrap around after it reaches $3fff). the ?idth?of the counter is programmable allowing a width between 9 and 16 (i.e. the counters may wrap around when reaching a value from $ff to $7fff, according to the value of the bits wbw(2:0) in pwbcsr0). the sign bit of the 16-bit fractional data word loaded in the pwmb count registers is ig- nored and pwmb operates assuming that this word is positive. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator programming model 9 - 8 pulse width modulators motorola 9.3 pulse width modulator programming model the pulse width modulator registers which are available to the programmer are shown in figure 9-5. these registers are described in the following paragraphs. 9.3.1 pwman count registers ?pwacr0, pwacr1, and pwacr2 the pwacrn (n=0?) count registers are 16-bit read/write registers. data written to the pwacrn register is automatically transferred to the associated register buffer pwabufn after the leading edge of the carrier signal pwacn or (when using an internal carrier) af- ter the wrap around of the pwacnn counter. 9.3.2 pwman control/status register 0 ?pwacsr0 pwacsr0 is a 16-bit read/write register controlling the prescale rates of the pwm clocks, their sources and the pwm data width.the pwacsr0 status bits allow the dsp program- mer to interrogate the pwma status. pwbcr0 15-bit counter control logic pwbc pwbcr1 control logic pwb1 pwbclk clk/2 7-bit prescaler sel pwbcsr0 global data bus pwbcsr1 interrupts interrupts external pin pwbbuf0 pwbbuf1 comparator and comparator and pwb0 control logic pwbcn pwmb0 pwmb1 15 15 15 15 24 clock and control logic figure 9-4 pwmb block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator programming model motorola pulse width modulators 9 - 9 8 15 14 13 12 11 10 9 reserved bit, read as zero, should be written with zero for future compatibility. war0 0 7654321 was1 was0 was2 war2 war1 waw1 wack waw0 wap2 waw2 wap0 wap1 pwma control and status register 0 (pwacsr0) x: $ffd9 8 15 14 13 12 11 10 9 wae0 0 7654321 wai0 wae1 wae2 wai1 wac1 wac0 wac2 wal0 pwma control and status register (pwacsr1) waei wal2 x: $ffd8 wal1 wai2 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 0 7654321 pwma0 count register (pwacr0) x: $ffda 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 0 7654321 pwma1 count register (pwacr1) x: $ffdb 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 0 7654321 pwma2 count register (pwacr2) x: $ffdc 8 15 14 13 12 11 10 9 wbs1 0 7654321 wbs0 wbr1 wbr0 wbw1 wbck wbw0 wbp2 wbw2 wbp0 wbp1 pwmb prescaler register (pwbcsr0) x: $ffd5 8 15 14 13 12 11 10 9 wbe0 0 7654321 wbi1 wbe1 wbi0 pwmb control and status register (pwbcsr1) wbc wbo wbei x: $ffd4 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 0 7654321 pwmb0 count register (pwbcr0) x: $ffd6 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 0 7654321 pwmb1 count register (pwbcr1) x: $ffd7 figure 9-5 pwm programming model f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator programming model 9 - 10 pulse width modulators motorola 9.3.2.1 pwman prescale (wap0-wap2) bits 0-2 the read/write wap0-wap2 bits specify the pwma prescale divide ratio. these bits spec- ify any power of two prescale factor in the range from 2 0 to 2 7 . the clock derived from the 56kcore clock (clk/2) or driven from the pwaclk pin is divided according to this pres- cale factor.table 9-1 shows the programming of the wap0-wap2 bits. these bits are cleared (prescale by one) after hardware reset or after a software reset (reset instruction). note: the wap0-wap2 bits should be changed only when all of the pwma blocks are disabled to ensure proper operation. 9.3.2.2 pwman clock source (wack) bit 3 the read/write wack bit specifies the clock source for the 7-bit clock prescaler. when wack is set, the prescaler clock is driven from the internal 56kcore clk/2. when wack is cleared, the prescaler clock is driven from the external clock fed through the pwaclk pin. this bit is cleared (external clock) after hardware reset or after a software reset (reset instruction). note: wack should be changed only when all of the pwma blocks are disabled to ensure proper operation. 9.3.2.3 pwman data width (waw0-waw2) bits 4-6 the read/write waw0-waw2 bits specify the pwma data width. these bits specify data widths from 9 to 16 bits in length. note: the data representation remains left-aligned, as a fractional number regardless of the value of waw0-waw2. table 9-1 prescale factor bits wap0-wap2 wap2-wap0 prescale factor $0 2 0 $1 2 1 $2 2 2 $3 2 3 $4 2 4 $5 2 5 $6 2 6 $7 2 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator programming model motorola pulse width modulators 9 - 11 table 9-1 shows the programming of the waw0-waw2 bits. these bits are cleared (16- bit data width) after hardware reset or after a software reset (reset instruction). note: the waw0-waw2 bits should be changed only when all of the pwma blocks are disabled to ensure proper operation. 9.3.2.4 pwman pwacsr0 reserved bits 7-9 bits 7-9 in the pwacsr0 are reserved and unused. they read as zero and should be writ- ten with zero for future compatibility. 9.3.2.5 pwman status (was0-was2) bits 10-12 the read-only status bit wasn (n=0?) is set when the data from pwman count register (pwacrn) is transferred to the pwman buffer register (pwabufn). the wasn status bit is cleared when the pwman count register (pwacrn) is written with new data. the wasn bit is set after hardware reset or after a software reset (reset instruction). the user program may test this bit to see if the count register (pwacrn) may be loaded with new data. 9.3.2.6 pwman error (war0-war2) bits 13-15 the read-only status bit warn (n=0?) is set when an error condition occurs in pw- man, e.g. when a carrier signal rising edge occurs before the pwman comparator detected equality between the pwacrn and pwacnn registers. the warn status bit is cleared when pwman is disabled (waen cleared). the warn bit is cleared after hard- ware reset or after a software reset (reset instruction). table 9-2 data width bits waw0-waw2 waw2-waw0 data width $0 16 $1 15 $2 14 $3 13 $4 12 $5 11 $6 10 $7 9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator programming model 9 - 12 pulse width modulators motorola 9.3.3 pwma control/status register 1 (pwacsr1) the pwacsr1 is a 16-bit read/write control/status register used to direct operation of the pwma. the pwacsr1 control bits enable/disable the pwma0, pwma1, and pwma2: registers interrupts carrier signal source pwma output pin polarity. the pwacsr1 bits are described in the following paragraphs. 9.3.3.1 pwacsr1 pwman enable (waen) bits 0-2 the read/write control bit waen (n=0?) enables/disables the operation of pwman. when waen is set, pwman is enabled. when waen is cleared, pwman is disabled and in the personal reset state. this bit is cleared after hardware reset or after a software re- set (reset instruction). 9.3.3.2 pwacsr1 pwman interrupt enable (wain) bits 3-5 the read/write control bit wain (n=0?) enables/disables the interrupts from pwman. when wain is set, an interrupt (pwman interrupt) is generated after the data is trans- ferred from the pwman count register (pwacrn) to the pwman buffer register (pwabufn), i.e after the occurrence of a new carrier signal edge. when wain is cleared, this interrupt is disabled. the wain bit is cleared after hardware reset or after a soft- ware reset (reset instruction). note: after being serviced, a pwman interrupt will be cleared only if the respective status bit (wasn) has been cleared. wasn is cleared by a write to pwacrn or reset. a pwman interrupt will not be cleared unless there has been a write to pwacrn or a reset. 9.3.3.3 pwacsr1 pwman carrier select (wacn) bits 6-8 the read/write control bit wacn (n=0?) selects between the external and internal car- rier for pwman. when wacn is set, pwman carrier is driven internally. the internal carrier signal is asserted every pwacnn wrap around. this wrap around may occur at different count values, according to the data width programed in the bits waw0-waw2 of pwacsr0. note that since the internal carrier can be software controlled, the period of the pwm signal (rising edge to rising edge) can be controlled or modulated indepen- dently from the pulse width controlled by the count register (rising edge to falling edge). when wacn is cleared, the pwman carrier is driven from the pwacn pin. this bit is cleared after hardware reset or after a software reset (reset instruction). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator programming model motorola pulse width modulators 9 - 13 note: the wacn bit should be changed only when the waen bit is cleared (i.e., the pwman block is disabled) to ensure proper operation. 9.3.3.4 pwacsr1 pwman output polarity (waln) bits 9-11 the read/write control bit waln (n=0?) selects the polarity of the pwapn and pwann pins. when waln is cleared, pwapn and pwann are active-low outputs. when waln is set, pwapn and pwann are active-high outputs. this bit is cleared after hardware reset or after a software reset (reset instruction). note: the waln bit should be changed only when the waen bit is cleared (i.e., the pwman block is disabled) to ensure proper operation. 9.3.3.5 pwacsr1 reserved bits 12-14 bits 12-14 in pwacsr1 are reserved and unused. they are read as zero and should be written with zero for future compatibility. 9.3.3.6 pwacsr1 pwma error interrupt enable (waei) bit 15 the read/write control bit waei enables/disables the error interrupt from pwma. when waei is set and an error condition occurs, the pwma error interrupt is generated. when waei is cleared, this interrupt is disabled. when an error interrupt occurs, the us- er? program should test all of the pwman error bits (war0, war1 and war2) and the pwmbn error bits (wbr0 and wbr1) in order to find out whether the pwman or the pwmbn block generated the error. the waei bit is cleared after hardware reset or after a software reset (reset instruction). 9.3.4 pwmb count registers ?pwbcr0, pwbcr1 the pwbcr0 and pwbcr1 count registers are 16-bit read/write registers. data written to these registers is automatically transferred to the associated register buffer after the leading edge of the carrier signal or (when using internal carrier) after the pwbcn counter wraps around. 9.3.5 pwmb control/status register 0 ?pwbcsr0 the pwbcsr0 is a 16-bit read/write register controlling the prescale rates of the pwmb clock, its source and the pwmb data width.the pwbcsr0 status bits allow the dsp pro- grammer to interrogate the pwmb status. 9.3.5.1 pwbcsr0 pwmb prescale (wbp0- wbp2) bits 0-2 the read/write wbp0-wbp2 bits specify the divide ratio of the pwmb prescale divider. these bits specify any power of two prescale factor in the range from 2 0 to 2 7 . the clock derived from the 56kcore clock (clk/2) or driven from the pwbclk pin is divided ac- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator programming model 9 - 14 pulse width modulators motorola cording to this prescale factor. table 9-1 shows the programming of the wbp0-wbp2 bits. these bits are cleared (prescale by one) after hardware reset or after a software reset (reset instruction). note: the wbp0-wbp2 bits should be changed only when all of the pwmb blocks are disabled to ensure proper operation. 9.3.5.2 pwbcsr0 pwmb clock source (wbck) bit 3 the read/write wbck bit specifies the clock source for the 7-bit clock prescaler. when wbck is set, the prescaler clock is driven from the internal 56kcore clk/2. when wbck is cleared, the prescaler clock is driven from the external clock fed through the pwbclk pin. this bit is cleared (external clock) after hardware reset or after a software reset (reset instruction). note: the wbck should be changed only when all of the pwmb blocks are disabled to ensure proper operation. 9.3.5.3 pwbcsr0 pwmb data width (wbw0-wbw2) bits 4-6 the read/write wbw0-wbw2 bits specify the pwmb data width. these bits specify any data width in the range from 9 bits to 16 bits. the data representation remains left- aligned, as a fractional number regardless of the values of these bits. table 9-1 shows the programming of the three wbw0-wbw2 bits. these bits are cleared (16-bit data width) after hardware reset or after a software reset (reset instruction). table 9-3 prescale factor bits wbp0-wbp2 wbp2-wbp0 prescale factor $0 2 0 $1 2 1 $2 2 2 $3 2 3 $4 2 4 $5 2 5 $6 2 6 $7 2 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator programming model motorola pulse width modulators 9 - 15 note: the wbw0-wbw2 bits should be changed only when all of the pwmb blocks are disabled to ensure proper operation. 9.3.5.4 pwbcsr0 reserved bits 7-11 bits 7-11 in pwbcsr0 are reserved and unused. they read as zero and should be written with zero for future compatibility. 9.3.5.5 pwbcsr0 pwmbn status (wbsn) bits 12-13 the read-only status bit wbsn (n=0?) is set when data from the pwmbn count register (pwbcrn) is transferred to the pwmbn buffer register (pwbbufn). the wbsn status bit is cleared when the pwmbn count register (pwbcrn) is written with new data. this bit is set after hardware reset or after a software reset (reset instruction). the user pro- gram may test this bit in order to tell if the count register (pwacrn) may be loaded with new data. 9.3.5.6 pwbcsr0 pwmbn error (wbrn) bit 14-15 the read-only status bit wbrn (n=0?) is set when an error condition occurs in the pwmbn, e.g. when a new rising edge of the carrier signal occurs before the pwmbn comparator detects equality between the pwbcrn and pwbcnn. the wbrn status bit is cleared when pwmbn is disabled (wben cleared). the wbrn bit is cleared after hardware reset or after a software reset (reset instruction). table 9-4 data width bits wbw2-wbw0 wbw2-wbw0 data width $0 16 $1 15 $2 14 $3 13 $4 12 $5 11 $6 10 $7 9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator programming model 9 - 16 pulse width modulators motorola 9.3.6 pwmb control/status register 1 ?pwbcsr1 the pwbcsr1 is a 16-bit read/write control/status register used to direct the pwmb op- eration. the pwbcsr1 control bits enable/disable the pwmb: registers interrupts carrier signal source the pwbcsr1 bits are described in the following paragraphs. 9.3.6.1 pwbcsr1 pwmbn enable (wben) bits 0-1 the read/write control bit wben (n=0?) enables/disables operation of the pwmbn. when wben is set, pwmbn is enabled. when wben is cleared, pwmbn is disabled and in the personal reset state. this bit is cleared after hardware reset or after a software re- set (reset instruction). 9.3.6.2 pwbcsr1 pwmbn interrupt enable (wbin) bits 2-3 the read/write control bit wbin (n=0?) enables/disables interrupts from pwmbn. when wbin is set, an interrupt (pwmbn interrupt) is generated after data is transferred from the pwmbn count register (pwbcrn) to the pwmbn buffer register (pwbbufn). when wbin is cleared, this interrupt is disabled. the wbin bit is cleared after hardware reset or after a software reset (reset instruction). note: after being serviced, a pwmbn interrupt will be cleared only if the respective status bit (wbsn) has been cleared. wbsn is cleared by a write to pwbcrn or reset. a pwmbn interrupt will not be cleared unless there has been a write to pwbcrn or a reset. 9.3.6.3 pwbcsr1 reserved bits 4-12 bits 4-12 in pwbcsr1 are reserved and unused. they read as zero and should be written with zero for future compatibility. 9.3.6.4 pwbcsr1 pwmb carrier select (wbc) bit 13 the read/write control bit wbc selects between the external and internal carrier for pw- mb. when wbc is set, pwmb carrier is driven internally. the internal carrier signal is asserted every pwbcn wrap around. this wrap around may occur at different count val- ues, according to the data width programed in the bits wbw0-wbw2 of pwbcsr0. note that since the internal carrier can be software controlled, the period of the pwm signal (rising edge to rising edge) can be controlled or modulated independently from the pulse width controlled by the count register (rising edge to falling edge). when wbc is cleared, pwmb carrier is driven from the pwbc pin. this bit is cleared after hardware reset or after a software reset (reset instruction). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description motorola pulse width modulators 9 - 17 note: the wbcn bit should be changed only when the wben bit is cleared (i.e., the pwmbn block is disabled) to ensure proper operation. 9.3.6.5 pwbcsr1 pwmb open drain output (wbo) bit 14 this read/write control bit configures the pwmb output pins (pwb0 and pwb1 ) as ei- ther open-drain pins or ttl level pins. when wbo is cleared, the open-drain configuration is forced on the pwmb output pins (pwb0 and pwb1 ). when wbo is set, these pins are ttl outputs. the wbo bit is cleared after hardware reset or after a soft- ware reset (reset instruction). 9.3.6.6 pwbcsr1 pwmb error interrupt enable (wbei) bit 15 the read/write control bit wbei enables/disables the error interrupt from pwmb. when wbei is set and an error condition occurs, a pwmb error interrupt is generated. when wbei is cleared, this interrupt is disabled. when an error interrupt occurs, the user? pro- gram should test all the pwman error bits (war0, war1 and war2) and the pwmbn error bits (wbr0 and wbr1) in order to find out whether the pwman or the pwmbn block generated the error. the wbei bit is cleared after hardware reset or after a soft- ware reset (reset instruction). 9.4 pulse width modulator functional description this section shows timing diagram which illustrate the operation of the pwm blocks. 9.4.1 timing diagrams note that in figure 9-6, the first assertion width for pwapn is n, and the second is m (both are in units of pwaclk). pwman? output is active low and is sent to pin pwapn because the pwabufn sign bit is low. again, in figure 9-7, n and m are the first and second pwm cycle values, respectively, and pwapn is active low. however, in this instance the second edge of the carrier signal occurs before the end of the first pwm pulse. hence, an error is flagged on waen. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description 9 - 18 pulse width modulators motorola pwacrn clk pwabufn pwapn pwacnn n n 1 2 n-1 n n+1 pwaclk m wasn pwman int. pwabufn(23) 0 pwann m 0 pwacn 1 2 figure 9-6 pwma timing ?external clock, external carrier, positive data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description motorola pulse width modulators 9 - 19 pwacrn clk pwapn pwacnn n n 1 2 n-1 n pwaclk m wasn pwman pwabufn(23) 0 pwann m 0 pwacn 1 2 m-1 m+1 m waen pwman pwabufn figure 9-7 pwma timing ?external clock, external carrier, error error interrupt interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description 9 - 20 pulse width modulators motorola figure 9-8 shows the case where the width of the first pwm cycle is zero (n=0), and there- fore the output is never driven low (active) for that cycle. the next width (m) is non-zero. pwacrn clk pwabufn pwapn pwacnn n=0 n=0 1 pwaclk m wasn pwman pwabufn(23) 0 pwann m 0 pwacn 1 2 figure 9-8 pwma timing ?external clock, external carrier, n=0 interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description motorola pulse width modulators 9 - 21 in figure 9-9, the pwm uses an internal carrier that has a rising edge whenever the counter (pwacnn) wraps around at the 2 w th count, where w is the width of the data as specified by waw0-waw2. pwacrn clk pwapn pwacnn n n 1 2 n-1 n n+1 pwma int. clk m wasn pwman pwabufn(23) 0 pwann m 0 waen 1 2 w-1 -1 pwabufn figure 9-9 pwma timing ?internal clock, internal carrier width=w interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description 9 - 22 pulse width modulators motorola figure 9-10 shows the maximum pulse width that can be used for 16-bit positive two? complement data, $7fff. note that this value does allow the pwapn pin to be deasserted for one pwma clock cycle. pwacrn clk pwabufn pwapn pwacnn n n 1 2 pwma m wasn pwman pwabufn(23) 0 pwann m 0 waen 1 2 w-1 -1 figure 9-10 pwma timing ?internal clock, internal carrier, n=$7fff, w=16 interrupt interrupt clk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description motorola pulse width modulators 9 - 23 figure 9-11 shows the results of negating the count register value shown in figure 9-10. the value becomes a 16-bit negative two? complement number, $8001. note that the out- put is seen on the pwann pin and is again deasserted for one pwma clock cycle. pwacrn clk pwabufn pwann pwacnn n n 1 2 pwma m wasn pwman pwabufn(23) 0 pwapn m 0 waen 1 2 w-1 -1 figure 9-11 pwma timing ?internal clock, internal carrier, n=$8001, w=16 interrupt interrupt clk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description 9 - 24 pulse width modulators motorola the maximum pulse width that can be used for 16-bit negative two? complement data is obtained by writing $8000 to the counter register. figure 9-12 shows the resulting signals. note that once driven active (low in this case), the pwann pin remains active yet avoids an error signal. pwacrn clk pwabufn pwann pwacnn n n 1 2 pwma m wasn pwman pwabufn(23) 0 pwapn m 0 waen 1 2 w-1 -1 figure 9-12 pwma timing ?internal clock, internal carrier, n=$8000, w=16 interrupt clk interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description motorola pulse width modulators 9 - 25 figure 9-13 again shows a pwma channel configured for a zero pulse width, followed by a non-zero pulse width m. in figure 9-13, however, the carrier and clock are both internal with a data width (w) of sixteen. therefore a single pwm cycle lasts for 2 16 pwm clock cycles, as opposed to that of figure 9-8 which lasts until the next rising edge of the external carrier. pwacrn clk pwabufn pwapn n=0 n=0 pwma m wasn pwman pwabufn(23) pwann m waen pwacnn 1 2 0 0 1 2 w-1 -1 figure 9-13 pwma timing ?internal clock, internal carrier, n=0, w=16 interrupt interrupt clk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description 9 - 26 pulse width modulators motorola figure 9-14 shows the timings for pwmb with a pulse width of n. each block of pwmb has only a single output pin, pwbn . 9.4.2 boundary conditions due to synchronization between the external signals (carrier, clock) and the internal clock, there may be some uncertainty in the: delay between the external carrier assertion and the pwm output assertion delay between the external clock edges and the pwm output for the same reasons, there might be synchronization delays between two pwms even if they use the same external clock and the same external carrier. the maximum delay val- ues are given in the dsp56003/005 data sheet. there is no error condition when the pwm clock is internal. pwbcrn clk pwbbufn pwbn pwbcn n n 1 2 n-1 n n+1 pwbclk m wbsn pwmbn pwbbufn(23) 0 m 0 pwbc 1 2 wbo denotes an open-drain output; a pull-up resistor should be connected to this pin figure 9-14 pwmb timing ?external clock, external carrier interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator functional description motorola pulse width modulators 9 - 27 if the external carrier signal is asserted after deassertion of the output pin, then it guaran- tees no error. if an error condition occurs in a pwm module due to premature assertion of the carrier signal of the module, then the output pin will remain asserted for a period determined by the data value in the respective count register. the respective status bit will be set due to this premature assertion of the carrier signal. the minimum assertion and deassertion duration of the carrier signal are given in the dsp56003/005 data sheet. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola 10 - 1 section 10 watchdog timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents 10 - 2 watchdog timer motorola paragraph number page number section 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2 watchdog timer architecture . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 watchdog timer functional description . . . . . . . . . . . . . 10-7 10.4 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . 10-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola watchdog timer 10 - 3 10.1 introduction this section describes the watchdog timer module of the dsp56003/005. the watch- dog timer can interrupt the dsp56003/005 after a specified number of clocks. it generates a non-maskable interrupt (nmi) to the 56kcore which has the same vector address as the nmi exception vector (p:$001e). 10.2 watchdog timer architecture figure 10-1 shows a block diagram of the watchdog timer. it includes: 16-bit read-write watchdog timer control/status register (wcsr) 16-bit read-write watchdog timer count register (wcr) 16-bit counter 7-bit clock prescaler logic for interrupt generation. the dsp56003/005 views the watchdog timer as a memory mapped peripheral occupying two 16-bit words in the x data memory space. the programming model is shown in figure 10-2. 10.2.1 watchdog timer count register (wcr) the count register is a 16-bit read-write register which contains the value to be loaded into the counter. this counter is loaded with the value contained in the count register on three occasions: when the watchdog timer enable bit is set (we=1) after being previously cleared (we=0) when the watchdog timer load (wld) bit is set while the watchdog is enabled (we=1) when the counter has been decremented to zero and a new watchdog clock occurs (we=1) in the last case, if the wcr is loaded with n, the counter will be reloaded after (n+1) watchdog clocks. the term ?atchdog clock?refers to the output of the clock prescaler. if the watchdog timer is disabled (we=0) and the wcr is written by the user program, the value is stored in the wcr and will be loaded into the counter when the we bit is set. if the watchdog timer is enabled (we=1) and the wcr is written by the user program, the value is stored in the wcr and will be loaded into the counter after the counter has been decremented to zero and a new watchdog clock occurs. if the watchdog timer is enabled (we=1) and the wld bit is written with ?ne? the wcr contents will be loaded into the counter regardless of the counter value at the moment. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer architecture 10 - 4 watchdog timer motorola 10.2.2 watchdog timer control/status register (wcsr) the watchdog timer control/status register is a 16-bit read/write register that con- trols the watchdog timer and verifies its status. the wcsr can be accessed both by normal move instructions as well as by bit manipulation instructions. the control and status bits are described in the following paragraphs. 7-bit prescaler 3 clk/4 nmi (from nmi pin nmi (to core) gdb 24 24 24 wcr wcsr watchdog timer interrupt 16-bit counter figure 10-1 16-bit timer module block diagram 16 edge detection) reserved bit, read as zero, should be written with zero for future compatibility. 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 wd4 0 7654321 wd2 wd0 wd1 wd3 wd6 wd5 wd15 wd7 wd8 wd9 watchdog timer count register (wcr) wd11 wd12 wd13 wd14 wd10 x: $ffe7 8 15 14 13 12 11 10 9 16 23 22 21 20 19 18 17 wie 0 7654321 wp2 wp0 wp1 ws wld we wdb watchdog timer control/status register (wcsr) x: $ffe6 figure 10-2 watchdog timer module programming model f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer architecture motorola watchdog timer 10 - 5 10.2.2.1 wcsr watchdog timer prescale (wp0-wp2) bits 0-2 the watchdog timer prescale bits (wp2-wp0) define the divide ratio of the prescale di- vider. these bits specify any power of two prescale factor in the range from 2 0 to 2 7 . table 10-1 shows the programming of the wp0-wp2 bits. these bits are cleared (pres- cale by one) after hardware reset or after software reset (reset instruction). note: the wp0-wp2 bits may be changed at any time, but the 7-bit prescaler will be loaded according to their value only in the following three cases: when the watchdog timer enable bit is set (we=1) after being previously cleared (we=0) when the wld bit is set, while the watchdog timer is enabled (we=1) after the counter has been decremented to zero and a new watchdog clock occurs (we=1) 10.2.2.2 wcsr watchdog timer status (ws) bit 3 the watchdog timer status bit, when set, indicates that the counter has been decre- mented to zero. the watchdog timer status bit is cleared when the wcsr is read. ws is also cleared by hardware reset and software reset (reset instruction). 10.2.2.3 wcsr watchdog timer interrupt enable (wie) bit 4 the watchdog timer interrupt enable bit is used to enable the watchdog timer interrupts after the counter reaches zero and a new watchdog clock occurs. if wcr is loaded with n, a non-maskable interrupt will occur after (n+1) watchdog clocks. setting wie (wie=1) will enable the interrupts. the interrupts are disabled when wie is cleared (wie=0). wie is cleared by hardware reset and software reset (reset instruction). table 10-1 prescale factor bits wp0-wp2 wp2-wp0 prescale factor $0 2 0 $1 2 1 $2 2 2 $3 2 3 $4 2 4 $5 2 5 $6 2 6 $7 2 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer architecture 10 - 6 watchdog timer motorola 10.2.2.4 wcsr watchdog timer enable (we) bit 5 the watchdog timer enable is used to enable or disable the timer. setting the we bit (we=1) will: enable the watchdog timer load the value specified by wp0-wp2 (according to table 10-1) into the 7-bit prescaler which has clk/4 as an input load the counter with the value contained in wcr and begin decrementing at each watchdog clock clearing the we bit will disable the watchdog timer and freeze the prescaler and counter. we is cleared by hardware reset and software reset (reset instruction). 10.2.2.5 wcsr watchdog timer load (wld) bit 6 the watchdog timer load is used to reload the watchdog timer 16-bit counter and the 7-bit prescaler respectively with the values specified by the wcr and wcsr. setting the wld bit (wld=1) will load the prescaler and the counter. the wld bit will be immedi- ately cleared by the internal hardware. clearing the wld bit will have no effect on the watchdog timer activity. wld is cleared by hardware reset and software reset (reset instruction). note: due to delays in the internal pipeline, the user should allow a two-instruction delay between setting the wld bit and attempting to write the wcr or wcsr registers with new values. 10.2.2.6 wcsr watchdog timer debug (wdb) bit 7 the watchdog timer debug is used to freeze the watchdog timer 16-bit counter and the 7-bit prescaler during debug mode. setting the wdb bit (wdb=1) will freeze the watchdog timer 16-bit counter and the 7-bit prescaler during debug mode. clearing the wdb bit (wdb=0) will allow the watchdog timer 16-bit counter and the 7-bit pres- caler to continue their operation during the debug mode. wdb is cleared by hardware reset and software reset (reset instruction). note: the wdb bit should be changed only when the watchdog timer is disabled to ensure proper functionality. 10.2.2.7 wcsr reserved bits 8-15 these reserved bits are read as zero and should be written with zero for future compatibility. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer functional description motorola watchdog timer 10 - 7 10.3 watchdog timer functional description the counter is loaded with the value contained by the wcr when we=1 and the counter is decremented by the watchdog clock, which is one fourth the 56kcore clock (clk/4), after prescaling according to the prescale factor. at the next watchdog clock after the counter reaches zero, the ws bit in wcsr is set and, if the wie is set, a non-maskable interrupt (nmi) is generated (see figure 10-3). the interrupt signal gen- erated by the watchdog timer is internally or-ed with the nmi signal (generated through the modc pin). the counter is reloaded with the value contained by the wcr and the entire process is repeated until the timer is disabled (we=0). figure 10-3 illus- trates this mode. figure 10-4 describes the watchdog timer disable. we wcr write preload (n) n counter n 0 n ws first clock last clock n-1 watchdog clk interrupt figure 10-3 watchdog timer interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . programming considerations 10 - 8 watchdog timer motorola 10.4 programming considerations the watchdog timer interrupt and the nmi are serviced through the same exception vector. it is the user? responsibility to identify the source of this interrupt. a typical sce- nario consists in using a long-interrupt routine for the nmi exception, in which a test of the ws (watchdog timer status bit) from wcsr (watchdog timer control/status register); if this bit is cleared, then the interrupt was generated through the modc pin; if this bit is set, then the interrupt was generated through the modc pin or by the watchdog timer. we wcr preload (n) n counter n-k n-k-1 n ws first clock n-k-1 stop counting n-1 watchdog clk interrupt figure 10-4 watchdog timer disable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola a - 1 appendix a bootstrap program and data rom listings 10 0 0 01 1 01 10 01 10110111011010011010010101 01010 10 00 0 1 1 0 1 1 00 1 1011011101101001101001010101010 0101101011010100110110101011010 1010010101010010101010010101010 0101010101010101010000010101100 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 10 0 0 01 1 01 10 01 10110111011010011010010101 01010 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 1000101010100100 0100010101011101 1010100011010101 1001011001110100 10 0 0 01 1 01 10 01 10110111011010011010010101 01010 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 0100101001011010 1010101010110110 1010101010010111 0101001010010111 1000101010100100 0100010101011101 1010100011010101 1001011001110100 1000101010100100 0100010101011101 1010100011010101 1001011001110100 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents a - 2 bootstrap program and data rom listings motorola paragraph number page number section a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3 a.2 bootstrap program listing . . . . . . . . . . . . . . . . . . . . . . . . . . a-4 a.3 arc-tangent table contents . . . . . . . . . . . . . . . . . . . . . . . . . a-7 a.4 sine table contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-10 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola bootstrap program and data rom listings a - 3 a.1 introduction this section presents the bootstrap program contained in the dsp56003/005 96-word boot rom. this program can load the internal program ram starting at p:$0 from an external eprom or the host interface, and may load any program ram segment from the sci serial interface. if mc:mb:ma=001, the program loads the internal program ram from 13,824 consecu- tive byte-wide p memory locations, starting at p:$c000 (bits 7-0). these will be packed into 4608 24-bit words and stored in contiguous program ram memory locations start- ing at p:$0. after assembling one 24-bit word, the bootstrap program stores the result in internal program ram memory. note that the routine loads data starting with the least significant byte of p:$0. if mc:mb:ma=111, the program loads the internal program ram from 13,824 consecu- tive byte-wide p memory locations, starting at p:$8000 (bits 7-0). these will be packed into 4608 24-bit words and stored in contiguous program ram memory locations start- ing at p:$0. after assembling one 24-bit word, the bootstrap program stores the result in internal program ram memory. note that the routine loads data starting with the least significant byte of p:$0. if mc:mb:ma=10x, the program loads internal program ram from the host interface, starting at p:$0. if only a portion of the p memory is to be loaded, the host interface boot- strap load program may be stopped by setting host flag 0 (hf0). this will terminate the bootstrap loading operation and start executing the loaded program at location p:$0 of the internal program ram. if mc:mb:ma=110, the program loads program ram from the sci interface. the num- ber of program words to be loaded and the starting address must be specified. the sci bootstrap code expects to receive 3 bytes specifying the number of program words, 3 bytes specifying the address in internal program ram to start loading the program words and then three bytes for each program word to be loaded. the number of words, the starting address and the program words are received least significant byte first fol- lowed by the mid and then by the most significant byte. after receiving the program words, program execution starts at the same address where loading started. the sci is programmed to work in asynchronous mode with 8 data bits, 1 stop bit and no parity. the clock source is external and the clock frequency must be 16x the baud rate. after each byte is received, it is echoed back through the sci transmitter. the bootstrap program listing is shown in figure a-1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap program listing a - 4 bootstrap program and data rom listings motorola a.2 bootstrap program listing boot equ $c000 ; this is the location in p memory ; on the external memory bus ; where the external byte-wide ; eprom would be located (option 1) boot1 equ $8000 ; this is the location in p memory ; on the external memory bus ; where the external byte-wide ; eprom would be located (option 2) pbc equ $ffe0 ; port b control register hsr equ $ffe9 ; host status register hrx equ $ffeb ; host receive register pcc equ $ffe1 ; port c control register scr equ $fff0 ; sci control register ssr equ $fff1 ; sci status register sccr equ $fff2 ; sci clock control register srxl equ $fff4 ; sci receive register low stxl equ $fff4 ; sci transmit register low p_size equ $1200 ; internal p_ram size org pl:$0,pl:$0 ; bootstrap code starts at $0 start move #<0,r0 ; default p address where prog ; will begin loading move #p_size,b1 ; b1 will keep the number of ; words to be loaded through host jclr #4,omr,epromld ; if mc:mb:ma=0xx, go load from ; eprom jclr #1,omr,hostld ; if mc:mb:ma=10x, go load from host jclr #0,omr,scild ; if mc:mb:ma=110, go load from sci move #boot1,r1 ; r1 = ext address of eprom jmp epromld1 ; this is the routine that loads from the host interface. ; mc:mb:ma=100 - reserved ; mc:mb:ma=101 - host hostld bset #0,x:pbc ; configure port b as host do b1,_loop3 ; load p_size instruction words _lbla jclr #3,x:hsr,_lblb ; if hf0=1, stop loading data. enddo ; must terminate the do loop jmp <_loop3 _lblb jclr #0,x:hsr,_lbla ; wait for hrdf to go high ;(meaning data is present). movep x:hrx,p:(r0)+ ; store 24-bit data in p mem. _loop3 ; and go get another 24-bit word. ; finish bootstrap finish move #<0,r1 figure a-1 dsp56003/005 bootstrap program listing (sheet 1 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap program listing motorola bootstrap program and data rom listings a - 5 ; this is the exit handler that returns execution to normal ; expanded mode and jumps to the reset vector. bootend andi #$ec,omr ; set operating mode to 0 ; (and trigger an exit from ; bootstrap mode). andi #$0,ccr ; clear ccr as if reset to 0. ; delay needed for op. mode change jmp (r1) ; then go to starting prog addr. ; this is the routine that loads from the sci. ; mc:mb:ma=110 - external sci clock ; mc:mb:ma=111 - reserved org pl:$0d00,pl:$0d00 ; starting address of 2nd rom scild movep #$0302,x:scr ; configure sci control reg movep #$c000,x:sccr ; configure sci clock control reg movep #7,x:pcc ; configure sclk, txd and rxd _sci1 do #6,_loop6 ; get 3 bytes for number of ; program words and 3 bytes ; for the starting address jclr #2,x:ssr,* ; wait for rdrf to go high movep x:srxl,a2 ; put 8 bits in a2 jclr #1,x:ssr,* ; wait for tdre to go high movep a2,x:stxl ; echo the received byte rep #8 asr a _loop6 move a1,r0 ; starting address for load move a1,r1 ; save starting address do a0,_loop4 ; receive program words do #3,_loop5 jclr #2,x:ssr,* ; wait for rdrf to go high movep x:srxl,a2 ; put 8 bits in a2 jclr #1,x:ssr,* ; wait for tdre to go high movep a2,x:stxl ; echo the received byte rep #8 asr a _loop5 movem a1,p:(r0)+ ; store 24-bit result in p mem. _loop4 jmp finish+1 ; boot from sci done figure a-1 dsp56003/005 bootstrap program listing (sheet 2 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . bootstrap program listing a - 6 bootstrap program and data rom listings motorola org pl:$1100,pl:$1100 ; starting address of 3rd rom ; this is the routine that loads from external eprom. ; mc:mb:ma=001 epromld move #boot,r1 ; r1 = ext address of eprom epromld1 do b1,_loop1 ; load p_size instruction words do #3,_loop2 ; each instruction has 3 bytes movem p:(r1)+,a2 ; get the 8 lsb from ext. p mem. rep #8 ; shift 8 bit data into a1 asr a _loop2 ; get another byte. movem a1,p:(r0)+ ; store 24-bit result in p mem. _loop1 ; and go get another 24-bit word. jmp finish ; boot from eprom done ; end of bootstrap code. number of program words: 70 figure a-1 dsp56003/005 bootstrap program listing (sheet 3 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . arctangent table contents motorola bootstrap program and data rom listings a - 7 a.3 arctangent table contents this arctangent table (see figure a-2) which is located in x memory rom contains 256 unsigned 24-bit values for the arctangent function with an argument range of 0-4/9 p . org x:$100 ; t_00 dc $000000 t_01 dc $03aa60 t_02 dc $0753cd t_03 dc $0afb57 t_04 dc $0ea00d t_05 dc $124107 t_06 dc $15dd60 t_07 dc $19743b t_08 dc $1d04c1 t_09 dc $208e27 t_0a dc $240fab t_0b dc $278894 t_0c dc $2af837 t_0d dc $2e5df4 t_0e dc $31b938 t_0f dc $35097b t_10 dc $384e43 t_11 dc $3b8723 t_12 dc $3eb3ba t_13 dc $41d3b3 t_14 dc $44e6c6 t_15 dc $47ecb6 t_16 dc $4ae552 t_17 dc $4dd073 t_18 dc $50adfc t_19 dc $537ddc t_1a dc $564007 t_1b dc $58f47d t_1c dc $5b9b44 t_1d dc $5e3469 t_1e dc $60c001 t_1f dc $633e26 t_20 dc $65aef6 t_21 dc $681298 t_22 dc $6a6931 t_23 dc $6cb2f1 t_24 dc $6ef005 t_25 dc $7120a0 t_26 dc $7344f8 t_27 dc $755d43 t_28 dc $7769ba t_29 dc $796a97 t_2a dc $7b6015 t_2b dc $7d4a70 t_2c dc $7f29e5 t_2d dc $80feaf t_2e dc $82c90c t_2f dc $848939 t_30 dc $863f71 t_31 dc $87ebf2 t_32 dc $898ef6 t_33 dc $8b28b7 t_34 dc $8cb972 t_35 dc $8e415e t_36 dc $8fc0b3 t_37 dc $9137aa t_38 dc $92a679 t_39 dc $940d55 t_3a dc $956c73 t_3b dc $96c405 t_3c dc $98143d t_3d dc $995d4d t_3e dc $9a9f64 t_3f dc $9bdab2 t_40 dc $9d0f62 t_41 dc $9e3da2 t_42 dc $9f659d t_43 dc $a0877d t_44 dc $a1a36a t_45 dc $a2b98d t_46 dc $a3ca0c t_47 dc $a4d50e t_48 dc $a5dab6 t_49 dc $a6db28 t_4a dc $a7d687 t_4b dc $a8ccf5 t_4c dc $a9be92 t_4d dc $aaab7f t_4e dc $ab93d9 t_4f dc $ac77be t_50 dc $ad574d t_51 dc $ae32a1 t_52 dc $af09d6 t_53 dc $afdd05 t_54 dc $b0ac4a t_55 dc $b177bd t_56 dc $b23f76 t_57 dc $b3038e t_58 dc $b3c41b t_59 dc $b48133 t_5a dc $b53aed t_5b dc $b5f15c t_5c dc $b6a496 t_5d dc $b754af t_5e dc $b801ba t_5f dc $b8abc8 t_60 dc $b952ee t_61 dc $b9f73b t_62 dc $ba98c2 t_63 dc $bb3793 t_64 dc $bbd3be t_65 dc $bc6d53 t_66 dc $bd0461 t_67 dc $bd98f7 t_68 dc $be2b24 t_69 dc $bebaf5 figure a-2 arc-tangent table contents listing (part 1 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . arctangent table contents a - 8 bootstrap program and data rom listings motorola t_6a dc $bf4878 t_6b dc $bfd3ba t_6c dc $c05cc9 t_6d dc $c0e3b0 t_6e dc $c1687d t_6f dc $c1eb3a t_70 dc $c26bf3 t_71 dc $c2eab4 t_72 dc $c36787 t_73 dc $c3e278 t_74 dc $c45b90 t_75 dc $c4d2d9 t_76 dc $c5485d t_77 dc $c5bc27 t_78 dc $c62e3e t_79 dc $c69eac t_7a dc $c70d7b t_7b dc $c77ab1 t_7c dc $c7e659 t_7d dc $c85079 t_7e dc $c8b91a t_7f dc $c92044 t_80 dc $c985fe t_81 dc $c9ea4f t_82 dc $ca4d3f t_83 dc $caaed4 t_84 dc $cb0f16 t_85 dc $cb6e0a t_86 dc $cbcbb8 t_87 dc $cc2826 t_88 dc $cc835a t_89 dc $ccdd59 t_8a dc $cd362a t_8b dc $cd8dd2 t_8c dc $cde458 t_8d dc $ce39c0 t_8e dc $ce8e0f t_8f dc $cee14c t_90 dc $cf337a t_91 dc $cf84a0 t_92 dc $cfd4c1 t_93 dc $d023e2 t_94 dc $d07209 t_95 dc $d0bf39 t_96 dc $d10b77 t_97 dc $d156c7 t_98 dc $d1a12e t_99 dc $d1eaaf t_9a dc $d2334f t_9b dc $d27b11 t_9c dc $d2c1fa t_9d dc $d3080c t_9e dc $d34d4c t_9f dc $d391be t_a0 dc $d3d564 t_a1 dc $d41842 t_a2 dc $d45a5c t_a3 dc $d49bb5 t_a4 dc $d4dc50 t_a5 dc $d51c30 t_a6 dc $d55b58 t_a7 dc $d599cc t_a8 dc $d5d78d t_a9 dc $d614a0 t_aa dc $d65107 t_ab dc $d68cc4 t_ac dc $d6c7db t_ad dc $d7024e t_ae dc $d73c1f t_af dc $d77551 t_b0 dc $d7ade7 t_b1 dc $d7e5e4 t_b2 dc $d81d48 t_b3 dc $d85418 t_b4 dc $d88a54 t_b5 dc $d8c000 t_b6 dc $d8f51e t_b7 dc $d929af t_b8 dc $d95db6 t_b9 dc $d99135 t_ba dc $d9c42e t_bb dc $d9f6a3 t_bc dc $da2895 t_bd dc $da5a08 t_be dc $da8afc t_bf dc $dabb74 t_c0 dc $daeb71 t_c1 dc $db1af6 t_c2 dc $db4a03 t_c3 dc $db789b t_c4 dc $dba6bf t_c5 dc $dbd471 t_c6 dc $dc01b2 t_c7 dc $dc2e85 t_c8 dc $dc5aea t_c9 dc $dc86e4 t_ca dc $dcb273 t_cb dc $dcdd99 t_cc dc $dd0858 t_cd dc $dd32b1 t_ce dc $dd5ca6 t_cf dc $dd8637 t_d0 dc $ddaf67 t_d1 dc $ddd836 t_d2 dc $de00a6 t_d3 dc $de28b8 t_d4 dc $de506d t_d5 dc $de77c7 figure a-2 arc-tangent table contents listing (part 2 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . arctangent table contents motorola bootstrap program and data rom listings a - 9 the data values for figure a-2 were calculated using the following formula : data 16777216 p ----------------------- - address 256 4 p 9 ------ cos ------------------------------- ? ? ? ?? atan = t_d6 dc $de9ec6 t_d7 dc $dec56d t_d8 dc $deebbc t_d9 dc $df11b3 t_da dc $df3756 t_db dc $df5ca4 t_dc dc $df819e t_dd dc $dfa646 t_de dc $dfca9d t_df dc $dfeea3 t_e0 dc $e0125b t_e1 dc $e035c4 t_e2 dc $e058e0 t_e3 dc $e07bb0 t_e4 dc $e09e34 t_e5 dc $e0c06e t_e6 dc $e0e25f t_e7 dc $e10407 t_e8 dc $e12567 t_e9 dc $e14681 t_ea dc $e16755 t_eb dc $e187e4 t_ec dc $e1a82e t_ed dc $e1c835 t_ee dc $e1e7fa t_ef dc $e2077d t_f0 dc $e226bf t_f1 dc $e245c0 t_f2 dc $e26482 t_f3 dc $e28306 t_f4 dc $e2a14c t_f5 dc $e2bf54 t_f6 dc $e2dd20 t_f7 dc $e2fab0 t_f8 dc $e31804 t_f9 dc $e3351f t_fa dc $e351ff t_fb dc $e36ea7 t_fc dc $e38b16 t_fd dc $e3a74d t_fe dc $e3c34d t_ff dc $e3df17 figure a-2 arc-tangent table contentslisting (part 3 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sine table contents a - 10 bootstrap program and data rom listings motorola a.4 sine table contents f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sine table contents motorola bootstrap program and data rom listings a - 11 this sine table (figure a-3) which is located in y memory rom is normally used by fft routines which use bit reversed address pointers. this table can be used as it is for up to 512 point ffts; however, for larger ffts, the table must be copied to a different memory location to allow the reverse-carry addressing mode to be used (see reverse-carry modifier (mn=$0000) in the dsp56000 family manual for additional information). org y:$100 ; s_00 dc $000000 ; +0.0000000000 s_01 dc $03242b ; +0.0245412998 s_02 dc $0647d9 ; +0.0490676016 s_03 dc $096a90 ; +0.0735644996 s_04 dc $0c8bd3 ; +0.0980170965 s_05 dc $0fab27 ; +0.1224106997 s_06 dc $12c810 ; +0.1467303932 s_07 dc $15e214 ; +0.1709619015 s_08 dc $18f8b8 ; +0.1950902939 s_09 dc $1c0b82 ; +0.2191012055 s_0a dc $1f19f9 ; +0.2429800928 s_0b dc $2223a5 ; +0.2667128146 s_0c dc $25280c ; +0.2902846038 s_0d dc $2826b9 ; +0.3136816919 s_0e dc $2b1f35 ; +0.3368898928 s_0f dc $2e110a ; +0.3598949909 s_10 dc $30fbc5 ; +0.3826833963 s_11 dc $33def3 ; +0.4052414000 s_12 dc $36ba20 ; +0.4275551140 s_13 dc $398cdd ; +0.4496113062 s_14 dc $3c56ba ; +0.4713967144 s_15 dc $3f174a ; +0.4928981960 s_16 dc $41ce1e ; +0.5141026974 s_17 dc $447acd ; +0.5349975824 s_18 dc $471ced ; +0.5555701852 s_19 dc $49b415 ; +0.5758082271 s_1a dc $4c3fe0 ; +0.5956993103 s_1b dc $4ebfe9 ; +0.6152315736 s_1c dc $5133cd ; +0.6343932748 s_1d dc $539b2b ; +0.6531729102 s_1e dc $55f5a5 ; +0.6715589762 s_1f dc $5842dd ; +0.6895405054 s_20 dc $5a827a ; +0.7071068287 s_21 dc $5cb421 ; +0.7242470980 s_22 dc $5ed77d ; +0.7409511805 s_23 dc $60ec38 ; +0.7572088242 s_24 dc $62f202 ; +0.7730104923 s_25 dc $64e889 ; +0.7883464098 s_26 dc $66cf81 ; +0.8032075167 s_27 dc $68a69f ; +0.8175848722 s_28 dc $6a6d99 ; +0.8314697146 s_29 dc $6c2429 ; +0.8448535204 s_2a dc $6dca0d ; +0.8577286005 s_2b dc $6f5f03 ; +0.8700870275 s_2c dc $70e2cc ; +0.8819212914 s_2d dc $72552d ; +0.8932244182 s_2e dc $73b5ec ; +0.9039893150 s_2f dc $7504d3 ; +0.9142097235 s_30 dc $7641af ; +0.9238795042 s_31 dc $776c4f ; +0.9329928160 s_32 dc $788484 ; +0.9415441155 s_33 dc $798a24 ; +0.9495282173 s_34 dc $7a7d05 ; +0.9569402933 s_35 dc $7b5d04 ; +0.9637761116 s_36 dc $7c29fc ; +0.9700313210 s_37 dc $7ce3cf ; +0.9757022262 s_38 dc $7d8a5f ; +0.9807853103 s_39 dc $7e1d94 ; +0.9852777123 s_3a dc $7e9d56 ; +0.9891765118 s_3b dc $7f0992 ; +0.9924796224 s_3c dc $7f6237 ; +0.9951847792 s_3d dc $7fa737 ; +0.9972904921 s_3e dc $7fd888 ; +0.9987955093 s_3f dc $7ff622 ; +0.9996988773 s_40 dc $7fffff ; +0.9999998808 s_41 dc $7ff622 ; +0.9996988773 s_42 dc $7fd888 ; +0.9987955093 s_43 dc $7fa737 ; +0.9972904921 s_44 dc $7f6237 ; +0.9951847792 s_45 dc $7f0992 ; +0.9924796224 s_46 dc $7e9d56 ; +0.9891765118 s_47 dc $7e1d94 ; +0.9852777123 s_48 dc $7d8a5f ; +0.9807853103 s_49 dc $7ce3cf ; +0.9757022262 s_4a dc $7c29fc ; +0.9700313210 s_4b dc $7b5d04 ; +0.9637761116 s_4c dc $7a7d05 ; +0.9569402933 s_4d dc $798a24 ; +0.9495282173 s_4e dc $788484 ; +0.9415441155 s_4f dc $776c4f ; +0.9329928160 s_50 dc $7641af ; +0.9238795042 s_51 dc $7504d3 ; +0.9142097235 s_52 dc $73b5ec ; +0.9039893150 s_53 dc $72552d ; +0.8932244182 s_54 dc $70e2cc ; +0.8819212914 s_55 dc $6f5f03 ; +0.8700870275 s_56 dc $6dca0d ; +0.8577286005 s_57 dc $6c2429 ; +0.8448535204 s_58 dc $6a6d99 ; +0.8314697146 s_59 dc $68a69f ; +0.8175848722 s_5a dc $66cf81 ; +0.8032075167 s_5b dc $64e889 ; +0.7883464098 s_5c dc $62f202 ; +0.7730104923 s_5d dc $60ec38 ; +0.7572088242 s_5e dc $5ed77d ; +0.7409511805 s_5f dc $5cb421 ; +0.7242470980 s_60 dc $5a827a ; +0.7071068287 s_61 dc $5842dd ; +0.6895405054 s_62 dc $55f5a5 ; +0.6715589762 s_63 dc $539b2b ; +0.6531729102 s_64 dc $5133cd ; +0.6343932748 s_65 dc $4ebfe9 ; +0.6152315736 s_66 dc $4c3fe0 ; +0.5956993103 s_67 dc $49b415 ; +0.5758082271 s_68 dc $471ced ; +0.5555701852 figure a-3 sine table contents (part 1 of 3 ) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sine table contents a - 12 bootstrap program and data rom listings motorola s_6a dc $41ce1e ; +0.5141026974 s_6b dc $3f174a ; +0.4928981960 s_6c dc $3c56ba ; +0.4713967144 s_6d dc $398cdd ; +0.4496113062 s_6e dc $36ba20 ; +0.4275551140 s_6f dc $33def3 ; +0.4052414000 s_70 dc $30fbc5 ; +0.3826833963 s_71 dc $2e110a ; +0.3598949909 s_72 dc $2b1f35 ; +0.3368898928 s_73 dc $2826b9 ; +0.3136816919 s_74 dc $25280c ; +0.2902846038 s_75 dc $2223a5 ; +0.2667128146 s_76 dc $1f19f9 ; +0.2429800928 s_77 dc $1c0b82 ; +0.2191012055 s_78 dc $18f8b8 ; +0.1950902939 s_79 dc $15e214 ; +0.1709619015 s_7a dc $12c810 ; +0.1467303932 s_7b dc $0fab27 ; +0.1224106997 s_7c dc $0c8bd3 ; +0.0980170965 s_7d dc $096a90 ; +0.0735644996 s_7e dc $0647d9 ; +0.0490676016 s_7f dc $03242b ; +0.0245412998 s_80 dc $000000 ; +0.0000000000 s_81 dc $fcdbd5 ; -0.0245412998 s_82 dc $f9b827 ; -0.0490676016 s_83 dc $f69570 ; -0.0735644996 s_84 dc $f3742d ; -0.0980170965 s_85 dc $f054d9 ; -0.1224106997 s_86 dc $ed37f0 ; -0.1467303932 s_87 dc $ea1dec ; -0.1709619015 s_88 dc $e70748 ; -0.1950902939 s_89 dc $e3f47e ; -0.2191012055 s_8a dc $e0e607 ; -0.2429800928 s_8b dc $dddc5b ; -0.2667128146 s_8c dc $dad7f4 ; -0.2902846038 s_8d dc $d7d947 ; -0.3136816919 s_8e dc $d4e0cb ; -0.3368898928 s_8f dc $d1eef6 ; -0.3598949909 s_90 dc $cf043b ; -0.3826833963 s_91 dc $cc210d ; -0.4052414000 s_92 dc $c945e0 ; -0.4275551140 s_93 dc $c67323 ; -0.4496113062 s_94 dc $c3a946 ; -0.4713967144 s_95 dc $c0e8b6 ; -0.4928981960 s_96 dc $be31e2 ; -0.5141026974 s_97 dc $bb8533 ; -0.5349975824 s_98 dc $b8e313 ; -0.5555701852 s_99 dc $b64beb ; -0.5758082271 s_9a dc $b3c020 ; -0.5956993103 s_9b dc $b14017 ; -0.6152315736 s_9c dc $aecc33 ; -0.6343932748 s_9d dc $ac64d5 ; -0.6531729102 s_9e dc $aa0a5b ; -0.6715589762 s_9f dc $a7bd23 ; -0.6895405054 s_a0 dc $a57d86 ; -0.7071068287 s_a1 dc $a34bdf ; -0.7242470980 s_a2 dc $a12883 ; -0.7409511805 s_a3 dc $9f13c8 ; -0.7572088242 s_a4 dc $9d0dfe ; -0.7730104923 s_a5 dc $9b1777 ; -0.7883464098 s_a6 dc $99307f ; -0.8032075167 s_a7 dc $975961 ; -0.8175848722 s_a8 dc $959267 ; -0.8314697146 s_a9 dc $93dbd7 ; -0.8448535204 s_aa dc $9235f3 ; -0.8577286005 s_ab dc $90a0fd ; -0.8700870275 s_ac dc $8f1d34 ; -0.8819212914 s_ad dc $8daad3 ; -0.8932244182 s_ae dc $8c4a14 ; -0.9039893150 s_af dc $8afb2d ; -0.9142097235 s_b0 dc $89be51 ; -0.9238795042 s_b1 dc $8893b1 ; -0.9329928160 s_b2 dc $877b7c ; -0.9415441155 s_b3 dc $8675dc ; -0.9495282173 s_b4 dc $8582fb ; -0.9569402933 s_b5 dc $84a2fc ; -0.9637761116 s_b6 dc $83d604 ; -0.9700313210 s_b7 dc $831c31 ; -0.9757022262 s_b8 dc $8275a1 ; -0.9807853103 s_b9 dc $81e26c ; -0.9852777123 s_ba dc $8162aa ; -0.9891765118 s_bb dc $80f66e ; -0.9924796224 s_bc dc $809dc9 ; -0.9951847792 s_bd dc $8058c9 ; -0.9972904921 s_be dc $802778 ; -0.9987955093 s_bf dc $8009de ; -0.9996988773 s_c0 dc $800000 ; -1.0000000000 s_c1 dc $8009de ; -0.9996988773 s_c2 dc $802778 ; -0.9987955093 s_c3 dc $8058c9 ; -0.9972904921 s_c4 dc $809dc9 ; -0.9951847792 s_c5 dc $80f66e ; -0.9924796224 s_c6 dc $8162aa ; -0.9891765118 s_c7 dc $81e26c ; -0.9852777123 s_c8 dc $8275a1 ; -0.9807853103 s_c9 dc $831c31 ; -0.9757022262 s_ca dc $83d604 ; -0.9700313210 s_cb dc $84a2fc ; -0.9637761116 s_cc dc $8582fb ; -0.9569402933 s_cd dc $8675dc ; -0.9495282173 s_ce dc $877b7c ; -0.9415441155 s_cf dc $8893b1 ; -0.9329928160 s_d0 dc $89be51 ; -0.9238795042 s_d1 dc $8afb2d ; -0.9142097235 s_d2 dc $8c4a14 ; -0.9039893150 s_d3 dc $8daad3 ; -0.8932244182 s_d4 dc $8f1d34 ; -0.8819212914 s_d5 dc $90a0fd ; -0.8700870275 figure a-3 sine table contents (part 2 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sine table contents motorola bootstrap program and data rom listings a - 13 s_d6 dc $9235f3 ; -0.8577286005 s_d7 dc $93dbd7 ; -0.8448535204 s_d8 dc $959267 ; -0.8314697146 s_d9 dc $975961 ; -0.8175848722 s_da dc $99307f ; -0.8032075167 s_db dc $9b1777 ; -0.7883464098 s_dc dc $9d0dfe ; -0.7730104923 s_dd dc $9f13c8 ; -0.7572088242 s_de dc $a12883 ; -0.7409511805 s_df dc $a34bdf ; -0.7242470980 s_e0 dc $a57d86 ; -0.7071068287 s_e1 dc $a7bd23 ; -0.6895405054 s_e2 dc $aa0a5b ; -0.6715589762 s_e3 dc $ac64d5 ; -0.6531729102 s_e4 dc $aecc33 ; -0.6343932748 s_e5 dc $b14017 ; -0.6152315736 s_e6 dc $b3c020 ; -0.5956993103 s_e7 dc $b64beb ; -0.5758082271 s_e8 dc $b8e313 ; -0.5555701852 s_e9 dc $bb8533 ; -0.5349975824 s_ea dc $be31e2 ; -0.5141026974 s_eb dc $c0e8b6 ; -0.4928981960 s_ec dc $c3a946 ; -0.4713967144 s_ed dc $c67323 ; -0.4496113062 s_ee dc $c945e0 ; -0.4275551140 s_ef dc $cc210d ; -0.4052414000 s_f0 dc $cf043b ; -0.3826833963 s_f1 dc $d1eef6 ; -0.3598949909 s_f2 dc $d4e0cb ; -0.3368898928 s_f3 dc $d7d947 ; -0.3136816919 s_f4 dc $dad7f4 ; -0.2902846038 s_f5 dc $dddc5b ; -0.2667128146 s_f6 dc $e0e607 ; -0.2429800928 s_f7 dc $e3f47e ; -0.2191012055 s_f8 dc $e70748 ; -0.1950902939 s_f9 dc $ea1dec ; -0.1709619015 s_fa dc $ed37f0 ; -0.1467303932 s_fb dc $f054d9 ; -0.1224106997 s_fc dc $f3742d ; -0.0980170965 s_fd dc $f69570 ; -0.0735644996 s_fe dc $f9b827 ; -0.0490676016 s_ff dc $fcdbd5 ; -0.0245412998 figure a-3 sine table contents (part 3 of 3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sine table contents a - 14 bootstrap program and data rom listings motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola b - 1 appendix b programming sheets the following pages are a set of programming sheets intended to simplify programming the various dsp56003/005 programmable registers. the registers are grouped between the central processing mod- ule and each peripheral. each register includes the name, address, reset value, and meaning of each bit. the sheets provide room to write the value for each bit and the hexadecimal equivalent for each register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents b - 2 programming sheets motorola paragraph number page number section b.1 peripheral addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-3 b.2 interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . b-4 b.3 exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 b.4 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-6 b.5 central processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-11 b.6 gp i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-15 b.7 host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-17 b.8 sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-22 b.9 ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-25 b.10 timer/counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-28 b.11 pulse width modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-29 b.12 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-35 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola programming sheets b - 3 peripheral addresses 23 16 15 8 7 0 x:$ffff interrupt priority register (ipr) x:$fffe port a ?bus control register (bcr) x:$fffd pll control register (pctl) x:$fffc once port gdb register x:$fffb reserved x:$fffa reserved x:$fff9 reserved x:$fff8 reserved x:$fff7 reserved x:$fff6 sci hi-rec/xmit data register (srx/stx) x:$fff5 sci mid-rec/xmit data register (srx/stx) x:$fff4 sci low-rec/xmit data register (srx/stx) x:$fff3 sci transmit data address register (stxa) x:$fff2 sci control register (sccr) x:$fff1 sci interface status register (ssr) x:$fff0 sci interface control register (scr) x:$ffef ssi receive/transmit data register (rx/tx) x:$ffee ssi status/time slot register (ssisr/tsr) x:$ffed ssi control register b (crb) x:$ffec ssi control register a (cra) x:$ffeb host receive/transmit register (hrx/htx) x:$ffea reserved x:$ffe9 host status register (hsr) x:$ffe8 host control register (hcr) x:$ffe7 watchdog timer count register (wcr) x:$ffe6 watchdog timer control/status register (wcsr) x:$ffe5 port c - gpio data register (pcd) x:$ffe4 port b - gpio data register (pbd) x:$ffe3 port c - gpio data direction register (pcddr) x:$ffe2 port b - gpio data direction register (pbddr) x:$ffe1 port c - gpio control register (pcc) x:$ffe0 port b - gpio control register (pbc) x:$ffdf timer count register (tcr) x:$ffde timer control/status register (tcsr) x:$ffdd reserved x:$ffdc pwma2 count register (pwacr2) x:$ffdb pwma1 count register (pwacr1) x:$ffda pwma0 count register (pwacr0) x:$ffd9 pwma control and status register 0 (pwacsr0) x:$ffd8 pwma control and status register 1 (pwacsr1) x:$ffd7 pwmb1 count register (pwbcr1) x:$ffd6 pwmb0 count register (pwbcr0) x:$ffd5 pwmb control and status register 0 (pwbcsr0) x:$ffd4 pwmb control and status register 1 (pwbcsr1) x:$ffd3 reserved x:$ffc0 reserved = read as a random number; write as don? care. figure b-1 on-chip peripheral memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupt vector addresses b - 4 programming sheets motorola interrupt vector addresses interrupt starting address ipl interrupt source p:$0000 3 hardware reset p:$0002 3 stack error p:$0004 3 trace p:$0006 3 swi p:$0008 0 - 2 irqa p:$000a 0 - 2 irqb p:$000c 0 - 2 ssi receive data p:$000e 0 - 2 ssi receive data with exception status p:$0010 0 - 2 ssi transmit data p:$0012 0 - 2 ssi transmit data with exception status p:$0014 0 - 2 sci receive data p:$0016 0 - 2 sci receive data with exception status p:$0018 0 - 2 sci transmit data p:$001a 0 - 2 sci idle line p:$001c 0 - 2 sci timer p:$001e 3 nmi/watchdog timer p:$0020 0 - 2 host receive data p:$0022 0 - 2 host transmit data p:$0024 0 - 2 host command (default) p:$0026 0 - 2 available for host command p:$0028 0 - 2 available for host command p:$002a 0 - 2 available for host command p:$002c 0 - 2 irqc p:$002e 0 - 2 irqd p:$0030 0 - 2 pwma0 p:$0032 0 - 2 pwma1 p:$0034 0 - 2 pwma2 p:$0036 0 - 2 pwmb0 p:$0038 0 - 2 pwmb p:$003a 0 - 2 pwm error p:$003c 0 - 2 timer/event counter p:$003e 3 illegal instruction p:$0040 0 - 2 available for host command p:$007e 0 - 2 available for host command table b-1 interrupt starting addresses and sources f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . exception priorities motorola programming sheets b - 5 priority exception level 3 (nonmaskable) highest hardware reset illegal instruction nmi stack error trace lowest swi levels 0, 1, 2 (maskable) highest irqa (external interrupt) irqb (external interrupt) irqc (external interrupt) irqd (external interrupt) host command interrupt host receive data interrupt host transmit data interrupt ssi rx data with exception interrupt ssi rx data interrupt ssi tx data with exception interrupt ssi tx data interrupt sci rx data with exception interrupt sci rx data interrupt sci tx data with exception interrupt sci tx data interrupt sci idle line interrupt sci timer interrupt timer/event counter interrupt pwm error pwma0 ready pwma1 ready pwma2 ready pwmb0 ready lowest pwmb1 ready table b-2 exception priorities within an ipl exception priorities f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instructions b - 6 programming sheets motorola mnemonic syntax parallel moves instruction osc. program clock words cycles s le unzvc abs d (parallel move) . . . . . . .1+mv 2+mv * * * * * * * - adc s,d (parallel move) . . . . . . .1+mv 2+mv * * * * * * * * add s,d (parallel move) . . . . . . .1+mv 2+mv * * * * * * * * addl s,d (parallel move) . . . . . . .1+mv 2+mv * * * * * * ?* addr s,d (parallel move) . . . . . . .1+mv 2+mv * * * * * * * * and s,d (parallel move) . . . . . . .1+mv 2+mv * * - - ? ? 0- and(i) #xx,d . . . . . . . . . . . . . . . . . . . . 1 2 ? ? ? ? ? ? ?? asl d (parallel move) . . . . . . .1+mv 2+mv * * * * * * ?? asr d (parallel move) . . . . . . .1+mv 2+mv * * * * * * 0? bchg #n,x: instructions motorola programming sheets b - 7 mnemonic syntax parallel moves instruction osc. program clock words cycles s le unzvc do x: instructions b - 8 programming sheets motorola mnemonic syntax parallel moves instruction osc. program clock words cycles s le unzvc macr (+ )s2,s1,d (parallel move) . . . . . . . . .1+mv 2+mv * * * * * * * - (+ )s1,s2,d (parallel move) (+ )s,#n,d ( no parallel move). . . . . . . . 1 2 move s,d . . . . . . . . . . . . . . . . . . . . .1+mv 2+mv * * - - - - - - no parallel data move (.....) . . . . . . . . . . . . . . . . . . . . . mv mv - - - - - - - - immediate short (.....)#xx,d . . . . . . . . . . . . . . . . . mv mv - - - - - - - - data move register to register (.....)s,d . . . . . . . . . . . . . . . . . . mv mv * * - - - - - - data move address register update (.....)ea . . . . . . . . . . . . . . . . . . . mv mv - - - - - - - - x memory data move (.....)x: instructions motorola programming sheets b - 9 mnemonic syntax parallel moves instruction osc. program clock words cycles s le unzvc move(m) p: instructions b - 10 programming sheets motorola mnemonic syntax parallel moves instruction osc. program clock words cycles s le unzvc reset . . . . . . . . . . . . . . . . . . . . 1 4 - - - - - - - - rnd d (parallel move) . . . . . . .1+mv 2+mv * * * * * * * - rol d (parallel move) . . . . . . .1+mv 2+mv * * - - ? ? 0? ror d (parallel move) . . . . . . .1+mv 2+mv * * - - ? ? 0? rti . . . . . . . . . . . . . . . . . . . . 1 4+rx ? ? ? ? ? ? ?? rts . . . . . . . . . . . . . . . . . . . . 1 4+rx - - - - - - - - sbc s,d (parallel move) . . . . . . .1+mv 2+mv * * * * * * * * stop . . . . . . . . . . . . . . . . . . . . 1 n/a - - - - - - - - sub s,d (parallel move) . . . . . . .1+mv 2+mv * * * * * * * * subl s,d (parallel move) . . . . . . .1+mv 2+mv * * * * * * ?* subr s,d (parallel move) . . . . . . .1+mv 2+mv * * * * * * * * swi . . . . . . . . . . . . . . . . . . . . 1 8 - - - - - - - - tcc s1,d1 . . . . . . . . . . . . . . . . . . . . 1 2 - - - - - - - - s1,d1 s2,d2 tfr s,d (parallel move) . . . . . . .1+mv 2+mv * * - - - - - - tst s (parallel move) . . . . . . .1+mv 2+mv * * * * * * 0- wait . . . . . . . . . . . . . . . . . . . . 1 n/a - - - - - - - - notation: - denotes the bit is unaffected by the operation. * denotes the bit may be set according to the definition, depending on parallel move conditions. ? denotes the bit is set according to a special definition. see the instruction descriptions in appendix a of the dsp56000 family manual (dsp56kfamum/ad) . 0 denotes the bit is cleared. instructions table b-3 instruction set summary ?sheet 5 of 5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor motorola programming sheets b - 11 application: date: programmer: * = reserved, program as zero sheet 1 of 4 1514131211109876543210 lf t s1 s0 i1 i0 l e u n z v c status register (sr) read/write * 0 carry over?w zero negative unnormalized extension limit fft scaling interrupt mask scaling mode reserved trace mode double precision multiply mode loop flag reset = $0300 dm s mode register (mr) condition code register (ccr) port a bus control register (bcr) x:$fffe read/write reset = $ffff 1514131211109876543210 external x memory external y memory external p memory external i/0 memory figure b-2 status register (sr) figure b-3 bus control register (bcr) central processor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor b - 12 programming sheets motorola ssl1 ssl0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 application: date: programmer: sheet 2 of 4 * = reserved, program as zero 1514131211109876543210 scl0 hpl1 hpl0 ibl2 ibl1 ibl0 ial2 ial1 ial0 interrupt priority x:$ffff read/write ssl1 ssl0 irqa mode ial2 trigger ial1 ial0 enabled ipl 0 level 0 0 no 1 neg. edge 0 1 yes 0 1 0 yes 1 1 1 yes 2 reset = $000000 central processor register (ipr) 23 22 21 20 19 18 16 17 * 0 * 0 * 0 * 0 scl1 ssi ipl $0 figure b-4 interrupt priority register (ipr) irqb mode ibl2 trigger ibl1 ibl0 enabled ipl 0 level 0 0 no 1 neg. edge 0 1 yes 0 1 0 yes 1 1 1 yes 2 irqc mode icl1 icl0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 irqd mode idl1 idl0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 hpl1 hpl0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 host ipl scl1 scl0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 sci ipl til1 til0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 timer/counter ipl pwl1 pwl0 enabled ipl 0 0 no 0 1 yes 0 1 0 yes 1 1 1 yes 2 pwm ipl pwl1 pwl0 til0 til1 icl1 icl0 idl1 idl0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor motorola programming sheets b - 13 application: date: programmer: sheet 3 of 4 1514131211109876543210 sd mc mb ma operating mode read/write ** 0 0 ** 0 0 ** 0 0 ** 0 0 yd reset = $000000 $0 $0 register (omr) $0 $0 19 18 17 16 ** 0 0 ** 0 0 23 22 21 20 ** 0 0 ** 0 0 de * 0 * 0 stop delay 0 = 128k t stabilization 1 = 16 t stabilization central processor * = bit 5 and bits 7 through 23 are reserved. program as zero mode m m m operating mode c b a 0 0 0 0 single-chip mode 1 0 0 1 bootstrap from eprom at p: $c000 2 0 1 0 normal expanded mode 3 0 1 1 development mode 4 1 0 0 reserved 5 1 0 1 bootstrap from host 6 1 1 0 bootstrap from sci (external clock) 7 1 1 1 bootstrap from eprom at p: $8000 data rom enable 0 = disable roms 1 = enable roms internal y memory disable 0 = y memory controlled by de bit 1 = all y memory external figure b-5 operating mode register (omr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor b - 14 programming sheets motorola application: date: programmer: sheet 4 of 4 1514131211109876543210 df3 df2 mf11 mf10 mf7 mf6 mf5 mf4 mf3 mf2 mf1 mf0 pll control x:$fffd read/write df1 df0 reset = $0x0000 register (pctl) 19 18 17 16 23 22 21 20 * 0 mf8 mf9 xtld pstp pen cod0 cod1 csrc ckos multiplication factor bits mf0 - mf11 mf11 - mf0 multiplication factor mf $000 1 $001 2 $002 3 $ffe 4095 $fff 4096 division factor bits df0 - df3 df3 - df0 division factor df $0 2 0 $1 2 1 $2 2 2 $e 2 14 $f 2 15 clock output disable bits cod0 - cod1 cod1 cod0 clkout pin 0 0 clock out enabled, full strength output buffer 0 1 clock out enabled, 2/3 strength output buffer 1 0 clock out enabled, 1/3 strength output buffer 1 1 clock out disabled xtal disable bit (xtld) 0 = enable xtal 1 = disable xtal stop processing state bit (pstp) 0 = pll disabled during stop processing state 1 = pll enabled during stop processing state pll enable bit (pen) 0 = disable pll 1 = enable pll chip clock source bit (csrc) 0 = output from low power divider 1 = output from vco ckout clock source bit (ckos) 0 = output from lpd 1 = output from vco * = reserved, program as zero . . . . . . . . . . . . central processor figure b-6 pll control register (pctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . gpio motorola programming sheets b - 15 application: date: programmer: 1514131211109876543210 pbc0 ************** $0 $0 $0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 port b control register (pbc) x:$ffe0 read/write reset = $000000 1514131211109876543210 * bd14 bd13 bd12 bd11bd10 bd9 bd8 bd7 bd6 bd5 bd4 bd3 bd2 bd1 bd0 1514131211109876543210 * pb14 pb13 pb12 pb11 pb10 pb9 pb8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port b data direction register (pbddr) x:$ffe2 read/write reset = $000000 port b data register (pbd) x:$ffe4 read/write reset = $000000 0 0 port b data (usually loaded by program) port b data direction control 0 = input 1 = output port b * = reserved, program as zero sheet 1 of 2 23 * 0 23 * 0 23 * 0 pbc1 pbc1 pbc0 function 0 0 general purpose i/o (reset condition) 0 1 host interface 1 0 host interface (with hack pin as gpio) 1 1 reserved figure b-7 port b control register (pbc) figure b-8 port b data direction register (pbddr) figure b-9 port b data register (pbd) * = reserved, program as zero * = reserved, program as zero gpio f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . gpio b - 16 programming sheets motorola application: date: programmer: port c control register (pcc) x:$ffe1 read/write reset = $000000 port c data direction register (pcddr) x:$ffe3 read/write reset = $000000 port c data register (pcd) x:$ffe5 read/write reset = $000000 port c data direction control 0 = input 1 = output port c 1514131211109876543210 * cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 *** $0 0 0 0 0 1514131211109876543210 * cc8 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 *** $0 0 0 0 0 1514131211109876543210 * pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 *** $0 0 0 0 0 port c pin control 0 = general purpose i/o pin 1 = peripheral pin * = reserved, program as zero sheet 2 of 2 gp i/o port c data (usually loaded by program) 23 * 0 23 * 0 23 * 0 * * * 0 0 0 * 0 * 0 * 0 * 0 * 0 * 0 std srd sck sc2 sc1 sc0 sclk txd rxd ssi sci * = reserved, program as zero * = reserved, program as zero figure b-10 port c control register (pcc) figure b-11 port c data direction register (pcddr) figure b-12 port c data register (pcd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host motorola programming sheets b - 17 application: date: programmer: host control register (hcr) x:$ffe8 read/write reset = $00 sheet 1 of 5 76543210 hf3 hf2 hcie htie hrie host receive interrupt enable 0 = disable 1 = enable ?interrupt on hrdf host transmit interrupt enable 0 = disable 1 = enable ?interrupt on htde host command interrupt enable 0 = disable 1 = enable ?interrupt on hcp host flags general purpose read/write flags * = reserved, program as zero 1514131211109876543210 ************** $0 $0 $0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 port b control register (pbc) x:$ffe0 read/write reset = $000000 port b *** 0 0 0 dsp side 23 * 0 pbc0 pbc1 pbc1 pbc0 function 0 0 general purpose i/o (reset condition) 0 1 host interface 1 0 host interface (with hack pin as gpio) 1 1 reserved 23 * 0 * = reserved, program as zero figure b-13 port b control register (pbc) figure b-14 host control register (hcr) host f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host b - 18 programming sheets motorola application: date: programmer: sheet 2 of 5 host * = reserved, program as zero host status register (hsr) x:$ffe9 read only reset = $000002 43210 hf1 hf0 hcp htdehrdf host transmit data empty 0 = wait 1 = write host command pending 0 = wait 1 = ready dma status (read only) 0 = disabled 1 = enabled host flags read only host receive data full 0 = wait 1 = read 7 dma 65 ** 0 0 dsp side host receive data register (hrx) x:$ffeb read only reset = $000000 host transmit data register (htx) x:$ffeb write only reset = $000000 host transmit data (usually loaded by program) 1514131211109876543210 transmit middle byte transmit low byte 1514131211109876543210 receive middle byte receive low byte host receive data (usually read by program) 23 22 21 20 19 18 17 16 receive high byte 23 22 21 20 19 18 17 16 transmit high byte 23 * 0 figure b-17 host transmit data register (htx) figure b-16 host receive data register (hrx) figure b-15 host status register (hsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host motorola programming sheets b - 19 application: date: programmer: sheet 3 of 5 host * = reserved, program as zero interrupt control register (icr) $0 read/write reset = $00 43210 hf1 hf0 treqrreq transmit request enable dma off 0 = interrupts disabled 1 = interrupts enabled dma on 0 = dsp host 1 = host dsp host flags write only initialize (write only) 0 = no action 1 = initialize dma host mode control 00 = dma off 01 = 24 bit dma 10 = 16 bit dma 11 = 8 bit dma receive request enable dma off 0 = interrupts disabled 1 = interrupts enabled dma on 0 = host dsp 1 = dsp host 7 init 65 * 0 processor side command vector register (cvr) $1 read/write reset = $12 43210 hv4 hv3 hv2 hv1 hv0 host command 0 = idle 1 = interrupt dsp host vector executive interrupt routine 0-63 7 hc 65 * hv5 0 hm1 hm0 figure b-19 command vector register (cvr) figure b-18 interrupt control register (icr) * = reserved, program as zero f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host b - 20 programming sheets motorola application: date: programmer: sheet 4 of 5 host interrupt status register (isr) $2 read/write reset = $06 43210 hf3 hf2 txderxdf transmit data register empty 0 = wait 1 = write transmitter ready 0 = data in hi 1 = data not in hi dma status 0 = dma disabled 1 = dma enabled host flags read only receive data register full 0 = wait 1 = read 7 hreq 65 * 0 processor side dma trdy host request 0 = hreq deasserted 1 = hreq asserted interrupt vector register (ivr) $3 read/write reset = $0f 43210 iv4 iv3 iv2 iv1 iv0 exception vector number for use by mc68000 processor family vectored interrupts . 7 iv7 65 iv6 iv5 * = reserved, program as zero figure b-20 interrupt status register (isr) figure b-21 interrupt vector register (ivr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . host motorola programming sheets b - 21 application: date: programmer: sheet 5 of 5 host processor side receive byte registers $7, $6, $5, $4 read only reset = $00 7070 host receive data (usually read by program) host transmit data (usually loaded by program) 7070 7070 receive middle byte receive low byte 7070 not used transmit high byte transmit byte registers $7, $6, $5, $4 write only reset = $00 00 000000 receive high byte not used $7 $6 $5 $4 $7 $6 $5 $4 transmit low byte transmit middle byte 00 000000 figure b-22 host receive byte registers (rxh/rxm/rxl) figure b-23 host transmit byte registers (txh/txm/txl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci b - 22 programming sheets motorola word select bits 0 0 0 = 8-bit synchronous data (shift register mode) 0 0 1 = reserved 0 1 0 = 10-bit asynchronous (1 start, 8 data, 1 stop) 0 1 1 = reserved 1 0 0 = 11-bit asynchronous (1 start, 8 data, even parity, 1 stop) 1 0 1 = 11-bit asynchronous (1 start, 8 data, odd parity, 1 stop) 1 1 0 = 11-bit multidrop (1 start, 8 data, even parity, 1 stop) 1 1 1 = reserved application: date: programmer: sci control register (scr) address x:$fff0 read/write 1514131211109876543210 rie ilie te re woms rwu wake sbk ssftd wds2 wds1 wds0 sheet 1 of 3 sckp tie tmie sci shift direction 0 = lsb first 1 = msb first send break 0=send break, then revert 1=continually send breaks wakeup mode select 0=idle line wakeup 1=address bit wakeup receiver wakeup enable 0=receiver has awakened 1=wakeup function enabled receiver enable 0=receiver disabled 1=receiver enabled wired-or mode select 1=multidrop 0=point to point transmitter enable 0=transmitter disabled 1=transmitter enabled transmit interrupt enable 0=transmit interrupts disabled 1=transmit interrupts enabled idle line interrupt enable 0=idle line interrupts disabled 1=idle line interrupts enabled timer interrupt enable 0=timer interrupts disabled 1=timer interrupts enabled sci clock polarity 0=clock polarity is positive 1=clock polarity is negative receive interrupt enable 0=receive interrupts disabled 1=receive interrupts enabled sci timer interrupt rate 0= ? 32, 1= ? 1 stir port c control register (pcc) x:$ffe1 read/write reset = $000000 1514131211109876543210 * cc8 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 *** $0 0 0 0 0 port c pin control 0 = general purpose i/o pin 1 = peripheral pin * * * 0 0 0 port c 23 * 0 23 * 0 * = reserved, program as zero * = reserved, program as zero figure b-24 port c control register (pcc) figure b-25 sci control register (scr) sci f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci motorola programming sheets b - 23 application: date: programmer: sheet 2 of 3 sci sci clock control register (sccr) address x:$fff2 read/write reset = $000000 1514131211109876543210 cd11cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 tcm rcm scp cod transmit/receive clock selection tcm rcm tx clock rx clock sclk pin mode 0 0 internal internal output synchronous/asynchronous 0 1 internal external input asynchronous only 1 0 external internal input asynchronous only 1 1 external external input synchronous/asynchronous clock divider bits cd11-cd0 cd11 - cd0 l cyc rate $000 l cyc /1 $001 l cyc /2 $002 l cyc /3 $ffe l cyc /4095 $fff l cyc /4096 . . . . . . clock out divider 0=divide clock by 16 before feed to sclk 1=feed clock to directly to sclk sci clock prescaler 0= ? 1 1= ? 8 receiver clock mode/source 0=internal clock for receiver 1=external clock from sclk transmitter clock mode/source 0=internal clock for transmitter 1=external clock from sclk sci status register (ssr) address x:$fff1 read only reset = $000003 76543210 r8 fe pe or idle rdrf tdretrne received bit 8 0=data 1=address framing error flag 0=no error 1=no stop bit detected parity error flag 0=no error 1=incorrect parity detected overrun error flag 0=no error 1=overrun detected idle line flag 0=idle not detected 1=idle state receive data register full 0=receive data register full 1=receive data register empty transmitter data register empty 0=transmitter data register full 1=transmitter data register empty transmitter empty 0=transmitter full 1=transmitter empty 23 * 0 23 * 0 * = reserved, program as zero * = reserved, program as zero figure b-27 sci clock control register (sccr) figure b-26 sci status register (ssr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci b - 24 programming sheets motorola application: date: programmer: sci sheet 3 of 3 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 stx stx stx note: stx is the same register decoded at three different addresses. x0 ? ? ? 23 16 15 8 7 0 x:$fff6 x:$fff5 x:$fff4 srx srx srx note: srx is the same register decoded at three different addresses. x0 ? ? ? sci transmit data registers address x:$fff4 ?x:$fff6 read/write reset = xxxxxx sci receive data registers address x:$fff4 - x:$fff6 read/write reset = xxxxxx unpacking txd sci transmit sr packing rxd sci receive sr figure b-29 sci receive data registers (srx) figure b-28 sci transmit data registers (stx) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ssi motorola programming sheets b - 25 application: date: programmer: ssi control register a (cra) x:$ffec read/write reset = $000000 1514131211109876543210 dc3 dc2 dc1 dc0 pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 prescale modulus select sheet 1 of 3 psr wl1 wl0 dc4 prescaler range 0 = / 1 1 = / 8 word length control 00 = 8 bits/word 01 = 12 bits/word 10 = 16 bits/word 11 = 24 bits/word frame rate divider control 00000 = 1 11111 = 32 port c control register (pcc) x:$ffe1 read/write reset = $0000 1514131211109876543210 * cc8 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 *** 0 0 0 0 0 port c pin control 0 = general purpose i/o pin 1 = peripheral pin 23 * 0 * * * 0 0 0 port c 23 * 0 * = reserved, program as zero * = reserved, program as zero figure b-30 ssi control register (pcc) figure b-31 ssi control register a (cra) ssi f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ssi b - 26 programming sheets motorola application: date: programmer: sheet 2 of 3 ssi ssi control register b (crb) x:$ffed read/write reset = $000000 1514131211109876543210 mod gck syn fsl1 fsl0 shfd sckd scd2 scd1scd0 of1 of0 rie tie re te sync/async control 0 = asynchronous 1 = synchronous frame sync length 1 0 = rx is word length 1 = rx is bit length frame sync length 0 0 = rx and tx same length 1 = rx and tx different length ssi mode select 0 = normal 1 = network transmit enable 0 = disable 1 = enable receive interrupt enable 0 = disable 1 = enable receive enable 0 = disable 1 = enable transmit interrupt enable 0 = disable 1 = enable gated clock control 0 = continuous clock 1 = gated clock output flag x if syn = 1 and scd1=1 ofx scx pin serial control direction bits scdx=0 scdx=1 (input) (output) sc0 pin rx clk flag 0 sc1 pin rx frame sync flag 1 sc2 pin tx frame sync tx, rx frame sync 23 * 0 * = reserved, program as zero figure b-32 ssi control register b (crb) shift direction 0 = msb first 1 = lsb first clock source direction 0 = external clock 1 = internal clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ssi motorola programming sheets b - 27 application: date: programmer: ssi status register (ssisr) x:$ffee (read) reset = $000040 sheet 3 of 3 ssi 76543210 rdf tde roe tue rfs tfs if1 if0 receive frame sync 0 = wait 1 = frame sync occurred transmitter underrun error flag 0 = ok 1 = error receiver overrun error flag 0 = ok 1 = error transmit data register empty 0 = wait 1 = write transmit frame sync 0 = sync inactive 1 = sync active receive data register full 0 = wait 1 = read serial input flag 0 if scd0=0 and syn=1 latch sc0 on fs serial input flag 1 if scd1=0 and syn=1 latch sc0 on fs ssi status bits 23 * 0 * = reserved, program as zero figure b-33 ssi status register (ssisr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer/counter b - 28 programming sheets motorola application: date: sheet 1 of 1 1514131211109876543210 23 * 0 timer control and status register (tcsr) x:$ffde (read/write) reset = $000200 te tie inv tc0 tc1 tc2 gpio ts dir di do * 0 * 0 * 0 * 0 * 0 timer enable bit 0 0 = timer disabled 1 = timer enabled timer interrupt enable bit 1 0 = interrupts disabled 1 = interrupts enabled inverter bit 2 0 = 0- to-1 transitions on tio input decrement the counter 1 = 1-to-0 transitions on tio input decrement the counter or 1 = timer pulse inverted before it goes to tio output gpio bit 6 0 = tio is not gpio 1 = tio is gpio if tc2-tc0 are clear timer control bits 3-5 (tc0 - tc2) tc2 tc1 tc0 tio clock mode 0 0 0 gpio internal timer 0 0 1 output internal timer pulse 0 1 0 output internal timer toggle 0 1 1 x x undefined 1 0 0 input internal input width 1 0 1 input internal input period 1 1 0 input external standard time counter 1 1 1 input external event counter timer status bit 7 0 = tcsr read; timer interrupt serviced; not dec. to 0; reset 1 = counter decremented to 0 direction bit 8 - gpio only 0 = tio pin is input 1 = tio pin is output data output bit 10 - gpio only 0 = zero written to tio pin 1 = one written to tio pin note: tc2-tc0, inv=0; dir=1 data input bit 9 - gpio only 0 = zero read from tio pin 1 = one read from tio pin note: tc2-tc0, dir, inv=0 * = reserved, program as zero figure b-34 timer control/status register (tcsr) figure b-35 timer count register (tcr) timer/counter 1514131211109876543210 timer count register (tcr) x:$ffdf (read/write) unaffected by reset 23 22 21 20 19 18 17 16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator motorola programming sheets b - 29 application: date: programmer: sheet 1 of 6 1514131211109876543210 pwma0 count x:$ffda read/write unaffected by reset register (pwacr0) $0 $0 19 18 17 16 ** 0 0 ** 0 0 23 22 21 20 ** 0 0 ** 0 0 * = reserved. program as zero figure b-36 pwma0 count register (pwacr0) load pulse width here. 1514131211109876543210 pwma1 count x:$ffdb read/write unaffected by reset register (pwacr1) $0 $0 19 18 17 16 ** 0 0 ** 0 0 23 22 21 20 ** 0 0 ** 0 0 * = reserved. program as zero figure b-37 pwma1 count register (pwacr1) load pulse width here. 1514131211109876543210 pwma2 count x:$ffdc read/write unaffected by reset register (pwacr2) $0 $0 19 18 17 16 ** 0 0 ** 0 0 23 22 21 20 ** 0 0 ** 0 0 * = reserved. program as zero figure b-38 pwma2 count register (pwacr2) load pulse width here. pulse width modulator f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator b - 30 programming sheets motorola pulse width modulator application: date: programmer: sheet 2 of 6 pwma control/status register 0 (pwacsr0) x:$ffd9 read/write reset = $1c00 1514131211109876543210 was1 was0 waw1 waw0 wack wap2 wap1 wap0 war1 war0 was2 pwma clock source (wack) 0 = external 1 = internal * = reserved, program as zero figure b-39 pwma control/status register 0 (pwacsr0) waw2 war2 * 0 ** 0 0 wap2 wap1 wap0 prescale factor 000 2 0 001 2 1 010 2 2 011 2 3 100 2 4 101 2 5 110 2 6 111 2 7 waw2 waw1 waw0 data width 000 16 001 15 010 14 011 13 100 12 101 11 110 10 111 9 pwma status (wasn) ?read only (one bit for each pulse width modulator) 0 = pwacrn written 1 = pwabufn written pwma error (warn) ?read only (one bit for each pulse width modulator) 0 = no error 1 = error f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator motorola programming sheets b - 31 pulse width modulator application: date: programmer: sheet 3 of 6 pwma control/status register 1 (pwacsr1) x:$ffd8 read/write reset = $0000 1514131211109876543210 wal2 wal1 wai2 wai1 wai0 wae2 wae1 wae0 * = reserved, program as zero figure b-40 pwma control/status register 1 (pwacsr1) waei * 0 ** 0 0 pwman output polarity (waln) (one bit for each pulse width modulator) 0 = active low 1 = active high pwman error interrupt enable (waei) 0 = interrupt disabled 1 = interrupt enabled pwman interrupt enable (wain) (one bit for each pulse width modulator) 0 = interrupt disabled 1 = interrupt enabled pwman carrier select (wacn) (one bit for each pulse width modulator) 0 = external 1 = internal pwman enable (waen) (one bit for each pulse width modulator) 0 = disabled 1 = enabled wac1 wac2 wal0 wac0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator motorola programming sheets b - 32 application: date: programmer: sheet 4 of 6 pulse width modulator 1514131211109876543210 pwmb0 count x:$ffd6 read/write unaffected by reset register (pwbcr0) $0 $0 19 18 17 16 ** 0 0 ** 0 0 23 22 21 20 ** 0 0 ** 0 0 * = reserved. program as zero figure b-41 pwmb0 count register 0 (pwbcr0) load pulse width here. 1514131211109876543210 pwmb1 count x:$ffd7 read/write unaffected by reset register (pwbcr1) $0 $0 19 18 17 16 ** 0 0 ** 0 0 23 22 21 20 ** 0 0 ** 0 0 * = reserved. program as zero figure b-42 pwmb1 count register 1 (pwbcr1) load pulse width here. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator motorola programming sheets b - 33 pulse width modulator application: date: programmer: sheet 5 of 6 pwmb control/status register 0 (pwbcsr0) x:$ffd5 read/write reset = $0000 1514131211109876543210 wbw1 wbw0 wbck wbp2 wbp1 wbp0 wbr0 wbs1 wbs0 pwmb clock source (wbck ) 0 = external 1 = internal * = reserved, program as zero figure b-43 pwmb control/status register 0 (pwbcsr0) wbw2 wbr1 * 0 ** 0 0 wbp2 wbp1 wbp0 prescale factor 000 2 0 001 2 1 010 2 2 011 2 3 100 2 4 101 2 5 110 2 6 111 2 7 wbw2 wbw1 wbw0 data width 000 16 001 15 010 14 011 13 100 12 101 11 110 10 111 9 ** 0 0 pwma error (wbrn) ?read only (one bit for each pulse width modulator) 0 = no error 1 = error pwma status (wbsn) ?read only (one bit for each pulse width modulator) 0 = pwacrn written 1 = pwabufn written f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pulse width modulator b - 34 programming sheets motorola pulse width modulator application: date: programmer: sheet 6 of 6 pwmb control/status register 1 (pwbcsr1) x:$ffd4 read/write reset = $0000 1514131211109876543210 wbi1 wbi0 wbe1 wbe0 * = reserved, program as zero figure b-44 pwmb control and status register 1 (pwbcsr1) wbei * 0 ** 0 0 pwmb open drain output (wbo) (one bit for both pulse width modulators) 0 = open drain 1 = ttl level output pwmbn error interrupt enable (wbei) 0 = interrupt disabled 1 = interrupt enabled pwmbn interrupt enable (wbin) (one bit for each pulse width modulator) 0 = interrupt disabled 1 = interrupt enabled pwmbn carrier select (wbc) 0 = external 1 = internal pwmbn enable (wben) (one bit for each pulse width modulator) 0 = disabled 1 = enabled * 0 ** 0 0 * 0 ** 0 0 wbo wbc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer motorola programming sheets b - 35 watchdog timer status 0 = wdg not zero or wcsr was read 1 = wdg decremented to zero application: date: programmer: sheet 1 of 2 1514131211109876543210 wld wie wp1 wp0 watchdog timer control/ x:$ffe6 read/write ** 0 0 ** 0 0 ** 0 0 ** 0 0 ws reset = $000000 $0 $0 status register (wcsr) $0 $0 19 18 17 16 ** 0 0 ** 0 0 23 22 21 20 ** 0 0 ** 0 0 wp2 watchdog timer enable 0 = wdg disabled 1 = wdg enabled * = reserved. program as zero watchdog timer load 0 = no change 1 = load counter and prescaler watchdog timer debug 0 = continue timing during debug 1 = freeze timing during debug figure b-45 watchdog timer control/status register (wcsr) wdb we wdg timer interrupt enable 0 = wdg interrupt disabled 1 = wdg interrupt enabled wp2 wp1 wp0 prescale factor 000 2 0 001 2 1 010 2 2 011 2 3 100 2 4 101 2 5 110 2 6 111 2 7 watchdog timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . watchdog timer b - 36 programming sheets motorola application: date: programmer: sheet 2 of 2 1514131211109876543210 wd6 wd4 wd1 wd0 watchdog timer x:$ffe7 read/write wd3 unaffected by reset count register (wcr) $0 $0 19 18 17 16 ** 0 0 ** 0 0 23 22 21 20 ** 0 0 ** 0 0 wd2 watchdog timer * = reserved. program as zero figure b-46 watchdog timer count register (wcr) wd7 wd5 load 16-bit time delay here. wd14 wd12 wd9 wd8 wd11 wd10 wd15 wd13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola c - 1 appendix c dsp56003 and dsp56005 differences ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . section contents c - 2 dsp56003 and dsp56005 differences motorola paragraph number page number section c.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3 c.2 differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3 c.3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-3 c.4 applications of the extra pins . . . . . . . . . . . . . . . . . . . . . . . c-10 c.5 (4.6) bus strobe and wait pins ?dsp56003 only . . . . . . . . . c-12 c.6 (4.7) bus arbitration and shared memory ?dsp56003 only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction motorola dsp56003 and dsp56005 differences c - 3 c.1 introduction this manual describes both the dsp56003 and the dsp56005. these dsps are basically identical; however, the dsp56003 is in a larger package with more pins than the dsp56005 and has several additional signals that are not available on the dsp56005. these addition- al pins are for bus arbitration, pll lock, and pll clock output polarity features. vertical bars in the margin throughout this manual have been used to flag portions of the text that describe these signals and apply only to the dsp56003. this appendix collects those sec- tions and describes the purpose of each feature. c.2 differences the additional dsp56003 features that differentiate it from the dsp56005 are: external memory bus arbitration signals - bus needed (bn ) - bus request (br ) - bus grant (bg ) - bus strobe (bs ) - bus wait (wt ) pll lock signal - phase and frequency locked (plock) pll clock output polarity signal - ckout polarity control (ckp) the dsp56003 is available in a 176 pin thin quad flat pack (tqfp), see table c-1 and table c-2. the dsp56005 is available in a 144 tqfp, see the dsp56003/dsp56005 data sheet for additional information. c.3 signal descriptions the pins are organized into the functional groups indicated in table c-1. some signals are discussed in the paragraphs that follow. c.3.1 (2.2.2.1) bus needed (bn ) ?active low output ?dsp56003 only the bn output pin is asserted whenever the chip requires the external memory expansion port (port a). during instruction cycles where the external bus is not required, bn is deas- serted. if an external device has requested the bus by asserting the br input and the dsp has granted the bus (by asserting bg ), the dsp will continue processing as long as no ex- ternal accesses are required. if an external access is required and the chip is not the bus master, it will stop processing and remain in wait states until bus ownership is returned. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions c - 4 dsp56003 and dsp56005 differences motorola if the bn pin is asserted when the chip is not the bus master, the chip? processing has stopped and the dsp is waiting to acquire bus ownership. an external arbiter may use this pin to help decide when to return bus ownership to the dsp. during hardware reset, bn is deasserted. note: the bn pin cannot be used as an early indication of imminent external bus access because it is valid later than the other bus control signal bs . c.3.2 (2.2.2.2) bus request (br ) ?active low input ?dsp56003 only the bus request br allows another device such as a processor or dma controller to be- come the master of the dsp external data bus d0-d23 and external address bus a0-a15. the dsp asserts bg after the br input is asserted. the dsp bus controller releases control of the external data bus d0-d23, address bus a0-a15 and bus control pins ps , ds , x/y , rd , and wr at the earliest time possible consistent with proper synchronization after the exe- cution of the current instruction has been completed. these pins are then placed in the high impedance state and the bg pin is asserted. the dsp continues executing instructions only figure c-1 (1-1) dsp56003/005 block diagram data 24 control 10=56003 5=56005 address 16 data alu 24 x 24 + 56 ? 56-bit mac two 56-bit accumulators pll clock gen. gdb pdb xdb ydb internal data bus switch external data bus switch bus control pab xab yab address generation unit external address bus switch y data memory irq 5 16-bit bus 24-bit bus 24-bit 56000 dsp core program address generator program decode controller interrupt control program control unit watch- dog timer 4 56003= 5 56005= 3 once ? 24-bit timer/ event counter pulse width modul. (5) sync. serial (ssi) or i/o serial comm. (sci) or i/o host interface (hi) or i/o 14 6 3 15 1 256 24 ram 256 24 rom (arc-tangent) x data memory 256 24 ram 256 24 rom (sine) program memory 4608 24 ram 96 24 rom (boot) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions motorola dsp56003 and dsp56005 differences c - 5 if internal program and data memory resources are accessed. if the dsp requests the exter- nal bus while br input pin is asserted, the dsp bus controller inserts wait states until the external bus becomes available (br and bg deasserted). when br is deasserted, the dsp will again assume bus mastership. br is an input during reset. notes: 1. interrupts are not serviced when a dsp instruction is waiting for the bus controller. 2. br is prevented from interrupting the execution of a read/modify/write instruction. 3. to prevent erroneous operation, the br pin should be pulled up when it is not in use. table c-1 (2-1) functional pin groupings functional group dsp56003 pins dsp56005 pins address bus 16 16 data bus 24 24 bus control 11 6 host interface (hi) 15 15 serial communications interface (sci) 3 3 synchronous serial interface (ssi) 6 6 timer/event counter 1 1 pulse width modulator a (pwma) 10 10 pulse width modulator b (pwmb) 4 4 on-chip emulation (once) port 4 4 power (v cc )1817 ground (gnd) 42 26 interrupt and mode control 6 6 phase-locked loop (pll) and clock 7 5 reserved 9 1 total number of pins 176 144 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions c - 6 dsp56003 and dsp56005 differences motorola figure c-2 (2-1) dsp56003/005 signals a0-a15 d0-d23 ds ps rd wr x/y br bg gndd v ccd gnda v cca gndc v ccc wt bs gndq v ccq extal xtal reset moda/irqa modb/irqb modc/nmi h0-h7 ha0-ha2 hr/w hen hreq hack gndh v cch rxd txd sclk v ccs gnds sc0-sc2 sck srd std dsck/os1 dsi/os0 dso dr interrupt/ mode control dsp56003/005 host serial synchronous pwap0 - pwap2 pwan0 - pwan2 ckout pulse width pwaclk pwac0 - pwac2 bn ckp v ccck gndck only tio timer/ event irqc irqd clock v ccp gndp pcap phase-locked plock pinit pwb0 , pwb1 pwbc pwbclk v ccw gndw counter oscillator extp modulator a (pwma0-2) pulse width modulator b (pwmb0-1) interface (hi) communication interface (sci) serial interface (ssi) loop (pll) on-chip emulator (once ) port dsp56003 dsp56003 only external bus control external address bus external data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions motorola dsp56003 and dsp56005 differences c - 7 c.3.3 (2.2.2.3) bus grant (bg ) ?active low output ?dsp56003 only this pin is asserted to acknowledge an external bus request. it indicates that the dsp has released control of the external address bus a0-a15, data bus d0-d23 and bus control pins ps , ds , x/y , extp , rd , and wr . the bg output is asserted in response to a br input. when the bg output is asserted, the external address bus a0-a15, data bus d0-d23 and bus con- trol pins are in the high impedance state. bg assertion may occur in the middle of an instruction which requires more than one external bus cycle for execution. note that bg as- sertion will not occur during indivisible read-modify-write instructions (bset, bclr, bchg). when br is deasserted, the bg output is deasserted and the dsp regains control of the external address bus, data bus, and bus control pins. this output is deasserted during hardware reset. c.3.4 (2.2.2.4) bus strobe (bs ) ?active low output ?dsp56003 only bus strobe is asserted at the start of a bus cycle and deasserted at the end of the bus cycle. this pin can be used as an ?arly bus start?signal by an address latch and as an ?arly table c-2 (2-3) power and ground pins function pin names dsp56003 dsp56005 v cc gnd v cc gnd v cc gnd address bus output buffer v cca gnda 3 5 3 5 data bus output buffer v ccd gndd 3 6 3 6 bus control v ccc gndc 1 1 1 1 host interface (hi) v cch gndh 2 4 2 4 port c (serial communications interface, synchronous serial interface) v ccs gnds 1 2 1 2 pulse width modulator (pwm) v ccw gndw 1 2 1 2 internal logic v ccq gndq 5 4 4 4 phase-locked loop (pll) v ccp gndp 1 1 1 1 clock v ccck gndck 1 1 1 1 thermal gnd 0 16 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions c - 8 dsp56003 and dsp56005 differences motorola bus end?signal by an external bus controller. it may also be used with the bus wait input, wt , to generate wait states, a feature which provides capabilities such as: connecting slower asynchronous devices to the dsp allowing devices with differing timing requirements to reside in the same memory space allowing a bus arbiter to provide a fast multiprocessor bus access providing an alternative to the wait and stop instructions to halt the dsp at a known program location and have a fast restart this output is deasserted during hardware reset. c.3.5 (2.2.2.5) bus wait (wt ) ?active low input ?dsp56003 only this input allows an external device to force the dsp to generate wait states for as long as wt is asserted. if wt is asserted while bs is asserted, wait states will be inserted into the current cycle. see the dsp56003/005 data sheet for timing details. c.3.6 (2.2.10.2) thermal ground (gnd) ?dsp56003 only these pins provide a thermal enhancement (i.e. a heat sink) to the chip. the pins should be di- rectly connected to the ground plane layer to help dissipate heat from the chip. this thermal connection is not necessary for operation. however, it will help keep the chip within the thermal specifications when thermal specification limits are otherwise being approached. c.3.7 (2.2.11.6) reset (reset ) ? input this input is a direct hardware reset of the processor. when reset is asserted, the dsp is ini- tialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the moda, modb, and modc pins. the chip also samples the pinit pin and writes its status into the pen bit of the pll control register. on the dsp56003 only , the dsp samples the ckp pin to determine the polarity of the ckout signal. when the chip comes out of the reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the reset signal. however, the probability that noise on reset will generate multiple resets increases with increasing rise time of the reset signal. c.3.8 (2.2.12.2) ckout polarity control (ckp) ? input ?dsp56003 only this input pin defines the polarity of the ckout clock output. strapping ckp through a resistor to gnd will make the ckout polarity the same as the extal polarity. strapping ckp through a resistor to v cc will make the ckout polarity the inverse of the extal po- larity. the ckout clock polarity is internally latched at the end of the hardware reset, so that any changes of the ckp pin logic state after deassertion of hardware reset will not affect the ckout clock polarity. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal descriptions motorola dsp56003 and dsp56005 differences c - 9 external address bus switch external address bus a0 - a15 x address (xa) y address (ya) program address (pa) 16 - bit internal address buses 16 external data b u s switch external data b u s d0 - d23 x data (xd) y data (yd) program data (pd) 24 - bit internal data buses 24 global data (gd) external bus control logic bus control signals rd ? read enable wr ?write enable ps ?program memory select ds ?data memory select x/y ?x memory/y memory select extp ?external peripheral memory strobe bn ? bus needed br ?bus request bg ?bus grant wt ?bus wait bs ?bus strobe figure c-3 (4-1) port a signals dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . applications of the extra pins c - 10 dsp56003 and dsp56005 differences motorola c.3.9 (2.2.12.7) phase and frequency locked (plock) ? output ?dsp56003 only this signal originates from the pll phase detector. the chip asserts plock when the pll is enabled and has locked on the proper phase and frequency of extal. plock is deasserted by the chip if the pll is enabled and has not locked on the proper phase and frequency. the processor is halted when plock is deasserted. plock is asserted if the pll is disabled. this signal is a reliable indicator of the pll lock state only after the chip has exited the hardware reset state. during hardware reset, the plock state is deter- mined by pinit and by the pll lock condition. c.4 applications of the extra pins the external memory bus arbitration signals are used to allow multiple devices to use the external memory bus without bus arbitration conflicts. c.4.1 bus control the bn signal allows the dsp to tell an external device that the dsp needs access to the external bus. when the dsp gains access, the bs signal tells external devices that the dsp is either about to use the bus or that it is using the bus. the (essentially) equivalent signals from the external viewpoint are br and bg . br is used by an external device to tell the dsp that the external device needs the bus. the bg signal tells the external device that the dsp has relinquished the bus and will wait to use the bus until after br becomes inactive. these four signals are useful in constructing: multiple dsp arrays mixed arrays of dsps and other processors shared memory systems using single port memory external memory mapped peripherals c.4.2 external memory interface wait states the dsp56003/005 features two methods to allow the user to accommodate slow mem- ory and slow peripherals by changing the port a bus timing. the first method uses the bus control register (bcr), see table c-3, which allows a fixed number of wait states to be inserted in a given memory access to all locations in each of the four memory spaces: x, y, p, and i/o. the second method uses the bus strobe (bs ) and bus wait (wt ) facility (dsp56003 only), which allows an external device to insert an arbitrary number of wait states (see table c-3) when accessing either a single location or multiple locations of external memory or i/o space. wait states are executed until the external device releases the dsp to finish the external memory cycle. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (4.6) bus strobe and wait pins ?dsp56003 only motorola dsp56003 and dsp56005 differences c - 11 c.4.3 pll and clock signal applications the pll locked signal indicates that the pll is in phase and on frequency (plock = 1) with the signal on extal or that the pll is adjusting its frequency (plock = 0). if the pll multiplier register (mf-mf11) has been changed, plock will be deasserted (plock = 0) and the clock will be cut off from the core processor until plock = 1. this provides an ex- ternal indicator that the multiplier was written and that the dsp core has paused until the pll is locked. the ckout polarity control allows the user to invert the clock out of the dsp without skewing it by the delay time of an inverter. the delay of an inverter can become critical when using fast static rams with access times of a few nano-seconds. c.5 (4.6) bus strobe and wait pins ?dsp56003 only the ability to insert wait states using bs and wt allows devices with differing timing requirements to reside in the same memory space, allows a bus arbiter to provide a fast mul- tiprocessor bus access, and provides another means of halting the dsp at a known program location with a fast restart. the timing of the bs and wt pins is illustrated in figure c-4. bs is asserted at the same time as the external address lines. bs can be used by external wait-state logic to estab- lish the start of an external access. bs is deasserted in t3 of each external bus cycle, sig- naling that the current bus cycle will complete. since the wt signal is internally synchronized, it can be asserted asynchronously with respect to the system clock. the wt signal should only be asserted while bs is asserted. asserting wt while bs is deas- serted will give indeterminate results. however, for the number of inserted wait states to be deterministic, wt timing must satisfy setup and hold timing with respect to the bcr contents wt (dsp56003 only) number of wait states generated 0 deasserted 0 0 asserted ?dsp56003 only 2 (minimum) > 0 deasserted equals value in bcr > 0 asserted ?dsp56003 only minimum equals 2 or value in bcr. maximum is determined by bcr or wt , whichever is larger. table c-3 (4-2) wait state control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (4.7) bus arbitration and shared memory ?dsp56003 only c - 12 dsp56003 and dsp56005 differences motorola negative-going edge of extal. the setup and hold times are provided in the dsp56003/005 data sheet . the timing of wr is controlled by the bcr and is indepen- dent of wt . the minimum number of wait states that can be inserted using the wt pin is two. the bcr is still operative when using bs and wt and defines the minimum number of wait states that are inserted. table c-3 summarizes the effect of the bcr and wt pin on the number of wait states generated. c.6 (4.7) bus arbitration and shared memory ?dsp56003 only the dsp56003 has five pins that control the external memory interface. they are bus needed (bn ), bus request (br ), bus grant (bg ), bus strobe (bs ) and bus wait (wt ) and they are described in section 2 ?dsp56003/005 pin descriptions. bus control t0 t1 t2 tw tw tw tw t3 t0 16 rd wr ps ds x/y extp wt bs 24 address bus a0 - a15 data b u s d0 - d23 dsp56003 t3 a0 - a15, d0 - d23, ps , ds , x/y , extp wt is sampled wt is sampled wt is sampled em sd 0 0 0 de mb ma 76 5 43210 set em = 1 operating mode register figure c-4 (4-10) bus strobe/wait sequence ?dsp56003 only dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (4.7) bus arbitration and shared memory ?dsp56003 only motorola dsp56003 and dsp56005 differences c - 13 the bus control signals provide the means to connect additional bus masters (which may be additional dsps, microprocessors, direct memory access (dma) controllers, etc.) to the external memory interface bus. they work together to arbitrate and deter- mine what device gets access to the bus. if an external device has requested the external bus by asserting the br input, and the dsp has granted the bus by asserting bg , the dsp will continue to process as long as it requires no external bus accesses itself. if the dsp does require an external access but is not the bus master, it will stop processing and remain in wait states until it regains bus ownership. the bn pin will be asserted, and an external device may use bn to help ?rbitrate? or decide when to return bus ownership to the chip. four examples of bus arbitration will be described later in this section: bus arbitration using only br and bg with internal control bus arbitration using bn , br , and bg with external control bus arbitration using br , bg and wt , bs with no overhead signaling using semaphores. the br input allows an external device to request and be given control of the external bus while the dsp continues internal operations using internal memory spaces. this indepen- dent operation allows a bus controller to arbitrate a multiple bus-master system indepen- dent of operation of each dsp. (a bus master can issue addresses on the bus; a bus slave can respond to addresses on the bus. a single device can be both a master and a slave, but can only be one or the other at any given time.) before br is asserted, all the external memory interface signals may be driven by the dsp. when br is asserted (see figure c-5), the dsp will assert bg after the current external access cycle completes and will simultaneously three-state (high-impedance) the external memory interface signals (see the dsp56003/005 data sheet for exact timing of br and bg ). the bus is then available to whatever external device has bus mastership. the external device will return bus mastership to the dsp by deasserting br . after the dsp completes the current cycle (an internally executed instruction with or without wait states), bg will be deasserted. when bg is deasserted, the a0-a15, ps , ds , x/y , extp , and rd , wr lines will be driven. however, the data lines will remain in three-state. all signals are now ready for a normal external access. during the wait state (see section 7 in the dsp56000 family manual ), the br and bg circuits remain active. however, the port is inactive - the control signals are deasserted, the data signals are inputs, and the address signals remain as the last address read or written. when br is asserted, all signals are three-stated (high impedance). table c-4 shows the status of br and bg during the wait state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (4.7) bus arbitration and shared memory ?dsp56003 only c - 14 dsp56003 and dsp56005 differences motorola c.6.1 (4.7.1) bus arbitration using only br and bg with internal control ? dsp56003 only perhaps the simplest example of a shared memory system using a dsp56003 is shown in figure c-6. the bus arbitration is performed within the dsp#2 by using software. dsp#2 controls all bus operations by using i/o pin out2 to three-state its own external mem- ory interface and by never accessing the external memory interface without first calling the subroutine that arbitrates the bus. when the dsp#2 needs to use external memory, it uses i/o pin out1 to request bus access and i/o pin in1 to read bus grant. dsp#1 does not need any extra code for bus arbitration since the br and bg hardware handles its bus arbitration automatically. the protocol for bus arbitration is as follows: at reset: dsp#2 sets out2=0 (br #2=0) and out1=1 (br #1=1), which gives dsp#1 access to the bus and suspends dsp#2 bus access. dsp56003/005 bus master a0 - a15, d0 - d23, ps , ds , x/y , rd , wr br bg a different bus master dsp56003/005 bus master figure c-5 (4-11) bus request/bus grant sequence ?dsp56003 only s i g n a l before br while bg after br after return to n o rm a l state after first table c-4 (4-3) br and bg during wait ?dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (4.7) bus arbitration and shared memory ?dsp56003 only motorola dsp56003 and dsp56005 differences c - 15 when dsp#2 wants control of the memory, the following steps are performed (see figure c-7): 1. dsp# 2 sets out1=0 (br #1=0). 2. dsp# 2 waits for in1=0 (bg #1=0 and dsp#1 off the bus). 3. dsp#2 sets out2=1 (br #2=1 to let dsp#2 control the bus). 4. dsp#2 accesses the bus for block transfers, etc. at full speed. 5. to release the bus, dsp#2 sets out2=0 (br #2=0) after the last external access. 6. dsp#2 then sets out1=1 (br #1=1) to return control of the bus to dsp#1. 7. dsp#1 then acknowledges mastership by deasserting bg #1. br bg control a0 - a15 d0 - d23 br out2 out1 in1 control a0 - a15 d0 - d23 cad memory bank dsp56003/005 #1 dsp56003/005 #2 bus arbiter figure c-6 (4-12) bus arbitration using only br and bg with internal control ? dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (4.7) bus arbitration and shared memory ?dsp56003 only c - 16 dsp56003 and dsp56005 differences motorola c.6.2 (4.7.2) bus arbitration using bn , br , and bg with external control ? dsp56003 only the system shown in figure c-8 can be implemented with external bus arbitration logic, which will save processing capacity on the dsps and can make bus access much faster at a cost of additional hardware. the bus arbitration logic takes control of the external bus by deasserting an enable signal (e1, e2, and e3) to all dsps, which will then acknowledge by granting the bus (bg =0). when a dsp (dsp#1 in figure c-8) needs the bus, it will enter the wait state with bn asserted. if dsp#1 has highest priority of the pending bus requests, the arbitration logic grants the bus to dsp#1 by asserting e1 (e2 for dsp#2; e3 for dsp#3) to let the dsp know that it can have the bus. dsp#1 will then deassert bg to tell the arbiter it has taken control of the bus. when the dsp no longer needs to make an external access it will deassert bn and the arbiter deasserts e1, after which the dsp deasserts bg . c.6.3 (4.7.3) arbitration using br and bg , and wt and bs with no overhead ?dsp56003 only by using the circuit shown in figure c-9, two dsps can share memory with hardware arbitration that requires no software on the part of the dsps. the protocol for bus arbi- tration in figure c-9 is as follows: at reset assume dsp#1 is not making external accesses so that br of dsp#2 is deas- serted. hence, bg of dsp#2 is deasserted, which three-states the buffers, giving dsp#2 control of the memory. data transferred out1 1234567 in1 out2 figure c-7 (4-13) two dsps with external bus arbitration timing here f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (4.7) bus arbitration and shared memory ?dsp56003 only motorola dsp56003 and dsp56005 differences c - 17 when dsp#1 wants control of the memory the following steps are performed (see figure c-10): 1. dsp#1 makes an external access, thereby asserting bs , which asserts wt (causing dsp#1 to execute wait states in the current cycle) and asserts dsp#2 br (requesting that dsp#2 release the bus). 2. when dsp#2 finishes its present bus cycle, it three-states its bus drivers and asserts bg . asserting bg enables the three-state buffers, placing the dsp#1 signals on the memory bus. asserting bg also deasserts wt , which allows dsp#1 to finish its bus cycle. 3. when dsp#1? memory cycle is complete, it releases bs , which deasserts br . dsp#2 then deasserts bg , three-stating the buffers and allowing dsp#2 to access the memory bus. 16 system memory 32k x 24 x data ram 32k x 24 y data ram 32k x 24 program ram address data control address data control 24 5 adc adc adc dsp56003 #1 dsp56003 #2 dsp56003 #3 bg br bn bg br bn bg br bn bus arbitration logic with priority encoder a1 e1 br1 a2 e2 br2 a3 e3 br3 figure c-8 (4-14) bus arbitration using bn, br, and bg with external control ? dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (4.7) bus arbitration and shared memory ?dsp56003 only c - 18 dsp56003 and dsp56005 differences motorola memory dac dsp #1 d0 - d23 a0 - a15 rd , wr , ds , ps , x/ y bs wt three-state buffer dir enable dsp #2 d0 - 23 a0 - a15 rd , wr , ds , ps , x/y bg br figure c-9 (4-15) bus arbitration using br and bg, and wt and bs with no overhead ?dsp56003 only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (4.7) bus arbitration and shared memory ?dsp56003 only motorola dsp56003 and dsp56005 differences c - 19 bs wt br bg 12 3 figure c-10 (4-16) two dsps with external bus arbitration timing ?dsp56003 only data transferred between dsp#1 and memory here f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ? motorola inc., 1995 motorola technical data semiconductor this document, containing changes, additional features, further explanations, and clarifications, is a supplement to the original document: change the following: page 5-19, figure 5-11 - replace ?:ffe?in two places with ?:$ffe8?on top and ?:ffe9?on bottom. page 6-26, program listing - move: ?ove (r0)+ ;and increment the packing pointer? to after the jcs instruction. replace ?ti? with ?ti x: replace ?lag move a,(r3)+ with ?lag move a,x:(r3)+ page 6-66, section 6.3.9, third sentence - replace ?its cd11?d0, scp, and stir in the sccr work together to determine the time base.?with ?its cd11?d0 and scp in the sccr and the stir bit in the scr work together to determine the time base. page 7-159, section 7.3.7.2, second paragraph - replace ?c15500?with ?c145500? page 7-62, figure 7-38 - replace ?c1550x?with ?c14550x? page 7-87, figure 7-54 - replace ?c15500?with ?c145500? page b-26, figure b-32 - change crb bits 2-4 description (see figure b-32 below). dsp56003um/ad user s manual dsp56003/005 24-bit digital signal processor addendum to 24-bit digital signal processor user? manual dsp56003/005 order this document by dsp56003umad/ad f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2 dsp56002 user s manual addendum motorola ssi ssi control register b (crb) x:$ffed read/write reset = $000000 1514131211109876543210 sync/async control 0 = asynchronous 1 = synchronous frame sync length 1 0 = rx is word length 1 = rx is bit length frame sync length 0 0 = rx and tx same length 1 = rx and tx different length ssi mode select 0 = normal 1 = network transmit enable 0 = disable 1 = enable receive interrupt enable 0 = disable 1 = enable receive enable 0 = disable 1 = enable transmit interrupt enable 0 = disable 1 = enable gated clock control 0 = continuous clock 1 = gated clock output flag x if syn = 1 and scd1=1 ofx scx pin 23 * 0 * = reserved, program as zero figure b-32 ssi control register b (crb) shift direction 0 = msb first 1 = lsb first clock source direction 0 = external clock 1 = internal clock rie tie re te mod gck syn fsl1 fsl0 shfdsckdscd2 scd1scd0 of1 of0 serial control direction bits 0 = input 1 = output f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56002 user s manual addendum 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . literature distribution centers: usa: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature centre; 88 tanners drive, blakelands, milton keynes, mk14 5bp, united kingdom. japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbor center, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, repre- sentation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limi- tation consequential or incidental damages. ?ypical?parameters can and do vary in different applications. all operating param- eters, including ?ypical? must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and b are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. once is a trademark of motorola, inc. all product and brand names appearing herein are trademarks or registered trademarks of their respective holders. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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