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apci-adadio 2192-09125-000-000 j605 apci-adadio page 1 introduction the apci-adadio is a 32-bit pci local bus board which provides 8 differential (apci-adadiocd) or 16 single-ended (APCI-ADADIOCS) multiplexed analogue inputs, two analogue outputs, 16 digital i/o lines and three counter/timer channels. all i/o signals are routed to a 50 way d-type socket which conforms to arcoms standard signal conditioning system (scs). features ? 8 differential or 16 single ended, multiplexed 12-bit adc channels. C 10khz channel-to-channel acquisition rate. C 100khz repeat rate. C 10us typical conversion rate. C +/- 5v, +/-10v,0-5v,0-10v selectable input ranges. ? two 12-bit(+/-1 bit accuracy) analogue output channels. C +/- 5v, +/-10v,0-5v,0-10v selectable input ranges. C 10us settling time to 12-bit accuracy. ? 16 ttl nibble-configurable i/o lines. C output 24ma at 0.45v, sources from 1k resistor at +5v. C selectable power-up states. ? 8254-compatible 3-channel counter/timer. C 1 adc timer, 1 interrupt timer, 1 general purpose timer. C 1mhz master operating frequency. ? i/o connector conforms to arcoms signal conditioning system (scs). ? board access led (red). ? user led (green). ? 32-bit pci 2.1 compatible bus interface. ? plug and play software compatible. ? ce compliant design. ? operating temperature range, 0c to 70c. ? power consumption 180ma @ +5v, 280ma @ +12v. ? mtbf: 220,426 hours (using generic figures from mil-hdbk-217f at ground benign). getting started ? power down your pc system. ? install the board in a spare pci slot (see installation for ce compliance). ? power up system with msdos. ? run apci.exe (supplied on the utility disk), this will search for the board and check i/o access. if this fails, check board is correctly located. warning this board contains c c m m o o s s devices which may be damaged by static electricity. please ensure anti- static precautions are taken at all times when handling this board. if for any reason this board is returned to arcom control systems, please ensure it is adequately packed, to prevent damage occurring during shipment.
page 2 oper ation pci bus interface the pci bus is a high speed alternative to i sa bus, it has been designed to o ver come some of the limitations of i sa bus, and pro vide faster throughput for i/o intensive peripher al devices. pci bus also supports plug and play configur ation which allo ws the system softwar e to allocate r esour ces during initialisation helping to o ver come addr ess conflicts, which might exist in a system. the apci-ad adio uses a single chip pci bus slave controller which is designed and manufactur ed b y pl x t echnology. this device has been designed to fully support the pci 2.1 specification and pro vides plug and play softwar e capabilities. during po wer-up initialisation the pci b ios will detect the car d and assign a unique i/o addr ess location and interrupt line. this ensur es that ther e ar e no r esour ce conflicts on the pci bus. multiple car ds ar e supported through this mechanism without the need for addr ess decode links. the pl x device contains a standar d type 00h configur ation space header. the table belo w sho ws the r egisters within this header which ar e r equir ed for configur ation of the apci-ad adio. configuration space header these r egisters can be accessed using pci b ios function calls. i/o map the apci-ad adio uses an indexed addr essing scheme to access the on-boar d devices and special function r egisters. t wo consecutive i/o locations ar e r equir ed to implement this scheme, the ba s e addr ess is used to set the index value and the ba s e+1 addr ess is used to access the device. adc and d a c data is accessed via a dedicated pair of r egisters which ar e not part of the indexing scheme. the i/o base addr ess is set b y the pci b ios during initialisation (r efer to the pci bus section of this manual for details). a pci b ios function call may be used to determine the base addr ess once the system has been initialised. multiple boar ds may be used in a system as each will be given a unique i/o base addr ess. 2192-09125-000-000 j605 apci-adadio o o f f f f s s e e t t 00-01h 02-03h 18-1b h 2c-2dh 2e-2f h 3ch r r e e g g i i s s t t e e r r n n a a m m e e v endor i d device i d base addr ess r egister subsystem v endor i d subsystem i d interrupt line d d e e s s c c r r i i p p t t i i o o n n i d of pci device manufactur er i d of pci device i/o base addr ess assigned to car d i d of boar d manufactur er i d of boar d interrupt line assigned to device v v a a l l u u e e 10b5h (pl x t echnology) 9050h 0000xxxx 13ab h (a r c o m) 0605h (apci-ad adio) 0x i/o address base base+1 base+2 base+3 function index r egister control/s tatus adc/d a c lsb data adc/d a c msb data read/write w rite r ead/w rite r ead/w rite r ead/w rite
page 3 2192-09125-000-000 j605 apci-adadio index r egisters s pecial f unction r egisters index 00 00 00 00 01 02 02 03 03 04 05 06 07 08 09 0a 0b 0c-7f index 80 81 register name s tatus adc s tart conversion adc data 0-3 adc data 4-11 multiplexer channel select d a c a r egister bit 0-3 d a c a r egister bit 4-11 d a cb r egister bit 0-3 d a cb r egister bit 4-11 counter/t imer channel 0 counter/t imer channel 1 counter/t imer channel 2 counter/t imer control clear counter/t imer interrupt digital i/o configur ation digital i/o 0-7 digital i/o 8-15 not used register name user l e d boar d i d read/write r ead base +1 w rite base +1 r ead base +2 r ead base +3 w rite base +1 w rite base +2 w rite base +3 w rite base +2 w rite base +3 r ead/w rite base +1 r ead/w rite base +1 r ead/w rite base +1 w rite base +1 w rite base +1 w rite base +1 r ead/w rite base +1 r ead/w rite base +1 n/a read/write w rite base +1 r ead base +1 bit function bit 0 adc r eady 0 = conversion completed since last r ead of adc data high b yte bit 1 counter/t imer r eady 0 = out1 has tr ansitioned lo w- high since clear ct c r eady was last accessed bit 0-7 any data starts conversion bit 0-3 adc 0-3 data bit 0-7 adc 4-11 data bit 0-3 mux channel addr ess bit 4-7 d a c a 0-3 lo w data bit 0-7 d a c a 4-11 high data bit 4-7 d a cb 0-3 lo w data bit 0-7 d a cb 4-11 high data counter 0 v alue counter 1 v alue counter 2 v alue control any data clears interrupt and sets status to 1 bit 0-3 0 = nibble output 1 = nibble input bit 0-7 0 = input l o w 1 = input high bit 0-7 0 = input l o w 1 = input high n/a bit function bit 0 0 = l e d off 1 = l e d on always r eturns 2dh
interrupts the apci-ad adio has one interrupt output signal which is routed to an i r q line during the pci b ios initialisation. this interrupt line is expanded on boar d to pro vide two interrupt sour ces. one of these interrupts is connected to the adc conversion complete signal and the other is connected to the output of counter/timer channel 1. if a counter/timer interrupt is gener ated a write sequence to index r egister 8 must be executed in or der to clear the pending interrupt. the adc interrupt is clear ed when the high b yte data is accessed. a pci b ios call can be used to determine the i r q signal assigned to this boar d. analogue to digital conv er tor the apci-ad adio contains a single 12-bit successive appro ximation analogue to digital convertor. the input to this device is connected to a 8 way (apci-ad adiocd) or 16 way multiplexer (apci- ad adiocs). p rior to an ad conversion the appropriate channel can be selected b y writing to the multiplexer channel select r egister (index 1). the adc may be trigger ed from thr ee differ ent sour ces, selected b y links lk9-11. only one of these links should be fitted at any time to ensur e corr ect oper ation. the thr ee sour ces ar e:- 1. softwar e trigger , initiated b y an i/o write sequence. 2. har dwar e trigger from an external tt l input (/r c onv ), appro ximately 1-2 us lo w pulse. 3. p eriodic timer , progr ammed from the on-boar d counter/timer channel 0. the follo wing sequence can be used to perform an a/d conversion when using the softwar e trigger mode. 1. w rite 01h to the ba s e addr ess. 2. w rite to ba s e+1 with the multiplexer value for the appropriate channel. 3. w ait for appro ximately 50usec for the input to settle. 4. w rite 00h to the ba s e addr ess. 5. w rite to ba s e+1 (any value) to start conversion. 6. w ait for appro ximately 20usec for the conversion to complete. 7. r ead ba s e+1 and check bit 0 is at logic ?0? i.e. conversion completed. 8. r ead ba s e+2 adc data lo w nibble (bits 0-3). 9. r ead ba s e+3 adc data high b yte (bits 4-11). the har dwar e trigger mode uses /r c onv on pl1 and the periodic timer mode uses counter/timer channel 0 output to trigger the adc. conversion is initiated from these sour ces when /r c onv or out0 ar e lo w. t o ensur e that the adc does not perform multiple conversions the har dwar e and timer pulses must be gr eater than 250ns and less than 6us. maximum data throughput can be obtained b y triggering a new conversion befor e data has been r ead from the last conversion. t o ensur e that the adc data r egisters contain the data from the last conversion they must be r ead within 6us of triggering a new conversion. digital to analogue conv er tor the apci-ad adio contains two 12-bit digital to analogue convertors. on-boar d links can be used to select between thr ee possible output r anges +/- 5v , 0-5v and 0-10v . the d a c values ar e updated b y page 4 2192-09125-000-000 j605 apci-adadio
writing to the data r egister at ba s e+2 (l o w nibble bits 0-3) and ba s e + 3 (high b yte bits 4-11). p rior to this the d a c channel must be selected b y writing a value of 02h to the index r egister for d a c a and 03h for d a c b. digital i/o the apci-ad adio pro vides 16 digital i/o lines, these ar e grouped into four nibbles. each nibble has a po wer-up/r eset state link and can be progr ammed as either input or output via the digital i/o configur ation r egister. access to the individual i/o lines is via index r egisters 0ah and 0b h. r eading these r egisters will pro vide the status of all i/o lines r egar dless of whether they ar e configur ed as input or output. it is possible to use these lines as bi-dir ectional with some car eful progr amming ensuring that a conflict does not exist on any of these lines. note: - if a nibble is to be used as an input the r eset state link must be set to the high position, otherwise the lines will be driven lo w as outputs which may cause damage. counter/t imer the apci-ad adio contains an 8254 compatible counter/timer , which pro vides thr ee 16-bit counter/timers. channel 0 can be used to trigger an a/d conversion and channel 1 can cause an interrupt r equest sequence to be initiated. a external connector (pl3) has been pro vided to allo w internal or external signals to be used as clock sour ces. the connector has been arr anged to allo w the on-boar d 1mhz clock to be connected to the clock input on channel 1 and 2 via links. the outputs of these timers can also be cascaded to pro vide longer timing sequences. counter 0 should always be progr ammed in mode 2 which ensur es that the output signal is only active for a single clock cycle (i.e. 1us when connected to the 1m hz clock). when the output from counter 2 is used as the clock sour ce the time between rising edges must not exceed 6 us or be less than 250ns. links throughout this section a ?+? indicates the default link position. default link p osition diagr am page 5 2192-09125-000-000 j605 apci-adadio
2192-09125-000-000 page 6 j605 apci-adadio lk1: psedo differential ground connection lk3: differential/single-ended input selection lk5-6: dac output range lk5 and lk6 ar e used to select the output r ange for d a c1 and d a c0 r espectively. the r ange settings ar e as belo w: lk7-8 and lk18 adc input ranges these links ar e used to select the adc input r ange. the r ange settings ar e as belo w: note: - both links should not be fitted in position b on lk7 and lk8. lk9-11 adc trigger sources these links ar e used to select between the thr ee differ ent adc trigger sour ces. each trigger sour ce is enabled when the link is fitted. t o ensur e corr ect oper ation only one link should be fitted. lk12-15 digital i/o reset state these links select the state of the digital i/o lines at r eset in nibble (4 bit) groups. the link associated with each nibble is sho wn belo w: lk15 digital i/o lines 0-3 lk14 digital i/o lines 4-7 lk13 digital i/o lines 8-11 lk12 digital i/o lines 12-15 note: if a nibble is to be used as an input the corr esponding link should be placed in position b to ensur e damage is not caused to the car d or external cir cuitry. lk16 counter/timer channel 0 clock source this link selects the clock sour ce for counter timer channel 0. fit omit apci-ad adiocs, fit only if inputs ar e isolated from 0v a apci-ad adiocd, differ ential inputs a b differ ential - apci-ad adiocd single ended - apci-ad adiocs +lk9 lk10 lk11 enable softwar e trigger enable har dwar e trigger enable counter/timer channel 0 trigger +a b none -5v to +5v 0v to +5v 0v to +10v a +b sets output lo w sets output high lk16a +lk16b clocked b y output from counter/timer channel 2 1m h z clock lk7 +a a b a lk8 lk18 r ange +a +omit -5v to +5v b a b omit omit fit 0v to +10v -10v to +10v 0v to +5v
page 7 2192-09125-000-000 j605 apci-adadio lk17 digital i/o reset test link used for automated boar d testing of the digital i/o lines , to ensur e they r eset into the corr ect states and should be left in position a. user configur ation r ecor d diagr am pseduo differ ential ground differ ential/single ended input d a c output r ange adc input r anges adc t rigger sour ces digital i/o r eset s tate counter/t imer channel 0 clock sour ce digital i/o r eset t est link lk1 lk3 lk5 lk6 lk7 lk8 lk18 lk9 lk10 lk11 lk12 lk13 lk14 lk15 lk16 lk17
2192-09125-000-000 page 8 j605 apci-adadio utility disk a demonstr ation progr am has been pro vided on the utility disk ad adio.e x e. this can be used to aid calibr ation and as sour ce code is pro vided it will help demonstr ate the method used for accessing devices. adadio.exe this progr am will display the adc inputs, scroll an active bit along the digital i/o and allo ws setting of the d a c?s. these will work with standar d link settings. decr ementing counter/timer counts and incr ementing interrupt counts ar e also displayed, but a link must be fitted between pins 9 and 10 on pl3. adadio.ini this is a text file which is used b y the ad adio progr am to select the number of channels, adc and d a c r anges etc. this file can be edited to r eflect any changes in the boar d settings. calibr ation calibr ating the adc in or der to calibr ate the adc it is necessary to use a pr ecision digital voltmeter (d vm) with at least 5 digit r esolution and a high stability lo w noise dc signal sour ce. during calibr ation it is necessary to continually r ead and display the adc data. a progr am ad adio.e x e has been pro vided on the utility disk to enable this. t wo trim adjusters, vr7 and vr1 , ar e pro vided for trimming the zero offset and gain r espectively. these trims ar e for fine-adjusting the standar d r anges. unipolar calibr ation set the necessary links for unipolar oper ation and the r equir ed voltage r ange. r un the ad adio.e x e progr am. zero offset adjust 1) set the input voltage to 0.0000v . 2) adjust vr7 to give 000 to 001 hex. full scale gain adjust 1) set the input voltage to full scale minus 1 lsb +4.9985 for the 5v r ange. +9.9975 for the 10v r ange. 2)adjust vr1 to give f f e to f f f . bipolar calibr ation set the necessary links for bipolar oper ation and the r equir ed voltage r ange. r un the ad adio.e x e progr am. bipolar offset adjust 1) set the input voltage to full scale negative plus 1 lsb -4.9975 for the 5v r ange. -9.9950 for the 10v r ange. 2) adjust vr7 to give 000 to 001 hex.
page 9 2192-09125-000-000 j605 apci-adadio full scale gain adjust 1) set the input voltage to full scale positive minus 1 lsb +4.9975 for the 5v r ange. +9.9950 for the 10v r ange. 2) adjust vr1 to give f f e to f f f . calibr ating the d a cs in or der to calibr ate the d a cs it is necessary to have a d vm with at least 5 digit r esolution. on the utility disk ther e is a a single trimmer (vr2) is pro vided to adjust the r efer ence voltage used b y the d a cs set the necessary links for the r equir ed mode and voltage r anges. r un the ad adio.e x e progr am . measur e the voltage between vr e f (tp3) and a g n d (tp9)and adjust vr2 until the r eading is +5.02v . note: - if the gain adjust trimmers (vr3-4) have insufficient r ange , adjust vr2 to r ead 5.01v , and r epeat the calibr ation procedur e. unipolar calibr ation - d a c channel a zero offset adjust 1) set d a c a output to 000 hex. 2) measur e the voltage between d a c a output and analogue ground and adjust vr5 to give 0.000v . full scale gain adjust 1) set d a c a output to 800 hex, 2) measur e the voltage between d a c a output and analogue ground and adjust vr3 to exactly half scale output. 2.500v for the 0-5v r ange. 5.000v for the 0-10v r ange. 3) set d a c a output to f f f hex and check output voltage is:- 4.9985 for the 0-5v r ange. 9.9975 for the 0-10v r ange. 4) adjust vr3 if necessary. r epeat for d a c b r eplacing vr5 with vr6, and vr3 with vr4. bipolar calibr ation - d a c channel a zero offset adjust 1) set d a c a output to 000 hex. 2) measur e the voltage between d a c a output and analogue ground and adjust vr5 to give full scale negative i.e -5.000v . full scale gain adjust 1) set the d a c a output to 800 hex. 2) measur e the voltage between d a c a output and analogue ground and adjust vr3 to give half scale output i.e 0.000v . 3) set d a c a to f f f hex and check full scale is 4.9975v . r epeat for d a c channel b r eplacing vr5 with vr6, and vr3 with vr4.
2192-09125-000-000 page 10 j605 apci-adadio test point locations trimmer locations test point location diagram trimmer location diagram t est p oint tp2 tp3 tp5 tp6 tp7 tp8 tp9 tp10 tp11 tp13 description d a c +5v v oltage r efer ence. +5v analogue supply voltage. +15v analogue supply voltage. -15v analogue supply voltage. adc chip enable signal. adc s tatus signal. analogue ground. digital ground. active lo w r eset signal. +5v digital supply. t rimmer vr1 vr2 vr3 vr4 vr5 vr6 vr7 f unction adc g ain d a c r efer ence v oltage d a c channel a g ain d a c channel b g ain d a c channel a zero offset d a c channel b zero offset adc zero offset
page 11 2192-09125-000-000 j605 apci-adadio d-50 i/o connector (p l1) pin assignments the pin assignments ar e listed with the pin number of the d-50 connector and also the pin number when a 50-way i dc ribbon cable is connected to the d-50. the pin assignments conform to the ar com signal conditioning system (scs) and may be connected to an external signal conditioning boar d. 1 0-way idc header (p l3) pl3 is used for connecting external signals to buffer ed versions of the counter/timer inputs and outputs for channels 1 and 2. f or maximum flexibility the connections have been arr anged to allo w clock inputs to be linked to the standar d 1m hz clock or other channel outputs using jumper links. ribbon cable pin no . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 d-t ype pin no . 1 34 18 2 35 19 3 36 20 4 37 21 5 38 22 6 39 23 7 40 24 8 41 25 9 signal name a n a l o g ue g r ou n d pdi f f ch0+ ch0-/ch8+ ch1+ ch1-/ch9+ ch2+ ch2-/ch10+ ch3+ ch3-/ch11+ a n a l o g ue g r ou n d pdi f f ch4+ ch4-/ch12+ ch5+ ch5-/ch13+ ch6+ ch6-/ch14+ ch7+ ch7-/ch15+ g n d pdi f f dig it a l i/o 0 dig it a l i/o 1 dig it a l i/o 2 ribbon cable pin no . 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 d-t ype pin no . 42 26 10 43 27 11 44 28 12 45 29 13 46 30 14 47 31 15 48 32 16 49 33 17 50 signal name dig it a l i/o 3 dig it a l i/o 4 dig it a l i/o 5 dig it a l i/o 6 dig it a l i/o 7 g n d /r c onv dig it a l i/o 8 dig it a l i/o 9 dig it a l i/o 10 dig it a l i/o 11 dig it a l i/o 12 dig it a l i/o 13 dig it a l i/o 14 dig it a l i/o 15 a n a l o g ue g r ou n d r e s e r ve d d a c a d a cb n/c n/c -12v +12v +5v +5v pin no . 1 3 5 7 9 signal name g n d clk2 out1 g a t e1 clk1m pin no . 2 4 6 8 10 signal name +5v clk1m g a t e2 out2 clk1
2192-09125-000-000 page 12 j605 apci-adadio installation for ce compliance t o maintain compliance with the r equir ements of the e mc dir ective (89/336/e ec), this product must be corr ectly installed. the pc system in which the boar d is housed must be ce compliant as declar ed b y the manufactur er. the external i/o cable should be the ar com c ab50ce, or a fully scr eened cable to the same pattern. 1. r emo ve the co ver of the pc observing any additional instructions of the pc manufactur er. 2. l ocate the boar d in a spar e pci slot and pr ess gently but firmly into place. 3. ensur e that the metal br acket attached to the boar d is fully seated. 4. fit the br acket clamping scr ew and firmly tighten this on the br acket. note:- good contact of the br acket to the chassis is essential. 5. r eplace the co ver of the pc observing any additional instructions of the pc manufactur er. the follo wing standar ds have been applied to this product: bs e n50081-1 : 1992 generic emissions s tandar d, r esidential, commer cial, light industry bs e n50082-1 : 1992 generic immunity s tandar d, r esidential, commer cial, light industry bs e n55022 : 1995 it e emissions, class b, limits and methods.
page 13 2192-09125-000-000 j605 apci-adadio r evision histor y manual issue a v1 iss 1 980512 first r eleased in this format. pcb comments
2192-09125-000-000 page 14 j605 apci-adadio product information f ull information about other ar com products is available via the f f a a x x - - o o n n - - d d e e m m a a n n d d s s y y s s t t e e m m , (t elephone numbers ar e listed belo w), or b y contacting our w w e e b b s s i i t t e e in the u k at: w w w w w w . . a a r r c c o o m m . . c c o o . . u u k k or in the u s at: w w w w w w . . a a r r c c o o m m c c o o n n t t r r o o l l s s . . c c o o m m u u s s e e f f u u l l c c o o n n t t a a c c t t i i n n f f o o r r m m a a t t i i o o n n c c u u s s t t o o m m e e r r s s u u p p p p o o r r t t s s a a l l e e s s t el: +44 (0)1223 412 428 t el: +44 (0)1223 411 200 f ax: +44 (0)1223 403 400 f ax: +44 (0)1223 410 457 e-mail: support@ar com.co .uk e-mail sales@ar com.co .uk or for the us e-mail icpsales@ar comcontrols.com u u n n i i t t e e d d k k i i n n g g d d o o m m arcom control systems ltd clifton road cambridge cb1 4wh, uk tel: 01223 411 200 fax:: 01223 410 457 fod: 01223 240 600 u u n n i i t t e e d d s s t t a a t t e e s s arcom control systems inc 13510 south oak street kansas city mo 64145 usa tel: 816 941 7025 fax:: 816 941 0343 fod: 800 747 1097 f f r r a a n n c c e e arcom control systems centre d?affaires scaldy 23 rue colbert 7885 saint quentin cedex, france tel: 0800 90 84 06 fax: 0800 90 84 12 fod: 0800 90 23 80 g g e e r r m m a a n n y y kostenlose infoline: tel: 0130 824 511 fax: 0130 824 512 fod: 0130 860 449 i i t t a a l l y y numeroverde: fod: 1678 73600 b b e e l l g g i i u u m m groen nummer: tel: 0800 7 3192 fax:: 0800 7 3191 n n e e t t h h e e r r l l a a n n d d s s gratis 0800 nummer: tel: 0800 022 11 36 fax:: 0800 022 11 48 the choice of boards or systems is the responsibility of the buyer, and the use to which they are put cannot be the liability o f arcom control systems ltd. however, arcom?s sales team is always available to assist you in making your decision. arcom control systems ltd operate a company-wide quality management system which has been certified by the british standards institution (bsi) as compliant with iso9001:1994 ? 1997 arcom control systems ltd arcom control systems is a subsidiary of fairey group plc. specifications are subject to change without notice and do not form part of any contract. all trademarks recognised.

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