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advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface features n selectable microprocessor or direct logic control modes. n quad t1/e1 line interface. n hardware and software reset options. n 3-state outputs. n 0.35 m cmos technology. n compliant with: at & t cb119 (10/79) bellcore tr-54016 (89) tr-tsy-000170 (10/97) tr-tsy-000009 (5/86) gr-499-core (12/95) gr-253-core (12/95) ansi t1.102 (93) t1.231 (93) t1.403 (95) itu-t g.703 (88) g.704 (91) g.706 (91) g.732 (88) g.735-9 (88) g.775 (11/94) g.823-4 (3/93) g.826 (11/93) i.431 (3/93) etsi tbr 12 (12/93) tbr 13 (1/96) n C40 c to +85 c operating temperature range. n fine-pitch (12.5 mil) surface-mount package, 144-pin tqfp. n transmitter includes transmit encoder (b8zs or hdb3), pulse shaping, and line driver. n five pulse equalization settings for template com- pliance at dsx cross connect. n receive includes equalization, digital clock and data recovery (immune to false lock), and receive decoder (b8zs or hdb3). n cept/e1 interference immunity as required by g.703. n transmit jitter <0.02 ui. n receive generated jitter <0.05 ui. n jitter attenuator selectable for use in transmit or receive path. jitter attenuation characteristics are data pattern independent. n for use with 100 w ds1 twisted-pair, 120 w e1 twisted-pair, and 75 w e1 coaxial cable. n common part available for transmit/receive transformers. n analog los alarm for signals less than C18 db for greater than 1 ms or 10 bit symbol periods to 255 bit symbol periods (selectable). n digital los alarm for 100 zeros (ds1) or 255 zeros (cept). n diagnostic loopback modes. n low power consumption. applications n t1/e1 network performance monitoring n sonet/sdh multiplexers n asynchronous multiplexers (m13) n digital access cross connects (dacs) n channel banks n digital radio base stations, remote wireless mod- ules n pbx interface
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 2 lucent technologies inc. table of contents contents page features ....................................................................................................................... ........................................... 1 applications ................................................................................................................... .......................................... 1 description.................................................................................................................... ........................................... 8 microprocessor mode ............................................................................................................ .................................. 8 overview ....................................................................................................................... ....................................... 8 pin information ................................................................................................................ ..................................... 9 system interface pin options................................................................................................... .......................... 14 microprocessor configuration modes............................................................................................. .................... 14 microprocessor interface pinout definitions.................................................................................... ................... 15 microprocessor clock (mpclk) specifications.................................................................................... .............. 16 internal chip select function .................................................................................................. ........................... 16 microprocessor interface register architecture ................................................................................. ................ 17 block diagrams ................................................................................................................. ................................. 18 data recovery.................................................................................................................. .................................. 20 jitter accommodation and jitter transfer without the jitter attenuator ......................................................... .... 20 receiver configuration modes ................................................................................................... ........................ 20 clock/data recovery mode (cdr) ................................................................................................. ................ 20 zero substitution decoding (code) .............................................................................................. ................. 20 alternate logic mode (alm) ..................................................................................................... ...................... 21 alternate clock mode (acm) ..................................................................................................... ..................... 21 rliu alarms.................................................................................................................... ................................ 21 ds1 receiver specifications .................................................................................................... .......................... 23 frequency response curves ...................................................................................................... ................... 24 cept receiver specifications ................................................................................................... ........................ 26 frequency response curves ...................................................................................................... ................... 27 output pulse generation........................................................................................................ ............................ 29 jitter......................................................................................................................... ........................................... 29 zero substitution encoding (code) .............................................................................................. .................... 30 alarm indication signal generator (xais) ....................................................................................... ............... 30 transmitter alarms ............................................................................................................. ................................ 30 loss of transmit clock (lotc) alarm ............................................................................................ ................ 30 transmit driver monitor (tdm) alarm ............................................................................................ ................. 30 ds1 transmitter pulse template and specifications .............................................................................. ........... 31 cept transmitter pulse template and specifications ............................................................................. ......... 33 jitter attenuator .............................................................................................................. .................................... 34 generated (intrinsic) jitter ................................................................................................... ........................... 34 jitter transfer function ....................................................................................................... ............................ 35 jitter accommodation ........................................................................................................... .......................... 35 jitter attenuator enable ....................................................................................................... ........................... 36 jitter attenuator receive path enable (jar) .................................................................................... .............. 36 jitter attenuator transmit path enable (jat) ................................................................................... .............. 36 frequency response curves ...................................................................................................... ................... 37 loopbacks ...................................................................................................................... .................................... 41 full local loopback (flloop) ................................................................................................... ................... 41 remote loopback (rloop) ........................................................................................................ ................... 41 digital local loopback (dlloop) ................................................................................................ .................. 41 powerdown (pwrdn).............................................................................................................. .......................... 42 reset ( reset , swreset) ..................................................................................................................... ........... 42
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 3 lucent technologies inc. table of contents (continued) contents page loss of xclk reference clock (loxc)............................................................................................ ................. 42 in-circuit testing and driver high-impedance state (ict )................................................................................. 42 liu delay values............................................................................................................... ................................. 42 line encoding/decoding ......................................................................................................... ........................... 43 alternate mark inversion (ami) ................................................................................................. ...................... 43 t1-binary 8 zero code suppression (b8zs) ....................................................................................... ........... 43 high-density bipolar of order 3 (hdb3) ......................................................................................... ................ 43 registers ...................................................................................................................... ...................................... 44 alarm registers (0000, 0001) ................................................................................................... ...................... 44 alarm mask registers (0010, 0011).............................................................................................. .................. 45 global control registers (0100, 0101).......................................................................................... .................. 45 channel configuration and control registers (01101001, 1011, 1100)...................................................... 46 xclk reference clock ........................................................................................................... ........................... 48 16x xclk reference clock ....................................................................................................... ..................... 48 primary line rate xclk reference clock and internal reference clock synthesizer .................................. 49 power supply bypassing......................................................................................................... ........................... 49 line circuitry ................................................................................................................. ..................................... 50 absolute maximum ratings....................................................................................................... ......................... 51 handling precautions ........................................................................................................... .............................. 51 operating conditions........................................................................................................... ............................... 51 power requirements............................................................................................................. ............................. 52 electrical characteristics ..................................................................................................... ............................... 52 microprocessor interface timing ................................................................................................ ........................ 53 data interface timing .......................................................................................................... ............................... 59 direct logic control mode ...................................................................................................... ............................... 60 overview ....................................................................................................................... ..................................... 60 device overview ................................................................................................................ ................................ 60 pin information ................................................................................................................ ................................... 61 system interface pin options................................................................................................... .......................... 66 block diagrams ................................................................................................................. ................................. 67 data recovery.................................................................................................................. .................................. 69 jitter accommodation and jitter transfer without the jitter attenuator ......................................................... .... 69 receiver configuration modes ................................................................................................... ........................ 69 clock/data recovery mode (cdr) ................................................................................................. ................ 69 zero substitution decoding (code) .............................................................................................. ................. 69 alternate logic mode (alm) ..................................................................................................... ...................... 69 alternate clock mode (acm) ..................................................................................................... ..................... 69 rliu alarms.................................................................................................................... ................................ 70 ds1 receiver specifications .................................................................................................... .......................... 72 frequency response curves...................................................................................................... .................... 73 cept receiver specifications ................................................................................................... ........................ 75 frequency response curves...................................................................................................... .................... 76 output pulse generation........................................................................................................ ............................ 78 jitter......................................................................................................................... ........................................... 78 transmitter configuration modes ................................................................................................ ....................... 79 zero substitution encoding (code) .............................................................................................. ................. 79 alarm indication signal generator (xais)....................................................................................... ................ 79 loss of transmit clock (lotc) alarm ............................................................................................ ................ 79 transmit driver monitor (tdm) alarm ............................................................................................ ................. 79
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 4 lucent technologies inc. table of contents (continued) contents page ds1 transmitter pulse template ................................................................................................. ...................... 80 cept transmitter pulse template................................................................................................ ..................... 81 jitter attenuator .............................................................................................................. .................................... 82 generated (intrinsic) jitter ................................................................................................... ........................... 82 jitter transfer function ....................................................................................................... ............................ 83 jitter accommodation ........................................................................................................... .......................... 83 jitter attenuator enable ....................................................................................................... ........................... 84 jitter attenuator receive path enable (jar) .................................................................................... .............. 84 jitter attenuator transmit path enable (jat) ................................................................................... .............. 84 frequency response curves ...................................................................................................... ................... 85 loopbacks ...................................................................................................................... .................................... 89 full local loopback (flloop ) ...................................................................................................................... 89 remote loopback (rloop ) ........................................................................................................................... 89 digital local loopback (dlloop ) .................................................................................................................. 89 powerdown (pwrdn).............................................................................................................. .......................... 89 reset ( reset ).............................................................................................................................. ...................... 89 loss of xclk reference clock (loxc)............................................................................................ ................. 89 in-circuit testing and driver high-impedance state (ict )................................................................................. 89 liu delay values............................................................................................................... ................................. 89 line encoding/decoding ......................................................................................................... ........................... 90 alternate mark inversion (ami) ................................................................................................. ...................... 90 t1-binary 8 zero code suppression .............................................................................................. ................ 90 high-density bipolar of order 3 (hdb3) ......................................................................................... ................ 90 xclk reference clock ........................................................................................................... ........................... 91 16x xclk reference clock ....................................................................................................... ..................... 91 primary line rate xclk reference clock and internal reference clock synthesizer .................................. 92 power supply bypassing......................................................................................................... ........................... 93 line circuitry ................................................................................................................. ..................................... 94 absolute maximum ratings....................................................................................................... ......................... 95 handling precautions ........................................................................................................... .............................. 95 operating conditions........................................................................................................... ............................... 95 power requirements............................................................................................................. ............................. 96 electrical characteristics ..................................................................................................... ............................... 96 data interface timing .......................................................................................................... ............................... 97 outline diagram................................................................................................................ ..................................... 98 144-pin tqfp ................................................................................................................... .................................. 98 ordering information........................................................................................................... ................................... 99
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 5 lucent technologies inc. list of figures figures page figure 1. TLIU04C1 microprocessor mode pin diagram............................................................................. ............. 9 figure 2. TLIU04C1 block diagram, cmode = 1 (microprocessor mode) ............................................................ 1 8 figure 3. block diagram of the quad line interface unit (single channel) ....................................................... .... 19 figure 4. ds1/t1 receiver jitter accommodation without jitter attenuator ....................................................... ... 24 figure 5. ds1/t1 receiver jitter transfer without jitter attenuator ............................................................ .......... 25 figure 6. cept/e1 receiver jitter accommodation without jitter attenuator ...................................................... . 27 figure 7. cept/e1 receiver jitter transfer without jitter attenuator ........................................................... ........ 28 figure 8. dsx-1 isolated pulse template ........................................................................................ ...................... 31 figure 9. itu-t g.703 pulse template ........................................................................................... ....................... 33 figure 10. ds1/t1 receiver jitter accommodation with jitter attenuator......................................................... ..... 37 figure 11. ds1/t1 jitter transfer of the jitter attenuator..................................................................... .................. 38 figure 12. cept/e1 receiver jitter accommodation with jitter attenuator ........................................................ ... 39 figure 13. cept/e1 jitter transfer of the jitter attenuator.................................................................... ................ 40 figure 14. line termination circuitry .......................................................................................... ........................... 50 figure 15. mode 1read cycle timing (mpmode = 0, mpmux = 0) ................................................................. 55 figure 16. mode 1write cycle timing (mpmode = 0, mpmux = 0) ................................................................. 5 5 figure 17. mode 2read cycle timing (mpmode = 0, mpmux = 1) ................................................................. 56 figure 18. mode 2write cycle timing (mpmode = 0, mpmux = 1) ................................................................. 5 6 figure 19. mode 3read cycle timing (mpmode = 1, mpmux = 0) ................................................................. 57 figure 20. mode 3write cycle timing (mpmode = 1, mpmux = 0) ................................................................. 5 7 figure 21. mode 4read cycle timing (mpmode = 1, mpmux = 1) ................................................................. 58 figure 22. mode 4write cycle timing (mpmode = 1, mpmux = 1) ................................................................. 5 8 figure 23. interface data timing (acm = 0)..................................................................................... ...................... 59 figure 24. TLIU04C1 direct logic control mode pin diagram...................................................................... ......... 61 figure 25. TLIU04C1 block diagram, cmode = 0 (direct logic mode)............................................................... . 67 figure 26. block diagram of the quad line interface unit (single channel) ...................................................... ... 68 figure 27. ds1/t1 receiver jitter accommodation without jitter attenuator ...................................................... .. 73 figure 28. ds1/t1 receiver jitter transfer without jitter attenuator ........................................................... ......... 74 figure 29. cept/e1 receiver jitter accommodation without jitter attenuator ..................................................... 76 figure 30. cept/e1 receiver jitter transfer without jitter attenuator .......................................................... ....... 77 figure 31. dsx-1 isolated pulse template ....................................................................................... ..................... 80 figure 32. itu-t g.703 pulse template .......................................................................................... ...................... 81 figure 33. ds1/t1 receiver jitter accommodation with jitter attenuator......................................................... ..... 85 figure 34. ds1/t1 jitter transfer of the jitter attenuator..................................................................... .................. 86 figure 35. cept/e1 receiver jitter accommodation with jitter attenuator ........................................................ ... 87 figure 36. cept/e1 jitter transfer of the jitter attenuator.................................................................... ................ 88 figure 37. line termination circuitry .......................................................................................... ........................... 94 figure 38. interface data timing (acm = 0)..................................................................................... ...................... 97
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 6 lucent technologies inc. list of tables table s page table 1. pin descriptions...................................................................................................... ................................. 10 table 2. system interface pin mapping.......................................................................................... ....................... 14 table 3. microprocessor configuration modes.................................................................................... .................. 14 table 4. mode [14] microprocessor pin definitions............................................................................. ............. 15 table 5. microprocessor input clock specifications............................................................................. ................. 16 table 6. liu register bank ..................................................................................................... .............................. 17 table 7. register map for code bits............................................................................................ ........................ 20 table 8. digital loss of signal standard select ................................................................................ .................... 22 table 9. lossd and rcvais control configurations (not valid during loopback modes) ................................ 22 table 10. ds1 rliu specifications .............................................................................................. ......................... 23 table 11. cept rliu specifications............................................................................................. ........................ 26 table 12. equalizer/rate control ............................................................................................... ........................... 29 table 13. register map for code bits........................................................................................... ....................... 30 table 14. dsx-1 pulse template corner points (from cb119) ...................................................................... ...... 31 table 15. ds1 transmitter specifications ....................................................................................... ...................... 32 table 16. cept transmitter specifications...................................................................................... ..................... 34 table 17. loopback control ..................................................................................................... ............................. 41 table 18. ami encoding ......................................................................................................... ............................... 43 table 19. ds1 b8zs encoding.................................................................................................... .......................... 43 table 20. itu hdb3 coding and dcpat binary coding .............................................................................. ........ 43 table 21. alarm registers ...................................................................................................... ............................... 44 table 22. alarm mask registers ................................................................................................. .......................... 45 table 23. global control register (0100)....................................................................................... ....................... 45 table 24. global control register (0101)....................................................................................... ....................... 46 table 25. channel configuration registers (01101001).......................................................................... .......... 46 table 26. channel configuration register (1011) ................................................................................ ................. 47 table 27. control register (1100) .............................................................................................. ........................... 47 table 28. xclk (16x, clks = 0) timing specifications ........................................................................... ............ 48 table 29. xclk (1x, clks = 1) timing specifications ............................................................................ ............. 49 table 30. termination components by application................................................................................ ............... 50 table 31. absolute maximum ratings............................................................................................. ...................... 51 table 32. esd threshold voltage ................................................................................................ ......................... 51 table 33. recommended operating conditions ..................................................................................... .............. 51 table 34. power consumption .................................................................................................... .......................... 52 table 35. power dissipation.................................................................................................... .............................. 52 table 36. logic interface characteristics ...................................................................................... ........................ 52 table 37. microprocessor interface i/o timing specifications ................................................................... ........... 53 table 38. data interface timing ................................................................................................ ............................ 59 table 39. pin descriptions..................................................................................................... ................................ 62 table 40. system interface pin mapping......................................................................................... ...................... 66 table 41. digital loss of signal standard select ............................................................................... ................... 70 table 42. lossd and rcvais control configurations (not valid during loopback modes) .............................. 71 table 43. ds1 rliu specifications .............................................................................................. ......................... 72 table 44. cept rliu specifications............................................................................................. ........................ 75 table 45. equalizer/rate control ............................................................................................... ........................... 78 table 46. dsx-1 pulse template corner points (from cb119) ...................................................................... ...... 80 table 47. ds1 transmitter specifications ....................................................................................... ...................... 80 table 48. cept transmitter specifications...................................................................................... ..................... 82 table 49. ami encoding ......................................................................................................... ............................... 90 table 50. ds1 b8zs encoding.................................................................................................... .......................... 90
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 7 lucent technologies inc. list of tables (continued) table s page table 51. itu hdb3 coding and dcpat binary coding .............................................................................. ........ 90 table 52. xclk (16x, clks = 0) timing specifications........................................................................... ............. 91 table 53. xclk (1x, clks = 1) timing specifications............................................................................ .............. 92 table 54. xclk specifications .................................................................................................. ............................ 92 table 55. termination components by application................................................................................ ............... 94 table 56. absolute maximum ratings............................................................................................. ...................... 95 table 57. esd threshold voltage ................................................................................................ ......................... 95 table 58. recommended operating conditions ..................................................................................... .............. 95 table 59. power consumption .................................................................................................... .......................... 96 table 60. power dissipation.................................................................................................... .............................. 96 table 61. logic interface characteristics ...................................................................................... ........................ 96 table 62. data interface timing ................................................................................................ ............................ 97
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 8 lucent technologies inc. description the TLIU04C1 is a quad line interface containing four line transmit and receive channels for use in both north american (t1/ds1) and european (e1/cept) applica- tions. the line interface unit has the same functions as the lucent t7698. the device can operate in either of two modes, chosen by the logic state of a control pin. a direct logic control mode provides the ability to define the architecture, ini- tiate loopbacks, and monitor alarms without connecting to a microprocessor by setting the logic levels on con- trol pins. the microprocessor mode uses a parallel microprocessor interface to allow the user to configure the device. the interface is compatible with many com- mercially available microprocessors. the block dia- grams of the microprocessor and direct logic modes are shown in figure 2 and figure 25, respectively. the block diagram of the line interface unit is shown in figure 3 on page 19 (it is repeated as figure 26). the line receiver performs clock and data recovery using a fully integrated digital phase-locked loop. this digital implementation prevents false lock conditions that are common when recovering sparse data patterns with analog phase-locked loops. equalization circuitry in the receiver provides a high level of interference immunity. as an option, the raw sliced data (no retiming) can be output on the receive data pins. transmit equalization is implemented with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. the quad device will interface to the digi- tal cross connect (dsx) at lengths of up to 655 ft. for ds1 operation or to line impedances of 75 w or 120 w for cept operation. a selectable jitter attenuator may be placed in the receive signal path for low-bandwidth line-synchronous applications, or it may be placed in the transmit path for multiplexer applications where ds1/cept signals are demultiplexed from higher rate signals. the jitter atten- uator will perform the clock smoothing required on the resulting demultiplexed gapped clock. microprocessor mode overview the TLIU04C1 device has the ability to operate in either a microprocessor mode or a direct logic control mode. the cmode pin is used to determine the oper- ating mode. to configure the device for microprocessor mode, the cmode pin is pulled high. the device is equipped with a microprocessor interface that can operate with most commercially available microprocessors. inputs mpmux and mpmode (pins 108 and 110) are used to configure this interface into one of four possible modes, as shown in table 3. the mpmux setting selects either a multiplexed 8-bit address/data bus (ad[7:0]) or a demultiplexed 4-bit address bus (a[3:0]) and an 8-bit data bus (ad[7:0]). the mpmode setting selects the associated set of control signals required to access a set of registers within the device. when the microprocessor interface is configured to operate in the multiplexed address/data bus modes (mpmux = 1), the user has access to an internal chip select function that allows the microprocessor to selec- tively read/write a specific TLIU04C1 in a multiple TLIU04C1 environment (see the internal chip select function section, page 16). the microprocessor interface can operate at speeds up to 16.384 mhz in interrupt-driven or polled mode with- out requiring any wait-states. for microprocessors operating at greater than 16.384 mhz, the rdy_dtack output is used to introduce wait-states in the read/write cycles. in the interrupt-driven mode, one or more device alarms will assert the active-high int output (pin 114) once per alarm activation. after the microprocessor reads the alarm status registers, the int output will deassert. in the polled mode, however, the micropro- cessor monitors the various device alarm status by periodically reading the alarm status registers without the use of int. a variety of liu mask controls are avail- able for control of the int pin.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 9 lucent technologies inc. microprocessor mode (continued) pin information 5-7728(f).a figure 1. TLIU04C1 microprocessor mode pin diagram gndd vdda1 rtip1 rring1 gnda1 rnd1/bpv1 rpd1/rdata1 a2 a1 a0 vddd gndd nc nc tclk2 tpd2/tdata2 tnd2 rclk2/alos2 rpd2/rdata2 rnd2/bpv2 gnda2 rring2 rtip2 vdda2 gndx2 tring2 vddx2 ttip2 gndx2 nc reset loxc xclk vddd gndd nc 36 37 gndd nc nc nc nc nc nc nc gndx3 ttip3 vddx3 tring3 gndx3 vdda3 rtip3 rring3 gnda3 rnd3/bpv3 rpd3/rdata3 rclk3/alos3 tnd3 tpd3/tdata3 tclk3 nc nc nc nc nc nc nc nc nc ict nc 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 mpmux wr _ds mpclk nc nc nc nc gndx4 ttip4 vddx4 tring4 gndx4 vdda4 rtip4 rring4 gnda4 rnd4/bpv4 rpd4/rdata4 tnd4 rclk4/alos4 tpd4/tdata4 tclk4 nc nc gndd vddd ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 vddd gndd 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nc gndx1 tring1 vddx1 ttip1 gndx1 nc nc nc nc nc nc nc gndd vddd cmode clks clkm rdy_dtack int cs ale_as rd _r/w a3 nc nc nc nc vddd nc tclk1 tpd1/tdata1 tnd1 rclk1/alos1 mpmode gndd nc nc
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 10 lucent technologies inc. microprocessor mode (continued) pin information (continued) table 1. pin descriptions * i = input, o = output, i u indicates an input with internal pull-up; i d indicates an input with internal pull-down, p = power. resistance value of all internal pull-ups or pull-downs is 50 k w , unless otherwise specified. pin symbol type * name/description 117 clks i d xclk select. this pin selects either a 16x rate clock for xclk (clks = 0) or a primary line rate clock for xclk (clks = 1). 116 clkm i d xclk mode. this pin must be set appropriately when using a primary line rate clock for xclk. cept: clkm = 1. ds1: clkm = 0. 118 cmode i d chip mode. this pin sets the chip mode for either direct logic mode or microprocessor mode. microprocessor: cmode = 1. direct logic: cmode = 0. 128, 132 25, 29, 56, 60, 97, 101 gnd x [14] p ground reference for line drivers. 129, 28, 57, 100 ttip[14] o transmit bipolar tip. positive bipolar transmit data to the analog line interface. 130, 27, 58, 99 v ddx [14] p power supply for line drivers. the TLIU04C1 device requires a 5 v 5% power supply on these pins. 131, 26, 59, 98 tring[14] o transmit bipolar ring. negative bipolar transmit data to the analog line interface. 133, 24, 61, 96 v dda [14] p power supply for analog circuitry. the TLIU04C1 device requires a 5 v 5% power supply on these pins. 134, 23, 62, 95 rtip[14] i receive bipolar tip. positive bipolar receive data from the analog line interface. 135, 22, 63, 94 rring[14] i receive bipolar ring. negative bipolar receive data from the analog line interface. 136, 21, 64, 93 gnd a [14] p ground reference for analog circuitry. 137, 20, 65, 92 rnd/bpv[14] o receive negative data. when in dual-rail (dual = 1: register 5, bit 4) clock recovery mode (cdr = 1: register 5, bit 0), this signal is the received negative nrz data to the terminal equipment. when in data slicing mode (cdr = 0), this signal is the raw sliced negative data of the front end. bipolar violation. when in single-rail (dual = 0: register 5, bit 4) clock recovery mode (cdr = 1: register 5, bit 0), and code = 1 (register 5, bit 3), this signal is asserted high to indicate the occurrence of a code violation in the receive data stream. a code violation is a bipolar violation that is not part of a zero substitution code. if code = 0, this signal is asserted to indicate the occurrence of a bipolar violation in the received data.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 11 lucent technologies inc. microprocessor mode (continued) pin information (continued) table 1. pin descriptions (continued) * i = input, o = output, i u indicates an input with internal pull-up; i d indicates an input with internal pull-down, p = power. resistance value of all internal pull-ups or pull-downs is 50 k w , unless otherwise specified. pin symbol type * name/description 138, 19, 66, 91 rpd/rdata [14] o receive positive data. when in dual-rail (dual = 1: register 5, bit 4) clock recovery mode (cdr = 1: register 5, bit 0), this signal is the received positive nrz data to the terminal equipment. when in data slicing mode (cdr = 0), this signal is the raw sliced positive data of the front end. receive data. when in single-rail (dual = 0: register 5, bit 4) clock recovery mode (cdr = 1: register 5, bit 0), this signal is the received nrz data. 139, 18, 67, 90 rclk/alos [14] o receive clock. in clock recovery mode (cdr = 1: register 5, bit 0), this signal is the recovered receive clock for the terminal equipment. the duty cycle of rclk is 50% 5%. analog loss of signal. in data slicing mode (cdr = 0: register 5, bit 0), this signal is asserted high to indicate low amplitude receive data at the rtip/ rring inputs. 140, 17, 68, 89 tnd[14] i transmit negative data. this signal is the transmit negative nrz data from the terminal equipment. 141, 16, 69, 88 tpd/tdata [14] i transmit positive data. when in dual-rail mode (dual = 1: register 5, bit 4), this signal is the transmit positive nrz data from the terminal equipment. transmit data. when in single-rail mode (dual = 0: register 5, bit 4), this signal is the transmit nrz data from the terminal equipment. 142, 15, 70, 87 tclk[14] i transmit clock. ds1 (1.544 mhz 32 ppm) or cept (2.048 mhz 50 ppm) clock signal from the terminal equipment. 110 mpmode i microprocessor mode. when mpmode = 1, the device uses the address latch enable type microprocessor read/write protocol with separate read and write controls. setting mpmode = 0 allows the device to use the address strobe type microprocessor read/write protocol with a separate data strobe and a combined read/write control. 108 mpmux i microprocessor multiplex mode. setting mpmux = 1 allows the microprocessor interface to accept multiplexed address and data signals. setting mpmux = 0 allows the microprocessor interface to accept demultiplexed (separate) address and data signals. 107 wr _ds i write (active-low). if mpmode = 1 (pin 110), this pin is asserted low by the microprocessor to initiate a write cycle. data strobe (active-low). if mpmode = 0 (pin 21), this pin becomes the data strobe for the microprocessor. when r/w = 0 (pin 111) initiating a write, a low applied to this pin latches the signal on the data bus into internal registers. 111 rd _r/w i read (active-low). if mpmode = 1 (pin 110), this pin is asserted low by the microprocessor to initiate a read cycle. read/write. if mpmode = 0 (pin 110), this pin is asserted high by the microprocessor to initiate a read cycle or asserted low to initiate a write cycle.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 12 lucent technologies inc. microprocessor mode (continued) pin information (continued) table 1. pin descriptions (continued) * i = input, o = output, i u indicates an input with internal pull-up; i d indicates an input with internal pull-down, p = power. resistance value of all internal pull-ups or pull-downs is 50 k w , unless otherwise specified. pin symbol type * name/description 112 ale_as i address latch enable. if mpmode = 1 (pin 110), this pin becomes the address latch enable for the microprocessor. when this pin transitions from high to low, the address bus inputs are latched into the internal registers. address strobe (active-low). if mpmode = 0 (pin 110), this pin becomes the address strobe for the microprocessor. when this pin transitions from high to low, the address bus inputs are latched into the internal registers. 113 cs i u chip select (active-low). this pin is asserted low by the microprocessor to enable the microprocessor interface. if mpmux = 1 (pin 108), cs can be externally tied low to use the internal chip selection function. an internal 100 k w pull-up is on this pin. 114 int o interrupt. this pin is asserted high to indicate an interrupt produced by an alarm condition in register 0 or 1. the activation of this pin can be masked by various register bits. 115 rdy_dtack o ready. if mpmode = 1 (pin 110), this pin is asserted high to indicate the device has completed a read or write operation. this pin is in a 3-state condition when cs (pin 113) is high. data transfer acknowledge (active-low). if mpmode = 0 (pin 110), this pin is asserted low to indicate the device has completed a read or write operation. 1, 12, 37, 48, 73, 84, 109, 120 gnd d p ground reference for microprocessor interface and digital circuitry. 2, 11, 47, 74, 83, 119 v ddd p power supply for microprocessor interface and digital circuitry. the TLIU04C1 device requires a 5 v 5% power supply on these pins. 46 xclk i u reference clock . the clock signal used for clock and data recovery and jitter attenuation. this clock must be ungapped and free of jitter. for clks = 0, a 16x clock (for ds1, xclk = 24.704 mhz 100 ppm and for cept, xclk = 32.768 mhz 100 ppm). for clks = 1, a 1x clock (for ds1, xclk = 1.544 mhz 100 ppm and for cept, xclk = 2.048 mhz 100 ppm). to meet tbr 12/13 jitter accommodation requirements (jabw0 = 1), clock tolerances must be 20 ppm. an internal 100 k w pull-up is on this pin. 45 loxc o loss of xclk . this pin is asserted high when the xclk signal (pin 46) is not present. 44 reset i u hardware reset (active-low) . if reset is forced low, all internal states in the line interface paths are reset and data flow through each channel will be momentarily disrupted. the reset pin must be held low for a minimum of 10 s.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 13 lucent technologies inc. microprocessor mode (continued) pin information (continued) table 1. pin descriptions (continued) pin symbol type * * i = input, o = output, i u indicates an input with internal pull-up; i d indicates an input with internal pull-down, p = power. resistance value of all internal pull-ups or pull-downs is 50 k w , unless otherwise specified. name/description 43 ict i u in-circuit test control (active-low) . if ict is forced low, certain output pins are placed in a high-impedance state. which output pins are affected is controlled by the ictmode bit (register 4, bit 3). 7582 ad[7:0] i/o microprocessor interface address/data bus. if mpmux = 0 (pin 108), these pins become the bidirectional, 3-statable data bus. if mpmux = 1, these pins become the multiplexed address/data bus. in this mode, only the lower 4 bits (ad[3:0]) are used for the internal register addresses. 710 a[3:0] i microprocessor interface address. if mpmux = 0 (pin 108), these pins become the address bus for the microprocessor interface registers. if mpmux = 1 (pin 108) and cs = 0 (pin 113), a3 (pin 7) can be externally tied high to use the internal chip selection function. the state of a[2:0] determines the address of the device. the device is addressed when the state of pins ad[6:4] matches the device address of a[2:0]. if this function is not used, a[3:0] must be externally tied low. 106 mpclk i microprocessor interface clock. microprocessor interface clock rates from twice the frequency of the line clock (3.088 mhz for ds1 operation, 4.096 mhz for cept operation) to 16.384 mhz are supported.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 14 lucent technologies inc. microprocessor mode (continued) system interface pin options the system interface can be configured to operate in a number of different modes. the different modes change the functionality of the system interface pins, as shown in table 2. dual-rail or single-rail operation is possible using the dual control bit (register 5, bit 4). dual-rail mode is enabled when dual = 1; single-rail mode is enabled when dual = 0. in dual-rail operation, data received from the line interface on rtip and rring appears on rpd and rnd at the system interface and data transmitted from the system interface on tpd and tnd appears on ttip and tring at the line interface. in single-rail operation, data received from the line interface on rtip and rring appears on rdata at the system interface and data transmitted from the system interface on tdata appears on ttip and tring at the line interface. in both dual-rail and single-rail operation, the clock/data recovery mode is selectable via the cdr bit (register 5, bit 0). when cdr = 1, the clock and data recovery is enabled and the system interface operates in a nonreturn-to- zero (nrz) digital format, recovering the clock and data from the incoming pulses. when cdr = 0, the clock and data recovery is disabled and the system interface operates on unretimed sliced data in rz data format. no clock is recovered, freeing up the rclk pin to be used to indicate an analog loss of signal (alos). if the incoming pulse height falls below C18 db, the alos pin is asserted high, and remains high until the signal rises above C14 db. in single-rail mode only, b8zs/hdb3 encoding/decoding may be selected by setting the control bits properly (see the zero substitution decoding (code) section, page 20, and the zero substitution encoding (code) section, page 30). when a coding violations occurs, the bpv pin is asserted high. table 2. system interface pin mapping microprocessor configuration modes table 3 highlights the four microprocessor modes controlled by the mpmux and mpmode inputs (pins 108 and 110). configuration rclk/ alos rpd/ rdata rnd/bpv tpd/ tdata tnd dual-rail with clock recovery (dual = 1, cdr = 1) rclk rpd rnd tpd tnd dual-rail with data slicing (dual = 1, cdr = 0) alos rpd rnd single-rail with clock recovery (dual = 0, cdr = 1) rclk rdata bpv tdata not used single-rail with data slicing (dual = 0, cdr = 0) alos rpd rnd table 3. microprocessor configuration modes mode mpmode mpmux address/data bus generic control, data, and output pin names mode 1 0 0 demuxed cs , as , ds , r/ w , a[3:0], ad[7:0], int, dtack mode 2 0 1 muxed cs , as , ds , r /w , ad[7:0], int, dtack mode 3 1 0 demuxed cs , ale, rd , wr , a[3:0], ad[7:0], int, rdy mode 4 1 1 muxed cs , ale, rd , wr , ad[7:0], int, rdy
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 15 lucent technologies inc. microprocessor mode (continued) microprocessor interface pinout definitions the mode 1mode 4 specific pin definitions are given in table 4. note that the microprocessor interface uses the same set of pins in all modes. table 4. mode [14] microprocessor pin definitions configuration pin number device pin name generic pin name pin type assertion sense function mode 1 107 wr _ds ds input active-low data strobe 111 rd _r/w r/w input read/write r/w = 1 => read r/w = 0 => write 112 ale_as as input address strobe 113 cs cs input active-low chip select 114 int int output active-high interrupt 115 rdy_dtack dtack output active-low data acknowledge 7582 ad[7:0] ad[7:0] i/o data bus 710 a[3:0] a[3:0] input address bus 106 mpclk mpclk input microprocessor clock mode 2 107 wr _ds ds input active-low data strobe 111 rd _r/w r/w input read/write r/w = 1 => read r/w = 0 => write 112 ale_as as input address strobe 113 cs cs input active-low chip select 114 int int output active-high interrupt 115 rdy_dtack dtack output active-low data acknowledge 7582 ad[7:0] ad[7:0] i/o address/data bus 106 mpclk mpclk input microprocessor clock mode 3 107 wr _ds wr input active-low write 111 rd _r/w rd input active-low read 112 ale_as ale input address latch enable 113 cs cs input active-low chip select 114 int int output active-high interrupt 115 rdy_dtack rdy output active-high ready 7582 ad[7:0] ad[7:0] i/o data bus 710 a[3:0] a[3:0] input address bus 106 mpclk mpclk input microprocessor clock mode 4 107 wr _ds wr input active-low write 111 rd _r/w rd input active-low read 112 ale_as ale input address latch enable 113 cs cs input active-low chip select 114 int int output active-high interrupt 115 rdy_dtack rdy output active-high ready 7582 ad[7:0] ad[7:0] i/o address/data bus 106 mpclk mpclk input microprocessor clock
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 16 lucent technologies inc. microprocessor mode (continued) microprocessor clock (mpclk) specifications the microprocessor interface is designed to operate at clock speeds up to 16.384 mhz without requiring any wait- states. wait-states may be needed if higher microprocessor clock speeds are required. the microprocessor clock (mpclk, pin 106) specification is shown in table 5. this clock must be supplied only if the rdy_dtack and int outputs are required to be synchronous to mpclk. otherwise, the mpclk pin must be connected to ground. internal chip select function when the microprocessor interface is configured to operate in the multiplexed address/data bus modes (mpmux = 1), the user has access to an internal chip select function. this function allows a microprocessor to selectively read or write a specific TLIU04C1 device in a system of up to eight devices on the microprocessor bus. externally tying cs = 0 (pin 113) and a3 = 1 (pin 7) on every device enables the internal chip select function. indi- vidual device addresses are established by externally connecting the other three address pins, a[2:0] (pins 8, 9, 10), to a unique address value in the range of 000 through 111. in order for a device to respond to the register read or write request from the microprocessor, the address data bus ad[6:4] (pins 76, 77, 78) must match the specific address defined on a[2:0]. if cs and a3 pins are tied low, the internal chip select function is disabled and all devices will respond to a microprocessor write request. however, if cs = 1, none of the devices will respond to the microprocessor read/write request. the i/o timing specifications for the microprocessor interface are given on page 53. table 5. microprocessor input clock specifications name period and toler ance t rise typ t fall typ duty cycle unit min high min low mpclk 61 to 323 5 5 27 27 ns
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 17 lucent technologies inc. microprocessor mode (continued) microprocessor interface register architecture the register bank architecture of TLIU04C1 consists of a register bank for the quad line interface unit. the register bank consists of sixteen 8-bit registers comprising the alarm, control, and configuration registers for the quad line interface unit. table 6 shows the register bank architecture. notes: a numerical suffix appended to the bit name identifies the channel number. bits shown in parentheses indicate the state forced during a reset condition. all registers must be configured by the user before the device can operate as required for the particular application. table 6. liu register bank designation address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 alarm registers (read only) 0 0000 lotc2 tdm2 dlos2 alos2 lotc1 tdm1 dlos1 alos1 1 0001 lotc4 tdm4 dlos4 alos4 lotc3 tdm3 dlos3 alos3 alarm mask registers (read/write) 2 0010 mlotc2 mtdm2 mdlos2 malos2 mlotc1 mtdm1 mdlos1 malos1 3 0011 mlotc4 mtdm4 mdlos4 malos4 mlotc3 mtdm3 mdlos3 malos3 global control registers (read/write) 4 0100 highz4 (1) highz3 (1) highz2 (1) highz1 (1) ictmode (0) losstd swreset (0) gmask (1) 5 0101 lossd acm alm dual code jat jar cdr channel configuration registers (read/write) 6 0110 eqa1 eqb1 eqc1 loopa1 loopb1 xais1 mask1 pwrdn1 7 0111 eqa2 eqb2 eqc2 loopa2 loopb2 xais2 mask2 pwrdn2 8 1000 eqa3 eqb3 eqc3 loopa3 loopb3 xais3 mask3 pwrdn3 9 1001 eqa4 eqb4 eqc4 loopa4 loopb4 xais4 mask4 pwrdn4 10 1010 0000 0 00 0 11 1011 0 code3 0 code4 0 0 0 0 12 1100 code1 code2 jabw0 (0) phizalm (0) prlalm (0) pflalm (0) rcvais (0) altimer (0) 13 1101 0 000 0 00 0 1415 11101111 reserved
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 18 lucent technologies inc. microprocessor mode (continued) block diagrams 5-7822(f).ar.1 figure 2. TLIU04C1 block diagram, cmode = 1 (microprocessor mode) ttip[14] tring[14] ict loxc quad line interface unit rtip[14] rring[14] quad transmit section quad receive section reset 4 4 4 clks 4 4 4 micro- interface processor a[3:0] ad[7:0] rdy_dtack int wr _ds ale_as cs mpmux mpmode mpclk rclk[14] rnd[14] rpd[14] tpd[14] tnd[14] tclk[14] clock multiplier clkm xclk rd _r/w
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 19 lucent technologies inc. microprocessor mode (continued) block diagrams (continued) the line interface block diagram is shown in figure 3. for illustration purposes, only one of the four on-chip line interfaces is shown. pin names that apply to all four channels are followed by the designation [14]. 5-4556(f).er.3 figure 3. block diagram of the quad line interface unit (single channel) rtip[14] rring[14] flloop (no liu ais) equalizer slicers clock and data recovery dlos rnd[14] rpd[14] rclk[14] decoder dlloop rloop tclk[14] tnd[14] jitter (receive path) tpd[14] flloop (during liu ais) pulse- width controller tdm lotc pulse equalizer transmit driver ttip[14] tring[14] loss of xclk monitor divide by 16 alarm signal (ais) encoder alos indication at t e n uato r jitter (transmit path) at t e n uato r (clock) (data) loss of tclk loxc xclk 16x clock multiplier clks intxclk
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 20 lucent technologies inc. microprocessor mode (continued) data recovery the receive line interface unit (rliu) format is bipolar alternate mark inversion (ami). the data rate tolerance is 130 ppm (ds1) or 80 ppm (cept). the receiver first restores the incoming data and detects analog loss of signal. subsequent processing is optional and depends on the programmable device configuration established within the microprocessor interface regis- ters. the rliu utilizes an equalizer to operate on line length with up to 15 db of loss at 772 khz (ds1) or 13 db loss at 1.024 mhz (cept). the signal is then peak-detected and sliced to produce digital representa- tions of the data. selectable clock and data recovery, digital loss of sig- nal, jitter attenuation, and data decoding are per- formed. for applications bypassing the clock and data recovery function (cdr = 0), the receive digital output format is unretimed sliced data (rz positive and nega- tive data). for clock and data recovery applications (cdr = 1), the receive digital output format is non- return-to-zero (nrz) with selectable dual-rail or single- rail system interface. the recovered clock (rclk, pins 139, 18, 67, 90) is only provided when cdr = 1 (see ta b l e 2 ) . the clock is recovered by a digital phase-locked loop that uses xclk (pin 46) as a reference to lock to the data rate component. because the internal reference clock is a multiple of the received data rate, the rclk output (pins 139, 18, 67, 90) will always be a valid ds1/ cept clock that eliminates false-lock conditions. dur- ing periods with no receive input signal, the free-run frequency of rclk is defined to be either xclk/16 or xclk, depending on the state of clks (pin 117). rclk is always active with a duty-cycle centered at 50%, deviating by no more than 5%. valid data is recovered within the first few bit periods after the appli- cation of xclk. the delay of the data through the receive circuitry is approximately 1 to 14 bit periods, depending on the cdr and code configurations. additional delay is introduced if the jitter attenuator is selected for operation in the receive path (see the liu delay values section, page 42). jitter accommodation and jitter transfer without the jitter attenuator the rliu is designed to accommodate large amounts of input jitter. the rlius jitter performance exceeds the requirements shown in the rliu specifications tables (table 10 and table 11). typical receiver perfor- mance without the jitter attenuator in the path is shown in figure 4 through figure 7. jitter transfer is indepen- dent of input ones density on the line interface. receiver configuration modes clock/data recovery mode (cdr) the clock/data recovery function in the receive path is selectable via the cdr bit (register 5, bit 0). if cdr = 1, the clock and data recovery function is enabled and provides a recovered clock (rclk) with retimed data (rpd/rdata, rnd). if cdr = 0, the clock and data recovery function is disabled, and the rz data from the slicers is provided over rpd and rnd to the system. in this mode, alos is available on the rclk/alos pins, and downstream functions selected by microprocessor register 5 (jar, acm, lossd) are ignored. zero substitution decoding (code) when single-rail operation is selected with dual = 0 (register 5, bit 4), the b8zs/hdb3 decoding can be selected. code = 1 selects the b8zs/hdb3 decoding operation in all four channels, regardless of the state of the code[14] bits. the b8zs/hdb3 decoding oper- ation can be selected for individual channels indepen- dently by setting code = 0 and programming code[14] bits for the respective channels. note: encoding and decoding are not independent. selecting b8zs/hdb3 decoding in the receiver selects b8zs/hdb3 encoding in the transmitter. table 7. register map for code bits when decoding is selected for a given channel, decoded receive data and code violations appear on the rdata and bpv pins, respectively. if coding is not selected, receive data and any bipolar violations (such as two consecutive ones of the same polarity) appear on the rdata and bpv pins, respectively. name location register bit code 5 3 code1 12 7 code2 12 6 code3 11 6 code4 11 4
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 21 lucent technologies inc. microprocessor mode (continued) receiver configuration modes (continued) alternate logic mode (alm) the alternate logic mode (alm) control bit (register 5, bit 5) selects the receive and transmit data polarity (i.e., active-high vs. active-low). if alm = 0, the receiver cir- cuitry (and transmit input) assumes the data to be active-low polarity. if alm = 1, the receiver circuitry (and transmit input) assumes the data to be active-high polarity. the alm control is used in conjunction with the acm control (register 5, bit 6) to determine the receive data retiming mode. alternate clock mode (acm) the alternate clock mode (acm) control bit (register 5, bit 6) selects the positive or negative clock edge of the receive clock (rclk) for receive data retiming. the acm control is used in conjunction with alm (register 5, bit 5) control to determine the receive data retiming modes. if acm = 1, the receive data is retimed on the positive edge of the receive clock. if acm = 0, the receive data is retimed on the negative edge of the receive clock. note that this control does not affect the timing relationship for the transmitter inputs. see figure 23 on page 59. rliu alarms analog loss of signal (alos) alarm . an analog sig- nal detector monitors the receive signal amplitude and reports its status in the analog loss of signal alarm bits in registers 0 and 1. analog loss of signal is indicated (alos = 1) if the amplitude at the rring and rtip inputs drops more than approximately 18 db below the nominal signal amplitude. the alos alarm condition will clear when the receive signal amplitude returns to greater than 14 db below normal. in this way, the alos circuitry provides 4 db of hysteresis to prevent alarm chattering. the alos alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). upon the transition from alos = 0 to alos = 1, a microprocessor interrupt will be generated if the corresponding alos interrupt mask bit (malos; registers 2 and 3, bits 0 and 4), the channel mask bit (mask; registers 69, bit 1), or the global mask bit (gmask; register 4, bit 0) is not set. the time required to detect alos is selectable. when altimer = 0 (register 12, bit 0), alos is declared between 1 ms and 2.6 ms after losing signal as required by i.431(3/93) and ets-300-233 (5/94). if altimer = 1, alos is declared between 10 and 255 bit symbol periods after losing signal as required by g.775 (11/95). the timing is derived from the xclk clock. the detection time is independent of signal amplitude before the loss condition occurs. normally, altimer = 1 would be used only in cept mode since no t1/ds1 standards require this mode. in t1/ds1 mode, this bit should normally be zero. the behavior of the receiver liu outputs under alos conditions is dependent on the loss shutdown control bit (lossd; register 5, bit 7) in conjunction with the receive alarm indication select control bit (rcvais; register 12, bit 1) as described in the loss shutdown (lossd) and receiver ais (rcvais) section on page 22. digital loss of signal (dlos) alarm . a digital loss of signal (dlos) detector guarantees the received signal quality as defined in the appropriate ansi, bellcore, and itu standards. the digital loss of signal alarms are reported in the alarm status registers 0 and 1. during ds1 operation, digital loss of signal (dlos = 1) is indi- cated if 100 or more consecutive zeros occur in the receive data stream. the dlos condition is deacti- vated when the average ones density of at least 12.5% is received in 100 contiguous pulse positions. the dlos alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). the losstd control bit (register 4, bit 2) selects the con- formance protocols for the dlos alarm indication per table 8. setting losstd = 1 adds an additional con- straint that there are less than 15 consecutive zeros in the ds1 data stream before dlos is deactivated.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 22 lucent technologies inc. microprocessor mode (continued) receiver configuration modes (continued) rliu alarms (continued) during cept operation, dlos is indicated when 255 or more consecutive zeros occur in the receive data stream. the dlos indication is deactivated when the average ones density of at least 12.5% is received in 255 contiguous pulse positions. losstd has no effect in cept mode. upon the transition from dlos = 0 to dlos = 1, a microprocessor interrupt will be generated if the corresponding dlos interrupt mask bit (mdlos; registers 2 and 3, bits 1 and 5), the channel mask bit (mask; registers 69, bit 1) or the global mask bit (gmask; register 4, bit 0) is not set. the dlos alarm may occur when flloop is activated (see loopbacks on page 41) due to the abrupt change in signal level at the receiver input. setting the flloop alarm prevention, pflalm = 1 (register 12, bit 2), prevents the dlos alarm from occurring when flloop is activated by quickly resetting the receivers internal peak detec- tor. it will not prevent the dlos alarm during the flloop period but only avoids the alarm created by the signal amplitude transient. loss shutdown (lossd) and receiver ais (rcvais). the loss shutdown control bit (lossd; register 5, bit 7) acts in conjunction with the receive alarm indication select (rcvais) control bit (register 12, bit 1) to place the digi- tal outputs in a predetermined state when a digital loss of signal (dlos) or analog loss of signal (alos) alarm occurs. if lossd = 0 and rcvais = 0, the rnd, rpd, and rclk outputs will be unaffected by the dlos alarm condition. however, when an alos alarm condition is indicated in the alarm status registers, the rpd and rnd outputs are forced to their inactive state (dependent on alm state) and the rclk free runs (based on xclk frequency). if lossd = 0, rcvais = 1, and a dlos or an alos alarm condition is indicated in the alarm status registers, the rpd and rnd outputs will present an alarm indication signal (ais, all ones) based on the free-running clock fre- quency, and the rclk free runs. if lossd = 1, regardless of the state of rcvais, and a dlos or an alos alarm condition is indicated in the alarm status registers, the rpd and rnd outputs are forced to their inactive state (dependent on alm state) and the rclk free runs. the rnd, rpd, and rclk signals will remain unaffected if any loopback (flloop, rloop, dlloop) is activated independent of lossd and rcvais settings. the lossd and rcvais behavior is summarized in table 9. table 8. digital loss of signal standard select losstd ds1 mode cept mode 0 t1m1.3/93-005, itu-t g.775 itu-t g.775 1 tr-tsy-000009 itu-t g.775 table 9. lossd and rcvais control configurations (not valid during loopback modes) lossd rcvais alarm rpd/rnd rclk 0 0 alos 0 if alm = 1, 1 if alm = 0 free runs 0 0 dlos normal data recovered clock 0 1 alos ais (all ones) free runs 0 1 dlos ais (all ones) free runs 1 x alos 0 if alm = 1, 1 if alm = 0 free runs 1 x dlos 0 if alm = 1, 1 if alm = 0 free runs
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 23 lucent technologies inc. microprocessor mode (continued) receiver configuration modes (continued) rliu alarms (continued) rliu bipolar violation (bpv) alarm. the bipolar violation (bpv) alarm is used only in the single-rail mode of operation. when b8zs(ds1)/hdb3(cept) coding is not used (i.e., code = 0), any violations in the receive data (such as two or more consecutive ones on a rail) are indicated on the rnd/bpv outputs. when b8zs(ds1)/ hdb3(cept) coding is used (i.e., code = 1), the hdb3/b8zs code violations are reflected on the rnd/bpv out- puts. ds1 receiver specifications during ds1/t1 operation, the rliu will perform as specified in table 10. table 10. ds1 rliu specifications parameter min typ max unit spec analog loss of signal: threshold to assert threshold to clear hysteresis time to assert (altimer = 0) 17.5 13.5 1.0 18 14 4 23 17.5 2.6 db * db * db ms * below the nominal pulse amplitude of 3.0 v with the line circuitry specified (see line circuitry on page 50). i.431 i.431 receiver sensitivity ? ? cable loss at 772 khz. 11 15 db jitter transfer: 3 db bandwidth peaking 3.84 0.1 khz db figure 5 on page 25 figure 11 on page 38 generated jitter 0.04 0.05 uip-p gr-499-core itu-t g.824 jitter accommodation figure 4 on page 24 figure 10 on page 37 return loss ? : 51 khz to 102 khz 102 khz to 1.544 mhz 1.544 mhz to 2.316 mhz ? using lucent transformer 2795b and components listed in table 30. 14 20 16 db db db digital loss of signal: flag asserted when consecutive bit positions contain flag deasserted when data density is and maximum consecutive zeros are 100 12.5 15 99 zeros % ones zeros zeros itu-t g.775, t1m1.3/93-005 tr-try-000009 itu-t g.775, t1m1.3/ 93-005
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 24 lucent technologies inc. microprocessor mode (continued) ds1 receiver specifications (continued) frequency response curves 5-5260(f)r.7 figure 4. ds1/t1 receiver jitter accommodation without jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 28 ui frequency (hz) 100k typical (subject to device characterization) (non-sonet cat ii interfaces) gr-499-core i.431(ds1), g.824(ds1) tr-tsy-000009 (ds1, muxes) gr-499/1244-core (cat i interfaces) t1.408/i.431(ds1)/g.824(ds1)
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 25 lucent technologies inc. microprocessor mode (continued) ds1 receiver specifications (continued) frequency response curves (continued) 5-5261(f)r.4 figure 5. ds1/t1 receiver jitter transfer without jitter attenuator 60 40 20 0 1 10 100 1k 10k 50 30 10 100k frequency (hz) jitter out/jitter in (db) ty p i c a l (subject to device characterization) gr-499-core (non-sonet cat ii to cat ii)
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 26 lucent technologies inc. microprocessor mode (continued) cept receiver specifications during cept/e1 operation, the rliu will perform as specified in table 11. table 11. cept rliu specifications parameter min typ max unit spec analog loss of signal: threshold to assert threshold to clear hysteresis time to assert (altimer = 0) time to assert (altimer = 1) 17.5 13.5 1.0 10 18 14 4 23 17.5 2.6 255 db * db * db ms ui * below the nominal pulse amplitude of 3.0 v with the line circuitry specified (see line circuitry on page 50). i.431, etsi 300 233 i.431, etsi 300 233 g.775 receiver sensitivity ? ? cable loss at 1.024 mhz. 11 13.5 db interference immunity ? : ? amount of cable loss for which the receiver will operate error-free in the presence of a C18 db interference signal summing with the intended signal source. 912db itu-t g.703 jitter transfer: 3 db bandwidth, single pole roll off peaking 5.1 0.5 khz db figure 7 on page 28 figure 13 on page 40 generated jitter 0.04 0.05 uip-p itu-t g.823, i.431 jitter accommodation figure 6 on page 27 figure 12 on page 39 return loss : 51 khz to 102 khz 102 khz to 1.544 mhz 1.544 mhz to 2.316 mhz using lucent transformer 2795d or 2795c and components listed in table 30. 14 20 16 db db db itu-t g.703 digital loss of signal: flag asserted when consecutive bit positions contain flag deasserted when data density is (losstd = 1) 255 12.5 zeros %ones itu-t g.775
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 27 lucent technologies inc. microprocessor mode (continued) cept receiver specifications (continued) frequency response curves 5-5262(f)r.8 figure 6. cept/e1 receiver jitter accommodation without jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 37 ui frequency (hz) g.823 100k typical (subject to device characterization) g.823,etsi-300-011a1 i.431(cept)/ets-300-011 i.431(cept)/ets-300-011
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 28 lucent technologies inc. microprocessor mode (continued) cept receiver specifications (continued) frequency response curves (continued) 5-5263(f)r.4 figure 7. cept/e1 receiver jitter transfer without jitter attenuator frequency (h z ) jitter out/jitter in (db) 60 40 20 0 1 10 100 1k 10k 50 30 10 100k typical (subject to device characterization) g.735-9 w/o jitter reducer
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 29 lucent technologies inc. microprocessor mode (continued) output pulse generation the transmitter accepts a clock with nrz data in single-rail mode (dual = 0: register 5, bit 4) or a clock with positive and negative nrz data in dual-rail mode (dual = 1) from the system. the device converts this data to a balanced bipolar signal (ami format) with optional b8zs(ds1)/hdb3(cept) encoding and jitter attenuation. low-impedance output drivers produce these pulses on the line interface. positive ones are output as a positive pulse on ttip, and negative ones are output as a positive pulse on tring. binary zeros are converted to null pulses. the total delay of the data from the system interface to the transmit driver is approximately 3 to 11 bit periods, depending on the code configuration (see the zero substitution decoding (code) section, page 20 and the zero substitution encoding (code) section, page 30). additional delay results if the jitter attenuator is selected for use in the transmit path (see the liu delay values section). transmit pulse shaping is controlled by the on-chip pulse-width controller and pulse equalizer. the pulse- width controller produces high-speed timing signals to accurately control the transmit pulse widths. this elimi- nates the need for a tightly controlled transmit clock duty cycle that is usually required in discrete imple- mentations. the pulse equalizer controls the ampli- tudes of the pulses. different pulse equalizations are selected through proper settings of eqa, eqb, and eqc (registers 69, bits 57) as described in ta b l e 1 2 . table 12. equalizer/rate control * in ds1 mode, the distance to the dsx for 22 gauge pic (abam) cable is specified. use the maximum cable loss figures for other cable types. in cept mode, equalization is specified for coaxial or twisted-pair cable. ? loss measured at 772 khz. ? in 75 w applications, option 1 is recommended over option 2 for lower device power dissipation. option 2 allows for the same transform er as used in cept 120 w applications. jitter the intrinsic jitter of the transmit path, i.e., the jitter at ttip/tring when no jitter is applied to tclk (and the jitter attenuator is not selected, jat = 0), is typically 5 nsp-p and will not exceed 0.02 uip-p. eqa eqb eqc service clock rate transmitter equalization * maximum cable loss ? feet meters db 0 0 0 ds1 1.544 mhz 0 ft. to 131 ft. 0 m to 40 m 0.6 0 0 1 131 ft. to 262 ft. 40 m to 80 m 1.2 0 1 0 262 ft. to 393 ft. 80 m to 120 m 1.8 0 1 1 393 ft. to 524 ft. 120 m to 160 m 2.4 1 0 0 524 ft. to 655 ft. 160 m to 200 m 3.0 101cept ? 2.048 mhz 75 w (option 2) 1 1 0 120 w or 75 w (option 1) 111not used
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 30 lucent technologies inc. microprocessor mode (continued) zero substitution encoding (code) zero substitution b8zs/hdb3 encoding can be acti- vated only in the single-rail system interface mode (dual = 0). code = 1 selects the b8zs/hdb3 encod- ing operation in all four channels, regardless of the state of the code[14] bits. the b8zs/hdb3 encod- ing operation can be selected for individual channels independently by setting code = 0 and programming code[14] bits for the respective channels. note: encoding and decoding are not independent. selecting b8zs/hdb3 encoding in the transmit- ter selects b8zs/hdb3 decoding in the receiver. table 13. register map for code bits when coding is selected for a given channel, data transmitted from the system interface on tdata (pins 141, 16, 69, 88) will be b8zs/hdb3 encoded before appearing on ttip and tring at the line interface. alarm indication signal generator (xais) when the transmit alarm indication signal control is set (xais = 1) for a given channel (registers 69, bit 2), a continuous stream of bipolar ones is transmitted to the line interface. the tpd/tdata and tnd inputs are ignored during this mode. the xais input is ignored when a remote loopback (rloop) is selected using loopback control bits (loopa and loopb; registers 69, bits 3 and 4). (see the loopbacks section.) the normal clock source for the ais signal is tclk. if tclk is not available (loss of tclk detected), then the ais signal clock defaults to intxclk/16. intxclk is either xclk, or 16x xclk, depending on the state of the clks input pin. see figure 3 on page 19, and clks in table 1, pin descriptions, on page 10. for any of the above options, the clock tolerance must meet the normal line transmission rates (ds1 1.544 mhz 32 ppm; cept 2.048 mhz 50 ppm). transmitter alarms loss of transmit clock (lotc) alarm a loss of transmit clock alarm (lotc = 1; registers 0 and 1, bits 3 and 7) is indicated if any of the clocks in the transmit path disappear. this includes loss of tclk input, loss of rclk during remote loopback, loss of jit- ter attenuator output clock (when enabled), or the loss of clock from the pulse-width controller. for all of these conditions, a core transmitter timing clock is lost and no data can be driven onto the line. output drivers ttip and tring are placed in a high- impedance state when this alarm condition is active. the lotc interrupt is asserted between 3 s and 16 s after the clock disappears, and deasserts imme- diately after detecting the first clock edge. the lotc alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). upon the tran- sition from lotc = 0 to lotc = 1, a microprocessor interrupt will be generated if the corresponding lotc interrupt mask bit (mlotc; registers 2 and 3, bits 3 and 7), the channel mask bit (mask; registers 69, bit 1), or the global mask bit (gmask; register 4, bit 0) is not set. an lotc alarm may occur when rloop is activated and deactivated due to the phase transient that occurs as tclk switches its source to and from rclk. setting the prevent rloop alarm bit (prlalm = 1; liu register 12, bit 3) prevents the lotc alarm from occur- ring at the activation and deactivation of rloop but allows the alarm to operate normally during the rloop active period. transmit driver monitor (tdm) alarm the transmit driver monitor detects two conditions: a nonfunctional link due to a fault on the primary of the transmit transformer, or periods of no data transmis- sion. the transmit driver monitor alarm (tdm; registers 0 and 1, bits 2 and 6) is the ored function of both faults and provides information about the integrity of the transmit signal path. the first monitoring function is provided to detect non- functional links and protect the device from damage. the alarm is set (tdm = 1) when one of the transmit- ter's line drivers (ttip or tring) is shorted to power supply or ground, or ttip and tring are shorted together. under these conditions, internal circuitry pro- tects the device from damage and excessive power supply current consumption by 3-stating the output drivers. the monitor detects faults on the transformer primary, but transformer secondary faults may not be detected. name location register bit code 5 3 code1 12 7 code2 12 6 code3 11 6 code4 11 4
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 31 lucent technologies inc. microprocessor mode (continued) transmitter alarms (continued) transmit driver monitor (tdm) alarm (continued) the monitor operates by comparing the line pulses with the transmit inputs. after 32 transmit clock cycles, the transmitter is powered up in its normal operating mode. the drivers attempt to correctly transmit the next data bit. if the error persists, tdm remains active to elimi- nate alarm chatter and the transmitter is internally pro- tected for another 32 transmit clock cycles. this process is repeated until the error condition is removed and the tdm alarm is deactivated. the tdm alarm sta- tus bit will latch the alarm and remain set until being cleared by a read (clear on read). the second monitoring function is to indicate periods of no data transmission. the alarm is set (tdm = 1) when 32 consecutive zeros have been transmitted, and the alarm condition is cleared on the detection of a single pulse. again, the tdm alarm status bit will latch the alarm and remain set until being cleared by a read (clear on read). this alarm condition does not alter the state or functionality of the signal path. upon the transition from tdm = 0 to tdm = 1, a micro- processor interrupt will be generated if the tdm inter- rupt mask bit (mtdm; registers 2 and 3, bits 2 and 6) is not set and the gmask bit (register 4, bit 0) is not set. a tdm alarm may occur when rloop is activated and deactivated. if the prevent rloop alarm bit (prlalm; register 12, bit 3) is not set, then rloop may activate an lotc alarm, which will put the output drivers ttip and tring in a high-impedance state as described in loss of transmit clock (lotc) alarm on page 30. the high-impedance state of the drivers may, in turn, gener- ate a tdm alarm. setting the highz alarm prevention phizalm = 1 (register 12, bit 4) prevents the tdm alarm from occurring when the drivers are in a high- impedance state. ds1 transmitter pulse template and specifi- cations the ds1 pulse shape template is specified at the dsx (defined by cb119 and ansi t1.102) and is illustrated in figure 8. the device also meets the pulse template specified by itu-t g.703 (not shown). 5-1160(f)r.1 figure 8. dsx-1 isolated pulse template table 14. dsx-1 pulse template corner points (from cb119) maximum curve minimum curve ns v ns v 0 250 325 325 425 500 675 725 1100 1250 0.05 0.05 0.80 1.15 1.15 1.05 1.05 C0.07 0.05 0.05 0 350 350 400 500 600 650 650 800 925 1100 1250 C0.05 C0.05 0.50 0.95 0.95 0.90 0.50 C0.45 C0.45 C0.20 C0.05 C0.05 1.0 0.5 0 C0.5 0 250 500 750 1000 1250 time (ns)
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 32 lucent technologies inc. microprocessor mode (continued) ds1 transmitter pulse template and specifications (continued) during ds1 operation, the ttip and tring pins will perform as specified in table 15. 1. in accordance with the line circuitry described (see line circuitry on page 50). 2. total power difference. 3. measured in a 2 khz band around the specified frequency. 4. using lucent transformer 2795b and components in table 30. 5. below the power at 772 khz. table 15. ds1 transmitter specifications parameter min typ max unit spec output pulse amplitude at dsx 1 2.5 3.0 3.5 v at&t cb119, ansi t1.102 output pulse width at line side of transformer 1 325 350 375 ns output pulse width at device pins ttip and tring 1 330 350 370 ns positive/negative pulse imbalance 2 0.10.4db power levels 3, 4 : 772 khz 1.544 mhz 5 12.6 29 39 17.9 dbm db
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 33 lucent technologies inc. microprocessor mode (continued) cept transmitter pulse template and specifications cept pulse shape template is specified at the system output (defined by itu-t g.703) and is illustrated in figure 9. 5-3145(f)r.1 figure 9. itu-t g.703 pulse template 269 ns (244 + 25) 219 ns (244 C 25) 244 ns 194 ns (244 C 50) 20% 488 ns (244 + 244) 20% 20% 10% 10% 10% 10% 0% 50% 10% v = 100% 10% nominal pulse
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 34 lucent technologies inc. microprocessor mode (continued) cept transmitter pulse template and specifications (continued) during cept operation, the transmitter tip/ring (ttip/tring pins) will perform as specified in table 16. jitter attenuator a selectable jitter attenuator is provided for narrow-bandwidth jitter transfer function applications. when placed in the liu receive path, the jitter attenuator provides narrow-bandwidth jitter filtering for line synchronization. the jitter attenuator can also be placed in the transmit path to provide clock smoothing for applications such as synchronous/ asynchronous demultiplexers. in these applications, tclk will have an instantaneous frequency that is higher than the data rate, and some periods of tclk are suppressed (gapped) in order to set the average long-term tclk fre- quency to within the transmit line rate specification. the jitter attenuator will smooth the gapped clock. generated (intrinsic) jitter generated jitter is the amount of jitter appearing on the output port when the applied input signal has no jitter. the jitter attenuator of this device outputs a maximum of 0.05 uip-p intrinsic jitter. table 16. cept transmitter specifications parameter min typ max unit spec output pulse amplitude * : 75 w 120 w * in accordance with the line circuitry described (see line circuitry on page 50), measured at the transformer secondary. 2.13 2.7 2.37 3.0 2.61 3.3 v v itu-t g.703 output pulse width at line side of transformer* 219 244 269 ns output pulse width at device pins ttip and tring* 224 244 264 ns positive/negative pulse imbalance: pulse amplitude pulse width C4 C4 1.5 1 4 4 % % zero level (percentage of pulse amplitude) C5 0 5 % return loss ? (120 w): 51 khz to 102 khz 102 khz to 2.048 mhz 2.048 mhz to 3.072 mhz ? using lucent transformer 2795d or 2795c and components in table 30. 9 15 11 db db db ch-ptt return loss ? (75 w): 51 khz to 102 khz 102 khz to 3.072 mhz 7 9 db db ets 300 166: 1993
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 35 lucent technologies inc. microprocessor mode (continued) jitter attenuator (continued) jitter transfer function the jitter transfer function describes the amount of jitter that is transferred from the input to the output over a range of frequencies. the jitter attenuator exhibits a single-pole roll-off (20 db/decade) jitter transfer characteristic that has no peaking and a nominal filter corner frequency (3 db bandwidth) of less than 4 hz for ds1 operation and approximately 10 hz for cept operation. optionally, a lower bandwidth of approximately 1.25 hz can be selected in cept operation by setting jabw0 = 1 (register 12, bit 5) for systems desiring compliance with etsi-tbr12/13 jitter attenuation requirements. when configured to meet etsi-tbr12/13, the clock connected to the xclk input must be 20 ppm. for a given frequency, different jitter amplitudes will cause a slight variation in attenuation because of finite quantization effects. jitter amplitudes of less than approximately 0.2 ui will have greater attenua- tion than the single-pole roll-off characteristic. the jitter transfer curve is independent of data patterns. typical jitter transfer curves of the jitter attenuator are given in figure 11 and figure 13. jitter accommodation the minimum jitter accommodation of the jitter attenuator occurs when the xclk frequency and the input clocks long-term average frequency are at their extreme frequency tolerances. when the jitter attenuator is used in the liu transmit path, the minimum accommodation is 28 uip-p at the highest jitter frequency of 15 khz. typical receiver jitter accommodation curves including the jitter attenuator in the liu receive path are given in figure 10 and figure 12. when the jitter attenuator is placed in the data path, a difference between the xclk/16 frequency and the incoming line rate for receive applications, or the tclk rate for transmit applications, will result in degraded low- frequency jitter accommodation performance. the peak-to-peak jitter accommodation (jap-p) for frequencies from above the corner frequency of the jitter attenuator (fc) to approximately 100 hz is given by the following equation: where: f data = 1.544 mhz for ds1 or 2.048 mhz for cept; for jabw0 = 0, fc = 3.8 hz for ds1 or 10 hz for cept, and for jabw0 = 1, fc = 1.25 hz for cept; d f xclk = xclk tolerance in ppm; d f data = data tolerance in ppm. note that for lower corner frequencies, the jitter accommodation is more sensitive to clock tolerance than for higher corner frequencies. when jabw0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on xclk should be tightened to 20 ppm in order to meet the jitter accommodation requirements of tbr12/13 as given in g.823 for line data rates of 50 ppm. jap-p 64 2f xclk dd f data C () f data 2 p f c ------------------------------------------------------------ C ? ?? ui =
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 36 lucent technologies inc. microprocessor mode (continued) jitter attenuator (continued) jitter attenuator enable the jitter attenuator is selected using the jar and jat bits (register 5, bits 1 and 2) of the microprocessor interface. these control bits are global and affect all four channels unless a given channel is in the power- down mode (pwrdn = 1). because there is only one attenuator function in the device, selection must be made between either the transmit or receive path. if both jat and jar are activated at the same time, the jitter attenuator will be disabled. note that the power consumption increases slightly on a per-channel basis when the jitter attenuator is active. if jitter attenuation is selected, a valid xclk (pin 46) signal must be available. jitter attenuator receive path enable (jar) when the jitter attenuator receive bit is set (jar = 1), the attenuator is enabled in the receive data path between the clock/data recovery and the decoder (see figure 3 on page 19). under this condition, the jitter characteristics of the jitter attenuator apply for the receiver. the receive path will then exhibit the jitter characteristics shown in figure 10 through figure 13. if cdr = 0 (register 5, bit 0), the jar bit is ignored because clock recovery will be disabled. jitter attenuator transmit path enable (jat) when the jitter attenuator transmit bit is set (jat = 1), the attenuator is enabled in the transmit data path between the encoder and the pulse-width controller/ pulse equalizer (see figure 3 on page 19). under this condition, the jitter characteristics of the jitter attenuator apply for the transmitter. when jat = 0, the encoder outputs bypass the disabled attenuator and directly enter the pulse-width controller/pulse equalizer. the transmit path will then pass all jitter from tclk to line interface outputs ttip/tring.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 37 lucent technologies inc. microprocessor mode (continued) jitter attenuator (continued) frequency response curves 5-5264(f)r.8 figure 10. ds1/t1 receiver jitter accommodation with jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 28 ui frequency (hz) 100k tr-tsy-000009 (ds1, muxes) gr-499/1244-core (cat i interfaces) i.431(ds1), g.824(ds1) typical (subject to device characterization) (non-sonet cat ii interfaces) gr-499-core t1.408/i.431(ds1)/g.824(ds1)
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 38 lucent technologies inc. microprocessor mode (continued) jitter attenuator (continued) frequency response curves (continued) 5-5265(f)r.4 figure 11. ds1/t1 jitter transfer of the jitter attenuator 60 40 20 0 1 10 100 1k 10k 50 30 10 100k frequency (hz) jitter out/jitter in (db) ty p i c a l (subject to device characterization) tr-tsy-000009 gr-253-core
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 39 lucent technologies inc. microprocessor mode (continued) jitter attenuator (continued) frequency response curves (continued) 5-5266(f)r.8 figure 12. cept/e1 receiver jitter accommodation with jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 37 ui frequency (hz) g.823 100k typical (subject to device characterization) g.823,etsi-300-011a1 i.431(cept)/ets-300-011 i.431(cept)/ets-300-011 jabw0 = 0 jabw0 = 1
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 40 lucent technologies inc. microprocessor mode (continued) jitter attenuator (continued) frequency response curves (continued) 5-5267(f)r.4 figure 13. cept/e1 jitter transfer of the jitter attenuator frequency (hz) jitter out/jitter in (db) 60 40 20 0 1 10 100 1k 10k 50 30 10 100k ty p i c a l (subject to device characterization) jabw0 = 1 jabw0 = 0 etsi tbr12/13 etsi-300-011 i.431, g.735-9 with jitter reducer g.735-9 at national boundaries
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 41 lucent technologies inc. microprocessor mode (continued) loopbacks the device has three independent loopback paths that are activated using loopa and loopb (registers 69, bits 3 and 4) as shown in table 17. the locations of these loopbacks are illustrated in figure 3 on page 19. table 17. loopback control * during the transmit ais condition, the looped data will be the transmitted data from the system and not the all-ones signal. ? transmit ais request is ignored. full local loopback (flloop) a full local loopback (flloop) connects the transmit line driver input to the receiver analog front-end circuitry. valid transmit output data continues to be sent to the network. if the transmit ais (all-ones signal) is sent to the net- work, the looped data is not affected. the alos alarm continues to monitor the receive line interface signal while dlos monitors the looped data. see digital loss of signal (dlos) alarm section on page 21 regarding the behavior of the dlos alarm upon acti- vation of flloop. remote loopback (rloop) a remote loopback (rloop) connects the recovered clock and retimed data to the transmitter at the system inter- face and sends the data back to the line. the receiver front end, clock/data recovery, encoder/decoder (if enabled) jitter attenuator (if enabled), and transmit driver circuitry are all exercised during this loopback. the transmit clock, transmit data, and xais inputs are ignored. valid receive output data continues to be sent to the system interface. this loopback mode is very useful for isolating failures between systems. see loss of transmit clock (lotc) alarm and transmit driver monitor (tdm) alarm on page 30 regarding the behavior of the lotc and tdm alarms upon activation and deactivation of rloop. digital local loopback (dlloop) a digital local loopback (dlloop) connects the transmit clock and data through the encoder/decoder pair to the receive clock and data output pins at the system interface. this loopback is operational if the encoder/decoder pair is enabled or disabled. the ais signal can be transmitted without any effect on the looped signal. operation symbol loopa loopb normal 0 0 full local loopback flloop* 0 1 remote loopback rloop ? 10 digital local loopback dlloop 1 1
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 42 lucent technologies inc. microprocessor mode (continued) powerdown (pwrdn) each line interface channel has an independent power- down mode controlled by pwrdn (registers 69, bit 0). this provides power savings for systems that use backup channels. if pwrdn = 1, the corresponding channel will be in a standby mode, consuming only a small amount of power. it is recommended that the alarm registers for the corresponding channel be masked with mask = 1 (registers 69, bit 1) during powerdown mode. if a line interface channel in power- down mode needs to be placed into service, the chan- nel should be turned on (pwrdn = 0) approximately 5 ms before data is applied. reset (reset , swreset) the device provides both a hardware reset ( reset ; pin 44) and a software reset (swreset; register 4, bit 1) that are functionally equivalent. int (pin 114) is also cleared. the writable microprocessor interface registers are not affected by reset, with the exception of bits in register 4 (see the global control registers (0100, 0101) section). during a reset condition, data transmission will be interrupted. the reset condition is initiated by setting reset = 0 or swreset = 1 for a minimum of 10 s. after releasing the reset control (reset = 1 or swreset = 0), the device will stay in the reset condition for approximately 2.7 ms to ensure stabilization of the pll. after leaving the reset condition (with reset = 1 or swreset = 0), the bits in register 4 will be reset and may need to be restored. loss of xclk reference clock (loxc) the loxc output (pin 45) is active when the xclk ref- erence clock (pin 46) is absent. the loxc flag is asserted a maximum of 16 s after xclk disappears, and deasserts immediately after detecting the first clock edge of xclk. during the loxc alarm condition, the clock recovery and jitter attenuator functions are automatically dis- abled. therefore, if cdr = 1 and/or jar = 1, the rclk, rpd, rnd, and dlos outputs will be unknown. if cdr = 0, there will be no effect on the receiver. if the jitter attenuator is enabled in the transmit path (jat = 1) dur- ing this alarm condition, then a loss of transmit clock alarm, lotc = 1, will also be indicated. in-circuit testing and driver high-imped- ance state ( ict ) the function of the ict input (pin 43) is determined by the ictmode bit (register 4, bit 3). if ictmode = 0 and ict is activated ( ict = 0), then all output buffers (ttip, tring, rclk, rpd, rnd, loxc, rdy_ dtack , int, ad[7:0]) are placed in a high-impedance state. for in-circuit testing, the reset pin can be used to activate ictmode = 0 without having to write the bit. if ictmode = 1 and ict = 0, then only the ttip and tring outputs of all channels will be placed in a high- impedance state. the ttip and tring outputs have a limiting high-impedance capability of approximately 8k w . liu delay values the transmit coder has 5 ui delay whether it is in the path or not and whether it is b8zs or hdb3. its delay is only removed when in single-rail mode. the remainder of the transmit path has 4.6 ui delay. the receive decoder has 5 ui delay whether it is in the path or not and whether it is b8zs or hdb3. its delay is only removed when in single-rail mode or cdr = 0. the afe (equalizer plus slicer) delay is nearly 0 ui delay. the jitter attenuator delay is nominally 33 ui but can be 2 ui64 ui depending on the state. the dpll used for timing recovery has 8 ui delay.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 43 lucent technologies inc. microprocessor mode (continued) line encoding/decoding alternate mark inversion (ami) the default line code used for t1 is alternate mark inversion (ami). the coding scheme represents a 1 with a pulse or mark on the positive or negative rail and a 0 with no pulse on either rails. this scheme is shown in table 18. table 18. ami encoding the t1 ones density rule requires that in every 24 bits of information to be transmitted, there must be at least three pulses, and no more than 15 zeros may be transmitted consecutively. at&t technical reference 62411 for digital transmissions requires that in every 8 bits of information, at least one pulse must be present. t1-binary 8 zero code suppression (b8zs) clear channel transmission can be accomplished using binary 8 zero code suppression (b8zs). eight consecutive zeros are replaced with the b8zs code. this code consists of two bipolar violations in bit positions 4 and 7 and valid bipolar marks in bit positions 5 and 8. the receiving end recognizes this code and replaces it with the original string of eight zeros. table 19 shows the encoding of a string of zeros using b8zs. b8zs is recommended when esf format is used. table 19. ds1 b8zs encoding high-density bipolar of order 3 (hdb3) the line code used for cept is described in itu rec. g.703 section 6.1 as high-density bipolar of order 3 (hdb3). hdb3 uses a substitution code that acts on strings of four zeros. the substitute hdb3 codes are 000v and b00v, where v represents a violation of the bipolar rule and b represents as inserted pulse conforming to the ami rule defined in itu rec. g.701, item 9004. the choice of the b00v or 000v is made so that the number of b pulses between consecutive v pulses is odd. in other words, successive v pulses are of alternate polarity so that no direct current (dc) component is introduced. the substitute codes follow each other if the string of zeros continues. the choice of the first substitute code is arbitrary. a line code error is defined as a bipolar violation and consists of two pulses of the same polarity that is not defined as one of the two substitute codes. coding violations are indicated as bipolar violations. an example is shown in table 20. table 20. itu hdb3 coding and dcpat binary coding input bit stream 1011 0000 0111 1010 ami data C0+C 0000 0+C+ C0+0 bit positions 12345678 12345678 before b8zs 0000000010100000000 after b8zs 000vb0vbb0b000vb0vb input bit stream 1011 0000 01 0000 0000 0000 0000 hdb3-coded data 1011 000v 01 000v b00v b00v b00v hdb3-coded levels C0+C 000C 0+ 000+ C00C +00+ C00C
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 44 lucent technologies inc. microprocessor mode (continued) registers as shown in table 6 on page 17, the quad liu registers consist of sixteen 8-bit registers (some of which are reserved). register 13 is an index register which must contain the value 00 to access the other 15 liu registers. registers 0 and 1 are the alarm registers used for storing the various device alarm status and are read only. all other registers are read/write. registers 2 and 3 contain the individual mask bits for the alarms in registers 0 and 1. registers 4 and 5 are designated as the global control registers used to set up the functions for all four channels. the channel configuration registers in registers 6 through 9 and register 12 are used to configure the individual channel functions and parameters. registers 10 and 11 must be cleared by the user after a powerup for proper device operation; code3 and code4 may be set as desired. (see table 26 on page 47.) register 13 is the global index register. registers 14 and 15 are reserved for proprietary functions and must not be addressed during oper- ation. the following sections describe these registers in detail. alarm registers (0000, 0001) the bits in the alarm registers represent the status of the transmitter and receiver alarms lotc, tdm, dlos, and alos for all four channels as shown in table 21. the alarm indicators are active-high and automatically clear on a microprocessor read if the corresponding alarm condition no longer exists. persistent alarm conditions will cause the bit to remain set. these are read-only registers. *the numerical suffix identifies the channel number. table 21. alarm registers bits symbol * description alarm register (0) 0, 4 alos[12] analog loss of signal alarm for channels 1 and 2. 1, 5 dlos[12] digital loss of signal alarm for channels 1 and 2. 2, 6 tdm[12] transmit driver monitor alarm for channels 1 and 2. 3, 7 lotc[12] loss of transmit clock alarm for channels 1 and 2. alarm register (1) 0, 4 alos[34] analog loss of signal alarm for channels 3 and 4. 1, 5 dlos[34] digital loss of signal alarm for channels 3 and 4. 2, 6 tdm[34] transmit driver monitor alarm for channels 3 and 4. 3, 7 lotc[34] loss of transmit clock alarm for channels 3 and 4.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 45 lucent technologies inc. microprocessor mode (continued) registers (continued) alarm mask registers (0010, 0011) the bits in the alarm mask registers in table 22 allow the microprocessor to selectively mask each channel alarm and prevent it from generating an interrupt. the mask bits correspond to the alarm status bits in the alarm registers and are active-high to disable the corresponding alarm from generating an interrupt. these registers are read/write registers. *the numerical suffix identifies the channel number. global control registers (0100, 0101) the bits in the global control registers in table 23 and table 24 allow the microprocessor to configure the various device functions over all the four channels. all the control bits (with the exception of losstd and ictmode) are active-high. these are read/write registers. table 22. alarm mask registers bits symbol * description alarm mask register (2) 0, 4 malos[12] mask analog loss of signal alarm for channels 1 and 2. 1, 5 mdlos[12] mask digital loss of signal alarm for channels 1 and 2. 2, 6 mtdm[12] mask transmit driver monitor alarm for channels 1 and 2. 3, 7 mlotc[12] mask loss of transmit clock alarm for channels 1 and 2. alarm mask register (3) 0, 4 malos[34] mask analog loss of signal alarm for channels 3 and 4. 1, 5 mdlos[34] mask digital loss of signal alarm for channels 3 and 4. 2, 6 mtdm[34] mask transmit driver monitor alarm for channels 3 and 4. 3, 7 mlotc[34] mask loss of transmit clock alarm for channels 3 and 4. table 23. global control register (0100) bits symbol description global control register (4) 0 gmask the gmask bit globally masks all the channel alarms when gmask = 1, pre- venting all the receiver and transmitter alarms from generating an interrupt. gmask = 1 after a device reset. 1 swreset the swreset provides the same function as the hardware reset. it is used for device initialization through the microprocessor interface. 2 losstd the losstd bit selects the conformance protocol for the dlos receiver alarm function. 3 ictmode the ictmode bit changes the function of the ict pin. ictmode = 0 after a device reset. 47 highz[14] a highz bit is available for each individual channel. when highz = 1, the ttip and tring transmit drivers for the specified channel are placed in a high-impedance state. highz [14] = 1 after a device reset.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 46 lucent technologies inc. microprocessor mode (continued) registers (continued) global control registers (0100, 0101) (continued) channel configuration and control registers (01101001, 1011, 1100) the control bits in the channel configuration registers in table 25 are used to select equalization, loopbacks, ais generation, channel alarm masking, and the channel powerdown mode for each channel (14). the pwrdn[14], mask[14], and xais[14] bits are active-high. these are read/write registers. control bits for zero substitution coding for channels 14 are listed in table 26 and table 27. * a numerical suffix identifies the channel number. ? channel suffix not shown in the description. table 24. global control register (0101) bits symbol description global control register (5) 0 cdr the cdr bit is used to enable and disable the clock/data recovery function. 1 jar the jar is used to enable and disable the jitter attenuator function in the receive path. the jar and jat control bits are mutually exclusive; i.e., either jar or the jat control bit can be set, but not both. 2 jat the jat is used to enable and disable the jitter attenuator function in the trans- mit path. the jat and jar control bits are mutually exclusive; i.e., either jat or the jar control bit should be set, but not both. 3 code the code bit is used to enable the b8zs/hdb3 zero substitution coding. it is used in conjunction with the dual bit and is valid only for single-rail operation. 4 dual the dual bit is used to select single or dual-rail mode of operation. 5 alm the alm bit selects the transmit and receive data polarity (i.e., active-low or active-high). the alm and acm bits are used together to determine the trans- mit and receive data retiming modes. 6 acm the acm bit selects the positive or negative edge of the receive clock (rclk [14]) for receive data retiming. the acm and alm bits are used together to determine the transmit and receive data retiming modes. 7 lossd the lossd bit selects the shutdown function for the digital loss of signal alarm (dlos). table 25. channel configuration registers (01101001) bits symbol * description ? channel configuration registers (69) 0 pwrdn[14] the pwrdn bit powers down a channel when not used. 1 mask[14] the mask bit masks all interrupts for the channel. 2 xais[14] the xais bit enables transmission of an all-ones signal to the line inter- face. 3 4 loopb[14] loopa[14] the loopb and loopa bits select the channel loopback modes. 5 6 7 eqc[14], eqb[14], eqa[14] the eqc, eqb, and eqa bits select the type of service (ds1 or cept) and the associated transmitter cable equalization/termination imped- ances.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 47 lucent technologies inc. microprocessor mode (continued) registers (continued) channel configuration and control registers (01101001, 1011, 1100 ) (continued) * a numerical suffix identifies the channel number. table 26. channel configuration register (1011) bits symbol * * a numerical suffix identifies the channel number. description channel configuration register (11) 03 reserved. write to 0. 4 code4 the code4 bit selects b8zs/hdb3 encoding (transmit) and decoding (receive) in channel 4. 5 reserved. write to 0. 6 code3 the code3 bit selects b8zs/hdb3 encoding (transmit) and decoding (receive) in channel 3. 7 reserved. write to 0. table 27. control register (1100) bit symbol * description control register (12) 0altimer the altimer bit is used to select the time required to declare alos. altimer = 0 selects 1 ms2.6 ms. altimer = 1 selects 10 bit255 bit periods. 1 rcvais the rcvais bit selects the shutdown function for the receiver during analog loss of signal alarm (alos). rcvais operates in conjunction with the lossd bit. 2 pflalm the pflalm prevents the dlos alarm from occurring during flloop activation. 3prlalm the prlalm prevents the lotc alarm from occurring during rloop activation/ deactivation. 4phizalm the phizalm prevents the tdm alarm from occurring when the driver is in a high- impedance state. 5 jabw0 the jabw0 bit selects the lower bandwidth jitter attenuator option in cept mode. 6 code2 the code2 bit selects b8zs/hdb3 encoding (transmit) and decoding (receive) in channel 2. 7 code1 the code1 bit selects b8zs/hdb3 encoding (transmit) and decoding (receive) in channel 1.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 48 lucent technologies inc. microprocessor mode (continued) xclk reference clock the device requires an externally applied clock, xclk (pin 46), for the clock and data recovery function and the jit- ter attenuation option. xclk must be a continuously active (i.e., ungapped, unjittered, and unswitched) and an independent reference clock such as from an external system oscillator or system clock for proper operation. it must not be derived from any recovered line clock (i.e., from rclk or any synthesized frequency of rclk). xclk may be supplied in one of four formats; 16x ds1, ds1, 16x cept, or cept. the format is selected globally for the device by clks (pin 117) and clkm (pin 116). clks determines the relationship between the primary line data rate and the clock signal applied to xclk. for clks = 0, a clock at 16x the primary line data rate clock (24.704 mhz for ds1 and 32.768 mhz for cept) must be applied to xclk. for clks = 1, a primary line data rate clock (1.544 mhz for ds1 and 2.048 mhz for cept) must be applied to xclk. the clks pin has an internal pull-down resistor allowing the pin to be left open, i.e., a no connect, in applications using a 16x reference clock. the clks pin must be pulled up to v dd for applications using a primary line data rate clock. clkm determines whether the clock synthesizer is operating in cept or ds1 mode when xclk is a primary line data rate clock. for clkm = 0, the clock synthesizer operates in ds1 mode (1.544 mhz). for clkm = 1, the clock synthesizer operates in cept mode (2.048 mhz). the clkm pin is ignored when clks = 0. the clkm pin has an internal pull-down resistor allowing the pin to be left open, i.e., a no connect, in applications using a ds1 line rate reference clock. the clkm pin must be pulled up to v dd for applications using a cept line data rate clock. 16x xclk reference clock the specifications for xclk using a 16x reference clock are defined in table 28. the 16x reference clock is selected when clks = 0. table 28. xclk (16x, clks = 0) timing specifications * when jabw0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on xclk should be tightened to 20 pp m in order to meet the jitter accommodation requirements of tbr12/13 as given in g.823 for line data rates of 50 ppm. ? if xclk is used as the source for ais (see alarm indication signal generator (xais) on page 30), it must meet the nominal trans mission specifications of 1.544 mhz 32 ppm for ds1 (t1) or 2.048 mhz 50 ppm for cept (e1). parameter value unit min typ max frequency: ds1 cept 24.704 32.768 mhz mhz range*, ? C100 100 ppm duty cycle 40 60 %
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 49 lucent technologies inc. microprocessor mode (continued) xclk reference clock (continued) primary line rate xclk reference clock and internal reference clock synthesizer in some applications, it is more desirable to provide a reference clock at the primary data rate. in such cases, the liu can utilize an internal 16x clock synthesizer allowing the xclk pin to accept a primary data rate clock. the specifications for xclk using a primary rate reference clock are defined in table 29. table 29. xclk (1x, clks = 1) timing specifications * when jabw0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on xclk should be tightened to 20 pp m in order to meet the jitter accommodation requirements of tbr12/13 as given in g.823 for line data rates of 50 ppm. ? if xclk is used as the source for ais (see alarm indication signal generator (xais) on page 30), it must meet the nominal trans mission specifications of 1.544 mhz 32 ppm for ds1 (t1) or 2.048 mhz 50 ppm for cept (e1). the data rate reference clock and the internal clock synthesizer are selected when clks = 1. in this mode, a valid and stable data rate reference clock must be applied to the xclk pin before and during the time a hardware reset is activated (reset = 0). the reset must be held active for a minimum of two data rate clock periods to ensure proper resetting of the clock synthesizer circuit. upon the deactivation of the reset pin (reset = 1), the liu will extend the reset condition internally for approximately 1/2(2 12 C 1) line clock periods, or 1.3 ms for ds1 and 1 ms for cept after the hardware reset pin has become inactive, allowing the clock synthesizer additional time to settle. no activity such as microprocessor read/write should be performed during this period. the device will be operational 2.7 ms after the deactivation of the hardware reset pin. issuing an liu software restart (liu_reg2 bit 5 (restart) = 1) does not impact the clock synthesizer circuit. power supply bypassing external bypassing is required for all channels. a 1.0 f capacitor must be connected between v ddx and gnd x . in addition, a 0.1 f capacitor must be connected between v ddd and gnd d , and a 0.1 f capacitor must be con- nected between v dda and gnd a . ground plane connections are required for gnd x , gnd d , and gnd a . power plane connections are also required for v ddx and v ddd . the need to reduce high-frequency coupling into the ana- log supply (v dda ) may require an inductive bead to be inserted between the power plane and the v dda pin of every channel. capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum effectiveness. parameter value unit min typ max frequency: ds1 cept 1.544 2.048 mhz mhz range*, ? C100 100 ppm duty cycle 40 60 % rise and fall times (10%90%) 5 ns
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 50 lucent technologies inc. microprocessor mode (continued) line circuitry the transmit and receive tip/ring connections provide a matched interface to the cable (i.e., terminating impedance matches the characteristic impedance of the cable). the diagram in figure 14 shows the appropriate external com- ponents to interface to the cable for a single transmit/receive channel. the component values are summarized in table 30, based on the specific application. 5-3693(f).d figure 14. line termination circuitry table 30. termination components by application resistor tolerances are 1%. transformer turns ratio tolerances are 2%. 1. use lucent 2795b transformer. 2. for cept 75 w applications, option 1 is recommended over option 2 for lower device power dissipation. option 2 increases power dissipa- tion by 13 mw per channel when driving 50% ones data. option 2 allows for the use of the same transformer as in cept 120 w applica- tions. 3. use lucent 2795d transformer. 4. use lucent 2795c transformer. 5. a 5% tolerance is allowed for the transmit load termination, r l . symbol name cable type unit ds1 1 twisted pair cept 75 w 2 coaxial cept 120 w 4 twisted pair option 1 3 option 2 4 c c center tap capacitor 0.1 0.1 0.1 0.1 m f r p receive primary impedance 200 200 200 200 w r r receive series impedance 71.5 28.7 59 174 r s receive secondary impedance 113 82.5 102 205 z eq equivalent line termination 100 75 75 120 tolerance 4 4 4 4 % r t transmit series impedance 0 26.1 15.4 26.1 w r l transmit load termination 5 100 75 75 120 n transformer turns ratio 1.14 1.08 1.36 1.36 rtip rring ttip tring device (1 channel) r l r s r r r r receive data r p z eq r t r t n:1 transmit data transformer equipment interface 1:n c c
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 51 lucent technologies inc. microprocessor mode (continued) absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this device specification. exposure to absolute maximum rat- ings for extended periods can adversely affect device reliability. table 31. absolute maximum ratings handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in the defined model. no industry-wide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters. operating conditions parameter min max unit dc supply voltage C0.5 6.5 v storage temperature C65 125 c maximum voltage (digital pins) with respect to v ddd 0.5v minimum voltage (digital pins) with respect to gnd d C0.5 v maximum allowable voltages (rtip[14], rring[14]) with respect to v dd 0.5v minimum allowable voltages (rtip[14], rring[14]) with respect to gnd C0.5 v table 32. esd threshold voltage device model voltage TLIU04C1 hbm tbd cdm (corner pins) tbd cdm (noncorner pins) tbd table 33. recommended operating conditions parameter symbol min typ max unit ambient temperature t a C40 85 c power supply v dd 4.75 5.0 5.25 v
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 52 lucent technologies inc. microprocessor mode (continued) power requirements the majority of the power used by the TLIU04C1 device is used by the line drivers. therefore, the power is very dependent on data pattern and signal amplitude. the signal amplitude is a function of the transmit equalization in ds1 mode. when configured for greater cable loss, the signal amplitude is greater at the output drivers, and thus uses more power. for this reason, the power specification of table 34 are given for various conditions. the typical specification is for a quasi-random signal and the maximum specification is for a mark (all ones) pattern. the power also varies somewhat for ds1 versus cept, so figures are given for both. table 34. power consumption power dissipation is the amount of power dissipated in the device. it is equal to the power drawn by the device minus the power dissipated in the line. table 35. power dissipation electrical characteristics parameter power unit typ max cept tbd tbd mw ds1 tbd tbd mw ds1 with max eq. tbd tbd mw parameter power unit typ max cept tbd tbd mw ds1 tbd tbd mw ds1 with max eq. tbd tbd mw table 36. logic interface characteristics note: the following internal resistors are provided: 50 k w pull-up on the ict and reset pins, 50 k w pull-down on the clks and clkm pins, and 100 k w pull-up on the cs , and xclk pins. this requires these input pins to sink no more than 20 a. the device uses ttl input and output buffers; all buffers are cmos-compatible. parameter symbol test conditions min max unit input voltage: low high v il v ih gnd d 2.1 0.8 v ddd v v input leakage i l 10a output voltage: low high v ol v oh i ol = C5.0 ma i oh = 5.0 ma gnd d v ddd C 0.5 0.4 v ddd v v input capacitance c i 3.0pf load capacitance * * 100 pf allowed for ad[7:0] (pins 7582). c l 50 pf
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 53 lucent technologies inc. microprocessor mode (continued) microprocessor interface timing the i/o timing specifications for the microprocessor interface are given in table 37 and shown in figures 1522. the microprocessor interface pins use cmos i/o levels. all outputs, except the address/data bus ad[7:0], are rated for a capacitive load of 50 pf. the ad[7:0] outputs are rated for a 100 pf load. the minimum read and write cycle time is 200 ns for all device configurations. the read and write timing diagrams for all four microprocessor interface modes are shown in figures 1522. table 37. microprocessor interface i/o timing specifications symbol configuration parameter setup (ns) (min) hold (ns) (min) delay (ns) (max) t1 modes 1 and 2 as asserted width 10 t2 address valid to as asserted 10 t3 as asserted to address invalid 10 t4 cs asserted to as asserted 10 t5 r/w valid to ds asserted 5 t6 as asserted to ds asserted 30 t7 cs asserted to dtack high 25 t8 ds asserted to dtack asserted 20 t9 ds asserted to data valid 50 t10 ds deasserted to cs deasserted 15 t11 ds deasserted to r/w invalid 5 t12 ds deasserted to dtack deasserted 20 t13 cs deasserted to dtack high impedance 10 t14 ds deasserted to data invalid 5 t15 r/w valid to ds asserted 5 t16 as asserted to ds asserted 10 t17 ds asserted width 5 t18 data valid to ds asserted 5 t19 ds deasserted to data invalid 10 t20 ds asserted to dtack asserted 20 t21 address valid to as asserted 10 t22 as asserted to address invalid 10
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 54 lucent technologies inc. microprocessor mode (continued) microprocessor interface timing (continued) table 37. microprocessor interface i/o timing specifications (continued) the read and write timing diagrams for all four microprocessor interface modes are shown in figures 1522. symbol configuration parameter setup (ns) (min) hold (ns) (min) delay (ns) (max) t23 modes 3 and 4 ale asserted width 10 t24 address valid to ale asserted 10 t25 ale asserted to address invalid 10 t26 cs asserted to ale asserted 10 t27 ale asserted to rd asserted 30 t28 cs asserted to rdy low 20 t29 falling edge of mpclk to rdy asserted 25 t30 rd asserted to data valid 50 t31 rd deasserted to data invalid 5 t32 rd deasserted to rdy deasserted 20 t33 rd deasserted to cs deasserted 15 t34 cs deasserted to rdy high impedance 10 t35 ale asserted to wr asserted 10 t36 wr asserted width 5 t37 data valid to wr asserted 5 t38 wr deasserted to data invalid 10 t39 wr deasserted to rdy deasserted 20 t40 wr deasserted to cs deasserted 15 t41 rising edge of mpclk to rdy asserted 25 t42 address valid to ale asserted 10 t43 ale asserted to address invalid 10
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 55 lucent technologies inc. microprocessor mode (continued) microprocessor interface timing (continued) 5-7192(f)r.2 figure 15. mode 1read cycle timing (mpmode = 0, mpmux = 0) 5-7193(f)r.3 figure 16. mode 1write cycle timing (mpmode = 0, mpmux = 0) t4 t1 t3 t6 t5 t8 t7 t9 t14 t12 t13 t10 t11 valid data cs as a[3:0] r/w ds dtack ad[7:0] t2 valid address t4 t1 t3 t7 t19 t12 t13 t10 t11 valid data cs as a[3:0] r/w ds dtack ad[7:0] t2 valid address t16 t15 t17 t20 t18
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 56 lucent technologies inc. microprocessor mode (continued) microprocessor interface timing (continued) 5-7194(f)r.3 figure 17. mode 2read cycle timing (mpmode = 0, mpmux = 1) 5-7195(f)r.4 figure 18. mode 2write cycle timing (mpmode = 0, mpmux = 1) t4 t1 t7 t14 t12 t10 t11 valid data cs as r/w ds dtack ad[7:0] t13 valid address t6 t21 t22 t5 t9 t8 t4 t1 t7 t18 t19 t12 t10 t11 valid data cs as r/w ds dtack ad[7:0] t13 valid address t16 t17 t20 t21 t22 t15
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 57 lucent technologies inc. microprocessor mode (continued) microprocessor interface timing (continued) 5-7196(f)r.3 figure 19. mode 3read cycle timing (mpmode = 1, mpmux = 0) 5-7197(f)r.3 figure 20. mode 3write cycle timing (mpmode = 1, mpmux = 0) cs ale a[3:0] rd rdy ad[7:0] mpclk valid address valid data t26 t23 t24 t25 t27 t28 t29 t30 t31 t32 t33 t34 cs ale a[3:0] wr rdy ad[7:0] mpclk valid address valid data t26 t23 t24 t25 t35 t28 t41 t37 t38 t39 t40 t34 t36
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 58 lucent technologies inc. microprocessor mode (continued) microprocessor interface timing (continued) 5-7198(f)r.2 figure 21. mode 4read cycle timing (mpmode = 1, mpmux = 1) 5-7199(f)r.5 figure 22. mode 4write cycle timing (mpmode = 1, mpmux = 1) cs ale rd rdy ad[7:0] mpclk valid data t26 t23 t27 t28 t29 t30 t31 t32 t34 t33 valid address t42 t43 cs ale wr rdy ad[7:0] mpclk valid data t26 t23 t35 t41 t37 t39 t34 t40 valid address t42 t36 t43 t38 t28
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 59 lucent technologies inc. microprocessor mode (continued) data interface timing * refers to each individual bit period for jat = 0 applications. ? refers to each individual bit period for jat = 1 applications using a gapped tclk. 5-1156(f).br.3 * invert rclk for acm = 1. figure 23. interface data timing (acm = 0) table 38. data interface timing note: the digital system interface timing is shown in figure 23 for acm = 0. if acm = 1, then the rclk signal in figure 23 will be inverted. symbol parameter min typ max unit ttcltcl average tclk clock period: ds1 cept 647.7 488.0 ns ns ttdc tclk duty cycle* tclk minimum high/low time ? 30 100 70 % ns ttdvtcl transmit data setup time 50 ns ttcltdx transmit data hold time 40 ns ttch1tch2 clock rise time (10%/90%) 40 ns ttcl2tcl1 clock fall time (90%/10%) 40 ns trchrcl rclk duty cycle 45 50 55 % trdvrch receive data setup time 140 ns trchrdx receive data hold time 180 ns trclrdv receive propagation delay 40 ns tclk-liu tpd-liu or tnd-liu rclk-liu* rpd-liu or rnd-liu ttch1tch2 ttcl2tcl1 ttdvtcl ttcltdx trclrdv trdvrch trchrdx ttcltcl
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 60 lucent technologies inc. direct logic control mode overview the TLIU04C1 device has the ability to operate in either a microprocessor mode or a direct logic control mode. the cmode pin is used to determine the operating mode. to configure the device for direct logic control mode, the cmode pin is pulled low. the device is equipped with direct logic control of the line interface configuration and options so that connection to a microprocessor is not required. control of the various functions is accomplished by providing a logic high or low at the control pins. functions such as e1/t1 modes, equalizer settings, diagnostic loopbacks, test modes, system interface timing and polarity, and standards compliance options are controlled in this manner. alarm conditions are also indicated by output levels directly on device pins. device overview the TLIU04C1 is a four-channel device. the lius convert bipolar line data pulses into logic level terminal data, with options for timing for jitter attenuation, equalization, zero bit coding, loopbacks, and other functions.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 61 lucent technologies inc. direct logic control mode (continued) pin information 5-3684(f).b figure 24. TLIU04C1 direct logic control mode pin diagram gndd vdda1 rtip1 rring1 gnda1 rnd1/bpv1 rpd1/rdata1 dlos2 tdm2 lotc2 vddd gndd almt2 xais2 tclk2 tpd2/tdata2 tnd2/code2 rclk2 rpd2/rdata2 rnd2/bpv2 gnda2 rring2 rtip2 vdda2 gndx2 tring2 vddx2 ttip2 gndx2 flloop2 reset loxc xclk vddd gndd pwrdn2 36 37 gndd pwrdn3 eqc3 eqb3 eqa3 dlloop3 rloop3 flloop3 gndx3 ttip3 vddx3 tring3 gndx3 vdda3 rtip3 rring3 gnda3 rnd3/bpv3 rpd3/rdata3 rclk3 tnd3/code3 tpd3/tdata3 tclk3 xais3 rloop2 dlloop2 eqb2 eqc2 rcvais altimer losstd lossd ict almt3 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 pwrdn4 eqc4 eqb4 eqa4 dlloop4 rloop4 flloop4 gndx4 ttip4 vddx4 tring4 gndx4 vdda4 rtip4 rring4 gnda4 rnd4/bpv4 rpd4/rdata4 tnd4/code4 rclk4 tpd4/tdata4 tclk4 xais4 almt4 gndd vddd lotc4 tdm4 dlos4 alos4 alos3 dlos3 tdm3 lotc3 vddd gndd 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 almt1 gndx1 tring1 vddx1 ttip1 gndx1 flloop1 rloop1 dlloop1 eqa1 eqb1 eqc1 pwrdn1 gndd vddd cmode clks clkm acm alm nc dual jat alos2 alos1 dlos1 tdm1 lotc1 vddd xais1 tclk1 tpd1/tdata1 tnd1/code1 rclk1 jar gndd eqa2 jabw0
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 62 lucent technologies inc. direct logic control mode (continued) pin information (continued) table 39. pin descriptions * i = input, o = output, i u indicates an input with internal pull-up; i d indicates an input with internal pull-down, p = power. resistance value of all internal pull-ups or pull-downs is 50 k w , unless otherwise specified. pin symbol type * qty name/description 117 clks i d 1 xclk select. this pin selects either a 16x line rate clock for xclk (clks = 0) or a primary line rate clock for xclk (clks = 1). 116 clkm i d 1 xclk mode. this pin sets the mode when using a primary line rate clock for xclk. cept: clkm = 1 ds1: clkm = 0 130, 27, 58, 99 v ddx [14] p 4 power supply for line drivers. the device requires a 5 v 5% power supply on these pins. 128, 132, 25, 29, 56, 60, 97, 101 gnd x [14] p 8 ground reference for line drivers. 129, 28, 57, 100 ttip[14] o 4 transmit bipolar tip. positive bipolar transmit data to the analog line interface. 131, 26, 59, 98 tring[14] o 4 transmit bipolar ring. negative bipolar transmit data to the analog line interface. 133, 24, 61, 96 v dda [14] p 4 power supply for analog circuitry. the device requires a 5 v 5% power supply on these pins. 136, 21, 64, 93 gnd a [14] p 4 ground reference for analog circuitry. 134, 23, 62, 95 rtip[14] i 4 receive bipolar tip. positive bipolar receive data from the analog line interface. 135, 22, 63, 94 rring[14] i 4 receive bipolar ring. negative bipolar receive data from the analog line interface. 142, 15, 70, 87 tclk[14] i 4 transmit clock. ds1 (1.544 mhz 32 ppm) or cept (2.048 mhz 50 ppm) clock signal from the terminal equipment. 141, 16, 69, 88 tpd/ tdata[14] i d 4 transmit data positive rail/transmit data. if dual = 0, this pin is used as 1.544 mbits/s or 2.048 mbits/s unipolar input data. if dual = 1, this pin is used as the transmit data positive rail. 140, 17, 68, 89 tnd/ code[14] i d 4 transmit data negative rail/substitution code enable. if dual = 0, this pin is set to insert a b8zs/hdb3 substitution code (per eqa, eqb, eqc) on the transmit side and to remove the substitution code on the receive side. if dual = 1, this pin is used as the transmit data negative rail. 139, 18, 67, 90 rclk[14] o 4 receive clock. this signal is the receive clock recovered from the line data. the duty cycle of rclk is 50% 5%. 138, 19, 66, 91 rpd/ rdata[14] o4 receive data positive rail/receive data. if dual = 0, this pin is used as 1.544 mbits/s or 2.048 mbits/s unipolar output data with a 100% duty cycle. if dual = 1, this pin is used to receive data positive rail.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 63 lucent technologies inc. direct logic control mode (continued) pin information (continued) table 39. pin descriptions (continued) * i = input, o = output, i u indicates an input with internal pull-up; i d indicates an input with internal pull-down, p = power. resistance value of all internal pull-ups or pull-downs is 50 k w , unless otherwise specified. ? only one loopback mode can be enabled at a time. enabling more than one results in all being deactivated. pin symbol type * qty name/description 137, 20, 65, 92 rnd/ bpv[14] o4 receive data negative rail/bipolar violation. if dual = 0 (single- rail mode), this pin will be asserted (1 for alm = 0, 0 for alm = 1) for one bit period after detection of a bipolar coding violation on the receive analog data (rtip, rring). if dual = 1, this pin is used as the receive data negative rail. 6, 7, 78, 79 alos [14] o 4 analog loss of signal (active-low). this pin is asserted low when the data signal at the receiver inputs falls below a threshold level. the pin is deasserted high when the signal rises above another, slightly higher threshold. the difference between these threshold levels provides hysteresis to prevent alarm chatter. 5, 8, 77, 80 dlos [14] o 4 digital loss of signal (active-low). guarantees the receive signal quality as defined in the appropriate ansi, bellcore, and itu standards. during ds1 operation, dlos is asserted low if 100 or more consecutive zeros occur in the receive data stream. in cept operation, dlos is asserted low when 255 or more consecutive zeros occur in the receive data stream. the pin is deasserted high when a ones density greater than 12.5% is detected over the 100 or 255 pulse positions. 4, 9, 76, 81 tdm [14] o 4 transmit drive monitor (active-low). transmit driver monitor detects two conditions: a nonfunctional link due to faults on the primary of the transmit transformer, and periods of no data transmission. tdm = 0 for active alarm. 3, 10, 75, 82 lotc [14] o 4 loss of transmit clock (active-low). lotc = 0 when there is a loss of any of the clocks in the transmit path including the tclk input, rclk in remote loopback, jitter attenuator output clock (when enabled), or the pulse-width controller clock. 45 loxc o 1 loss of xclk. this pin is asserted high when the xclk signal is not present. 144, 13, 72, 85 almt [14] i u 4 alarm test enable (active-low). for almt = 0, alarm pins are forced as follows; dlos = 0, alos = 0, tdm = 0, lotc = 0, and bpv = activate state per alm. loxc is forced high if almt is asserted for all four channels. almt does not affect data transmission. 127, 30, 55, 102 flloop [14] i u 4 full local loopback enable (active-low). ? this pin is cleared for a full local loopback (transmit converter output to receive converter input). most of the transmit and receive analog circuitry is exercised in this loopback. 126, 31, 54, 103 rloop [14] i u 4 remote loopback enable (active-low). ? this pin is cleared for a remote loopback (dsx to dsx). in remote loopback, a high on xais inserts the ais signal on the transmit side. 125, 32, 53, 104 dlloop [14] i u 4 digital local loopback enable (active-low). ? this pin is cleared for a digital local loopback. only the transmit and receive digital sections are exercised in this loopback.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 64 lucent technologies inc. direct logic control mode (continued) pin information (continued) table 39. pin descriptions (continued) * i = input, o = output, i u indicates an input with internal pull-up; i d indicates an input with internal pull-down, p = power. resistance value of all internal pull-ups or pull-downs is 50 k w , unless otherwise specified. pin symbol type * qty name/description 124, 33, 52, 105 eqa[14] i d 4 equalizer control a. one of three control pins for selecting transmit equalizers and ds1/cept mode. see table 45. 123, 34, 51, 106 eqb[14] i d 4 equalizer control b. one of three control pins for selecting transmit equalizers and ds1/cept mode. see table 45. 122, 35, 50, 107 eqc[14] i d 4 equalizer control c. one of three control pins for selecting transmit equalizers and ds1/cept mode. see table 45. 46 xclk i u 1 reference clock . a valid reference clock must be provided at this input. xclk must be an independent, continuously active, 50% duty cycle, ungapped, and unjittered clock to guarantee device performance specifications. xclk has an internal 100 k w pull-up resistor. see table 54. 143, 14, 71, 86 xais[14] i d 4 transmit ais. this pin is set to insert the alarm indication signal (all ones) on the transmit line interface. this control has priority over a remote loopback if both are operated simultaneously. 39 rcvais i d 1 receive ais. this pin selects the shutdown function for the receiver during analog and digital loss of signal. rcvais operates in conjunction with lossd. see table 42. 42 lossd i d 1 loss of signal shutdown control. this pin selects the shutdown function for the receiver during analog and digital loss of signal. lossd operates in conjunction with rcvais. see table 42. 41 losstd i d 1 digital loss of signal standard selection. the losstd pin selects the standard that is followed to deactivate a digital loss of signal in ds1 mode. for losstd = 0, dlos is deactivated when the average ones density is at least 12.5% over 100 contiguous pulse positions (t1m1.3/93-005, itu-t g775). for losstd = 1, an additional constraint of less than 15 consecutive zeros is required along with the 12.5% ones density (tr-tsy-000009). the losstd pin has no effect in cept mode, which requires 12.5% ones density over 255 contiguous pulse positions (itu-t g.775). 40 altimer i d 1 analog loss of signal timer. this pin selects the time required to detect an analog loss of signal. for altimer = 0, alos is declared between 1 ms and 2.6 ms after losing signal as required by i.431(3/93) and etsi-300-233 (5/94). for altimer = 1, alos is declared between 10 and 255 bit symbol periods after losing signal as required by g.775 (11/95). 121, 36, 49, 108 pwrdn[14] i d 4 powerdown enable. when this pin is activated (pwrdn = 1), the circuitry of the channel is put into a standby mode in which minimal power is consumed.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 65 lucent technologies inc. direct logic control mode (continued) pin information (continued) table 39. pin descriptions (continued) * i = input, o = output, i u indicates an input with internal pull-up; i d indicates an input with internal pull-down, p = power. resistance value of all internal pull-ups or pull-downs is 50 k w , unless otherwise specified. pin symbol type * qty name/description 111 jat i d 1 jitter attenuator in the transmit path. setting jat = 1 enables the jitter attenuator in the transmit path for all four channels. setting jat = 0 disables the jitter attenuator in the transmit path. if both jat = 1 and jar = 1, the jitter attenuator is disabled. 110 jar i d 1 jitter attenuator in the receive path. setting jar = 1 enables the jitter attenuator in the receive path for all four channels. setting jar = 0 disables the jitter attenuator in the receive path. if both jat = 1 and jar = 1, the jitter attenuator is disabled. 118 cmode i d 1 chip mode. this pin sets the chip mode for either direct logic mode or microprocessor mode. microprocessor: cmode = 1 direct logic: cmode = 0 38 jabw0 i d 1 jitter attenuator bandwidth adjust. setting this pin selects the lower bandwidth jitter attenuator option in cept mode, lowering the bandwidth from 10 hz to 1.25 hz. when this option is used, xclk must be 20 ppm. see table 54. 114 alm i d 1 alternate logic mode (alm). if alm = 0, the receiver circuitry (and transmit input) assumes the data to be active-low polarity. if alm = 1, the data is assumed to be active-high polarity. 115 acm i d 1 alternate clock mode (acm). the alternate clock mode control pin selects the positive or negative clock edge of the receive clock (rclk) for receiver data retiming. for acm = 1, the receive data is retimed on the positive edge of the receive clock. when acm = 0, the receive data is retimed on the negative edge of the receive clock. (this does not affect transmit clock timing.) see figure 38. 112 dual i d 1 dual-rail mode select. this pin is cleared (dual = 0) for single- rail mode and set (dual = 1) for dual-rail mode. 44 reset i u 1 hardware reset (active-low). if reset is forced low, all internal states in the transceiver paths are reset and data flow through each channel will be momentarily disrupted. the reset pin must be held low for a minimum of 1 ms. 43 ict i u 1 high-impedance mode (active-low). when ict = 0, all output buffers (ttip, tring, rclk, rpd, rnd, loxc, lotc , tdm , dlos , alos ) are placed in a high-impedance state. ttip and tring outputs have a limited high-impedance capability of approximately 8 k w . 2, 11, 47, 74, 83, 119 v ddd p6 power supply for digital circuitry. 1, 12, 37, 48, 73, 84, 109, 120 gnd d p8 ground reference for digital circuitry. 113 nc 1 no connect.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 66 lucent technologies inc. direct logic control mode (continued) system interface pin options the system interface can be configured to operate in a number of different modes. the different modes change the functionality of the system interface pins, as shown in table 40. dual-rail or single-rail operation is possible using the dual control pin (pin 112). dual-rail mode is enabled when dual = 1; single-rail mode is enabled when dual = 0. in dual-rail operation, data received from the line interface on rtip and rring appears on rpd and rnd at the system interface and data transmitted from the system interface on tpd and tnd appears on ttip and tring at the line interface. in single-rail operation, data received from the line interface on rtip and rring appears on rdata at the system interface and data transmitted from the system interface on tdata appears on ttip and tring at the line interface. in single-rail mode only, tnd is not needed for data and is used for controlling the b8zs/hdb3 encoding/decoding. the coding may be selected by pulling the code pins high. rnd is also not needed for data in single-rail mode, and is used for indicating bipolar violations. when a coding violations occurs, the bpv pin is asserted according to the alm setting (pin 114). table 40. system interface pin mapping configuration rpd/rdata rnd/bpv tpd/tdata tnd/code single-rail mode (dual = 0) rdata bpv tdata code dual-rail mode (dual = 1) rpd rnd tpd tnd
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 67 lucent technologies inc. direct logic control mode (continued) block diagrams 5-7823(f) figure 25. TLIU04C1 block diagram, cmode = 0 (direct logic mode) ttip[14] tring[14] quad line interface unit rtip[14] rring[14] quad transmit section quad receive section reset clock multiplier xclk lotc [14] tdm [14] dlos [14] alos [14] xais[14] almt [14] pwrdn[14] flloop [14] rloop [14] eqa[14] eqb[14] eqc[14] clks clkm tclk[14] tpd[14] acm alm dual jat jar jabw0 rcvais losstd lossd ict loxc rclk[14] rnd[14] rpd[14] altimer tnd[14] dlloop [14]
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 68 lucent technologies inc. direct logic control mode (continued) block diagrams (continued) the line interface block diagram is shown in figure 26. for illustration purposes, only one of the four on-chip line interfaces is shown. pin names that apply to all four channels are followed by the designation [14]. 5-4556(f).er.3 figure 26. block diagram of the quad line interface unit (single channel) rtip[14] rring[14] flloop (no liu ais) equalizer slicers clock and data recovery dlos rnd[14] rpd[14] rclk[14] decoder dlloop rloop tclk[14] tnd[14] jitter (receive path) tpd[14] flloop (during liu ais) pulse- width controller tdm lotc pulse equalizer transmit driver ttip[14] tring[14] loss of xclk monitor divide by 16 alarm signal (ais) encoder alos indication at t e n uato r jitter (transmit path) at t e n uato r (clock) (data) loss of tclk loxc xclk 16x clock multiplier clks intxclk
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 69 lucent technologies inc. direct logic control mode (continued) data recovery the receive line interface unit (rliu) format is bipolar alternate mark inversion (ami). the data rate tolerance is 130 ppm (ds1) or 80 ppm (cept). the receiver first restores the incoming data and detects analog loss of signal. subsequent processing is optional and depends on the programmable device configuration established with the use of the direct logic control pins. the rliu utilizes an equalizer to operate on line length with up to 15 db of loss at 772 khz (ds1) or 13 db loss at 1.024 mhz (cept). the signal is then peak- detected and sliced to produce digital representations of the data. clock and data recovery, digital loss of signal, jitter attenuation, and data decoding are performed. the receive digital output format is non-return-to-zero (nrz) with selectable dual-rail or single-rail system interface. the clock is recovered by a digital phase-locked loop that uses xclk as a reference to lock to the data rate component. because the internal reference clock is a multiple of the received data rate, the rclk output will always be a valid ds1/cept clock that eliminates false-lock conditions. during periods with no receive input signal, the free-run frequency of rclk is defined to be either xclk/16 or xclk, depending on the state of clks. rclk is always active with a duty-cycle cen- tered at 50%, deviating by no more than 5%. valid data is recovered within the first few bit periods after the application of xclk. the delay of the data through the receive circuitry is approximately 1 to 14 bit peri- ods, depending on the code configurations. additional delay is introduced if the jitter attenuator is selected for operation in the receive path (see the liu delay values section, page 89). jitter accommodation and jitter transfer without the jitter attenuator the rliu is designed to accommodate large amounts of input jitter. the rlius jitter performance exceeds the requirements shown in the rliu specifications tables (table 43 and table 44). typical receiver perfor- mance without the jitter attenuator in the path is shown in figure 27 through figure 30. jitter transfer is inde- pendent of input ones density on the line interface. receiver configuration modes clock/data recovery mode (cdr) the clock/data recovery function in the receive path can be bypassed by setting the flloop , rloop and dlloop pins for all channels low. any other combina- tion of the twelve loopback pins results in the clock and data recovery function being enabled and providing a recovered clock (rclk) with retimed data (rpd/ rdata, rnd). if all twelve of the loopback pins are asserted, the clock and data recovery function is dis- abled, and the rz data from the slicers is provided over rpd and rnd to the system. in this mode, down- stream functions selected by the jar, acm, and lossd pins are ignored. zero substitution decoding (code) when single-rail operation is selected with dual = 0, the b8zs/hdb3 decoding can be selected. code[1 4] pulled high selects the b8zs/hdb3 decoding opera- tion for each individual channel. note: encoding and decoding are not independent. selecting b8zs/hdb3 decoding in the receiver selects b8zs/hdb3 encoding in the transmitter. when decoding is selected for a given channel, decoded receive data and code violations appear on the rdata and bpv pins, respectively. if coding is not selected, receive data and any bipolar violations (such as two consecutive ones of the same polarity) appear on the rdata and bpv pins, respectively. alternate logic mode (alm) the alternate logic mode (alm) control pin selects the receive and transmit data polarity (i.e., active-high vs. active-low). if alm = 0, the receiver circuitry (and trans- mit input) assumes the data to be active-low polarity. if alm = 1, the receiver circuitry (and transmit input) assumes the data to be active-high polarity. the alm control is used in conjunction with the acm control to determine the receive data retiming mode. alternate clock mode (acm) the alternate clock mode (acm) control pin selects the positive or negative clock edge of the receive clock (rclk) for receive data retiming. the acm control is used in conjunction with the alm control to determine the receive data retiming modes. if acm = 1, the receive data is retimed on the positive edge of the receive clock. if acm = 0, the receive data is retimed on the negative edge of the receive clock. note that this control does not affect the timing relationship for the transmitter inputs. see figure 38 on page 97.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 70 lucent technologies inc. direct logic control mode (continued) receiver configuration modes (continued) rliu alarms analog loss of signal (alos ) alarm . an analog sig- nal detector monitors the receive signal amplitude and reports its status on the analog loss of signal alarm pins. an analog loss of signal is indicated if the ampli- tude at the rring and rtip inputs drops more than approximately 18 db below the nominal signal ampli- tude. the alos alarm condition will clear when the receive signal amplitude returns to greater than 14 db below normal. in this way, the alos circuitry provides 4 db of hysteresis to prevent alarm chattering. the time required to detect alos is selectable. when altimer = 0, alos is declared between 1 ms and 2.6 ms after losing signal as required by i.431(3/93) and ets-300-233 (5/94). if altimer = 1, alos is declared between 10 and 255 bit symbol periods after losing signal as required by g.775 (11/95). the timing is derived from the xclk clock. the detection time is independent of signal amplitude before the loss condi- tion occurs. normally, altimer = 1 would be used only in cept mode since no t1/ds1 standards require this mode. in t1/ds1 mode, this pin should normally be tied low. the behavior of the receiver outputs under alos con- ditions depends on the loss shutdown (lossd) control pin in conjunction with the receiver ais (rcvais) con- trol pin as described in the loss shutdown (lossd) and receiver ais (rcvais) section on page 71. digital loss of signal (dlos ) alarm . a digital loss of signal (dlos ) detector guarantees the received signal quality as defined in the appropriate ansi, bellcore, and itu standards. the digital loss of signal alarms are reported on the dlos alarm pins. during ds1 opera- tion, a digital loss of signal is indicated if 100 or more consecutive zeros occur in the receive data stream. the dlos condition is deactivated when the average ones density of at least 12.5% is received in 100 con- tiguous pulse positions. the losstd control bit selects the conformance protocols for the dlos alarm indication per table 41. setting losstd = 1 adds an additional constraint that there are less than 15 con- secutive zeros in the ds1 data stream before dlos is deactivated. during cept operation, dlos is indicated when 255 or more consecutive zeros occur in the receive data stream. the dlos indication is deactivated when the average ones density of at least 12.5% is received in 255 contiguous pulse positions. losstd has no effect in cept mode. table 41. digital loss of signal standard select losstd ds1 mode cept mode 0 t1m1.3/93-005, itu-t g.775 itu-t g.775 1 tr-tsy-000009 itu-t g.775
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 71 lucent technologies inc. direct logic control mode (continued) receiver configuration modes (continued) rliu alarms (continued) loss shutdown (lossd) and receiver ais (rcvais). the loss shutdown control pin (lossd) acts in conjunc- tion with the receiver ais (rcvais) control pin to place the digital outputs in a predetermined state when a digital loss of signal (dlos ) or analog loss of signal (alos ) alarm occurs. if lossd = 0 and rcvais = 0, the rnd, rpd, and rclk outputs will be unaffected by the dlos alarm condition. however, when an alos alarm condition exists, the rpd and rnd outputs are forced to their inactive state (dependent on alm state) and the rclk free runs (based on xclk frequency). if lossd = 0, rcvais = 1, and a dlos or an alos alarm condition exists, the rpd and rnd outputs will present an alarm indication signal (ais, all ones) based on the free-running clock frequency, and the rclk free runs. if lossd = 1, regardless of the state of rcvais, and a dlos or an alos alarm condition exists, the rpd and rnd outputs are forced to their inactive state (dependent on alm state) and the rclk free runs. the rnd, rpd, and rclk signals will remain unaffected if any loopback (flloop , rloop , dlloop ) is activated independent of lossd and rcvais settings. the lossd and rcvais behavior is summarized in table 42. rliu bipolar violation (bpv) alarm. the bipolar violation (bpv) alarm is used only in the single-rail mode of operation. when b8zs(ds1)/hdb3(cept) coding is not used (i.e., code[14] = 0), any violations in the receive data (such as two or more consecutive ones on a rail) are indicated on the rnd/bpv outputs. when b8zs(ds1)/ hdb3(cept) coding is used (i.e., code[14] = 1), the hdb3/b8zs code violations are reflected on the rnd/ bpv outputs. table 42. lossd and rcvais control configurations (not valid during loopback modes) lossd rcvais alarm rpd/rnd rclk 00alos 0 if alm = 1, 1 if alm = 0 free runs 00dlos normal data recovered clock 01alos ais (all ones) free runs 01dlos ais (all ones) free runs 1xalos 0 if alm = 1, 1 if alm = 0 free runs 1xdlos 0 if alm = 1, 1 if alm = 0 free runs
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 72 lucent technologies inc. direct logic control mode (continued) ds1 receiver specifications during ds1/t1 operation, the rliu will perform as specified in table 43. table 43. ds1 rliu specifications parameter min typ max unit spec analog loss of signal: threshold to assert threshold to clear hysteresis time to assert (altimer = 0) 17.5 13.5 1.0 18 14 4 23 17.5 2.6 db * db * db ms * below the nominal pulse amplitude of 3.0 v with the line interface circuitry specified (see line circuitry on page 94). i.431 i.431 receiver sensitivity ? ? cable loss at 772 khz. 11 15 db jitter transfer: 3 db bandwidth peaking 3.84 0.1 khz db figure 28 on page 74 figure 34 on page 86 generated jitter 0.04 0.05 uip-p gr-499-core itu-t g.824 jitter accommodation figure 27 on page 73 figure 33 on page 85 return loss ? : 51 khz to 102 khz 102 khz to 1.544 mhz 1.544 mhz to 2.316 mhz ? using lucent transformer 2795b and components listed in table 55. 14 20 16 db db db digital loss of signal: flag asserted when consecutive bit positions contain flag deasserted when data density is and maximum consecutive zeros are 100 12.5 15 99 zeros % ones zeros zeros itu-t g.775, t1m1.3/93-005 tr-try-000009 itu-t g.775, t1m1.3/ 93-005
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 73 lucent technologies inc. direct logic control mode (continued) ds1 receiver specifications (continued) frequency response curves 5-5260(f)r.7 figure 27. ds1/t1 receiver jitter accommodation without jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 28 ui frequency (hz) 100k typical (subject to device characterization) (non-sonet cat ii interfaces) gr-499-core i.431(ds1), g.824(ds1) tr-tsy-000009 (ds1, muxes) gr-499/1244-core (cat i interfaces) t1.408/i.431(ds1)/g.824(ds1)
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 74 lucent technologies inc. direct logic control mode (continued) ds1 receiver specifications (continued) frequency response curves (continued) 5-5261(f)r.4 figure 28. ds1/t1 receiver jitter transfer without jitter attenuator 60 40 20 0 1 10 100 1k 10k 50 30 10 100k frequency (hz) jitter out/jitter in (db) ty p i c a l (subject to device characterization) gr-499-core (non-sonet cat ii to cat ii)
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 75 lucent technologies inc. direct logic control mode (continued) cept receiver specifications during cept/e1 operation, the rliu will perform as specified in table 44. table 44. cept rliu specifications parameter min typ max unit spec analog loss of signal: threshold to assert threshold to clear hysteresis time to assert (altimer = 0) time to assert (altimer = 1) 17.5 13.5 1.0 10 18 14 4 23 17.5 2.6 255 db * db * db ms ui * below the nominal pulse amplitude of 3.0 v with the line circuitry specified (see line interface unit: line circuitry sectio n). i.431, etsi 300 233 i.431, etsi 300 233 g.775 receiver sensitivity ? ? cable loss at 1.024 mhz. 11 13.5 db interference immunity ? : ? amount of cable loss for which the receiver will operate error-free in the presence of a C18 db interference signal summing with the intended signal source. 912db itu-t g.703 jitter transfer: 3 db bandwidth, single pole roll off peaking 5.1 0.5 khz db figure 30 on page 77 figure 36 on page 88 generated jitter 0.04 0.05 uip-p itu-t g.823, i.431 jitter accommodation figure 29 on page 76 figure 35 on page 87 return loss : 51 khz to 102 khz 102 khz to 1.544 mhz 1.544 mhz to 2.316 mhz using lucent transformer 2795d or 2795c and components listed in table 55. 14 20 16 db db db itu-t g.703 digital loss of signal: flag asserted when consecutive bit positions contain flag deasserted when data density is (losstd = 1) 255 12.5 zeros %ones itu-t g.775
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 76 lucent technologies inc. direct logic control mode (continued) cept receiver specifications (continued) frequency response curves 5-5262(f)r.8 figure 29. cept/e1 receiver jitter accommodation without jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 37 ui frequency (hz) g.823 100k typical (subject to device characterization) g.823,etsi-300-011a1 i.431(cept)/ets-300-011 i.431(cept)/ets-300-011
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 77 lucent technologies inc. direct logic control mode (continued) cept receiver specifications (continued) frequency response curves (continued) 5-5263(f)r.4 figure 30. cept/e1 receiver jitter transfer without jitter attenuator frequency (h z ) jitter out/jitter in (db) 60 40 20 0 1 10 100 1k 10k 50 30 10 100k typical (subject to device characterization) g.735-9 w/o jitter reducer
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 78 lucent technologies inc. direct logic control mode (continued) output pulse generation the transmitter accepts a clock with nrz data in single-rail mode (dual = 0) or a clock with positive and negative nrz data in dual-rail mode (dual = 1) from the system. the device converts this data to a balanced bipolar signal (ami format) with optional b8zs(ds1)/hdb3(cept) encoding and jitter attenuation. low-impedance output drivers produce these pulses on the line interface. positive ones are output as a positive pulse on ttip, and negative ones are output as a positive pulse on tring. binary zeros are converted to null pulses. the total delay of the data from the system interface to the transmit driver is approximately 3 to 11 bit periods, depending on the code configuration (see the clock/data recovery mode (cdr) section, page 69 and the zero substitution encoding (code) section, page 79). additional delay results if the jitter attenuator is selected for use in the transmit path (see the liu delay values sec- tion). transmit pulse shaping is controlled by the on-chip pulse-width controller and pulse equalizer. the pulse-width con- troller produces high-speed timing signals to accurately control the transmit pulse widths. this eliminates the need for a tightly controlled transmit clock duty cycle that is usually required in discrete implementations. the pulse equalizer controls the amplitudes of the pulses. different pulse equalizations are selected through proper settings of the eqa, eqb, and eqc pins as described in table 45. table 45. equalizer/rate control * in ds1 mode, the distance to the dsx for 22 gauge pic (abam) cable is specified. use the maximum cable loss figures for other cable types. in cept mode, equalization is specified for coaxial or twisted-pair cable. ? loss measured at 772 khz. ? in 75 w applications, option 1 is recommended over option 2 for lower device power dissipation. option 2 allows for the same transform er as used in cept 120 w applications. jitter the intrinsic jitter of the transmit path, i.e., the jitter at ttip/tring when no jitter is applied to tclk (and the jitter attenuator is not selected, jat = 0), is typically 5 nsp-p and will not exceed 0.02 uip-p. eqa eqb eqc service clock rate transmitter equalization * maximum cable loss ? feet meters db 0 0 0 ds1 1.544 mhz 0 ft. to 131 ft. 0 m to 40 m 0.6 0 0 1 131 ft. to 262 ft. 40 m to 80 m 1.2 0 1 0 262 ft. to 393 ft. 80 m to 120 m 1.8 0 1 1 393 ft. to 524 ft. 120 m to 160 m 2.4 1 0 0 524 ft. to 655 ft. 160 m to 200 m 3.0 101cept ? 2.048 mhz 75 w (option 2) 1 1 0 120 w or 75 w (option 1) 111not used
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 79 lucent technologies inc. direct logic control mode (continued) transmitter configuration modes zero substitution encoding (code) zero substitution b8zs/hdb3 encoding can be acti- vated only in the single-rail system interface mode (dual = 0). the b8zs/hdb3 encoding operation can be selected for individual channels independently by setting the code[14] pins high for the respective channels. note: encoding and decoding are not independent. selecting b8zs/hdb3 encoding in the transmit- ter selects b8zs/hdb3 decoding in the receiver. when coding is selected for a given channel, data transmitted from the system interface on tdata will be b8zs/hdb3 encoded before appearing on ttip and tring at the line interface. alarm indication signal generator (xais) when the transmit alarm indication signal control pin is set (xais[14] = 1) for a given channel, a continuous stream of bipolar ones is transmitted to the line inter- face. the tpd/tdata and tnd inputs are ignored dur- ing this mode. the xais input is ignored when a remote loopback is selected using loopback control pin (rloop) transmitter alarms. the normal clock source for the ais signal is tclk. if tclk is not available (loss of tclk detected), then the ais signal clock defaults to intxclk/16. intxclk is either xclk, or 16x xclk, depending on the state of the clks input pin. see figure 26 on page 68, and clks in table 39, pin descriptions, on page 62. loss of transmit clock (lotc) alarm a loss of transmit clock alarm (lotc[14]) is indicated if any of the clocks in the transmit path disappear. this includes loss of tclk input, loss of rclk during remote loopback, loss of jitter attenuator output clock (when enabled), or the loss of clock from the pulse- width controller. for all of these conditions, a core transmitter timing clock is lost and no data can be driven onto the line. output drivers ttip and tring are placed in a high- impedance state when this alarm condition is active. the lotc pin is asserted low between 3 s and 16 s after the clock disappears, and deasserts immediately after detecting the first clock edge. transmit driver monitor (tdm) alarm the transmit driver monitor detects two conditions: a nonfunctional link due to a fault on the primary of the transmit transformer, or periods of no data transmis- sion. the transmit driver monitor alarm (tdm[14]) is the ored function of both faults and provides informa- tion about the integrity of the transmit signal path. the first monitoring function is provided to detect non- functional links and protect the device from damage. the alarm is set (tdm = 0) when one of the transmit- ter's line drivers (ttip or tring) is shorted to power supply or ground, or ttip and tring are shorted together. under these conditions, internal circuitry protects the device from damage and excessive power supply cur- rent consumption by 3-stating the output drivers. the monitor detects faults on the transformer primary, but transformer secondary faults may not be detected. the monitor operates by comparing the line pulses with the transmit inputs. after 32 transmit clock cycles, the transmitter is powered up in its normal operating mode. the drivers attempt to correctly transmit the next data bit. if the error persists, tdm remains active to elimi- nate alarm chatter and the transmitter is internally pro- tected for another 32 transmit clock cycles. this process is repeated until the error condition is removed and the tdm alarm is deactivated. the second monitoring function is to indicate periods of no data transmission. the alarm is set (tdm = 0) when 32 consecutive zeros have been transmitted and the alarm condition is cleared on the detection of a single pulse. this alarm condition does not alter the state or functionality of the signal path.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 80 lucent technologies inc. direct logic control mode (continued) ds1 transmitter pulse template the ds1 pulse shape template is specified at the dsx (defined by cb119 and ansi t1.102) and is illustrated in figure 31. the device also meets the pulse template specified by itu-t g.703 (not shown). 5-1160(f)r.1 figure 31. dsx-1 isolated pulse template table 46. dsx-1 pulse template corner points (from cb119) 1.0 0.5 0 C0.5 0 250 500 750 1000 1250 time (ns) maximum curve minimum curve ns v ns v 0 250 325 325 425 500 675 725 1100 1250 0.05 0.05 0.80 1.15 1.15 1.05 1.05 C0.07 0.05 0.05 0 350 350 400 500 600 650 650 800 925 1100 1250 C0.05 C0.05 0.50 0.95 0.95 0.90 0.50 C0.45 C0.45 C0.20 C0.05 C0.05 during ds1 operation, the ttip and tring pins will perform as specified in table 47. 1. in accordance with the line circuitry described (see line circuitry on page 94). 2. total power difference. 3. measured in a 2 khz band around the specified frequency. 4. using lucent transformer 2795b and components in table 55. 5. below the power at 772 khz. table 47. ds1 transmitter specifications parameter min typ max unit spec output pulse amplitude at dsx 1 2.5 3.0 3.5 v at&t cb119, ansi t1.102 output pulse width at line side of transformer 1 325 350 375 ns output pulse width at device pins ttip and tring 1 330 350 370 ns positive/negative pulse imbalance 2 0.10.4db power levels 3, 4 : 772 khz 1.544 mhz 5 12.6 29 39 17.9 dbm db
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 81 lucent technologies inc. direct logic control mode (continued) cept transmitter pulse template cept pulse shape template is specified at the system output (defined by itu-t g.703) and is illustrated in figure 32. 5-3145(f)r.1 figure 32. itu-t g.703 pulse template 269 ns (244 + 25) 219 ns (244 C 25) 244 ns 194 ns (244 C 50) 20% 488 ns (244 + 244) 20% 20% 10% 10% 10% 10% 0% 50% 10% v = 100% 10% nominal pulse
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 82 lucent technologies inc. direct logic control mode (continued) cept transmitter pulse template (continued) during cept operation, the transmitter tip/ring (ttip/tring pins) will perform as specified in table 48. jitter attenuator a selectable jitter attenuator is provided for narrow-bandwidth jitter transfer function applications. when placed in the liu receive path, the jitter attenuator provides narrow-bandwidth jitter filtering for line synchronization. the jitter attenuator can also be placed in the transmit path to provide clock smoothing for applications such as synchronous/ asynchronous demultiplexers. in these applications, tclk will have an instantaneous frequency that is higher than the data rate, and some periods of tclk are suppressed (gapped) in order to set the average long-term tclk fre- quency to within the transmit line rate specification. the jitter attenuator will smooth the gapped clock. generated (intrinsic) jitter generated jitter is the amount of jitter appearing on the output port when the applied input signal has no jitter. the jitter attenuator of this device outputs a maximum of 0.05 uip-p intrinsic jitter. table 48. cept transmitter specifications parameter min typ max unit spec output pulse amplitude * : 75 w 120 w * in accordance with the line circuitry described (see line circuitry on page 94), measured at the transformer secondary. 2.13 2.7 2.37 3.0 2.61 3.3 v v itu-t g.703 output pulse width at line side of transformer* 219 244 269 ns output pulse width at device pins ttip and tring * 224 244 264 ns positive/negative pulse imbalance: pulse amplitude pulse width C4 C4 1.5 1 4 4 % % zero level (percentage of pulse amplitude) C5 0 5 % return loss ? (120 w): 51 khz to 102 khz 102 khz to 2.048 mhz 2.048 mhz to 3.072 mhz ? using lucent transformer 2795d or 2795c and components in table 30. 9 15 11 db db db ch-ptt return loss ? (75 w): 51 khz to 102 khz 102 khz to 3.072 mhz 7 9 db db ets 300 166: 1993
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 83 lucent technologies inc. direct logic control mode (continued) jitter attenuator (continued) jitter transfer function the jitter transfer function describes the amount of jitter that is transferred from the input to the output over a range of frequencies. the jitter attenuator exhibits a single-pole roll-off (20 db/decade) jitter transfer characteristic that has no peaking and a nominal filter corner frequency (3 db bandwidth) of less than 4 hz for ds1 operation and approximately 10 hz for cept operation. optionally, a lower bandwidth of approximately 1.25 hz can be selected in cept operation by setting jabw0 = 1 (register 12, bit 5) for systems desiring compliance with etsi-tbr12/13 jitter attenuation requirements. when configured to meet etsi-tbr12/13, the clock connected to the xclk input must be 20 ppm. for a given frequency, different jitter amplitudes will cause a slight variation in attenuation because of finite quantization effects. jitter amplitudes of less than approximately 0.2 ui will have greater attenua- tion than the single-pole roll-off characteristic. the jitter transfer curve is independent of data patterns. typical jitter transfer curves of the jitter attenuator are given in figure 34 and figure 36. jitter accommodation the minimum jitter accommodation of the jitter attenuator occurs when the xclk frequency and the input clocks long-term average frequency are at their extreme frequency tolerances. when the jitter attenuator is used in the liu transmit path, the minimum accommodation is 28 uip-p at the highest jitter frequency of 15 khz. typical receiver jitter accommodation curves including the jitter attenuator in the liu receive path are given in figure 33 and figure 35. when the jitter attenuator is placed in the data path, a difference between the xclk/16 frequency and the incoming line rate for receive applications, or the tclk rate for transmit applications, will result in degraded low- frequency jitter accommodation performance. the peak-to-peak jitter accommodation (jap-p) for frequencies from above the corner frequency of the jitter attenuator (fc) to approximately 100 hz is given by the following equation: where: f data = 1.544 mhz for ds1 or 2.048 mhz for cept; for jabw0 = 0, fc = 3.8 hz for ds1 or 10 hz for cept, and for jabw0 = 1, fc = 1.25 hz for cept; d f xclk = xclk tolerance in ppm; d f data = data tolerance in ppm. note that for lower corner frequencies, the jitter accommodation is more sensitive to clock tolerance than for higher corner frequencies. when jabw0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on xclk should be tightened to 20 ppm in order to meet the jitter accommodation requirements of tbr12/13 as given in g.823 for line data rates of 50 ppm. jap-p 64 2f xclk dd f data C () f data 2 p f c ------------------------------------------------------------ C ? ?? ui =
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 84 lucent technologies inc. direct logic control mode (continued) jitter attenuator (continued) jitter attenuator enable the jitter attenuator is selected using the jar and jat pins. these control pins are global and affect all four channels unless a given channel is in the powerdown mode (pwrdn = 1). because there is only one attenu- ator function in the device, selection must be made between either the transmit or receive path. if both jat and jar are activated at the same time, the jitter atten- uator will be disabled. note that the power consumption increases slightly on a per-channel basis when the jitter attenuator is active. if jitter attenuation is selected, a valid xclk signal must be available. jitter attenuator receive path enable (jar) when the jitter attenuator receive bit is set (jar = 1), the attenuator is enabled in the receive data path between the clock/data recovery and the decoder (see figure 26 on page 68). under this condition, the jitter characteristics of the jitter attenuator apply for the receiver. when jar = 0, the clock/data recovery out- puts bypass the disabled attenuator and directly enter the decoder function. the receive path will then exhibit the jitter characteristics shown in figure 27 through figure 30. jitter attenuator transmit path enable (jat) when the jitter attenuator transmit bit is set (jat = 1), the attenuator is enabled in the transmit data path between the encoder and the pulse-width controller/ pulse equalizer (see figure 26 on page 68). under this condition, the jitter characteristics of the jitter attenuator apply for the transmitter. when jat = 0, the encoder outputs bypass the disabled attenuator and directly enter the pulse-width controller/pulse equalizer. the transmit path will then pass all jitter from tclk to line interface outputs ttip/tring.
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 85 lucent technologies inc. direct logic control mode (continued) jitter attenuator (continued) frequency response curves 5-5264(f)r.8 figure 33. ds1/t1 receiver jitter accommodation with jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 28 ui frequency (hz) 100k tr-tsy-000009 (ds1, muxes) gr-499/1244-core (cat i interfaces) i.431(ds1), g.824(ds1) typical (subject to device characterization) (non-sonet cat ii interfaces) gr-499-core t1.408/i.431(ds1)/g.824(ds1)
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 86 lucent technologies inc. direct logic control mode (continued) jitter attenuator (continued) frequency response curves (continued) 5-5265(f)r.4 figure 34. ds1/t1 jitter transfer of the jitter attenuator 60 40 20 0 1 10 100 1k 10k 50 30 10 100k frequency (hz) jitter out/jitter in (db) ty p i c a l (subject to device characterization) tr-tsy-000009 gr-253-core
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 87 lucent technologies inc. direct logic control mode (continued) jitter attenuator (continued) frequency response curves (continued) 5-5266(f)r.8 figure 35. cept/e1 receiver jitter accommodation with jitter attenuator 0.1 ui 1.0 ui 10 ui 100 ui 10 100 1k 10k 1 37 ui frequency (hz) g.823 100k typical (subject to device characterization) g.823,etsi-300-011a1 i.431(cept)/ets-300-011 i.431(cept)/ets-300-011 jabw0 = 0 jabw0 = 1
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 88 lucent technologies inc. direct logic control mode (continued) jitter attenuator (continued) frequency response curves (continued) 5-5267(f)r.4 figure 36. cept/e1 jitter transfer of the jitter attenuator frequency (hz) jitter out/jitter in (db) 60 40 20 0 1 10 100 1k 10k 50 30 10 100k ty p i c a l (subject to device characterization) jabw0 = 1 jabw0 = 0 etsi tbr12/13 etsi-300-011 i.431, g.735-9 with jitter reducer g.735-9 at national boundaries
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 89 lucent technologies inc. direct logic control mode (continued) loopbacks the device has three independent loopback paths that are activated using the flloop , rloop , and dlloop pins. the locations of these loopbacks are illustrated in figure 26. full local loopback (flloop ) a full local loopback (flloop ) connects the transmit line driver input to the receiver analog front-end cir- cuitry. valid transmit output data continues to be sent to the network. if the transmit ais (all-ones signal) is sent to the network, the looped data is not affected. the alos alarm continues to monitor the receive line inter- face signal while dlos monitors the looped data. remote loopback (rloop ) a remote loopback (rloop ) connects the recovered clock and retimed data to the transmitter at the system interface and sends the data back to the line. the receiver front end, clock/data recovery, encoder/ decoder (if enabled) jitter attenuator (if enabled), and transmit driver circuitry are all exercised during this loopback. the transmit clock, transmit data, and xais inputs are ignored. valid receive output data continues to be sent to the system interface. this loopback mode is very useful for isolating failures between systems. digital local loopback (dlloop ) a digital local loopback (dlloop ) connects the trans- mit clock and data through the encoder/decoder pair to the receive clock and data output pins at the system interface. this loopback is operational if the encoder/ decoder pair is enabled or disabled. the ais signal can be transmitted without any effect on the looped signal. powerdown (pwrdn) each line interface channel has an independent power- down mode controlled by pwrdn. this provides power savings for systems that use backup channels. if pwrdn = 1, the corresponding channel will be in a standby mode, consuming only a small amount of power. if a line interface channel in powerdown mode needs to be placed into service, the channel should be turned on (pwrdn = 0) approximately 5 ms before data is applied. reset (reset ) the device provides a hardware reset ( reset ; pin 44). when the device is in reset, all signal-path and alarm monitor states are initialized to a known starting config- uration. during a reset condition, data transmission will be interrupted. the reset condition is initiated by setting reset = 0 for a minimum of 10 s. on coming out of the reset condi- tion (reset = 1), a time of at least 2.7 ms should be allowed to ensure stabilization of the pll. loss of xclk reference clock (loxc) the loxc output (pin 45) is active when the xclk ref- erence clock (pin 46) is absent. the loxc flag is asserted a maximum of 16 s after xclk disappears, and deasserts immediately after detecting the first clock edge of xclk. during the loxc alarm condition, the clock recovery and jitter attenuator functions are automatically dis- abled. therefore, if cdr = 1 and/or jar = 1, the rclk, rpd, rnd, and dlos outputs will be unknown. if cdr = 0, there will be no effect on the receiver. if the jitter attenuator is enabled in the transmit path (jat = 1) dur- ing this alarm condition, then a loss of transmit clock alarm, lotc = 1, will also be indicated. in-circuit testing and driver high-imped- ance state (ict ) the affect of asserting the ict input (pin 43) is that all output buffers (ttip, tring, rclk, rpd, rnd, loxc, rdy_ dtack , int, ad[7:0]) are placed in a high-imped- ance state. the ttip and tring outputs have a limit- ing high-impedance capability of approximately 8 k w . liu delay values the transmit coder has 5 ui delay whether it is in the path or not and whether it is b8zs or hdb3. its delay is only removed when in single-rail mode. the remainder of the transmit path has 4.6 ui delay. the receive decoder has 5 ui delay whether it is in the path or not and whether it is b8zs or hdb3. its delay is only removed when in single-rail mode or cdr = 0. the afe (equalizer plus slicer) delay is nearly 0 ui delay. the jitter attenuator delay is nominally 33 ui but can be 2 ui64 ui depending on the state. the dpll used for timing recovery has 8 ui delay.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 90 lucent technologies inc. direct logic control mode (continued) line encoding/decoding alternate mark inversion (ami) the default line code used for t1 is alternate mark inversion (ami). the coding scheme represents a 1 with a pulse or mark on the positive or negative rail and a 0 with no pulse on either rails. this scheme is shown in table 49. table 49. ami encoding the t1 ones density rule requires that in every 24 bits of information to be transmitted, there must be at least three pulses, and no more than 15 zeros may be transmitted consecutively. at&t technical reference 62411 for digital transmissions requires that in every 8 bits of information, at least one pulse must be present. t1-binary 8 zero code suppression clear channel transmission can be accomplished using binary 8 zero code suppression (b8zs). eight consecu- tive zeros are replaced with the b8zs code. this code consists of two bipolar violations in bit positions 4 and 7 and valid bipolar marks in bit positions 5 and 8. the receiving end recognizes this code and replaces it with the original string of eight zeros. table 50 shows the encoding of a string of zeros using b8zs. b8zs is recommended when esf format is used. table 50. ds1 b8zs encoding high-density bipolar of order 3 (hdb3) the line code used for cept is described in itu rec. g.703 section 6.1 as high-density bipolar of order 3 (hdb3). hdb3 uses a substitution code that acts on strings of four zeros. the substitute hdb3 codes are 000v and b00v, where v represents a violation of the bipolar rule and b represents as inserted pulse conforming to the ami rule defined in itu rec. g.701, item 9004. the choice of the b00v or 000v is made so that the number of b pulses between consecutive v pulses is odd. in other words, successive v pulses are of alternate polarity so that no direct current (dc) component is introduced. the substitute codes follow each other if the string of zeros continues. the choice of the first substitute code is arbitrary. a line code error is defined as a bipolar violation and consists of two pulses of the same polarity that is not defined as one of the two substitute codes. both excessive zeros and coding violations are indicated as bipolar violations. an example is shown in table 51. table 51. itu hdb3 coding and dcpat binary coding input bit stream 1011 0000 0111 1010 ami data C0+C 0000 0+C+ C0+0 bit positions 12345678 12345678 before b8zs 0000000010100000000 after b8zs 000vb0vbb0b000vb0vb input bit stream 1011 0000 01 0000 0000 0000 0000 hdb3-coded data 1011 000v 01 000v b00v b00v b00v hdb3-coded levels C0+C 000C 0+ 000+ C00C +00+ C00C
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 91 lucent technologies inc. direct logic control mode (continued) xclk reference clock the device requires an externally applied clock, xclk (pin 46), for the clock and data recovery function and the jit- ter attenuation option. xclk must be a continuously active (i.e., ungapped, unjittered, and unswitched) and an independent reference clock such as from an external system oscillator or system clock for proper operation. it must not be derived from any recovered line clock (i.e., from rclk or any synthesized frequency of rclk). xclk may be supplied in one of four formats: 16x ds1, ds1, 16x cept, or cept. the format is selected globally for the device by clks (pin 117) and clkm (pin 116). clks determines the relationship between the primary line data rate and the clock signal applied to xclk. for clks = 0, a clock at 16x the primary line data rate clock (24.704 mhz for ds1 and 32.768 mhz for cept) must be applied to xclk. for clks = 1, a primary line data rate clock (1.544 mhz for ds1 and 2.048 mhz for cept) must be applied to xclk. the clks pin has an internal pull-down resistor allowing the pin to be left open, i.e., a no connect, in applications using a 16x reference clock. the clks pin must be pulled up to v dd for applications using a primary line data rate clock. clkm determines whether the clock synthesizer is operating in cept or ds1 mode when xclk is a primary line data rate clock. for clkm = 0, the clock synthesizer operates in ds1 mode (1.544 mhz). for clkm = 1, the clock synthesizer operates in cept mode (2.048 mhz). the clkm pin is ignored when clks = 0. the clkm pin has an internal pull-down resistor allowing the pin to be left open, i.e., a no connect, in applications using a ds1 line rate reference clock. the clkm pin must be pulled up to v dd for applications using a cept line data rate clock. 16x xclk reference clock the specifications for xclk using a 16x reference clock are defined in table 52. the 16x reference clock is selected when clks = 0. table 52. xclk (16x, clks = 0) timing specifications * when jabw0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on xclk should be tightened to 20 pp m in order to meet the jitter accommodation requirements of tbr12/13 as given in g.823 for line data rates of 50 ppm. ? if xclk is used as the source for ais (see alarm indication signal generator (xais) on page 79), it must meet the nominal trans mission specifications of 1.544 mhz 32 ppm for ds1 (t1) or 2.048 mhz 50 ppm for cept (e1). parameter value unit min typ max frequency: ds1 cept 24.704 32.768 mhz mhz range*, ? C100 100 ppm duty cycle 40 60 %
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 92 lucent technologies inc. direct logic control mode (continued) xclk reference clock (continued) primary line rate xclk reference clock and internal reference clock synthesizer in some applications, it is more desirable to provide a reference clock at the primary data rate. in such cases, the liu can utilize an internal 16x clock synthesizer allowing the xclk pin to accept a primary data rate clock. the specifications for xclk using a primary rate reference clock are defined in table 53. table 53. xclk (1x, clks = 1) timing specifications * when jabw0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on xclk should be tightened to 20 pp m in order to meet the jitter accommodation requirements of tbr12/13 as given in g.823 for line data rates of 50 ppm. ? if xclk is used as the source for ais (see alarm indication signal generator (xais) on page 79), it must meet the nominal trans mission specifications of 1.544 mhz 32 ppm for ds1 (t1) or 2.048 mhz 50 ppm for cept (e1). the data rate reference clock and the internal clock synthesizer is selected when clks = 1. in this mode, a valid and stable data rate reference clock must be applied to the xclk pin before and during the time a hardware reset is activated (reset = 0). the reset must be held active for a minimum of two data rate clock periods to ensure proper resetting of the clock synthesizer circuit. upon the deactivation of the reset pin (reset = 1), the liu will extend the reset condition internally for approximately 1/2(2 12 C 1) line clock periods, or 1.3 ms for ds1 and 1 ms for cept after the hardware reset pin has become inactive, allowing the clock synthesizer additional time to settle. no activity such as microprocessor read/write should be performed during this period. the device will be operational 2.7 ms after the deactivation of the hardware reset pin. issuing an liu software restart (liu_reg2 bit 5 (restart) = 1) does not impact the clock synthesizer circuit. the choices for xclk are summarized in table 54. table 54. xclk specifications * to meet tbr 12/13 for jitter accommodation. parameter value unit min typ max frequency: ds1 cept 1.544 2.048 mhz mhz range*, ? C100 100 ppm duty cycle 40 60 % rise and fall times (10%90%) 5 ns clks clkm jabw0 * mode specifications 0 0 0 16x ds1 24.740 mhz 32 ppm 0 1 0 16x cept 32.768 mhz 50 ppm 0 1 1 16x cept 32.768 mhz 20 ppm 1 0 0 ds1 1.544 mhz 32 ppm 1 1 0 cept 2.048 mhz 50 ppm 1 1 1 cept 2.048 mhz 20 ppm
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 93 lucent technologies inc. direct logic control mode (continued) power supply bypassing external bypassing is required for all channels. a 1.0 f capacitor must be connected between v ddx and gnd x . in addition, a 0.1 f capacitor must be connected between v ddd and gnd d , and a 0.1 f capacitor must be con- nected between v dda and gnd a . ground plane connections are required for gnd x , gnd d , and gnd a . power plane connections are also required for v ddx and v ddd . the need to reduce high-frequency coupling into the ana- log supply (v dda ) may require an inductive bead to be inserted between the power plane and the v dda pin of every channel. capacitors used for power supply bypassing should be placed as close as possible to the device pins for maximum effectiveness.
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 94 lucent technologies inc. direct logic control mode (continued) line circuitry the transmit and receive tip/ring connections provide a matched interface to the cable (i.e., terminating impedance matches the characteristic impedance of the cable). the diagram in figure 37 shows the appropriate external com- ponents to interface to the cable for a single transmit/receive channel. the component values are summarized in table 55, based on the specific application. 5-3693(f).d figure 37. line termination circuitry table 55. termination components by application resistor tolerances are 1%. transformer turns ratio tolerances are 2%. 1. use lucent 2795b transformer. 2. for cept 75 w applications, option 1 is recommended over option 2 for lower device power dissipation. option 2 increases power dissipa- tion by 13 mw per channel when driving 50% ones data. option 2 allows for the use of the same transformer as in cept 120 w applica- tions. 3. use lucent 2795d transformer. 4. use lucent 2795c transformer. 5. a 5% tolerance is allowed for the transmit load termination, r l . symbol name cable type unit ds1 1 twisted pair cept 75 w 2 coaxial cept 120 w 4 twisted pair option 1 3 option 2 4 c c center tap capacitor 0.1 0.1 0.1 0.1 m f r p receive primary impedance 200 200 200 200 w r r receive series impedance 71.5 28.7 59 174 r s receive secondary impedance 113 82.5 102 205 z eq equivalent line termination 100 75 75 120 tolerance 4 4 4 4 % r t transmit series impedance 0 26.1 15.4 26.1 w r l transmit load termination 5 100 75 75 120 n transformer turns ratio 1.14 1.08 1.36 1.36 rtip rring ttip tring device (1 channel) r l r s r r r r receive data r p z eq r t r t n:1 transmit data transformer equipment interface 1:n c c
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 95 lucent technologies inc. direct logic control mode (continued) absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this device specification. exposure to absolute maximum rat- ings for extended periods can adversely affect device reliability. table 56. absolute maximum ratings handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in the defined model. no industry-wide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters. operating conditions parameter min max unit dc supply voltage C0.5 6.5 v storage temperature C65 125 c maximum voltage (digital pins) with respect to v ddd 0.5v minimum voltage (digital pins) with respect to gnd d C0.5 v maximum allowable voltages (rtip[14], rring[14]) with respect to v dd 0.5v minimum allowable voltages (rtip[14], rring[14]) with respect to gnd C0.5 v table 57. esd threshold voltage device model voltage TLIU04C1 hbm tbd cdm (corner pins) tbd cdm (noncorner pins) tbd table 58. recommended operating conditions parameter symbol min typ max unit ambient temperature t a C40 85 c power supply v dd 4.75 5.0 5.25 v
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 96 lucent technologies inc. direct logic control mode (continued) power requirements the majority of the power used by the TLIU04C1 device is used by the line drivers. therefore, the power is very dependent on data pattern and signal amplitude. the signal amplitude is a function of the transmit equalization in ds1 mode. when configured for greater cable loss, the signal amplitude is greater at the output drivers, and thus uses more power. for this reason, the power specification of table 59 are given for various conditions. the typical specification is for a quasi-random signal and the maximum specification is for a mark (all ones) pattern. the power also varies somewhat for ds1 versus cept, so figures are given for both. table 59. power consumption power dissipation is the amount of power dissipated in the device. it is equal to the power drawn by the device minus the power dissipated in the line. table 60. power dissipation electrical characteristics parameter power unit typ max cept tbd tbd mw ds1 tbd tbd mw ds1 with max eq. tbd tbd mw parameter power unit typ max cept tbd tbd mw ds1 tbd tbd mw ds1 with max eq. tbd tbd mw table 61. logic interface characteristics note: the following internal resistors are provided: 50 k w pull-up on the ict and reset pins, 50 k w pull-down on the clks and clkm pins, and 100 k w pull-up on the cs , and xclk pins. this requires these input pins to sink no more than 20 a. the device uses ttl input and output buffers; all buffers are cmos-compatible. parameter symbol test conditions min max unit input voltage: low high v il v ih gnd d 2.1 0.8 v ddd v v input leakage i l 10a output voltage: low high v ol v oh i ol = C5.0 ma i oh = 5.0 ma gnd d v ddd C 0.5 0.4 v ddd v v input capacitance c i 3.0pf load capacitance * * 100 pf allowed for microprocessor mode ad[7:0] (pins 7582). c l 50 pf
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 97 lucent technologies inc. direct logic control mode (continued) data interface timing * refers to each individual bit period for jat = 0 applications. ? refers to each individual bit period for jat = 1 applications using a gapped tclk. 5-1156(f).br.3 * invert rclk for acm = 1. figure 38. interface data timing (acm = 0) table 62. data interface timing note: the digital system interface timing is shown in figure 38 for acm = 0. if acm = 1, then the rclk signal in figure 38 will be inverted. symbol parameter min typ max unit ttcltcl average tclk clock period: ds1 cept 647.7 488.0 ns ns ttdc tclk duty cycle* tclk minimum high/low time ? 30 100 70 % ns ttdvtcl transmit data setup time 50 ns ttcltdx transmit data hold time 40 ns ttch1tch2 clock rise time (10%/90%) 40 ns ttcl2tcl1 clock fall time (90%/10%) 40 ns trchrcl rclk duty cycle 45 50 55 % trdvrch receive data setup time 140 ns trchrdx receive data hold time 180 ns trclrdv receive propagation delay 40 ns tclk-liu tpd-liu or tnd-liu rclk-liu* rpd-liu or rnd-liu ttch1tch2 ttcl2tcl1 ttdvtcl ttcltdx trclrdv trdvrch trchrdx ttcltcl
advance data sheet, rev. 2 TLIU04C1 quad t1/e1 line interface april 1999 98 lucent technologies inc. outline diagram 144-pin tqfp dimensions are in millimeters. 5-3815(f)r.6 0.45/0.75 gage plane seating plane 1.00 ref 0.25 0.19/0.27 0.08 m 0.106/0.200 1.60 max seating plane 0.08 0.50 typ 1.40 0.05 0.05/0.15 detail a detail b pin #1 identifier zone 20.00 0.20 22 . 00 0 . 20 109 144 1 36 37 72 73 108 20.00 0.20 22.00 0.20
advance data sheet, rev. 2 april 1999 TLIU04C1 quad t1/e1 line interface 99 lucent technologies inc. ordering information device code package temperature comcode (ordering number) TLIU04C1 144-pin tqfp C40 c to +85 c 108420761
advance data sheet, rev. 2 t7698 quad t1/e1 line interface and octal t1/e1 monitor april 1999 for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 1189 324 299 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 45 77 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 1999 lucent technologies inc. all rights reserved april 1999 ds99-158t1e1-02 (replaces ds99-158t1e1-01)

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