View LC78834M_3031427.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ordering number : en * 4838 93098ha (ot) / 93094th (ot) no. 4838-1/14 LC78834M sanyo electric co.,ltd. semiconductor bussiness headquarters tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan stereo 18-bit digital audio d/a converter with on-chip 4 fs digital filters cmos lsi any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. overview the LC78834M is a cmos stereo 18-bit d/a converter lsi that includes 4 oversampling digital filters, output op amps, and analog filter op amps on chip. functions and features digital filter block ? oversampling filters: two-stage fir filter structure (43rd order and 11th order) de-emphasis filters: support for fs = 32, 44.1, and 48 khz soft muting d/a converter block dynamic level shifting 18-bit d/a converter two d/a converter channels built in (in-phase outputs) built-in output op amps built-in analog filter op amps system clock: support for both 384 fs and 512 fs single 5 v power supply low voltage operation supported ( 3.5 v) si gate cmos process (low power) package dimensions unit: mm 3091-mfp28 preliminary specifications absolute maximum ratings at v ss = 0 v allowable operating ranges parameter symbol conditions ratings unit maximum supply voltage v dd max ?.3 to +7.0 v input voltage v in ?.3 to v dd + 0.3 v output voltage v out ?.3 to v dd + 0.3 v operating temperature topr ?0 to +75 ? storage temperature tstg ?0 to +125 ? parameter symbol conditions min typ max unit supply voltage v dd 3.5 5.0 5.5 v operating temperature topr ?0 +75 ? [LC78834M] sanyo: mfp28
dc characteristics at ta = ?0 to +75 c, v dd = 3.5 to 5.5 v, v ss = 0 v ac characteristics at ta = ?0 to +75 c, v dd = 3.5 to 5.5 v, v ss = 0 v audio input waveforms no. 4838- 2 /14 LC78834M parameter symbol conditions ratings unit min typ max input high-level voltage (1) v ih 1 pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 15 and 16 2.2 v input low-level voltage (1) v il 1 pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 15 and 16 0.8 v input high-level voltage (2) v ih 2 pin 13 0.7 v dd v input low-level voltage (2) v il 2 pin 13 0.3 v dd v output high-level voltage v oh pin 11, i oh = ? ma 2.4 v output low-level voltage v ol pin 11, i ol = 3 ma 0.4 v input leakage current v l pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 15 and 16, v i = v ss , v dd ?5 +25 a parameter symbol conditions ratings unit min typ max oscillator frequency f x the xin pin when a crystal oscillator is used 1.0 25 mhz clock pulse width t cw the xin pin when an external clock signal is provided 18 ns clock pulse period t cy the xin pin when an external clock signal is provided 40 1000 ns bclk pulse width t bcw 60 ns bclk pulse period t bcy 120 ns data setup time t ds 40 ns data hold time t dh 40 ns lrck setup time t lrs 40 ns lrck hold time t lrh 40 ns
electrical characteristics for d/a converter (1) at ta = 25 c, av dd = dv dd = 5.0 v, agnd = dgnd = 0 v, unless otherwise specified electrical characteristics for d/a converter (2) at ta = 25 c, av dd = dv dd = 3.5 v, agnd = dgnd = 0 v, unless otherwise specified note: 1. ? db?means the full scale output level. 2. with the xin pin (pin 13) at 1.5 to 3.5 v, f x = 16.9344 mhz, fs = 44.1 khz (384 fs) 3. with the xin pin (pin 13) at 1.0 to 2.5 v, f x = 16.9344 mhz, fs = 44.1 khz (384 fs) operational amplifier block at ta = 25 c, av dd = dv dd = 5.0 v, agnd = dgnd = 0 v, unless otherwise specified no. 4838- 3 /14 LC78834M parameter symbol conditions ratings unit min typ max d/a converter resolution res 18 bits total harmonic distortion thd 1 khz, at 0 db, * 1 0.08 % dynamic range dr 1 khz, at ?0 db 90 db crosstalk ct 1 khz, at 0 db, * 1 ?5 db signal-to-noise ratio s/n jis-a 96 db full-scale output voltage vfs 2.2 2.4 2.6 vp-p power dissipation pd 1 khz, at 0 db, * 2 135 200 mw output load resistance rl pins 21 and 23 5 k parameter symbol conditions ratings unit min typ max d/a converter resolution res 18 bits total harmonic distortion thd 1 khz, at 0 db, * 1 0.12 % dynamic range dr 1 khz, at ?0 db 90 db crosstalk ct 1 khz, at 0 db, * 1 ?5 db signal-to-noise ratio s/n jis-a 96 db full-scale output voltage vfs 1.5 1.7 1.9 vp-p power dissipation pd 1 khz, at 0 db, * 3 50 75 mw output load resistance rl pins 21 and 23 15 k parameter symbol conditions ratings unit min typ max slew rate sr rl = 10 k 9 v/ s input offset voltage vio 1.5 mv gain-bandwidth product ft v in = 2 vp-p 2.0 mhz maximum output voltage vopp rl = 10 k 0.3 4.7 v common-mode input vic 0.6 3.6 v voltage range output load resistance rl pins 18 and 26 5 k
test circuits d/a converter block operational amplifier block block diagram no. 4838- 4 /14 LC78834M
pin assignment pin functions no. 4838- 5 /14 LC78834M pin no. symbol function 1 initb initialization signal input. the LC78834M is initialized on a low input. 2 bclk bit clock input 3 data digital audio data input data is input in a two? complement msb first format. 4 lrck lr clock input high: ch1 input; low: ch2 input de-emphasis filter 32, 44.1, or 48 khz mode selection 5 fs1 6 fs2 7 emp de-emphasis filter on/off switching high: on; low: off. 8 mute mute signal input high: soft muting on. 9 cksl system clock selection high: 512 fs; low: 384 fs 10 dv dd digital system power supply 11 ckout clock output 12 xout crystal oscillator output (system clock output) 13 xin crystal oscillator input (system clock input) 14 dgnd digital system ground digital audio data format selection 15 mode high: 18-bit data input low: 16-bit data input see section 4., ?igital audio data input? page 8. 16 test test. connect to dgnd in normal operation. 17 refl low-level reference voltage normally connected to agnd through a capacitor. 18 op2o op amp 2 output 19 op2n op amp 2 inverting input 20 op2p op amp 2 non-inverting input 21 ch2out ch2 analog output 22 agnd analog system ground 23 ch1out ch1 analog output 24 op1p op amp 1 non-inverting input 25 op1n op amp 1 inverting input 26 op1o op amp 1 output 27 refh high-level reference voltage normally connected to agnd through a capacitor. 28 av dd analog system ground fs1 l h h l fs2 l l h h fs 44.1 khz 32 khz 48 khz
LC78834M operation 1. digital filters the LC78834M performs the following processing. oversampling two 2 interpolation filters (constructed as fir filters) are cascade connected. two fir filter stages, a 43rd order and an eleventh order, are cascade connected to perform 4 oversampling. de-emphasis a first-order iir filter is used for digital de-emphasis. the filter coefficients are set up to correspond to the sampling frequency fs, which may be 32, 44.1, or 48 khz. see page 11 for the filter characteristics when de-emphasis is on. de-emphasis on/off de-emphasis on: emp pin = high de-emphasis off: emp pin = low filter coefficient selection no. 4838- 6 /14 LC78834M fs1 l h h l fs2 l l h h fs 44.1 khz 32 khz 48 khz
soft mute the soft muting function uses the built-in digital attenuator. the following formula gives the attenuation. 20 ?log (att/256) db the att parameter is an integer between 0 and 256. however, note that the attenuation will be when att is zero. when the mute pin is set to the high level, one is subtracted from the att parameter repeatedly moving it towards zero thus changing the attenuation towards . inversely, when the mute pin is set to the high level, one is added to the att parameter repeatedly moving it towards 256 thus changing the attenuation towards unity. the time required for the soft mute function to operate is about 1024/fs. 2. initialization the LC78834M must be initialized when power is first applied and when the system clock is switched. the LC78834M is initialized by setting the initb pin to the low level. the required length of this initial low level period is defined as follows. once the power supply has stabilized, input the xin, bclk and lrck signals. the low level on the initb pin must be held until at least one full cycle of the lrck signal has completed, as shown in the figure. no. 4838- 7 /14 LC78834M
3. system clock the LC78834M can handle two system clocks types: either a 384 fs clock or a 512 fs clock. the cksl pin selects which clock type is used. ckout pin the ckout pin is a system clock output pin. 4. digital audio data input digital audio data is a 16- or 18-bit serial signal in a two? complement msb first format. the 16- or 18-bit serial data is input from the data pin to an internal register on the rising edge of the bclk signal, and that register is read in on the rising and falling edges of the lrck signal. digital audio data input timing note: when the mode pin is low, data 1 is read in, and when high, data 2 . no. 4838- 8 /14 LC78834M cksl system clock l 384 fs h 512 fs
5. d/a converter block the LC78834M incorporates two independent 18-bit d/a converters, one each for channel 1 and channel 2, as well as two output op amps. these d/a converters are based on a dynamic level shifting conversion scheme which combines resistor string d/a conversion (r-string dac), pwm (pulse width modulation) d/a conversion (pwm dac), and level shifting d/a conversion (level shift dac) as shown in the figure. no. 4838- 9 /14 LC78834M
r-string dac the r-string dac is a 9-bit d/a converter that consists of 512 (= 2 9 ) individual resistors (each with resistance r) connected in series that divide the voltage applied at the ends of that resistor string into 512 equal sections. two adjacent potentials, v1 and v2, of the voltage divided potentials, are selected by a switching circuit according to the upper 9 bits of the data (d9 to d15). these two potentials are output to the pwm dac. note that v2 ?v1 will be equal to (vh ?vl)/512. pwm dac the pwm dac is a 3-bit d/a converter that divides the span of the two potentials v1 and v2 output from the r- string dac by eight. this circuit outputs one or the other of the two potentials v1 and v2 from the ch1out (or ch2out) pin depending on the value of the middle three bits (d6 to d8) of the data. level-shift dac the level-shift dac is a 6-bit d/a converter that consists of two variable resistors, vrh and vrl, inserted in series at the ends of the r-string dac resistor string. the level-shift dac controls the vrh and vrl variable resistors according to the lower six bits of the data (d0 to d5) as follows. the sum of the resistances of vrh and vrl is held constant for all values of the data. the values of vrh and vrl are set to be between 0 and 63 times r/512 according to the value of the data. (here, r is the value of the resistance of the individual resistors in the r-string dac.) this changes the values of the r-string dac outputs v1 and v2 in the range 0 to 63 ? v/512 (where ? v = (vh ?vl)/512) in steps of ? v/512. reference resistors rh and rl capacitors (about 10 f) must be connected between refh and agnd and between refl and agnd. when av dd = 5.0 v and agnd = 0 v, the LC78834M? maximum output amplitude should be set to be the range 1.3 to 3.7 v (2.4 vp-p) for a 0 db playback level by the resistors rh and rl. no. 4838- 10 /14 LC78834M
filter characteristics 4 oversampling ripple: within 0.05 db attenuation: not more than ?5 db 1. de-emphasis 2. de-emphasis on pass band characteristics no. 4838- 11 /14 LC78834M
sample application circuit external system clock supply circuit notes: 1. the nodes marked dv dd and dgnd must be connected to the digital system power supply, and the nodes marked av dd and agnd must be connected to the analog system power supply. 2. ta low-impedance high-stability power supply (equivalent to a commercial three-terminal regulator) must be used for av dd . 3. since it is possible for latchup to occur if the pin 10 (dv dd ) and the pin 28 (av dd ) power supply rise timings differ, the pin 10 and pin 28 power supply application circuit must be designed so that no time differential occurs. 4. after power is applied, the xin pin clock signal must be provided promptly. if the xin pin is held fixed (at low or high) after power is supplied, the ic may be destroyed. no. 4838- 12 /14 LC78834M
no. 4838- 13 /14 LC78834M power application timing 1. the analog power supply (av dd ) and the digital power supply (dv dd ) must be brought up at the same time and must be turned off at the same time. 2. if a time difference occurs between the analog and digital power supplies, design the circuit to meet the following conditions. the power supply rise and fall times must be less than 3 ms apart as shown in figure 1. if the time difference is over 3 ms, then allocate 5 ms or over as the rise or fall time of the power supply that rises or falls first respectively. furthermore, the time difference must be under 50 ms. figure 1 figure 2
ps no. 4838- 14 /14 LC78834M this catalog provides information as of september, 1998. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

▲Up To Search▲

Price & Availability of LC78834M

	To Download LC78834M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .