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| EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 1 1 . general description the EM78P451 is an 8 - bit microprocessor designed and developed with low - power, high speed cmos technology. its operational kernel is implemented with risc - like architecture and is available in the mask rom version. the one time progr ammable (otp) version is flexible, both in mass production or engineering test stages. otp provide users with unlimited volume with favorable price opportunities. this device is equipped with the serial peripheral interface (spi) function and an easy - imple mented rs - 232. the EM78P451 is very suitable for wired communication. only 58 easy - to - learn instructions are needed and user?s program can be emulated with emc in - circuit emulator (ice).
EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 2 2 . feature s ? operating voltage range: 2.3v~5.5v. ? operating temper ature range: 0 c~70 c. ? operating frequency rang (base on 2 clocks ): * crystal mode: dc~20mhz at 5v, dc~8mhz at 3v, dc~4mhz at 2.3v. * rc mode: dc~4mhz at 5v, dc~4mhz at 3v, dc~4mhz at 2.3v. ? low power consumption: * less then 3 ma at 5v/4mhz * typicall y 10 m a during sleep mode ? serial peripheral interface (spi) available. ? 4k 13 bits on chip rom (EM78P451). ? 11 special function registers. ? 140 8 bits on chip general - purposed registers. ? 5 bi - directional i/o ports (35 i/o pins). ? 3 led direct si nking pins with internal serial resistors. ? built - in rc oscillator with external serial resistor, 10% variation. ? built - in power - on reset. ? 5 stacks for subroutine nesting. ? 8 - bit real time clock/counter (tcc) with overflow interrupt. ? two machine clocks or four machine clocks per instruction cycle. ? power down mode. ? programmable wake up from sleep circuit on i/o ports. ? programmable free running on - chip watchdog timer. ? 12 wake - up pins. ? 2 open - drain pins. ? 2 r - option pins. ? 32 programmable pull - high input pins. ? packages: * 40 pin dip 600mil : EM78P451p. * 44 pin qfp : EM78P451aq. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 3 ? four types of interrupts. * external interrupt (/int). * spi transmission completed interrupt. * tcc overflow interrupt. * timer1 comparator match interrupt. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 4 3 . p in a ssignment 2 3 4 5 6 7 8 9 10 11 12 1 13 14 15 16 17 18 19 20 39 38 37 36 35 34 33 32 31 30 29 40 28 27 26 25 24 23 22 21 vss int data p91 sdi/p92 sdo/p93 sck/p94 ss/p95 clk p90 osco p50 p51 p52 p53 p54 p55 p56 p57 p80 p81 p83 p84 p60 p87 p86 p85 p62 p61 p63 p64 p65 p66 r-osci vdd p71 p72 p67 p82 EM78P451p/wm p70 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 p55 p56 p86 p85 p84 p83 p82 nc p81 p80 p57 33 32 31 30 29 28 27 26 25 24 23 p87 p64 p63 p72 p65 p66 p60 p61 p62 p67 p71 p90 p91 sdi/p92 sdo/p93 p50 p51 p52 p53 p54 sck/p94 ss/p95 data clk vss osco r-osci vdd nc nc nc int EM78P451aq p70 fig. 1 pin assignment table 1 pin description symbol pin no. type function description r - osci 39 i * in xtal mode: crystal input; in inte rnal c, external r mode: 56kohm 5% pull high for 1.8432mhz. osco 40 o * in xtal mode: crystal output; in rc mode: instruction clock output. p90~p95 5~10 i/o * general bi - directional i/o port. all of its pins can be pulled - high by software. p90 and p91 ar e pin - change wake up pins. p80~p87 19~26 i/o * general bi - directional i/o port. all of its pins can be pulled - high by software. p80 and p81 are also used as the r - option pins. p70~p72 37~35 i/o * led direct - driving pin with internal serial resistor used as output and is software defined. clk 4 i/o * by connecting p74 and p76 together. * p74 can be pulled - high by software and it is also a pin - change wake up pin. * p76 can be defined as an open - drain output. data 3 i/o * by connecting p75 and p77 togeth er. * p75 can be pulled - high by software and it is also a pin - change wake up pin. * p77 can be defined as an open - drain output. p60~p67 27~34 i/o * general bi - directional port. all of its pins can be pulled - high by software, and pin - change wake up pins. p50~p57 11~18 i/o * general bi - directional i/o port. all of its pins can be pulled - high individually by software. vdd 38 - * power supply pin. vss 1 - * ground pin. /int 2 i * an interrupt schmitt - triggered pin. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 5 * the function of interrupt triggers a t the falling edge. * users can enable it by software. the internal pull - up resistor is around 50k ohms. sdi 7 i/o * serial data in for spi sdo 8 i/o * serial data out for spi. sck 9 i/o * serial clock for spi. /ss 10 i/o * /slave select for spi. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 6 4 . f unction description ioc5 r5 p 5 0 p 5 1 p 5 2 p 5 3 p 5 4 p 5 5 p 5 6 p 5 7 ioc6 r6 p 6 0 p 6 1 p 6 2 p 6 3 p 6 4 p 6 5 p 6 6 p 6 7 ioc7 r7 p 7 0 p 7 1 p 7 2 ioc8 r8 p 8 0 p 8 1 p 8 2 p 8 3 p 8 4 p 8 5 p 8 6 p 8 7 ioc9 r9 p 9 0 p 5 5 / / s s spi engin tmr1 acc r3 stack 1 stack 2 stack 3 stack 4 stack 5 p c rom instruction register instruction decoder alu interrupt control / int r4 ram wdt timer prescaler oscillator/ timming control wdt time-out r1(tcc) sleep & wake up control data & control bus p 9 4 / s c k p 9 3 / s d o p 9 2 / s d i p 9 1 fig. 2 functional block diagram 4 .1 operational registers 1. r0 (indirect address register) r0 is not a physically implemented register. it is used as an indirect addressing pointer. a ny instruction using r0 as register actually accesses data pointed by the ram select register (r4). 2. r1 (tcc) ? increased by the instruction cycle clock. ? written and read by program as any other register. 3. r2 (program counter) & stack ? r2 and the ha rdware stacks are 12 bits wide. ? the structure is depicted in fig. 3. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 7 ? generates 4k 13 on - chip rom addresses to the relative programming instruction codes. one program page is 1024 words long. ? all the r2 bits are set to "1"s as a reset condition oc curs. ? "jmp" instruction allows direct loading of the lower 10 program counter bits. thus, "jmp" allows jump to any location on one page. ? "call" instruction loads the lower 10 bits of the pc, and then pc+1 is pushed into the stack. thus, the subroutine entry address can be located anywhere within a page ? "ret" ("retl k", "reti") instruction loads the program counter with the contents at the top of stack. ? "mov r2, a" allows the loading of an address from the "a" register to the lower 8 bits of pc, and the ninth and tenth bits (a8~a9) of pc are cleared. ? "add r2, a" allows a relative address be added to the current pc, and the ninth and tenth bits of pc are cleared. ? any instruction that is written to r2 (e.g. "add r2, a", "mov r2, a", "bc r2,6", ) (except "tbl") will cause the ninth and tenth bits (a8~a9) of pc to be cleared. thus, the computed jump is limited to the first 256 locations of any program page. ? "tbl" allows a relative address be added to the current pc (r2+a ? r2), and contents of the ninth and tenth bits (a8~a9) of pc are not changed. thus, the computed jump can be on the second (or third, 4th) 256 locations on one program page. ? in case of EM78P451, the most significant bits (a10~a11) will be loaded with the contents of bits ps0~ps1 in the status register (r3) upon the execution of a "jmp", "call", or any other instructions which writes to r2. ? all instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents r2. such instruct ion will need one more instruction cycle. pc a11a10 a9a8 a7 ~ a0 call ret retl reti stack 1 stack 2 stack 3 stack 4 stack 5 000 3ff page 0 00 400 7ff page 1 800 bff page 2 c00 fff page 3 01 10 11 001:hareware in terrupt location 002:software interrupt (int instruction) location fff:reset location fig. 3 program counter organization EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 8 4. r3 (status register) 7 6 5 4 3 2 1 0 gp ps1 ps0 t p z dc c ? bit 0 (c) carry flag ? bit 1 (dc) auxiliary carry flag ? bit 2 (z) zero flag. set to "1" if the result of an arithmetic or logic operation is zero. ? bit 3 (p) power down bit. set to 1 during power on or by a "wdtc" command and reset to 0 by a "slep" command. ? bit 4 (t) time - out bit. set to 1 with the "slep" and th e "wdtc" commands, or during power up and reset to 0 with wdt timeout. ? bits 5 (ps0) ~ 6 (ps1) page select bits. ps0~ps1 are used to pre - select a program memory page. when executing a "jmp", "call", or other instructions which causes the program counter t o be changed (e.g. mov r2, a), ps0~ps1 are loaded into the 11th and 12th bits of the program counter where it selects selecting one of the available program memory pages. note that ret (retl, reti) instruction does not change the ps0~ps1 bits. that is, the return will always be to the page from where the subroutine was called, regardless of the current setting of ps0~ps1 bits. ps1 bit is not used (read as "0") and cannot be modified in EM78P451. ps1 ps0 program memory page [address] 0 0 page 0 [000 - 3ff] 0 1 page 1 [400 - 7ff] 1 0 page 2 [800 - bff] 1 1 page 3 [c00 - fff] ? bit 7 ( gp) general read/write bit. 5. r4 (ram select register) ? bits 0~5 are used to select the registers (address: 00~3f) in the indirect addressing mode. ? bits 6~7 determine which bank is activated among the 4 banks. ? if no indirect addressing is used, the rsr is used as an 8 - bit general - purposed read/writer register. ? see the configuration of the data memory in fig. 4. 6. r5~r8 (port 5 ~ port8) ? four general 8 bits i/o registers ? bo th p74 and p76 read or write data from the data pin, while both p75 and p77 read or write data from the clk pin. 7. r9 (port9) ? a general 6 - bit i/o register. the values of the two most significant bits are read as "0". EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 9 fig. 4 data memory configuration r0 r1 (tcc) r2 (pc) r3 (status) r4 (rsr) r5 (port 5) r6 (port 6) r7 (port 7) r9 (port 9) ra rb rc rd re rf 16 x8 common register 31 x8 bank register (bank 0) 31 x8 bank register (bank 1) 31 x8 bank register (bank 2) 31 x8 bank register (bank 3) 00 01 02 03 04 05 07 06 08 0 a 09 0 b 0 c 0 d 0 e 0 f 11 10 1 e 1 f 3 e 20 21 3 f r3f stack 4 stack 3 stack 2 stack 1 iocc iocd ioc5 ioc6 ioc7 ioc8 ioc9 ioce iocf stack 0 r8 (port 8) 00 01 10 11 EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 10 8. ra (spirb: spi read buffer) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 0x0a spirb/ra srb7 srb6 srb5 srb4 srb3 srb2 srb1 ? srb7~srb0 are the 8 - bit data when complete transmission by spi. 9. rb (spiwb: spi write buffer) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0b spiwb/rb swb7 swb6 swb5 swb4 swb3 swb2 swb1 swb0 ? swb7~swb0 are the 8 - bit data that are waiting for transmission by spi. 10. rc (spis: spi status segister) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0c spis/rc -- -- -- tm1if od3 od4 rbfif rbf ? tm1if (bit 4): 1 = in timer1 mode, receiving completed, and an interrupt occurs if enabled. 0 = in timer1 mode, receiving not completed yet, and an interrupt does not occur. ? od3 (bit 3): open - drain control bit 1 = open - drain enable for sdo, 0 = open - drain disable for sdo. ? od4 (bit 2): open - drain control bit 1 = open - drain enable for sck, 0 = open - drain disable for sck. ? rbfif (bit 1):read buffer full interrupt flag 1 = rece iving completed, spirb is fully exchanged, and an interrupt occurs if enabled. 0 = receiving not completed yet; and spirb has not fully exchanged. ? rbf (bit 0): read buffer full flag 1 = receiving completed; spirb is fully exchanged. 0 = receiving not com pleted yet, and spirb has not fully exchanged. 11. rd (spic: spi control register) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0d spic/rd ces spie sro sse - sbrs2 sbrs1 sbrs0 ? ces (bit 7): clock edge select bit 1 = data shifts out on falling edge, and shifts in on rising edge. data is on hold during the high level. 0 = data shifts out on rising edge, and shifts in on falling edge. data is on hold during the low level. ? spie (bit 6): spi enable bit 1= enable spi mode EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 11 0= disable spi mod e ? sro (bit 5): spi read overflow bit 1 = a new data is received while the previous data is still being held in the spib register. in this situation, the data in spis register will be destroyed. to avoid setting this bit, users had better read spirb regis ter even if only the transmission is implemented. 0 = no overflow. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 12 ? "1" means interrupt request, "0" means non - interrupt. ? r 3f can be cleared by instruction, but cannot be set by instruction. ? iocf is the interrupt mask register. ? note that to read r3f will result to "logic and" of r3f and iocf. 4 .2 special purpose registers 1. a (accumulator) ? internal data transfer, or ins truction operand holding. ? a non - addressable register. 2. cont (control register) 7 6 5 4 3 2 1 0 /phen /int - - pab psr2 psr1 psr0 ? bit 7 (/phen) i/o pin pull - high enable flag. 0: for p60~p67, p74~p75 and p90~p95, the pull - high function is enabled. 1: the pull - high function is disabled. ? bit 6 (int) an interrupt enable flag cannot be written by the contw instruction. 0: interrupt masked by the disi instruction. 1: interrupt enabled by the eni or reti instruction. ? bit4, 5 not used, and to be read as ?0?. ? bit 3 (pab) prescaler assignment bit. 0: tcc 1: wdt ? bit 0 (psr0) ~ bit 2 (psr2) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1: 64 1 1 1 1:256 1:128 ? bits 0~3, and 7 of the cont register are readable and writable. 3. ioc5 ~ ioc9 (i/o port control register) ? "1" put the relative i/o pin into high impedance, while "0" put the relative i/o pin as output. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 13 ? both p74 and p76 should not be defined as output pins at the same time. this also applies to both p75 and p77. ? only the lower 6 bits of the ioc9 register are used. 4. iocc (t1con: timer1 control register) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0c t1con/ iocc 0 0 0 0 0 tm1e tm1p1 tm1p0 ? tm1e (bit2): timer1 function enable bit 1 = enable timer1 function. 0 = disable timer1 function as default. ? tm1p (bit1~bit0): timer1 prescaler bit timer1 prescaler table for fosc will be illustrated in the section on ti mer1 in later pages. 5. iocd (pull - high control register) 7 6 5 4 3 2 1 0 s7 - - - /pu9 /pu8 /pu6 /pu5 ? the default values of /pu5, /pu6, /pu8, and /pu9 are one, which means the pull - high function is disabled. ? /pu6 and /pu9 are ?and? gating with /phen , that is, when each one is written as ?0? pull high is enabled. ? s7 defines the driving ability of the p70 - p72. 0: normal output. 1: enhance the driving ability of led. 6. ioce (wdt control register) 7 6 5 4 3 2 1 0 - ode wdte slpc roc - - /wue ? bit 0 (/wue) control bit used to enable the wake - up function of p60~p67, p74~p75, and p90~p91. 0: enable the wake - up function. 1: disable the wake - up function. the /wue bit can be read and written. ? bit 3 (roc) roc is used for the r - option. setting roc to "1" will enable the status of r - option pins (p80, p81) to be read by the controller. clearing roc will disable the r - option function. otherwise, the r - option function is introduced. users must connect the p81 pin or/and p80 pin to vss by a 560k w external resis tor (rex). if rex is connected/disconnected with vdd, the status of p80 (p81) will be read as "0"/"1" (refer to fig. 7(b)). the roc bit can be read and written. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 14 ? bit 4 (slpc) this bit is set by hardware at the falling edge of wake - up signal and is cleared in software. slpc is used to control the oscillator operation. the oscillator is disabled (oscillator is stopped, and the controller enters the sleep2 mode) on the high - to - low transition and is enabled (the controller is awakened from sleep2 mode) on low - to - high transition. in order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18 ms (oscillator start - up timer (ost)) before the next program instruction is executed. the ost is always activated by wake - up from sleep mode whether the code option bit enwdt is "0" or not. after waking up, the wdt is enabled if code option enwdt is "1". the block diagram of sleep2 mode and wake - up caused by input triggered is depicted in fig. 5. the slpc bi t can be read and written. ? bit 5 (wdte) control bit used to enable watchdog timer. the wdte bit can be used only if enwdt, the code option bit, is "1". if the enwdt bit is "1", then wdt can be disabled/enabled by the wdte bit. 0: disable wdt. 1: enable w dt. the wdte bit is not used if enwdt, the code option bit enwdt, is "0". that is, if the enwdt bit is "0", wdt is always disabled no matter what the wdte bit is. the wdte bit can be read and written. ? bit 6 (ode) open - drain control bit. 0: both p76 and p 77 are normally i/o pins. 1: both p76 and p77 pins have the open - drain function inside. the ode bit can be read and written. ? bits 1~2, and 7 not used. 7. iocf (interrupt mask register) 7 6 5 4 3 2 1 0 - - - - tm1ie spiie exie tcie ? bit 0 (tcie) tcif i nterrupt enable bit. 0: disable tcif interrupt 1: enable tcif interrupt ? bit 1 (exie) exif interrupt enable bit. 0: disable exif interrupt 1: enable exif interrupt ? bit 2 (spiie) spi interrupt enable bit. 0: disable spi interrupt EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 15 1: enable spi interrupt ? bit 3 (tm1ie) tm1ie interrupt enable bit. 0: disable tm1ie interrupt 1: enable tm1ie interrupt ? bits 4~7 not used. ? individual interrupt is enabled by setting its associated control bit in iocf to "1". ? the iocf register could be read and written. oscillator enable d isable reset q d q clk p r c l clear from s/w set 4 /wue /wue /wue vcc p60~p67 vcc /wue p74~p75, p90~p91 /phen 8 fig. 5 block diagram of sleep mode and wake - up circuits on i/o ports EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 16 4 .3 tcc/wdt presacler an 8 - bit counter is available as prescaler for the tcc or wdt. the prescaler is available for either the tcc or wdt o nly at any given time, and the pab bit of cont register is used to determine the prescaler assignment. the psr0~psr2 bits determine the prescale ratio. the prescaler is cleared each time the instruction is written to tcc under tcc mode. the wdt and prescal er, when assigned to wdt mode, are cleared by the wdtc or slep instructions. fig. 6 depicts the circuit diagram of tcc/wdt. ? r1(tcc) is an 8 - bit timer/counter. tcc will increase by one at every instruction cycle (without prescaler). ? the watchdog timer i s a free running on - chip rc oscillator. the wdt will keep running even when the oscillator driver has been turned off (i.e. in sleep mode). during normal operation or sleep mode, a wdt time - out (if enabled) will cause the device to reset. the wdt can be en abled or disabled any time during the normal mode by software programming (if code option bit enwdt is "1"). refer to wdte bit of ioce register. without presacler, the wdt time - out period is approximately 18 ms 1 . 4 .4 i/o ports the i/o registers, from port 5 to port 9, are bi - directional tri - state i/o ports. p60~p67, p74~p75, and p90~p91 provide internal pull - high. p60~p67, p74~p75, and p90~p95 provide programmable wake - up function through software. p76~p77 can have open - drain output by software control. p8 0~p81 are the r - option pins which are enabled by software. when the r - option function is used, it is recommended that p80 and p81 are used as output pins. during r - option enabled state, p80 and p81 must be programmed as input pins. if an external resistor is connected to p80 (p81) for the r - option function, the current consumption should be taken as an important factor in the applications for low power consideration. the i/o ports can be defined as "input" or "output" pins by the i/o control registers (ioc5 ~ioc9) under program control. the i/o registers and i/o control registers are both readable and writable. the i/o interface circuit is shown in fig. 7. note that the reading path source of input and output pins is different when reading the i/o port. 1 note: vdd = 5v, set up time period = 16.2ms 5% vdd = 3v, set up time period = 18.0ms 5% EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 17 clk(=fosc/2) data bus 1 0 m u x sync 2 cycles tcc(r1) pab tcc overflow interrupt 0 1 wdt wdte (in ioce) m u x wdt timeout 8 - bit counter 8 - to - 1 mux psr0~psr2 0 1 mux pab fig. 6 block diagram of tcc wdt pdrd q q clk d p r c l pcwr pdwr q q clk d p r c l port 0 1 m u x iod pcrd fig. 7 (a) the circuit of i/o port and i/o control register EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 18 pdrd q q clk d p r c l pcwr pdwr q q clk d p r c l 0 1 m u x iod roc vcc weakly pull - up port rex* *the rex is 560k ohm external resistor pcrd fig.7(b) the circuit of i/o port with r - option (p80, p81) 4 .5 serial peripheral interface mode 1. overview & features overview: figures 8, 9, and 10 show how EM78P451 communicates with other devices through spi module. if EM78P451 is a master controller, it sends clock through the sck pin. a co uple of 8 - bit data are transmitted and received at the same time. however, if EM78P451is defined as a slave, its sck pin could be programmed as an input pin. data will continue to be shifted based on both the clock rate and the selected edge. features: ? o peration in either master mode or slave mode, ? three - wire or four - wire synchronous communication; that is, full duplex ? programmable baud rates of communication, ? programming clock polarity, (rd bit7) ? interrupt flag available for the read buffer full, EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 19 ? up to 8 mhz ( maximum ) bit frequency, spi module sck spir reg sdi spiw reg spis reg /ss slave device sdo bit 7 spi module spir reg spiw reg spis reg master device fig. 8 spi master/slave communication sdi sdo sck /ss p50 p51 p52 p53 master slave device 1 slave device 2 slave device 3 slave device 4 vdd sdo sdi sck /ss sdo sdi sck /ss sdo sdi sck /ss sdo sdi sck /ss fig. 9 the spi configuration of single - master and multi - slave EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 20 or slave1 slave 2 for master 1 slave 3 for master 1/2 slave 4 for master1/2 slave 5 for master 2 or slave6 sdi sdo sck /ss sdi sdo sck /ss p50 p51 p52 p53 p50 p51 p52 p53 sdo sdi sck /ss sdo sdi sck /ss sdo sdi sck /ss sdo sdi sck /ss master1 master2 fig. 10 the spi configuration of single - master and multi - slave EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 21 2. spi function description read write spir reg spis reg shift right bit 0 bit 7 prescaler 4, 8, 16, 32, 64 spiw reg p92/sdi p93/sdo p95/ /ss p94/sck / ss edge select edge select spic bit6 tsco tmr1/2 sbr2~sbr0 8 clock select 2 noise filter spic reg sbr0 ~sbr2 rbf rbfi buffer full detector set to 1 se fig. 11 spi block diagram spi mode select register 8-1 mux 2 1 0 spic spi write register (0x0b) 7~0 spiwb spi shift buffer spi read register (0x0a) data bus fosc 1 0 t1con 6 4 spic 1 0 4 spis spic spi 7 2 intc 7~0 spirb sdo sdi /ss shift clock fig. 12 the function block diagram of spi transmission EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 22 the following describes the function of each block and explains how to carry out the spi communication with the signals depicted in fig.11 and fig.12: ? p92/sdi: serial data in. ? p93/sdo: s erial data out. ? p94/sck: serial clock. ? p95//ss: /slave select (option). this pin (/ss) may be required during a slave mode. ? rbf: set by buffer full detector, and reset in software. ? rbif: set by buffer full detector, and reset in software. ? buff er full detector: sets to 1 when an 8 - bit shifting is completed. ? sse: loads the data in spis register, and begin to shift ? spis reg.: shifting byte in and out. the msb is shifted first. both the spis register and the spiw register are loaded at the sam e time. once data are written, spis starts transmission / reception. the received data will be moved to the spir register as the shifting of the 8 - bit data is completed. the rbf (read buffer full) flag and the rbfi(read buffer full interrupt) flag are then set. ? spir reg.: read buffer. the buffer will be updated as the 8 - bit shifting is completed. the data must be read before the next reception is completed. the rbf flag is cleared as the spir register reads. ? spiw reg.: write buffer. the buffer will deny any attempt to write until the 8 - bit shifting is completed. the sse bit will be kept in 1 if the communication is still undergoing. this flag must be cleared as the shifting is completed. users can determine if the next write attempt is available. ? sbr s2~sbrs0 : programming the clock frequency/rates and sources. ? clock select : selecting either the internal or external clock as the shifting clock. ? edge select : selecting the appropriate clock edges by programming the ces bit 3. spi signal & pin descri ption the detailed functions of the four pins, sdi, sdo, sck, and /ss, which are shown in fig. 9, are as follows: sdi/p92 (pin 7): ? serial data in, ? receive serially, the most significant bit (msb) first, least significant bit (lsb) last, ? defined as h igh - impedance, if not selected, ? program the same clock rate and clock edge to latch on both the master and slave devices, EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 23 ? the received byte will update the transmitted byte, ? both the rbf and rbfif bits (located in register 0x0c) will be set as the sp i operation is completed. ? timing is shown in fig.13 and14. sdo/p93 (pin 8): ? serial data out, ? transmit serially; the most significant bit (msb) first, least significant bit (lsb) last, ? program the same clock rate and clock edge to latch on both the master and slave devices, ? the received byte will update the transmitted byte, ? the ces (located in register 0x0d) bit will be reset, as the spi operation is completed. ? timing is shown in fig.13 and 14. sck/p94 (pin 9): ? serial clock ? generated by a master device ? synchronize the data communication on both the sdi and sdo pins ? the ces (located in register 0x0d) is used to select the edge to communicate. ? the sbr0~sbr2 (located in register 0x0d) is used to determine the baud rate of communication ? the ces, sbr0, sbr1, and sbr2 bits have no effect in the slave mode ? timing is show in fig.13 and 14 /ss/p95 (pin 10): ? slave select; negative logic, ? generated by a master device to signify the slave(s) to receive data, ? goes low before the first c ycle of sck appears, and remains low until the last (eighth) cycle is completed, ? ignores the data on the sdi and sdo pins while /ss is high, because the sdo is no longer driven. ? timing is shown in fig.13 and fig. 14. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 24 4. programmed the related register s as the spi mode is defined, the related registers of this operation are shown in table 2 and table 3. table 2 related control registers of the spi mode address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0d *spic/rd c es spie sro sse -- sbr2 sbr1 sbr0 0x0f intc/iocf -- -- -- -- tm1ie spiie exie tcie ? spic: spi control register. ? ces (bit 7): clock edge select bit 1 = data shifts out on falling edge, and shifts in on rising edge. data is on hold during the high leve l. 0 = data shifts out on rising edge, and shifts in on falling edge. data is on hold during the low level. ? spie (bit 6): spi enable bit 1 = enable spi mode 0 = disable spi mode ? sro (bit 5): spi read overflow bit 1 = a new data is received while the prev ious data is still being on hold in the spib register. under this condition, the data in spis register will be destroyed. to avoid setting this bit, users should read the spirb register even if the transmission is implemented only. 0 = no overflow. < note > : this can only occur under slave mode. ? sse (bit 4): spi shift enable bit 1 = start to shift, and stays on 1 while the current byte continues to transmit. 0 = reset as soon as the shifting is completed and the next byte is ready to shift. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 25 ? bit 3 (tm1ie) tm1ie interrupt enable bit. 0: disable tm1ie interrupt 1: enable tm1ie interrupt ? bit 2 (spiie) spi interr upt enable bit. 0: disable spi interrupt 1: enable spi interrupt ? bit 1 (exie) exif interrupt enable bit. 0: disable exif interrupt 1: enable exif interrupt ? bit 0 (tcie) tcif interrupt enable bit. 0: disable tcif interrupt 1: enable tcif interrupt table 3 related status/data registers of the spi mode address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0a spirb/ra srb7 srb6 srb5 srb4 srb3 srb2 srb1 srb0 0x0b spiwb/rb swb7 swb6 swb5 swb4 swb3 swb2 swb1 swb0 0x0c spis/ rc 0 0 0 tm1if od3 od4 rbfif rbf ? spirb: spi read buffer. once the serial data is received completely, it will load to spirb from spisr. the rbf bit and the rbfif bit in the spis register will be set also. ? spiwb: spi write buffer. as a transmitted data is loaded, the spis register stands by and start to shift the data when sensing sck edge with sse set to ?1?. ? spis : spi status register ? tm1if (bit 4): timer1 interrupt flag. ? od3 (bit 3): open - drain control bit (p93) 1 = open - drain enable for sdo, 0 = open - drain disable for sdo. ? od4 (bit 2): open drain - control bit (p94) 1 = open - drain enable for sck, 0 = open - drain disable for sck. ? rbfif (bit 1): read buffer full interrupt flag 1 = receive is completed, spib is full, and an interrupt occurs if enab led. 0 = receive is ongoing, spib is empty. ? rbf (bit 0): read buffer full flag 1 = receive is completed, spib is full. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 26 0 = receive is ongoingt, spib is empty. 5. spi mode timing the edge of sck is selected by programming bit ces. the waveform shown in fi g.13 is applicable regardless of whether the EM78P451 is under master or slave mode with /ss disabled. however, the waveform in fig. 14 can only be implemented in slave mode with /ss enabled. fig. 13 spi mode with /ss disable fig. 14 spi mode with /ss enable EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 27 6. software application of spi example for spi: for master org 0x0 setting: clra iow 0x05 ;s et p ort 5 output iow 0x06 ;s et p ort 6 output mov 0x05,a mov a,@0b11001111 ;s et prescaler for wdt contw mov a,@0b00010001 ;d isable wakeup functi on iow 0x0e mov a,@0b00000000 ;d isable interrupt iow 0x0f mov a,@0 x 07 ;sdi input and sdo, sck output iow 0 x 09 mov a,@0b10000000 ;c lear rbf and rbfif flag mov 0 x 0c,a mov a,@0b11100000 ;s elect clock ed ge and enable spi mov 0x0d,a start: wdtc bc 0x0c,1 ;c lear rbfif flag mov a,@0xff mov 0x05,a ;s how a signal at p ort 5 mov 0x0a,a ;m ove ff at read buffer mov a,@0xaa ;m ove aa at write buffer mov 0x0b,a bs 0x0d,4 ;s tart to shift spi data nop jbc 0x 0d,4 ;p olling loop for chec king spi transmission complet ed jmp $ - 2 EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 28 bc 0x03,2 call delay ;t o catch the data fro m slaver mov a,0x0a xor a,@0x5a ;c ompare the data from slaver jbs 0x03,2 jmp start flag: mov a,@0x55 ;s how the signal when receiving corre ct data from slaver mov 0x05,a call delay jmp start delay: ; ( user ? s program ) eop org 0xfff jmp setting EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 29 for slaver org 0x0 initi: jmp init org 0x2 interrupt: ;i nterrupt address mov a,@0x55 mov 0x06,a ;s how a signal at p ort 6 when enterin g interrupt mov a,@0b11100110 ;e nable spi, /ss disabled mov 0x0d,a bs 0x0d,4 ;k eep sse at 1 to wait for sck signal in order to s hift data mov a,@0x00 ;m ove 00 to write buffer in o rder to keep master ? s read buffer as 00 mov 0x0b,a bs 0x0d,4 ;k eep sse at 1 to wait for sck signal in order to s hift data nop jbc 0x0d,4 ;p olling loop for chec king spi transmission complet ed jmp $ - 2 bs 0x0d,4 ;k eep sse at 1 to wait for sck signal in order to s hift data bc 0x03,2 mov a,0x0a mov 0x06,a ;r ead master ? s d ata from read buffer xor a,@0xaa ;c heck pass signal fro m read buffer jbs 0x03,2 jmp $ - 6 jmp spi org 0x30 init: clra iow 0x05 iow 0x06 mov 0 x 05,a mov 0x06,a EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 30 mov a,@0xff iow 0x08 mov a,@0b11001111 ;s et prescaler for wdt contw mov a,@0b00010001 ;d isable wakeup functi on iow 0x0e mov a,@0b00000010 ;e nable external inter rupt iow 0xf eni mov a,@0b00110111 iow 0 x 09 bc 0x3f,1 ;c lear rbfif flag nop jbs 0x3f,1 ;p olling loop for chec king interrupt occur ence jmp $ - 2 jmp interrupt spi: bs 0x0 d,4 ;k eep sse enabled as long as p ossible wdtc mov a,@0x0f ;s how a signal when en tering spi loop mov 0x06,a jbc 0x08,1 ;c hoose p81 as a signal button jmp spi mov a,@0x5a ;m ove 5a into write buffer wh en p81 button is pushed mov 0x0b,a nop jbc 0x0d, 4 ;p olling loop for chec king spi transmission complet ed jmp $ - 2 bs 0xd,4 nop nop mov a,@0xf0 ;d isplay at p ort 6 when p81 button is pushed mov 0x06,a mov a,@0x00 ;s end a signal to mast er to prevent infini te loop EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 31 mov 0x0b,a nop jbc 0x0d,4 jmp $ - 2 bs 0x0d,4 bs 0 x 0c,7 bc 0 x 0c,1 nop jmp spi delay: ; ( user ? s program ) eop org 0xfff jmp initi EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 32 4 .6 timer 1 1. overview timer1(tmr1) is an eight - bit clock counter with a programmable prescaler. it is designed for the spi module as a baud rate cloc k generator. tmr1 can be read and written and cleared on any reset conditions. if employed, it can be turned down for power saving by setting tmr1en bit [t1con<2>] to 0. 2. function description fig. 15 shows timer1 block diagram. each signal and block is d escribed as follows: fig. 15 timer1 block diagram ? osc/4 : input clock. ? prescaler : option of 1:1, 1:4, 1:8, and 1:16 defined by t1p1 and t1p02 (t1con<1, 0>). it is cleared when a value is written to tmr1 or t1con, and during any kind of reset as well. ? pwp : pulse width preset register. the desired width of baud clock is written in advance. ? tmr1 : timer 1 register. tmr1 increases until it matches with pwp, and then resets to 0. if it is chosen optionally in the spi mode, its outp ut is fed as a shifting clock. ? comparator: to change the output status while a match occurs. the tmr1if flag will be set at the same time. 3. programmed the related registers the related registers of the defining tmr1 operation are shown in table 4 and table 5 EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 33 table 4 related control registers of the tmr1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0c spis/rc 0 0 0 tm1if od3 od4 rbfif rbf 0x0f intc/iocf 0 0 0 0 tm1ie spiie exie tcie table 5 related status/data registers oftmr1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0e tmr1/re tmr17 tmr16 tmr15 tmr14 tmr13 tmr12 tmr11 tmr10 0x0f pwp/rf pwp7 pwp6 pwp5 pwp4 pwp3 pwp2 pwp1 pwp0 0x0c t1con/iocc 0 0 0 0 0 tm1e tm 1p1 tm1p0 ? tmr1: timer1 register tmr17~tmr10 is bit set of timer1 register and it increases until the value matches pwp and then it reset to 0. ? pwp: pulse width preset register pwp7~pwp0 is bit set of pulse width preset for the desired width of baud cl ock in advance. ? t1con: timer1 control register tm1e (bit2): timer1 enable bit tm1p1 and tm1p0 (bit1~0): timer1 prescaler for fsco tm1p1 tm1p0 prescaler rate 0 0 1:1 0 1 1:4 1 0 1:8 1 1 1:16 EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 34 4 .7 reset and wake - up a reset is initiated by (1) power o n reset, or (2) wdt timeout. (if enabled) wdte setup time wdt wdt timeout power- on reset voltage detector oscillator vdd d q clk clr clk reset fig. 16 block diagram of reset the device is kept in a reset condition for a period of approx. 18ms 1 (one oscillator start - up timer period) after the reset is detec ted and fig.16 is the block diagram of reset. once the reset occurs, the following functions are performed. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all "1". ? when power is switched on, bits 5~6 of r3 and th e upper 2 bits of r4 are cleared. ? all i/o port pins are configured as input mode (high - impedance state). ? the watchdog timer and prescaler are cleared. ? the watchdog timer is enabled if code option bit enwdt is "1". ? the cont register is set to al l "1" except bit 6 (int flag). ? bits 3,6 of ioce register are cleared, bits 0,4~5 of ioce register are set to "1". 1 note: vdd = 5v, set up time period = 16.2ms 5% vdd = 3v, set up time period = 18.0ms 5% EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 35 ? bits 0 of r3f and bits 0 of iocf registers are cleared. the sleep mode (power down) is achieved by executing the slep instruction (named as sleep1 mode). while entering sleep mode, the wdt (if enabled) is cleared but keeps on running. the controller is awakened by wdt timeout (if enabled), and it will cause the controller to reset. the t and p flags of r3 are used to determine the source o f the reset (wake - up). in addition to the basic sleep1 mode, EM78P451 has another sleep mode (caused by clearing "slpc" bit of ioce register, designated as sleep2 mode). in the sleep2 mode, the controller can be awakened by - (a) any one of the wake - up pins is set to ?0.? (refer to fig.17 ). upon waking, the controller will continue to execute the program in - line. in this case, before entering sleep2 mode, the wake - up function of the trigger sources (p60~p67, p74~p75, and p90~p91)should be selected (e.g. inp ut pin) and enabled (e.g. pull - high, wake - up control). one caution should be noted is that after waking up, the wdt is enabled if code option bit enwdt is "1". the wdt operation (to be enabled or disabled) should be appropriately controlled by software aft er waking up. (b) wdt time - out (if enabled). on wake - up, will cause the controller reset. table 6 the summary of the initialized values for registers address name reset type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit na me c57 c56 c55 c54 c53 c52 c51 c50 n/a ioc5 power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name c67 c66 c65 c64 c63 c62 c61 c60 n/a ioc6 power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name c77 c76 c75 c74 c73 c72 c71 c70 n/a ioc7 power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name c87 c86 c85 c84 c83 c82 c81 c80 n/a ioc8 power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name c97 c96 c95 c94 c93 c92 c91 c90 n/a ioc9 power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name /phen /int - - pab psr2 psr1 psr0 n/a cont power - on 1 0 1 1 1 1 1 1 /reset and wdt 1 p 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name - - - - - - - - EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 36 0x00 r0(iar) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name - - - - - - - - 0x01 r1(tcc) power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake - up from pin change p p p p p p p p bit name - - - - - - - - 0x02 r2(pc) power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change **p **p **p **p **p **p **p **p bit name gp ps1 ps0 t p z dc c 0x03 r3(sr) power - on 0 0 0 t t u u u /reset and wdt 0 0 0 t t p p p wake - up from pin change p p p t t p p p bit name rsr.1 rsr.0 - - - - - - 0x04 r4(rsr) power - on 0 0 u u u u u u /reset and wdt 0 0 p p p p p p wake - up from pin change p p p p p p p p bit name p57 p56 p55 p54 p53 p52 p51 p50 0x05 r5(p5) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name p67 p66 p65 p64 p63 p62 p61 p60 0x06 r6(p6) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name p77 p76 p75 p74 p73 p72 p71 p70 0x07 r7( p7) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name p87 p86 p85 p84 p83 p82 p81 p80 0x08 r8(p8) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name p97 p96 p95 p94 p93 p92 p91 p90 0x09 r9(p9) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name srb7 srb6 srb5 srb4 srb3 srb2 srb1 srb0 0x0a ra(spirb) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p bit name swb7 swb6 swb5 swb4 swb3 swb2 swb1 swb0 0x0b rb(spiwb) power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p b it name ensd o obdc ibdc tiif od3 od4 rbfif rbf 0x0c rc(spis) power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake - up from pin change p p p p p p p p bit name ces spie sro spise - sbrs 2 sbrs 1 sbrs 0 EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 37 0x0d rd(spic) power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake - up from pin change p p p p p p p p bit name tmr1 7 tmr1 6 tmr1 5 tmr1 4 tmr1 3 tmr1 2 tmr1 1 tmr1 0 0x0e re(tmr1) power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake - up from pin change p p p p p p p p bit name pwp7 pwp6 pwp5 pwp4 pwp3 pwp2 pwp1 pwp0 0x0f rf(pwp) power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name - - - - t1if spiif exif tcif 0x3f r3f(isr) power - on u u u u 0 0 0 0 /reset and wdt u u u u 0 0 0 0 wake - up from pin change u u u u p p p p bit name - - - - - t1e t1p1 t1p0 0x0c iocc power - on 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 wake - up from pin change p p p p p p p p bit name s7 - - - /pu9 /pu8 /pu6 /pu5 0x0d iocd power - on 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 wake - up from pin change p p p p p p p p bit name - ode wte slpc roc - - /wue 0x0e ioce power - on u 0 1 1 0 u u 1 /reset and wdt u 0 1 1 0 u u 1 wake - up from pin change u p 1 1 p u u p bit name - - - - t1ie spiie exie tcie 0x0f iocf power - on u u u u 0 0 0 0 /reset and wdt u u u u 0 0 0 0 wake - up from pin change u u u u p p p p bit name - - - - - - - - 0x10~0x3e gpr power - on u u u u u u u u /reset and wdt p p p p p p p p wake - up from pin change p p p p p p p p ** to execute the next instruction after the ?slpc? bit status of ioce register being on high - to - low transition. x: not used. u: unknown or don?t care. p: previous value before reset. t: check table 7 the status of rst, t, and p of status register a reset condition is initiated by the following events: 1. a power - on condition, 2. watchdog timer time - out. the values of t and p, listed in table 7 are used to check how the processor wakes up. tabl e 8 shows the events that may affect the status of t and p. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 38 table 7 the values of rst, t and p after reset reset type t p power on 1 1 wdt during operating mode 0 p wdt wake - up during sleep1 mode 0 0 wdt wake - up during sleep2 mode 0 p wake - up on pin change during sleep2 mode p p *p: previous value before reset table 8 the status of rst, t and p being affected by events event t p power on 1 1 wdtc instruction 1 1 wdt time - out 0 *p slep instruction 1 0 wake - up on pin change during sleep2 mode p p *p: previous value before reset 4 .8 interrupt the EM78P451 has the following interrupts. 1. /tcc overflow interrupt 2. external interrupt (/int) 3. serial peripheral interface (spi) transmission completed interrupt. 4. timer1 comparator completed interrupt. r3f is the interrupt status register, which records the interrupt request in flag bit. iocf is the interrupt mask register. global interrupt is enabled by eni instruction and is disabled by disi instruc tion. when one of the interrupts (if enabled) is generated, will cause the next instruction to be fetched from address 001h. once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the r3f register. t he interrupt flag bit must be cleared by software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. the flag in the interrupt status register (r3f) is set regardless of the status of its mask bit or the exe cution of eni instruction. note that reading r3f will obtain the output of logic and of r3f and iocf (refer to fig. 17). the reti instruction exits interrupt routine and enables the global interrupt (execution of eni instruction). when an interrupt is gene rated by int instruction (if enabled), it causes the next instruction to be EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 39 fetched from address 002h. q q clk d p r c l q q clk d p r c l /irqn r3f reset iocf rfwr iocf rd iocfwr rfrd irqn irqm iod eni/disi interrupt fig. 17 interrupt input circuit 4 .9 oscillator 1. oscillator modes the EM78P451 can operate in four dif ferent oscillator modes. there are high xtal (hxt) oscillator mode, low xtal (lxt) oscillator mode, external rc oscillator mode (erc), and internal c ?b external r oscillator modes. user can select one of them by programming ms, rct, irc, hlf and hlp in the c ode option register. table 9 depicts how these three modes are defined. table 9 oscillator modes by ms, irc, rct. mode ms irc rct hlf hlp high xtal oscillator 1 x x 1 x low xtal oscillator 1 x x 0 0 external rc oscillator 0 1 1 x x external r and internal c oscillator 0 1 0 x x EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 40 and c2. since each resonator has its own attribute, user should refer to its specification fo r appropriate values of c1 and c2. rs, a serial resistor may be necessary for at strip cut crystal or low frequency mode. osci osco EM78P451 ext. clock fig. 18 circuit for external clock input osci osco EM78P451 c1 c2 xtal rs fig. 19 circuit for crystal/resonator table 10 capacitor selection guide for crystal oscillator ceramic resonators oscillator type frequency mode frequency c1 (pf) c2 (pf) 455 khz 10~150 10~150 1. 0 mhz 40~80 40~80 2.0 mhz 20~40 20~40 ceramic resonator hxt 4.0 mhz 10~30 10~30 32.768 khz 25 15 100 khz 25 25 lxt 200 khz 25 25 455 khz 20~40 20~150 1.0 mhz 15~30 15~30 2.0 mhz 15 15 crystal oscillator hxt 4.0 mhz 15 15 EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 41 osci EM78P451 c 7404 330 330 xtal 7404 7404 fig. 2 0 circuit for crystal/resonator - series mode osci EM78P451 7404 4.7k 10k xtal 7404 c1 vdd 10k c2 fig. 21 circuit for crystal/resonator - parallel mode 3. rc oscillator mode for some applications that do not need a very precise timing c alculation, the rc oscillator (fig 22 & fig 23) offers a lot of cost savings. nevertheless, it should be noted that the frequency of the rc oscillator is influenced by the supply voltage, the values of the resistor (rext), the capacitor (cext), and even by the operation temperature. moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. in order to maintain a stable system frequency, the values of the cext should not be less than 20pf, and that the value of rext should not be greater than 1 m ohm. if they cannot be kept in this range, the frequency is easily affected by noise, humidity, and leakage. the smaller the rext in the rc oscillator, the faster its frequency will be. on the contrary, for ver y low EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 42 rext values, for instance, 1 k w , the oscillator becomes unstable because the nmos cannot discharge the current of the capacitance correctly. based on the reasons above, it must be kept in mind that all of the supply voltage, the operation temperature , the components of the rc oscillator, the package types, the way the pcb is layout, will affect the system frequency. osci EM78P451 vcc rext cext fig. 22 circuit for external rc oscillator mode osci EM78P451 vcc rext fig. 23 circuit for external r, internal c oscillator mode calibrate frequency of external rc oscillator (for reference only) c ext r ext fosc @5.0v,25 j 3.3k 3.4mhz 5.1k 2.2mhz 10k 1.3mhz 20pf 100k 144khz 3.3k 1.39mhz 5.1k 935khz 10k 500khz 100pf 100k 54.5khz EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 43 3.3k 740khz 5.1k 490khz 10k 255khz 300pf 100k 28khz internal c, external r table (for reference only) external r (ohm) fosc @5.0v, 25 j (hz) 10k 12m 15k 7.7m 20k 5.7m 30k 3.65m 51k 2.24m 100k 1.14m 150k 749k 20 0k 559k 510k 214k 2m 56k 3.3m 32.8k 4 .10. code option register : address 12 11 10 9 8 7 6 5 4 3 2 1 0 0xfff ms enwdt clks ptb hlf rct hlp del0 del1 id3 id2 id1 id0 ? bit 12 (ms): oscillator type selection. 0: rc type 1: xtal type ? bit 11 (enwdt): wa tchdog timer enabled. 0: enable 1: disable ? bit 10 (clks): clocks of each instruction cycle. 0: two clocks 1: four clocks ? bit 9 (ptb): protect bit. 0: protect enabled 1: protect disabled ? bit 8 (hlf): xtal frequency selection. 0: low frequency (32.768k hz) 1: high frequency this bit is useful only when bit 12 (ms) is 1. when ms is 0, hlf must be 0. EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 44 ? bit 7 (rct): resistor capacitor. 0: internal rc 1: external rc ? bit 6 (hlp): power consumption selection. 0: low power 1: high power ? bit 5 ~ bit 4: del1 and del0 (sdi) input delay time options. del 1 del 0 delay time 1 1 0 ns 0 1 50 ns 1 0 100 ns ? bit3~0 (id): user?s id code. ? procedures to configure the rc oscillators by programming the option code: i. enable external rc oscillator: ms (0) - > irc (1 ) - > rct (1) ii. enable external r and internal c oscillator: ?ms (0) - > irc (1) - > rct (0) 4 .11 instruction set each instruction in the instruction set is a 13 - bit word divided into an op code and one or more operands. all instructions are executed within one single instruction cycle (consisting of 2 oscillator periods), unless the program counter is changed by - (a) executing the instruction "mov r2,a", "add r2,a", "tbl", or any other instructions that write to r2 (e.g. "sub r2,a", "bs r2,6", "clr r2", ). (b) execute call, ret, reti, retl, jmp, conditional skip (jbs, jbc, jz, jza, djz, djza) which were tested to be true. under these cases, the execution takes two instruction cycles. in addition, the instruction set has the following features: (1). every bit of any register can be set, cleared, or tested directly. (2). the i/o register can be regarded as general register. that is, the same instruction can operate on i/o register. the symbol "r" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. bits 6 and 7 in r4 determine the selected register bank. "b" represents a bit field designator that selects the value for EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 45 the bit located in the register "r" and affects operation. "k" represents an 8 or 10 - bit constant or literal value. instruction binary hex mnemonic operation status affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a ? cont none 0 0000 0000 0011 0003 slep 0 ? wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 ? wdt t,p 0 0000 0000 rrrr 000r iow r a ? iocr none EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 46 instruction binary hex mnemonic operation status affected 0 011 1 01rr rrrr 07rr swap r r(0 - 3) ? r(4 - 7) none 0 0111 10rr rrrr 07rr jza r r+1 ? a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 ? r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 ? r(b) none EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 47 4. 12 timing diagram s reset timing (clk="0") clk /reset nop instruction 1 executed tdrh tcc input timing (clks="0") clk tcc ttcc tins ac testing : input is driven at 2.4v for logic "1",and 0.4v for logic "0".timing measurements are made at 2.0v for logic "1",and 0.8v for logic "0". ac test input/output waveform 2.4 0.4 2.0 0.8 test points 2.0 0.8 EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 48 5 . a bsolute m aximum rating items rating temperature under bias 0 c to 70 c storage temperature - 65 c to 150 c input voltage - 0.3v to +6.0v output voltage - 0.3v to +6.0v operating frequency (2clk) dc to 20mhz EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 49 6 . e lectrical c haracteristics (1) dc characteristic (ta=0 c~70 c, vdd=5v 5% , vss=0v) symbol parameter condition min typ max unit xtal vdd to 2.3v dc 4 x tal vdd to 3v dc 8 fxt xtal vdd to 5v two clocks dc 20 mhz rc vdd to 2.3v dc 4 rc vdd to 3v dc 4 frc rc vdd to 5v two clocks dc 4 mhz iil input leakage current vin = vdd, vss 1 m a vih1 input high voltage vdd=5v) 2.0 v vil1 input low voltage (vdd= 5v) 0.8 v vihx1 clock input high voltage (vdd=5v) osci 2.5 v vilx1 clock input low voltage (vdd=5v) osci 1.0 v vih2 input high voltage(vdd=3v) 1.5 v vil2 input low voltage (vdd=3v) 0.4 v vihx2 clock input high voltage (vdd=3v) osci 1.5 v vilx2 clock input low voltage (vdd=3v) osci 0.6 v voh1 output high voltage (ports 5,6,8, p74~p77, p90~p92,p95~p97,and pf5~pf7) ioh = - 8.0ma 2.4 v s7=1(iocd register bit7), ioh = - 7.0ma 2 2.4 voh2 output high voltage (p70~p72) s7=0(iocd regis ter bit7), ioh = - 7.0ma 2.4 v voh3 output high voltage (p93/sdo,p94/sck) ioh = - 5.0ma 2.4 v vol1 output low voltage (ports 5,6,8, p74~p77, p90~p92,p95~p97,and pf5~pf7)) iol = 5.0ma 0.4 v s7=1(iocd register bit7), i oh = 10.0ma 0.4 0.8 vol2 output low voltage (p70~p72) s7=0(iocd register bit7), ioh = 10.0ma 0.4 v vol3 output low voltage (p93/sdo, p94/sck) iol = 7.0ma 0.4 v EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 50 vol4 output low voltage (p74~p77) iol = 15.0ma 0.4 iph pull - high current pull - high active, input pin at vss - 50 - 100 - 240 m a iph2 pull - high current (p74,p75) pull - high active, input pin at vss 1 ma isb power down current all input and i/o pin at vdd, output pin floating, wdt enabled 10 m a icc operating supply current /reset="high", fosc=1.84324mhz (ck2="0"), o utput pin floating 3 ma (2) ac characteristic (ta=0 c~70 c, vdd=5v 5% , vss=0v) symbol parameter conditions min typ max unit dclk input clk duty cycle 45 50 55 % tins instruction cycle time (ck2="0") rc type 500 dc ns ttcc tcc input period (tins+20)/ n* ns twdt watchdog timer period ta=25 c 18 ms tdrh device reset hold period ta=25 c 18 1 ms n= selected prescaler ratio. 1 note: vdd = 5v, set up time period = 16.2 ms 5% vdd = 3v, set up time period = 18.0ms 5% EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 51 7 . application circuit EM78P451 EM78P451 otp rom this specification is subject to change without prior notice. 2002/03/01 52 a ppendix package types: otp mcu package type pin count package size EM78P451p dip 40 600 mil em7 8p451aq qfp 44 |
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