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general description the DS8113 smart card interface is a low-cost, analog front-end for a smart card reader, designed for all iso 7816, emv?, and gsm11-11 applications. the DS8113 supports 5v, 3v, and 1.8v smart cards. the DS8113 provides options for low active- and stop-mode power consumption, with as little as 10na stop-mode current. the DS8113 is designed to interface between a system microcontroller and the smart card interface, providingall power supply, esd protection, and level shifting required for ic card applications. an emv level 1 certified library (written for the maxq2000 microcontroller) and hardware reference design is available. contact maxim technical support at micro.support@maxim-ic.com regarding requirements for other microcontroller platforms. an evaluation kit, DS8113 -kit, is available to aid in prototyping and evaluation. applications consumer set-top boxes access control banking applications pos terminals debit/credit payment terminals pin pads automated teller machines telecommunications pay/premium television features analog interface and level shifting for ic card communication 8kv (min) esd (iec) protection on card interface ultra-low stop-mode current, less than 10na typical internal ic card supply-voltage generation: 5.0v ?%, 80ma (max) 3.0v ?%, 65ma (max) 1.8v ?0%, 30ma (max) automatic card activation and deactivation controlled by dedicated internal sequencer i/o lines from host directly level shifted for smart card communication flexible card clock generation, supporting external crystal frequency divided by 1, 2, 4, or 8 high-current, short-circuit and high-temperature protection low active-mode current d s 8 1 1 3 smart card interface ________________________________________________________________ maxim integrated products 1 or dering information rev 1; 2/08 note: contact the factory for availability of other variants and package options. + denotes a lead-free package. emv is a trademark owned by emvco llc. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim website at www.maxim--c.com. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . p a r t t e m p r a n g e p i n - p a c k a g e d s 8 1 1 3 - r n g + - 4 0 c t o + 8 5 c 2 8 s o selector guide appears at end of data sheet. pgnd 28 27 26 25 24 23 22 aux2in aux1in i/oin xtal2 top view DS8113 xtal1 off gnd 21 vdd 20 rstin 19 cmdvcc 18 1_8v 17 vcc 16 rst 15 clk 5v/3v clkdiv2 clkdiv1 cp1 vdda vup pres pres i/o aux2 aux1 4 1 2 3 5 6 7 8 9 10 11 12 13 14 cgnd cp2 so pin configuration
d s 8 1 1 3 smart card interface 2 _______________________________________________________________________________________ absolute maximum ratings recommended dc operating conditions (v dd = +3.3v, v dda = +5.0v, t a = +25, unless otherwise noted.) (note 1) stresses beyond those listed under bsolute maximum ratings?ay cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on vdd relative to gnd...............-0.5v to +6.5v v oltage range on vdda relative to pgnd ..........-0.5v to +6.5v voltage range on cp1, cp2, and vup relative to pgnd...............................................-0.5v to +7.5v v oltage range on all other pins relative to gnd......................................-0.5v to (v dd + 0.5v) maximum junction temperature .....................................+125 m aximum power dissipation (t a = -25 to +85? .......700mw storage temperature range .............................-55 to +150c soldering temperature.........refer to the ipc/jedec j-std-020 s pecification. p a r a m e t e r s y m b o l c o n d i t i o n s m i n t y p m a x u n i t s p o w e r s u p p l y d i g i t a l s u p p l y v o l t a g e v d d 2 . 7 6 . 0 v c a r d v o l t a g e - g e n e r a t o r s u p p l y v o l t a g e v d d a v d d a > v d d 5 . 0 6 . 0 v v t h 2 t h r e s h o l d v o l t a g e ( f a l l i n g ) 2 . 3 5 2 . 4 5 2 . 5 5 v r e s e t v o l t a g e t h r e s h o l d s v h y s 2 h y s t e r e s i s 5 0 . 0 1 0 0 1 5 0 m v c u r r e n t c o n s u m p t i o n a c t i v e v d d c u r r e n t 5 v c a r d s ( i n c l u d i n g 8 0 m a d r a w f r o m 5 v c a r d ) i d d _ 5 0 v i c c = 8 0 m a , f x t a l = 2 0 m h z , f c l k = 1 0 m h z , v d d a = 5 . 0 v 8 0 . 7 5 8 5 . 0 0 m a a c t i v e v d d c u r r e n t 5 v c a r d s ( c u r r e n t c o n s u m e d b y d s 8 1 1 3 o n l y ) i d d _ i c i c c = 8 0 m a , f x t a l = 2 0 m h z , f c l k = 1 0 m h z , v d d a = 5 . 0 v ( n o t e 2 ) 0 . 7 5 5 . 0 0 m a a c t i v e v d d c u r r e n t 3 v c a r d s ( i n c l u d i n g 6 5 m a d r a w f r o m 3 v c a r d ) i d d _ 3 0 v i c c = 6 5 m a , f x t a l = 2 0 m h z , f c l k = 1 0 m h z , v d d a = 5 . 0 v 6 5 . 7 5 7 0 . 0 0 m a a c t i v e v d d c u r r e n t 3 v c a r d s ( c u r r e n t c o n s u m e d b y d s 8 1 1 3 o n l y ) i d d _ i c i c c = 6 5 m a , f x t a l = 2 0 m h z , f c l k = 1 0 m h z , v d d a = 5 . 0 v ( n o t e 2 ) 0 . 7 5 5 . 0 0 m a a c t i v e v d d c u r r e n t 1 . 8 v c a r d s ( i n c l u d i n g 3 0 m a d r a w f r o m 1 . 8 v c a r d ) i d d _ 1 8 v i c c = 3 0 m a , f x t a l = 2 0 m h z , f c l k = 1 0 m h z , v d d a = 5 . 0 v 3 0 . 7 5 3 5 . 0 0 m a a c t i v e v d d c u r r e n t 1 . 8 v c a r d s ( c u r r e n t c o n s u m e d b y d s 8 1 1 3 o n l y ) i d d _ i c i c c = 3 0 m a , f x t a l = 2 0 m h z , f c l k = 1 0 m h z , v d d a = 5 . 0 v ( n o t e 2 ) 0 . 7 5 5 . 0 0 m a i n a c t i v e - m o d e c u r r e n t i d d c a r d i n a c t i v e , a c t i v e - h i g h p r e s , d s 8 1 1 3 n o t i n s t o p m o d e 5 0 . 0 2 0 0 a s t o p - m o d e c u r r e n t i d d _ s t o p d s 8 1 1 3 i n u l t r a - l o w - p o w e r s t o p m o d e ( c m d v c c , 5 v / 3 v , a n d 1 _ 8 v s e t t o l o g i c 1 ) ( n o t e 3 ) 0 . 0 1 2 . 0 0 a
d s 8 1 1 3 smart card interface _______________________________________________________________________________________ 3 recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25, unless otherwise noted.) (note 1) p a r a m e t e r s y m b o l c o n d i t i o n s m i n t y p m a x u n i t s c l o c k s o u r c e c r y s t a l f r e q u e n c y f x t a l e x t e r n a l c r y s t a l 0 2 0 m h z f x t a l 1 0 2 0 m h z v i l _ x t a l 1 l o w - l e v e l i n p u t o n x t a l 1 - 0 . 3 0 . 3 x v d d x t a l 1 o p e r a t i n g c o n d i t i o n s v i h _ x t a l 1 h i g h - l e v e l i n p u t o n x t a l 1 0 . 7 x v d d v d d + 0 . 3 v e x t e r n a l c a p a c i t a n c e f o r c r y s t a l c x t a l 1 , c x t a l 2 1 5 p f i n t e r n a l o s c i l l a t o r f i n t 2 . 2 2 . 7 3 . 2 m h z s h u t d o w n t e m p e r a t u r e s h u t d o w n t e m p e r a t u r e t s d + 1 5 0 c r s t p i n o u t p u t l o w v o l t a g e v o l _ r s t 1 i o l _ r s t = 1 m a 0 0 . 3 v c a r d - i n a c t i v e m o d e o u t p u t c u r r e n t i o l _ r s t 1 v o _ l r s t = 0 v 0 - 1 m a o u t p u t l o w v o l t a g e v o l _ r s t 2 i o l _ r s t = 2 0 0 a 0 0 . 3 v o u t p u t h i g h v o l t a g e v o h _ r s t 2 i o h _ r s t = - 2 0 0 a v c c - 0 . 5 v c c v r i s e t i m e t r _ r s t c l = 3 0 p f 0 . 1 s f a l l t i m e t f _ r s t c l = 3 0 p f 0 . 1 s s h u t d o w n c u r r e n t t h r e s h o l d i r s t ( s d ) - 2 0 m a c u r r e n t l i m i t a t i o n i r s t ( l i m i t ) - 2 0 + 2 0 m a c a r d - a c t i v e m o d e r s t i n t o r s t d e l a y t d ( r s t i n - r s t ) 2 s c l k p i n o u t p u t l o w v o l t a g e v o l _ c l k 1 i o l c l k = 1 m a 0 0 . 3 v c a r d - i n a c t i v e m o d e o u t p u t c u r r e n t i o l _ c l k 1 v o l c l k = 0 v 0 - 1 m a o u t p u t l o w v o l t a g e v o l _ c l k 2 i o l c l k = 2 0 0 a 0 0 . 3 v o u t p u t h i g h v o l t a g e v o h _ c l k 2 i o h c l k = - 2 0 0 a v c c - 0 . 5 v c c v r i s e t i m e t r _ c l k c l = 3 0 p f ( n o t e 4 ) 8 n s f a l l t i m e t f _ c l k c l = 3 0 p f ( n o t e 4 ) 8 n s c u r r e n t l i m i t a t i o n i c l k ( l i m i t ) - 7 0 + 7 0 m a c l o c k f r e q u e n c y f c l k o p e r a t i o n a l 0 1 0 m h z d u t y f a c t o r c l = 3 0 p f 4 5 5 5 % c a r d - a c t i v e m o d e s l e w r a t e s r c l = 3 0 p f 0 . 2 v / n s v c c p i n o u t p u t l o w v o l t a g e v c c 1 i c c = 1 m a 0 0 . 3 v c a r d - i n a c t i v e m o d e o u t p u t c u r r e n t i c c 1 v c c = 0 v 0 - 1 m a
d s 8 1 1 3 smart card interface 4 _______________________________________________________________________________________ recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25, unless otherwise noted.) (note 1) p a r a m e t e r s y m b o l c o n d i t i o n s m i n t y p m a x u n i t s 6 5 m a < i c c ( 5 v ) < 8 0 m a 4 . 5 5 5 . 0 0 5 . 2 5 i c c ( 5 v ) < 6 5 m a 4 . 7 5 5 . 0 0 5 . 2 5 i c c ( 3 v ) < 6 5 m a 2 . 7 8 3 . 0 0 3 . 2 2 i c c ( 1 . 8 v ) < 3 0 m a 1 . 6 5 1 . 8 0 1 . 9 5 5 v c a r d ; c u r r e n t p u l s e s o f 4 0 n c w i t h i < 2 0 0 m a , t < 4 0 0 n s , f < 2 0 m h z 4 . 6 5 . 4 3 v c a r d ; c u r r e n t p u l s e s o f 2 4 n c w i t h i < 2 0 0 m a , t < 4 0 0 n s , f < 2 0 m h z 2 . 7 5 3 . 2 5 o u t p u t l o w v o l t a g e v c c 2 1 . 8 v c a r d ; c u r r e n t p u l s e s o f 1 2 n c w i t h i < 2 0 0 m a , t < 4 0 0 n s , f < 2 0 m h z 1 . 6 2 1 . 9 8 v v c c ( 5 v ) = 0 t o 5 v - 8 0 v c c ( 3 v ) = 0 t o 3 v - 6 5 o u t p u t c u r r e n t i c c 2 v c c ( 1 . 8 v ) = 0 t o 1 . 8 v - 3 0 m a s h u t d o w n c u r r e n t t h r e s h o l d i c c ( s d ) 1 2 0 m a c a r d - a c t i v e m o d e s l e w r a t e v c c s r u p / d o w n ; c < 3 0 0 n f ( n o t e 5 ) 0 . 0 5 0 . 1 6 0 . 2 2 v / s d a t a l i n e s ( i / o a n d i / o i n ) i / o i / o i n f a l l i n g e d g e d e l a y t d ( i o - i o i n ) 2 0 0 n s p u l l u p p u l s e a c t i v e t i m e t p u 1 0 0 n s m a x i m u m f r e q u e n c y f i o m a x 1 m h z i n p u t c a p a c i t a n c e c i 1 0 p f i / o , a u x 1 , a u x 2 p i n s o u t p u t l o w v o l t a g e v o l _ i o 1 i o l _ i o = 1 m a 0 0 . 3 v o u t p u t c u r r e n t i o l _ i o 1 v o l _ i o = 0 v 0 - 1 m a c a r d - i n a c t i v e m o d e i n t e r n a l p u l l u p r e s i s t o r r p u _ i o t o v c c 9 1 1 1 9 k o u t p u t l o w v o l t a g e v o l _ i o 2 i o l _ i o = 1 m a 0 0 . 3 v i o h _ i o = < - 2 0 a 0 . 8 x v c c v c c o u t p u t h i g h v o l t a g e v o h _ i o 2 i o h _ i o = < - 4 0 a ( 3 v / 5 v ) 0 . 7 5 x v c c v c c v o u t p u t r i s e / f a l l t i m e t o t c l = 3 0 p f 0 . 1 s i n p u t l o w v o l t a g e v i l _ i o - 0 . 3 + 0 . 8 i n p u t h i g h v o l t a g e v i h _ i o 1 . 5 v c c v i n p u t l o w c u r r e n t i i l _ i o v i l _ i o = 0 v 6 0 0 a i n p u t h i g h c u r r e n t i i h _ i o v i h _ i o = v c c 2 0 a i n p u t r i s e / f a l l t i m e t i t 1 . 2 s c u r r e n t l i m i t a t i o n i i o ( l i m i t ) c l = 3 0 p f - 1 5 + 1 5 m a c a r d - a c t i v e m o d e c u r r e n t w h e n p u l l u p a c t i v e i p u c l = 8 0 p f , v o h = 0 . 9 x v d d - 1 m a
d s 8 1 1 3 smart card interface _______________________________________________________________________________________ 5 recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25, unless otherwise noted.) (note 1) p a r a m e t e r s y m b o l c o n d i t i o n s m i n t y p m a x u n i t s i / o i n , a u x 1 i n , a u x 2 i n p i n s o u t p u t l o w v o l t a g e v o l i o l = 1 m a 0 0 . 3 v n o l o a d 0 . 9 x v d d v d d + 0 . 1 o u t p u t h i g h v o l t a g e v o h i o h < - 4 0 a 0 . 7 5 x v d d v d d + 0 . 1 v o u t p u t r i s e / f a l l t i m e t o t c l = 3 0 p f , 1 0 % t o 9 0 % 0 . 1 s i n p u t l o w v o l t a g e v i l - 0 . 3 0 . 3 x v d d v i n p u t h i g h v o l t a g e v i h 0 . 7 x v d d v d d + 0 . 3 v i n p u t l o w c u r r e n t i i l _ i o v i l = 0 v 6 0 0 a i n p u t h i g h c u r r e n t i i h _ i o v i h = v d d 1 0 a i n p u t r i s e / f a l l t i m e t i t v i l t o v i h 1 . 2 s i n t e g r a t e d p u l l u p r e s i s t o r r p u p u l l u p t o v d d 9 1 1 1 3 k c u r r e n t w h e n p u l l u p a c t i v e i p u c l = 3 0 p f , v o h = 0 . 9 x v d d - 1 m a c o n t r o l p i n s ( c l k d i v 1 , c l k d i v 2 , c m d v c c , r s t i n , 5 v / 3 v , 1 _ 8 v ) i n p u t l o w v o l t a g e v i l - 0 . 3 0 . 3 x v d d v i n p u t h i g h v o l t a g e v i h 0 . 7 x v d d v d d + 0 . 3 v i n p u t l o w c u r r e n t i i l _ i o 0 < v i l < v d d 5 a i n p u t h i g h c u r r e n t i i h _ i o 0 < v i h < v d d 5 a i n t e r r u p t o u t p u t p i n ( o f f ) o u t p u t l o w v o l t a g e v o l i o l = 2 m a 0 0 . 3 v o u t p u t h i g h v o l t a g e v o h i o h = - 1 5 a 0 . 7 5 x v d d v i n t e g r a t e d p u l l u p r e s i s t o r r p u p u l l u p t o v d d 1 6 2 0 2 4 k p r e s , p r e s p i n s i n p u t l o w v o l t a g e v i l _ p r e s 0 . 3 x v d d v i n p u t h i g h v o l t a g e v i h _ p r e s 0 . 7 x v d d v i n p u t l o w c u r r e n t i i l _ p r e s v i l _ p r e s = 0 v 4 0 a i n p u t h i g h c u r r e n t i i h _ p r e s v i h _ p r e s = v d d 4 0 a
d s 8 1 1 3 smart card interface 6 _______________________________________________________________________________________ recommended dc operating conditions (continued) (v dd = +3.3v, v dda = +5.0v, t a = +25, unless otherwise noted.) (note 1) p a r a m e t e r s y m b o l c o n d i t i o n s m i n t y p m a x u n i t s t i m i n g a c t i v a t i o n t i m e t a c t 5 0 2 2 0 s d e a c t i v a t i o n t i m e t d e a c t 5 0 8 0 1 0 0 s w i n d o w s t a r t t 3 5 0 1 3 0 c l k t o c a r d s t a r t t i m e w i n d o w e n d t 5 1 4 0 2 2 0 s p r e s / p r e s d e b o u n c e t i m e t d e b o u n c e 5 8 1 1 m s note 1: operation guaranteed at -40 and +85?but not tested. note 2: idd_ic measures the amount of current used by the DS8113 to provide the smart card current minus the load. note 3: stop mode is enabled by setting cmdvcc , 5v/ 3v , and 1_8v to a logic-high. note 4: parameters are guaranteed to meet all iso 7816, gsm11-11, and emv 2000 requirements. for the 1.8v card, the maximum rise and fall time is 10ns. note 5: parameter is guaranteed to meet all iso 7816, gsm11-11, and emv 2000 requirements. for the 1.8v card, the minimum slew rate is 0.05v/? and the maximum slew rate is 0.5v/?.
d s 8 1 1 3 smart card interface _______________________________________________________________________________________ 7 pin description p i n n a m e f u n c t i o n 1 , 2 c l k d i v 1 , c l k d i v 2 c l o c k d i v i d e r . d e t e r m i n e s t h e d i v i d e d - d o w n i n p u t c l o c k f r e q u e n c y ( p r e s e n t e d a t x t a l 1 o r f r o m a c r y s t a l a t x t a l 1 a n d x t a l 2 ) o n t h e c l k o u t p u t p i n . d i v i d e r s o f 1 , 2 , 4 , a n d 8 a r e a v a i l a b l e . 3 5 v / 3 v 5 v / 3 v s e l e c t i o n p i n . a l l o w s s e l e c t i o n o f 5 v o r 3 v f o r c o m m u n i c a t i o n w i t h a n i c c a r d . l o g i c - h i g h s e l e c t s 5 v o p e r a t i o n ; l o g i c - l o w s e l e c t s 3 v o p e r a t i o n . t h e 1 _ 8 v p i n o v e r r i d e s t h e s e t t i n g o n t h i s p i n i f a c t i v e . s e e t a b l e 3 f o r a c o m p l e t e d e s c r i p t i o n o f c h o o s i n g c a r d v o l t a g e s . 4 p g n d a n a l o g g r o u n d 5 , 7 c p 2 , c p 1 s t e p - u p c o n v e r t e r c o n t a c t . u n u s e d f o r t h e d s 8 1 1 3 . 6 v d d a c h a r g e p u m p s u p p l y . m u s t b e e q u a l t o o r h i g h e r t h a n v d d . f o r t h e d s 8 1 1 3 t h i s m u s t b e a t l e a s t 5 . 0 v . 8 v u p c h a r g e p u m p o u t p u t . u n u s e d f o r t h e d s 8 1 1 3 . 9 p r e s c a r d p r e s e n c e i n d i c a t o r . a c t i v e - l o w c a r d p r e s e n c e i n p u t s f r o m t h e d s 8 1 1 3 t o t h e m i c r o c o n t r o l l e r . w h e n t h e p r e s e n c e i n d i c a t o r b e c o m e s a c t i v e , a d e b o u n c e t i m e o u t b e g i n s . a f t e r 8 m s ( t y p ) t h e o f f s i g n a l b e c o m e s a c t i v e . 1 0 p r e s c a r d p r e s e n c e i n d i c a t o r . a c t i v e - h i g h c a r d p r e s e n c e i n p u t s f r o m t h e d s 8 1 1 3 t o t h e m i c r o c o n t r o l l e r . w h e n t h e p r e s e n c e i n d i c a t o r b e c o m e s a c t i v e , a d e b o u n c e t i m e o u t b e g i n s . a f t e r 8 m s ( t y p ) t h e o f f s i g n a l b e c o m e s a c t i v e . 1 1 i / o s m a r t c a r d d a t a - l i n e o u t p u t . c a r d d a t a c o m m u n i c a t i o n l i n e , c o n t a c t c 7 . 1 2 , 1 3 a u x 2 , a u x 1 s m a r t c a r d a u x i l i a r y l i n e ( c 4 , c 8 ) o u t p u t . d a t a l i n e c o n n e c t e d t o c a r d r e a d e r c o n t a c t s c 4 ( a u x 1 ) a n d c 8 ( a u x 2 ) . 1 4 c g n d s m a r t c a r d g r o u n d 1 5 c l k s m a r t c a r d c l o c k . c a r d c l o c k , c o n t a c t c 3 . 1 6 r s t s m a r t c a r d r e s e t . c a r d r e s e t o u t p u t f r o m c o n t a c t c 2 . 1 7 v c c s m a r t c a r d s u p p l y v o l t a g e . d e c o u p l e t o c g n d ( c a r d g r o u n d ) w i t h 2 x 1 0 0 n f o r 1 0 0 + 2 2 0 n f c a p a c i t o r s ( e s r < 1 0 0 m ) . 1 8 1 _ 8 v 1 . 8 v o p e r a t i o n s e l e c t i o n . a c t i v e - h i g h s e l e c t i o n f o r 1 . 8 v s m a r t c a r d c o m m u n i c a t i o n . a n a c t i v e - h i g h s i g n a l o n t h i s p i n o v e r r i d e s a n y s e t t i n g o n t h e 5 v / 3 v p i n . 1 9 c m d v c c a c t i v a t i o n s e q u e n c e i n i t i a t e . a c t i v e - l o w i n p u t f r o m h o s t . 2 0 r s t i n c a r d r e s e t i n p u t . r e s e t i n p u t f r o m t h e h o s t . 2 1 v d d s u p p l y v o l t a g e 2 2 g n d d i g i t a l g r o u n d 2 3 o f f s t a t u s o u t p u t . a c t i v e - l o w i n t e r r u p t o u t p u t t o t h e h o s t . u s e a 2 0 k i n t e g r a t e d p u l l u p r e s i s t o r t o v d d . 2 4 , 2 5 x t a l 1 , x t a l 2 c r y s t a l / c l o c k i n p u t . c o n n e c t a n i n p u t f r o m a n e x t e r n a l c l o c k t o x t a l 1 o r c o n n e c t a c r y s t a l a c r o s s x t a l 1 a n d x t a l 2 . f o r t h e l o w i d l e - m o d e c u r r e n t v a r i a n t , a n e x t e r n a l c l o c k m u s t b e d r i v e n o n x t a l 1 . 2 6 i / o i n i / o i n p u t . h o s t - t o - i n t e r f a c e c h i p d a t a i / o l i n e . 2 7 , 2 8 a u x 1 i n , a u x 2 i n c 4 / c 8 i n p u t . h o s t - t o - i n t e r f a c e i / o l i n e f o r a u x i l i a r y c o n n e c t i o n s t o c 4 a n d c 8 .
d s 8 1 1 3 detailed description the DS8113 is an analog front-end for communicating with 1.8v, 3v, and 5v smart cards. it is a dual input- voltage device, requiring one supply to match that of a host microcontroller and a separate +5v supply for generating correct smart card supply voltages. the DS8113 translates all communication lines to the cor- rect voltage level and provides power for smart card operation. it is a low-power device, consuming very lit- tle current in active-mode operation (during a smart card communication session), and is suitable for use in battery-powered devices such as laptops and pdas, consuming only 10na in stop mode. see figure 1 for a functional diagram. power supply the DS8113 is a dual-supply device. the supply pins for the device are vdd, gnd, vdda, and pgnd. v d d should be in the range of 2.7v to 6.0v, and is the sup- ply for signals that interface with the host controller. it should, therefore, be the same supply as used by the host controller. all smart card contacts remain inactive during power-on or power-off. the internal circuits are kept in the reset state until v dd reaches v th2 + v hys2 and for the duration of the internal power-on reset pulse, t w . a deactivation sequence is executed when v dd falls below v th2 . an internal regulator generates the 1.8v, 3v, or 5v card supply voltage (v cc ). the regulator should be supplied separately by vdda and pgnd. vdda should be con- nected to a minimum 5.0v supply in order to provide the correct supply voltage for 5v smart cards. voltage supervisor the voltage supervisor monitors the v dd supply. a 220 s reset pulse (t w ) is used internally to keep the device inactive during power-on or power-off of thev dd supply. see figure 2. the DS8113 card interface remains inactive no matter the levels on the command lines until duration t w after v dd has reached a level higher than v th2 + v hys2 . when v dd falls below v th2 , the DS8113 executes a card deactivation sequence if its card interface is active. smart card interface 8 _______________________________________________________________________________________ temperature monitor card voltage generator clock generation control sequencer power-supply supervisor i/o transceiver vdd gnd vdda pgnd cp1 cp2 vup vcc xtal1 xtal2 clkdiv1 clkdiv2 1_8v 5v/3v cmdvcc rstin cgnd rst clk i/o aux1 aux2 pres pres off i/oin aux1in aux2in DS8113 figure 1. functional diagram vdd alarm (internal signal) power on t w t w power off v th2 + v hys2 v th2 supply dropout figure 2. voltage supervisor behavior
clock circuitry the card clock signal (clk) is derived from a clock sig- nal input to xtal1 or from a crystal operating at up to 20mhz connected between xtal1 and xtal2. the output clock frequency of clk is selectable through inputs clkdiv1 and clkdiv2. the clk signal fre- quency can be f x tal , f x tal/2 , f x tal/4 , or f x tal/8 . see table 1 for the frequency generated on the clk signal given the inputs to clkdiv1 and clkdiv2. note that clkdiv1 and clkdiv2 must not be changed simultaneously; a delay of 10ns minimum between changes is needed. the minimum duration of any state of clk is eight periods of xtal1. the frequency change is synchronous: during a transi- tion of the clock divider, no pulse is shorter than 45% of the smallest period, and the first and last clock pulses about the instant of change have the correct width. when changing the frequency dynamically, the change is effective for only eight periods of xtal1 after the command. the f xtal duty factor depends on the input signal on xtal1. to reach a 45% to 55% duty factor on clk, xtal1 should have a 48% to 52% duty factor with tran- sition times less than 5% of the period. with a crystal, the duty factor on clk can be 45% to 55% depending on the circuit layout and on the crystal characteristics and frequency. in other cases, the duty factor on clk is guaranteed between 45% and 55% of the clock period. if the crystal oscillator is used or if the clock pulse on xtal1 is permanent, the clock pulse is applied to the card as shown in the activation sequences in figures 3 and 4. if the signal applied to xtal1 is controlled by the host microcontroller, the clock pulse is applied to the card when it is sent by the system microcontroller (after completion of the activation sequence). i/o transceivers the three data lines i/o, aux1, and aux2 are identical. this section describes the characteristics of i/o and i/oin but also applies to aux1, aux1in, aux2, and aux2in. i/o and i/oin are pulled high with an 11k resistor (i/o to vcc and i/oin to vdd) in the inactive state. the first side of the transceiver to receive a falling edge becomes the master. when a falling edge is detected (and the master is decided), the detection of falling edges on the line of the other side is disabled; that side then becomes a slave. after a time delay t d(edge) , an n transistor on the slave side is turned on, thus transmit- ting the logic 0 present on the master side. when the master side asserts a logic 1, a p transistor on the slave side is activated during the time delay t pu and then both sides return to their inactive (pulled up) states. this active pullup provides fast low-to-high tran - sitions. after the duration of t pu , the output voltage depends only on the internal pullup resistor and the load current. current to and from the card i/o lines is limited internally to 15ma. the maximum frequency on these lines is 1mhz. inactive mode the DS8113 powers up with the card interface in the inactive mode. minimal circuitry is active while waiting for the host to initiate a smart card session. ? all card contacts are inactive (approximately 200 to gnd). ? pins i/oin, aux1in, and aux2in are in the high- impedance state (11k pullup resistor to vdd). ? voltage generators are stopped. ? xtal oscillator is running (if included in the device). ? voltage supervisor is active. ? the internal oscillator is running at its low frequency. activation sequence after power-on and the reset delay, the host microcon- troller can monitor card presence with signals off and cmdvcc , as shown in table 2. d s 8 1 1 3 smart card interface _______________________________________________________________________________________ 9 table 1. clock frequency selection c l k d i v 1 c l k d i v 2 f c l k 0 0 f x t a l / 8 0 1 f x t a l / 4 1 1 f x t a l / 2 1 0 f x t a l table 2. card presence indication o f f c m d v c c s t a t u s h i g h h i g h c a r d p r e s e n t . l o w h i g h c a r d n o t p r e s e n t .
d s 8 1 1 3 if the card is in the reader (if pres is active), the host microcontroller can begin an activation sequence (start a card session) by pulling cmdvcc low. the following events form an activation sequence (figure 3): 1) cmdvcc is pulled low. 2) the internal oscillator changes to high frequency (t 0 ). 3) the voltage generator is started (between t 0 and t 1 ). 4) v c c rises from 0 to 5v, 3v, or 1.8v with a con- trolled slope (t 2 = t 1 + 1.5 t). t is 64 times the internal oscillator period (approximately 25?). 5) i/o, aux1, and aux2 are enabled (t 3 = t 1 + 4t) (they were previously pulled low). 6) the clk signal is applied to the c3 contact (t 4 ). 7) rst is enabled (t 5 = t 1 + 7t). to apply the clock to the card interface: 1) set rstin high. 2) set cmdvcc low. 3) set rstin low between t 3 and t 5 ; clk will now start. 4) rst stays low until t 5 , then rst becomes the copy of rstin. 5) rstin has no further effect on clk after t 5 . if the applied clock is not needed, set cmdvcc low with rstin low. in this case, clk starts at t 3 (minimum 200ns after the transition on i/o, see figure 4); after t 5 , rstin can be set high to obtain an answer to request (atr) from an inserted smart card. do not perform acti- vation with rstin held permanently high. active mode when the activation sequence is completed, the DS8113 card interface is in active mode. the host microcontroller and the smart card exchange data on the i/o lines. smart card interface 10 ______________________________________________________________________________________ atr cmdvcc rst rstin clk vcc i/o i/oin t 0 t 1 t 2 t 3 t 4 t 5 = t act figure 3. activation sequence using rstin and cmdvcc
d s 8 1 1 3 smart card interface ______________________________________________________________________________________ 11 atr cmdvcc rst rstin clk vcc i/o i/oin t 0 t 1 t 2 t 3 t 4 t 5 = t act 200ns figure 4. activation sequence at t 3 rst clk vcc cmdvcc i/o t 10 t de t 12 t 13 t 14 t 15 figure 5. deactivation sequence
d s 8 1 1 3 deactivation sequence when a session is completed, the host microcontroller sets the cmdvcc line high to execute an automatic deactivation sequence and returns the card interface to the inactive mode (figure 5). 1) rst goes low (t 10 ). 2) clk is held low (t 12 = t 10 + 0.5 t) where t is 64 times the period of the internal oscillator (approxi- mately 25?). 3) i/o, aux1, and aux2 are pulled low (t 13 = t 10 + t). 4) v cc starts to fall (t 14 = t 10 + 1.5 t). 5) when v cc reaches its inactive state, the deactiva- tion sequence is complete (at t de ). 6) all card contacts become low impedance to gnd; i/oin, aux1in, and aux2in remain at v dd (pulled up through an 11k resistor). 7) the internal oscillator returns to its lower frequency. v cc generator the v cc generator has a capacity to supply up to 80ma continuously at 5v, 65ma at 3v, and 30ma at 1.8v. an internal overload detector triggers at approxi- mately 120ma. current samples to the detector are fil- tered. this allows spurious current pulses (with a duration of a few ?) up to 200ma to be drawn without causing deactivation. the average current must stay below the specified maximum current value. to main- tain v cc voltage accuracy, a 100nf capacitor (with an esr < 100m ) should be connected to cgnd and placed near the DS8113 vcc pin, and a 100nf or 220nf capacitor (220nf is the best choice) with the same esr should be connected to cgnd and placed near the smart card reader c1 contact. fault detection the following fault conditions are monitored: ? short-circuit or high current on vcc ? removal of a card during a transaction ? d d dropping ? card voltage generator operating out of the speci- fied values (v d da too low or current consumption too high) ? overheating there are two different cases (figure 6): ? cmdvcc high outside a card session. output off is low if a card is not in the card reader and high if a card is in the reader. the v dd supply is monitored decrease in input voltage generates an internal power-on reset pulse but does not affect the off signal. short-circuit and tempera- ture detection is disabled because the card is not powered up. ? cmdvcc low within a card session. output off goes low when a fault condition is detected, and an emergency deactivation is performed auto- matically (figure 7). when the system controller resets cmdvcc to high, it may sense the off level again after completing the deactivation sequence. this distinguishes between a card extraction and a hardware problem ( off goes high again if a card is present). depending on the con- nector card--resent switch (normally closed or normally open) and the mechanical characteristics of the switch, bouncing can occur on the pres sig- nals at card insertion or withdrawal. the DS8113 has a debounce feature with an 8ms typi- cal duration (figure 6). when a card is inserted, output off goes high after the debounce time delay. when the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on pres and output off goes low. smart card interface 12 ______________________________________________________________________________________
d s 8 1 1 3 smart card interface ______________________________________________________________________________________ 13 debounce debounce vcc pres off deactivation caused by cards withdrawal deactivation caused by short circuit cmdvcc figure 6. behavior of pres, off , cmdvcc , and vcc rst clk vcc pres off i/o t 10 t de t 12 t 13 t 14 t 15 figure 7. emergency deactivation sequence (card extraction)
d s 8 1 1 3 stop mode (low-power mode) a low-power state, stop mode, can be entered by forc- ing the cmdvcc , 5v/ 3v , and 1_8v input pins to a logic-high state. stop mode can only be entered when the smart card interface is inactive. in stop mode all internal analog circuits are disabled. the off pin fol- lows the status of the pres pin. to exit stop mode, change the state of one or more of the three control pins to a logic-low. an internal 220? (typ) power--p delay and the 8ms pres debounce delay are in effect and off is asserted to allow the internal circuitry to sta- bilize. this prevents smart card access from occurring after leaving the stop mode. figure 8 shows the control sequence for entering and exiting stop mode. note that an in-progress deactivation sequence always finishes before the DS8113 enters low-power stop mode. smart card interface 14 ______________________________________________________________________________________ cmdvcc 1_8v 5v/3v stop mode off pres vcc deactivate interface activate stop mode deactivate stop mode 220 s delay off follows pres in stop mode off asserted to wait for delay 8ms debounce figure 8. stop-mode sequence
smart card power select the DS8113 supports three smart card v cc voltages: 1.8v, 3v, and 5v. the power select is controlled by the 1_8v and 5v/ 3v signals as shown in table 3. the 1_8v signal has priority over 5v/ 3v . when 1_8v is asserted high, 1.8v is applied to vcc when the smart card is active. when 1_8v is deasserted, 5v/ 3v dictates v c c power range. v c c is 5v if 5v/ 3v is asserted to a logic- high state, and v cc is 3v if 5v/ 3v is pulled to a logic-low state. care must be exercised when switching from one v cc power selection to the other. if both 1_8v and 5v/ 3v are high with cmdvcc high at the same time, the DS8113 enters stop mode. to avoid acciden- tal entry into stop mode, the state of 1_8v and 5v/ 3v must not be changed simultaneously. a minimum delay of 100ns should be observed between changing the states of 1_8v and 5v/ 3v . see figure 9 for the recom- mended sequence of changing the v c c range. d s 8 1 1 3 smart card interface ______________________________________________________________________________________ 15 v cc select stop mode 1.8v 1.8v 3 v3v 5v 1_8v 5v/3v cmdvcc figure 9. smart card power select table 3. v cc select and operation mode 1 _ 8 v 5 v / 3 v c m d v c c v c c s e l e c t ( v ) c a r d i n t e r f a c e s t a t u s 0 0 0 3 a c t i v a t e d 0 0 1 3 i n a c t i v a t e d 0 1 0 5 a c t i v a t e d 0 1 1 5 i n a c t i v a t e d 1 0 0 1 . 8 a c t i v a t e d 1 0 1 1 . 8 i n a c t i v a t e d 1 1 0 1 . 8 r e s e r v e d ( a c t i v a t e d ) 1 1 1 1 . 8 n o t a p p l i c a b l e s t o p m o d e
d s 8 1 1 3 smart card interface 16 ______________________________________________________________________________________ applications information performance can be affected by the layout of the appli- cation. for example, an additional cross-capacitance of 1pf between card reader contacts c2 (rst) and c3 (clk) or c2 (rst) and c7 (i/o) can cause contact c2 to be polluted with high-frequency noise from c3 (or c7). in this case, include a 100pf capacitor between contacts c2 and cgnd. application recommendations include the following: ? ensure there is ample ground area around the DS8113 and the connector; place the DS8113 very near to the connector; decouple the vdd and vdda lines separately. these lines are best posi- tioned under the connector, connected in a star on the main trace. ? the DS8113 and the host microcontroller must use the same vdd supply. pins clkdiv1, clkdiv2, rstin, pres, aux1in, i/oin, aux2in, 5v/ 3v , 1_8v, cmdvcc , and off are referenced to vdd; if pin xtal1 is to be driven by an external clock, also reference this pin to vdd. ? trace c3 (clk) should be placed as far as possi- ble from the other traces. ? the trace connecting cgnd to c5 (gnd) should be straight (the two capacitors on c1 (vcc) should be connected to this ground trace). ? avoid ground loops among cgnd, pgnd, and gnd. with all these layout precautions, noise should be kept to an acceptable level and jitter on c3 (clk) should be less than 100ps. reference layouts, designs, and an evaluation kit are available on request. package information (for the latest package outline information, go to www.maxim-ic.com/packages .) package type document no. 28 so (300 mils) 21-0042 selector guide n ote: c ontact the factory for availability of other variants and p ackage options. + denotes a lead-free package. p a r t l o w s t o p - m o d e p o w e r l o w a c t i v e - m o d e p o w e r p i n - p a c k a g e d s 8 1 1 3 - r n g + y e s y e s 2 8 s o
d s 8 1 1 3 smart card interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. emvco approval of the interface module (ifm) contained in this terminal shall mean only that the ifm has been tested in accordance and for sufficient conformance with the emv specifications, version 3.1.1, as of the date of testing. emvco approval is not in any way an endorsement or warranty regarding the completeness of the approval process or the functionality, quality or performance of any particular product or service. emvco does not warrant any products or services provided by third parties, including, but not limited to, the producer or provider of the ifm and emvco approval does not under any circumstances include or imply any product warranties from emvco, including, without limitation, any implied warranties of merchantability, fitness for pur- pose, or noninfringement, all of which are expressly disclaimed by emvco. all rights and remedies regarding products and services which have received emvco approval shall be provided by the party providing such products or services, and not by emvco and emvco accepts no liability whatsoever in connection therewith. revision history r e v i s i o n n u m b e r r e v i s i o n d a t e d e s c r i p t i o n p a g e s c h a n g e d 0 1 / 0 8 i n i t i a l r e l e a s e . i n t h e r e c o m m e n d e d d c o p e r a t i n g c o n d i t i o n s t a b l e , c h a n g e d i / o i n , a u x 1 i n / a u x 2 i n s p e c s t o r e f e r e n c e v d d r a t h e r t h a n v c c a n d c o r r e c t e d v o h t o a . 5 1 2 / 0 8 i n t h e p i n d e s c r i p t i o n , r e m o v e d r e f e r e n c e s t o a c t i v e l o w f r o m t h e p r e s d e s c r i p t i o n . 7

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