product brief august 2000 atm utopia slave core v2.0 features n utopia level 1/level 2 with parity generation/ checking. in level 2, all multi-phy modes are sup- ported: 1 rxclav/1 txclav direct status multiplexed status pollin g n 8-/16-bit bus width n pro g rammable cell len g th n 25/33/50 mhz operation n meets all utopia setup and clock-to-output speci- fications n fifo control/monitorin g with the followin g options: internal 128 9/64 17 orca ? fifos ( scal- able ) n flexible control inputs with options for the follow- in g : internal/external hardwirin g access via a parallel or serial microprocessor interface n supports the orca series 2 and series 3 families of fpgas standards compliance n atm forum utopia level 1 version 2.1 n atm forum utopia level 2 version 1.0 benefits n faster development for improved time-to-market with atm functions n lower development cost throu g h desi g n reuse n vhdl * source code for eas y desi g n inte g ration n orca -specific optimization, tailor-made for hi g h performance n ample desi g n flexibilit y usin g built-in interface and function options n verified functionality and standards compliance 0390(f) figure 1. atm utopia slave core application description the atm utopia slave core from modelware ? implements, in modular vhdl, the atm forum's utopia level 1 and level 2 specifications. the core interfaces to the application (e.g., atm ph y sical or adaptation la y er ) via a g eneric fifo-like access interface and to the atm la y er via a utopia level 1 or level 2 interface ( fi g ure 1 ) . the core uses internal fifos for cell bufferin g and timin g transfer between the application and the atm la y er. the core (using 18-bit internal fifos) operates at 50 mhz in an or2t15a-6 or an or3t55-7 orca fpga. * vhdl is a registered trademark of gateway design automation corporation. ? modelware is a registered trademark of modelware, inc. utopia slave core access utopia atm layer function interface appl. (e.g., phy or aal) control status
atm utopia slave core v2.0 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. copyright ? 2000 lucent technologies inc. all rights reserved august 2000 pb00-087ncip for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) product brief august 2000 design package the atm utopia slave core package contains: n vhdl source code n vhdl testbench n scripts and data files for simulation ( behavioral and g ate-level ) , s y nthesis, and fpga la y out n detailed documentation: reference g uide: features, architecture, inter- faces, and operation user's guide: simulation, synthesis, and fpga layout procedures required tools n mti v-s y stem for simulation n exemplar leonardospectrum * for s y nthesis n lucent technologies orca foundry for fpga layout * exemplar and leonardospectrum are trademarks of exemplar lo g ic, inc. additional resources n orca atm ph y sical la y er csc application note ( ap97-050fpga available from lucent technolo- g ies ) n orca or2cxxa and or2txxa series field pro- g rammable gate arra y s data sheet ( ds98-022 ) , januar y 1998 n orca or3cxxa and or3txxa series field pro- g rammable gate arra y s data sheet ( ds98-163-1 ) , au g ust 1998 n as y nchronous transfer mode: atm architecture and implementation , martin et al., prentice hall 1996 ordering information modelware, inc. tel: (732)936-1808 fax: (732)936-1838 e-mail: sales@modelware.com internet: www.modelware.com
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