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stel-2050a 2 features n constraint length 7 n rates 1 / 3 , 1 / 2 , 2 / 3 * and 3 / 4 * (*punctured) n built in ber monitor n programmable scrambler: v.35 (ccitt or iess) or "invert g2" n differential encoder and decoder n three bit soft decision inputs in signed magnitude or 2's complement formats n up to 256 kbps data rate (C40 to 85 c) n 0.6 micron cmos technology n coding gain of 5.2 db (@ 10 -5 ber, rate 1 / 2 ) n industry standard polynomials g1=171 8 , g2=133 8 , g3=145 8 , n all control and data i/o via microprocessor interface n low power consumption n 28-pin plcc and cldcc packages n commercial and military temperature ranges available block diagram differential decoder and v.35 descram- blers differential encoder and v.35 scramblers drate trellis ram data addr do di state-metric ram address sequencer and control logic branch metric and add-compare- select logic path history and auto node-sync logic iclk sst0 sst1 thresh mis 3 sync oclk convolutional encoder read, wrstb, csel "inv g2" scrambler microprocessor interface, mode select and control scram1-0 reset (to all registers) encoder section decoder section 2 "inv g2" descrambler buffer register & mux addr data pncg1 pncg2 ber monitor g1out g2out g3out int 2 3 3 3 8 4 3 drdy dataclk datain dout berr g1err g2err g3err sync 1-0 g1d 2-0 g2d 2-0 g3d 2-0 sm2c
3 stel-2050a functional description convolutional encoding and viterbi decoding are used to provide forward error correction (fec) which improves digital communication performance over a noisy link. in satellite communication systems where transmitter power is limited, fec techniques can reduce the required transmission power. the stel-2050a is a specialized product designed to perform this specific communications related function. the encoder creates a stream of symbols which are transmitted at 2 (rate 1 / 2 ) or 3 (rate 1 / 3 ) times the information rate. this encoding introduces a high degree of redundancy which enables accurate decoding of information despite a high symbol error rate resulting from a noisy link. the coding overhead pin configuration package: 28 pin plcc (j-bend) thermal coefficient, q ja = 45 /w 15 v ss 16 data 7 17 data 6 18 v dd 19 data 5 20 data 4 21 data 3 can be reduced at the expense of the coding gain by puncturing (deleting) some of the symbols. the stel-2050a is designed to operate in this way at rates 2 / 3 and 3 / 4 , when 3 symbols are transmitted for every 2 bits encoded (rate 2 / 3 ) or 4 symbols are transmitted for every 3 bits encoded (rate 3 / 4 ). the resulting bandwidth overhead is just 50% and 33% respectively, compared with 100% at rate 1 / 2 . the stel-2050a incorporates all the memories required to perform these functions. in addition, the stel-2050a incorporates a differential encoder and decoder, three different scrambling algorithms, a ber monitor and a microprocessor interface. the stel- 2050a is available in a 28-pin plcc (plastic leaded chip carrier) and also in a ceramic leaded chip carrier (j-bend leads). notes: 1 tolerance not cumulative 2 dimension at seating plane pin connections 1v ss 2 read 3 csel 4v dd 5 reset 6v ss 7 iclk 22 v ss 23 data 2 24 data 1 25 data 0 26 int 27 i.c. 28 wrstb 8v ss 9 oclk 10 v dd 11 addr 3 12 addr 2 13 addr 1 14 addr 0 notes: 1. i.c. denotes internal connection. this pin must be left unconnected. do not use for a via. 2. connect all unused inputs to v ss , leave unused outputs unconnected. 25 24 23 22 21 20 19 222 4321876 1111111 2345678 5 6 7 8 9 10 11 0.450 .01" top view 0.020" min. 0.175" max. 0.492" .01" 0.018" .003" (2) 0.05" (1)
stel-2050a 4 function block description the convolutional coder is functionally independent of the decoder. writing a new data bit into address 4 h automatically clocks the data down the 7-bit shift register. the symbols g1, g2, and g3 are generated from the modulo-2 sum (exclusive-or) of the inputs to the 3 generators from the taps on the shift register. the 3 polynomials are 171 8 (g1), 133 8 (g2), and 145 8 (g3). the three symbols generated for each input data bit are written into the read mode register at address 5 h . at the decoder symbols are written into addresses 0 h and (for rate 1 / 3 operation only) 1 h . the drate bit in address 2 h determines whether the decoder operates in rate 1 / 2 or rate 1 / 3 mode. when operating at rate 1 / 2 the decoding process starts automatically as soon as data is written into address 0 h and the g3 data is ignored by the decoder. when operating at rate 1 / 3 the g1 and g2 symbols must be written first, since the decoding process starts automatically as soon as data is written into address 1 h . at least 70 cycles of iclk must elapse between each write operation to address 0 h . (rate 1 / 2 ) or 1 h (rate 1 / 3 ) to allow the decoder to process each data bit. for hard decision binary symbols the symbol should be written into bits g1d2 , g2d2 and g3d2 respectively, and the other symbol bits set high. three- bit soft decision symbols may be input in signed magnitude or twos complement code, according to the setting of the code control bit, sm2c , in address 2 h . the bit should be set high when using hard decision data. a single decoded data bit, dout , is written into address 3 h (read mode) for every set of input symbols. the data bit corresponding to a particular symbol set will be output after a delay of 71 symbol sets. therefore, when using the stel-2050a to decode blocks of data 71 additional dummy zero symbols (g1 and g2 for rate 1 / 3 or g3 for rate 1 / 3 ) must be written into address 0 h or 1 h to flush the last 71 decoded data bits out of the decoder. node synchronization (correctly grouping incoming symbols into g1, g2, and g3 sets) is inherent with many communication techniques such as tdma and spread spectrum systems. if node synchronization is not an inherent property of the communications link then the internal auto node sync circuit can be used to do this. this is accomplished by internally connecting the node sync outputs ( sst0 and sst1 ) to the node sync inputs ( sync0 and sync1 ) by setting the autons bit in address 3 h high. the threshold for determining the out of sync condition is user selectable by means of the thresh 2-0 bits in address 2 h . a bit error rate monitor function is provided by re- encoding the decoded data bits and comparing the result with a delayed version of the input symbols. the error information is available in two ways. first, each time an error occurs the error bits in address 3 h (read mode) are set high according to which symbol is found to be in error, and second a running count of the errors in a block of data is generated. the length of the block is determined by the 24-bit word bper 23-0 stored in addresses 6 h -8 h multiplied by 1000, i.e. block length = 1000 x bper 23-0 the number of errors in this period is divided by 8 and accumulated. if the accumulator overflows during this period its output will be caused to saturate at a value of ffff h . at the end of the period the error divider ( ? 8) and the error and period accumulators are cleared and the error count is stored in addresses 7 h and 8 h (read mode) so that the actual bit error rate over this period is: 8 x berct 15-0 ber = 1000 x bper 23-0 note that the ber monitor will indicate an error each time an input symbol is punctured, so that the ber indicated by the berct 15-0 output will not be valid when using punctured codes. in addition, the error divider truncates the error count since it takes 8 errors to increase the count by one, and this truncation can cause significant under-reporting of the error rate unless the value of berct 15-0 is large enough to make the truncation insignificantly small. further information on the theory of operation of viterbi decoders may be obtained from text books such as "error-correcting codes", by peterson and weldon (mit press), or "error control coding", by lin and costello (prentice-hall), or papers such as "convolutional codes and their performance in communication systems", by dr. a. j. viterbi, ieee trans. on communications, october 1971. input signals reset asynchronous master reset . a logic low on this pin will clear all registers on the stel-2050aa in both the encoder and decoder sections of the chip. reset should remain low for at least 3 cycles of iclk to clear the decoder. a software reset is also effected by writing dummy data to address 5 h . the address lines, write and csel lines should generate a valid write state for at least 3 cycles of iclk to clear the decoder. iclk, oclk system clock. a crystal may be connected between iclk and oclk or a cmos level clock may be fed into iclk . the clock frequency should be at least 70 times the decoded data rate but no more than 18 mhz.
5 stel-2050a data7-0 all i/o and control functions are accessed via the data 7-0 bus with the associated control signals. the stel-2050aa is used as a memory or i/o mapped peripheral to the host processor. addr3-0 the 4-bit address bus is used to access the various i/o functions, as shown in the table below. note that some addresses contain both read and write registers, i.e., the read and write mode registers at these addresses are separate and contain different data. write the write input is used to write data to the microprocessor data bus. it is active low and is normally connected to the write line of the host processor. read the read input is used to read data from the microprocessor data bus. it is active low and is normally connected to the read line of the host processor. csel the c hip sel ect input can be used to selectively enable the microprocessor data bus. it is active low. int the int errupt output indicates when the period counter in the ber monitor has completed a count period and that a new value of berct is ready to be read from addresses 7 h and 8 h , when int will go high for one symbol period. input (write) functions addresses 0 h , 1 h g1d2-0, g2d2-0, g3d2-0 the three 3-bit soft decision symbols are written into the registers at addresses 0 h and 1 h and the decoding process begins when the data has been written. when operating at rate 1 / 2 the operation will begin as soon as the g1d 2-0 and g2d 2-0 data is written into address 0 h ; when operating at rate 1 / 3 the operation begins when the g3d 2-0 data is written into address 1 h , so that it is necessary to write the g1d 2-0 and g2d 2-0 data first. the order in which the symbols are entered into the decoder from the registers depends on the state of the sync0 and sync1 bits. the decoder can make use of soft decision information, which includes both polarity information and a confidence measure, to improve the decoder performance. if hard decision (single bit) symbols are used the signals are written into bits g1d 2 , g2d 2 and g3d 2 and the other bits are set high. see sm2c for a description of the input data codes. pncg1, pncg2 the pncg1 and pncg2 bits are used to control the stel-2050aa when operating in punctured mode and are written along with the symbol data. in unpunctured operation (rates 1 / 2 and 1 / 3 ) these bits should be set low. in punctured operation the pncg1 bit must be set high to indicate that the g1 symbol is punctured and the pncg2 bit must be set high to indicate that the g2 symbol is punctured. a symbol will be punctured when the pncg1 or pncg2 bits are high when the symbol data is written into address 0 h . zero value metrics will be substituted internally for the actual metrics corresponding to the g1 2-0 or g2 2-0 data at that time. address 2 h thresh 2-0 a counter is used to determine the number of either traceback mismatches or metric renormalizations per 256 bits in the auto node-sync circuit, and the threshold at which the counter triggers the sst0 and sst1 bits to change states is set with the data on the thresh 2-0 bits. the threshold values will be as shown in the following table. thresh 2-0 threshold value 01 12 24 38 416 532 664 7 128 since the actual error rate obtained will depend on the signal to noise ratio (e b /n o ) in the signal, the optimum value of the threshold will also depend on e b /n o and should be set accordingly. the actual mismatch or renomalization count is stored in the read mode register at address 6 h . mis two algorithms for auto node-sync are incorporated into the stel-2050aa. when the mis bit is set high the traceback mis match algorithm is selected, and when this bit is set low the metric renormalization algorithm is selected. scram0, scram1 the scram ble bits are used to enable the three different scrambler functions included in the stel-2050aa, as shown in the following table: microprocessor interface
stel-2050a 6 scram0 scram1 function 0 0 scrambler disabled 1 0 invert g2 0 1 v.35 (ccitt compatible) 1 1 v.35 (iess compatible) the "invert g2" scrambler simply inverts the g2 symbols generated in the encoder. the decoder then re-inverts the received g2 symbols before decoding. two different "v.35" scrambler formats are provided since there are two versions of this standard in existence: the true, ccitt version of the standard, and the iess version, which has become a de facto standard through widespread use. in each case, the scrambling function is provided at the encoder and the descrambler is provided at the decoder. sm2c the state of the s igned m agnitude/ 2 's c omplement bit determines the format of the incoming soft- decision symbols into the decoder. when sm2c is set high the input code is signed magnitude, and when it is low the code is two's complement. the codes are shown in the following table: code control: sm2c=1 sm2c=0 symbol input: gxd2-gxd0 gxd2-gxd0 most confident '+' level 0 1 1 0 1 1 data = 0 0 1 0 0 1 0 001 001 least confident '+' level 0 0 0 0 0 0 least confident 'C' level 1 0 0 1 1 1 data = 1 1 0 1 1 1 0 110 101 most confident 'C' level 1 1 1 1 0 0 the sm2c bit should be set high when using hard decision data. the polarity of the input signals is such that a constant + level on both g1 and g2 produces an output data stream of zeros. drate the d ecoder rate bit selects whether the decoder will read two symbols ( drate set high) or three symbols ( drate set low) for every data bit decoded. during rate 1 / 2 operation the g3 symbol is completely ignored by the decoder. drate should be set high for rate 3 / 4 operation. address 3 h sync0, sync1 the symbol sync0 and symbol sync1 bits are used for the node sync operation. when using the internal auto node sync mode these two bits are overwritten by sst0 and sst1 , respectively by setting the autons bit high. when this is done it is necessary to avoid writing data into address 3 h during the operation of the decoder to prevent manually overwriting the sync0 and sync1 bits, since this will affect the operation of the auto node sync circuit. the operation of the decoder is affected in the following way by the sync0 and sync1 inputs: symbol entered into decoder during symbol period n rate sync0 sync1 g1 g2 g3 100 g1 n g2 n C 110 g2 n-1 g1 n C 101 g2 n g1 n C 111 g2 n-1 g1 n C 000 g1 n g2 n g3 n 010 g3 n-1 g1 n g2 n 001 g2 n-1 g3 n-1 g1 n 0 1 1 invalid state note that whenever the states of the sync0 and sync1 inputs are changed there will be a delay of 71 bit periods before valid data starts appearing at the decoder output. autons when the autons bit is set high it causes the sst0 and sst1 bits to overwrite the sync0 and sync1 bits respectively, thereby turning on the internal auto node sync function. difen when the difen bit is set high the differential encoder and decoder in the stel-2050aa are enabled. differential encoding is done after v.35 scrambling (when used) but before invert g2 scrambling (when used) in the encoder. the sequence is reversed in the decoder. note that the ber monitor function will only operate correctly when this bit is set low. address 4 h datain the encoder input data bit is written into the register at address 4 h . a dataclk signal is automatically generated internally each time data is written into this location, causing the data to be latched into the encoder shift register and generating a new set of encoded symbols. when the encoder is used in a burst application the encoder register should be flushed with seven dummy data bits (zeroes) at the end of the burst. address 5 h reset a software reset is effected by writing dummy data to address 5 h . the address lines, write and csel lines
7 stel-2050a should generate a valid write state for at least 3 cycles of iclk to clear the decoder. addresses 6 h - 8 h bper 23-0 the 24-bit b er per iod data is used to set the period (number of data bits) over which the mean ber is measured by the ber monitor. the period used is 1000 times the value of bper 23-0 . output (read) functions address 3 h dout decoded d ata out . the signal is stored in the read register at address 3 h when the next symbol data is written to start the decoding process for the next bit. there is a delay of 71 data bits from the time a set of symbols is written into the stel-2050aa to the time the corresponding data bit is available. consequently, in order to flush the last 71 bits of data out of the system at the end of a burst it is necessary to continue writing dummy input symbols and reading the output data for 71 symbol periods after the last valid symbol has been entered. g1err, g2err and g3err the g1 err or, g2 err or and g3 err or bits indicate that an error has been detected in the g1, g2 or g3 symbols, respectively, corresponding to the current output bit. these functions will only be valid when operating at rates 1 / 2 and 1 / 3 with the difen bit set low. berr the b it err or bit indicates that an error has been detected in any of the symbols corresponding to the current output bit. this function is the logical or of g1err , g2err , and (at rate 1 / 3 only) g3err . this function will only be valid when operating at rates 1 / 2 and 1 / 3 with the difen bit set low. address 4 h sync the sync bit provides an indication of the status of the internal auto node sync circuit. this bit will pulse high for one symbol period if the mismatch or renormalization count exceeds the threshold value, indicating that the node sync has been changed. sst0, sst1 the s ync st ate 0 and s ync st ate 1 signals are the outputs of the internal auto node sync circuit. they will overwrite the sync0 and sync1 bits respectively when autons is set high. they may also be used in conjunction with an external node sync algorithm implementation which can use the sst0 and sst1 data. msmch the msmch bit is normally set high. it will be set low each time a traceback mismatch occurs and will stay low for one bit period. when using the traceback mismatch algorithm for automatic node sync the mismatch counter will be incremented at the same time. rnorm the renorm bit is normally set low. it will be set high each time the metrics are renormalized and will stay high for one bit period. when using the metric renormalization algorithm for automatic node sync the renormalization counter will be incremented at the same time. address 5 h g1out, g2out, g3out these are the output symbols from the encoder. they depend on the seven most recent data bits ( datain ) clocked into the encoder shift register and are formed by the modulo-2 sum of the inputs to the generators from the 7-bit shift register. they are stored in the read mode register at address 5 h . address 6 h count7-0 the 8-bit count data gives the current value of the mismatch or renormalization count which is used for comparison with the threshold. addresses 7 h - 8 h berct15-0 the 16-bit b it er ror c oun t data represents the mean bit error rate over the period determined by the ber period data bper 23-0 . the actual ber is given by: 8 x berct 15-0 ber = 1000 x bper 23-0 the value will be updated each time the period counter completes its count. this will be indicated by the int output going high for one clock cycle. if the accumulator overflows during a measurement period its output will be caused to saturate at a value of ffff h . note that the ber monitor will indicate an error each time an input symbol is punctured, so that the ber indicated by the berct 15-0 output will not be valid when using punctured codes unless the effect of the puncturing can be compensated externally. address e h ack ack nowledge. the signal is stored in the read register at address e h . this bit goes high when a new symbol set has been written into the decoder and the decoding process has started and goes low again 70 clock cycles later to indicate that a new data bit is ready to be read.
stel-2050a 8 microprocessor interface memory map write mode registers addr 3-0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0* pncg1 g1d2 g1d1 g1d0 pncg2 g2d2 g2d1 g2d0 1* g3d2 g3d1 g3d0 2* drate sm2c scram0 scram1 mis thresh 2 thresh 1 thresh 0 3 difen autons sync1 sync0 4 datain 5 reset 6 bper 7 bper 6 bper 5 bper 4 bper 3 bper 2 bper 1 bper 0 7 bper 15 bper 14 bper 13 bper 12 bper 11 bper 10 bper 9 bper 8 8 bper 23 bper 22 bper 21 bper 20 bper 19 bper 18 bper 17 bper 16 * indicates that these are also readable registers read mode registers addr 3-0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 3 berr g3err g2err g1err dout 4 rnorm msmch sst1 sst0 sync 5 g3out g2out g1out 6 count 7 count 6 count 5 count 4 count 3 count 2 count 1 count 0 7 berct 7 berct 6 berct 5 berct 4 berct 3 berct 2 berct 1 berct 0 8 berct 15 berct 14 berct 13 berct 12 berct 11 berct 10 berct 9 berct 8 e ack electrical characteristics absolute maximum ratings note : stresses greater than those shown below may cause permanent damage to the device. exposure of the device to these conditions for extended periods may also affect device reliability. all voltages are referenced to v ss . symbol parameter range units t stg storage temperature C40 to +125 c (plastic package) ? C65 to +150 c (ceramic package) v ddmax supply voltage on v dd C0.3 to + 7 volts v i(max) input voltage C0.3 to v dd +0.3 volts i i dc input current 10 ma
9 stel-2050a a.c. characteristics (operating conditions: v dd = 5.0 v 5%, v ss =0 v, t a = 0 to 70 c, commercial v dd = 5.0 v 10%, v ss =0 v, t a =C55 to 125 c, military) symbol parameter min. max. units conditions t rs reset pulse width 3*t iclk t sr reset to iclk setup 2 nsec. t w write pulse width 5 nsec. t ci iclk to int delay 10 35 nsec. t su csel , data or addr to 5 nsec. write or read setup t hd write or read to 5 nsec. csel , data or addr hold t zv data hi-z to valid 12 nsec. load = 15 pf t vz data valid to hi-z 12 nsec. load = 15 pf d.c. characteristics (operating conditions: v dd = 5.0 v 5%, v ss =0 v, t a = 0 to 70 c, commercial v dd = 5.0 v 10%, v ss =0 v, t a =C55 to 125 c, military) symbol parameter min. typ. max. units conditions i dd(q) supply current, quiescent 1.0 ma static, no clock i dd supply current, operational 2.0 ma/mhz v ih(min) high level input voltage standard operating conditions 2.0 volts logic '1' extended operating conditions 2.25 volts logic '1' v il(max) low level input voltage 0.8 volts logic '0' i ih(min) high level input current 10 35 110 m av in = v dd v oh(min) high level output voltage 2.4 4.5 volts i o = C6.0 ma v ol(max) low level output voltage 0.2 0.4 volts i o = +6.0 ma i os output short circuit current 20 65 130 ma v out = v dd , v dd = max C10 C45 C130 ma v out = v ss , v dd = max c in input capacitance 2 pf all inputs c out output capacitance 4 pf all outputs recommended operating conditions symbol parameter range units v dd supply voltage +5 5% volts (commercial grade) ? +5 10% volts (military grade) t a operating temperature (ambient) 0 to +70 c (commercial grade) ? C55 to +125 c (military grade)
stel-2050a 10 reset (or csel/write/addr 5h ) iclk int t rs t sr t ci reset and microprocessor interface timing 1. write operatons don't care don't care don't care don't care write csel addr 3-0 data 7-0 t w t su t hd 2. read operatons read csel don't care don't care t su t hd t zv t vz addr 3-0 data 7- 0
11 stel-2050a the automatic node sync circuit built into the stel-2050a can be used to provide node sync in applications where this is not intrinsic to the nature of the operation. the automatic node sync is enabled by setting the autons bit high. the threshold should be set according to the expected signal to noise ratio of the input signal for optimum operation of the system. punctured mode operation in punctured codes some of the symbols generated by the convolutional encoder are deleted, or punctured, from the transmitted sequence. for example, in an unpunctured rate 1 / 2 sequence, four bits would be transmitted for every two data bits. if every fourth bit was punctured from the sequence then only three bits would be transmitted for every two data bits. this would result in a rate 2 / 3 code. the stel-2050a is designed to operate in punctured mode as well as normal, rate 1 / 2 , mode. this is easily accomplished by means of the pncg1 and pncg2 bits, which delete the symbol which would normally have been loaded into the decoder at the time when either of these bits is set high. the punctured symbols are replaced using automatic node sync internally by zero metric values. the viterbi algorithm treats the zero value metrics by giving them zero weight in the computations relative to the other symbols. the coding gain is significantly less than that for unpunctured operation, but this is the trade-off for the reduced bandwidth required to transmit the symbols. the recommended puncturing sequences for rates 2 / 3 and 3 / 4 punctured operation are shown in the table. the sequences shown in boldface are the basic sequence, which are then repeated. the use of the pncg1 and pncg2 bits is shown below for rate 3 / 4 . the punctured symbols are marked with asterisks. rates higher than 3 / 4 are not recommended with the stel-2050a. rate symbol sequence 2 / 3 g1 g2 g1 p g1 g2 g1 p g1 g2 g1 p g1 g2 g1 p g1 g2 3 / 4 g1 g2 p g2 g1 p g1 g2 p g2 g1 p g1 g2 p g2 g1 p g1 drdy** g2 pncg1 pncg2 *** ** * denotes punctured symbols. ** denotes that drdy is set high at these times.
stel-2050a 12 bpsk communication system using convolutional encoding and viterbi decoding. rate = 1 / 2 rate 1 / 2 conv. encoder bpsk demod. rate 1 / 2 viterbi decoder bpsk modulator channel bw=1024 khz coded data @ 512 kbps tx data 256 kbps rx data 256 kbps coded data @ 512 kbps the data rate. the performance improvement that can be expected is shown in the graph below. the convolutional encoder is functionally independent from the decoder. a single data bit is clocked into the 7 bit shift register on the rising edge of data clk . the decoder portion of the stel-2050a is designed to accept symbols synchronously. drdy is supplied by the user to clock in the symbols. the maximum data rate is 256 kbps, using a clock frequency of 18 mhz. this corresponds to 512 k symbols per second at rate 1 / 2 and 768 k symbols per second at rate 1 / 3 . 18 mhz crystals are readily available, and this clock frequency can be used at all data rates, although the power consumption can be reduced by using lower clock frequencies. the stel-2050a can be used in a variety of different environments. one example is shown below. it cannot be used as a common encoder or decoder in multi- channel applications because of the memory incorporated on the chip which is dedicated to a single channel. an example of a system using the convolutional coder and viterbi decoder is illustrated here. the system modulates a data stream of rate 512 kbps using binary psk (bpsk). to be able to use convolutional coding/ decoding, the system must have available the additional bandwidth needed to transmit symbols at twice the data rate (for rate 1 / 2 encoding). alternatively, the system could make use of two parallel channels to transmit two streams of symbols at bpsk communication system using convolutional encoding and viterbi decoding. rate = 1 / 2 10 C1 10 C2 10 C3 10 C4 10 C5 10 C6 10 C7 2 3 4 5 6 7 8 9 10 11 e b /n 0 db ber uncoded coded coding gain

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