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| ? freescale semiconductor, inc., 2004. all rights reserved. freescale semiconductor product preview this document contains information on a product under developm ent. freescale reserves the right to change or discontinue this product without notice. mc9328mx21/d rev. 1.1, 09/29/2004 mc9328mx21 package information (mapbga?289) ordering information: see table 1 on page 4 1 introduction freescale?s i.mx family of microprocessors has demonstrated leadership in the portable handheld market. building on the success of the mx (media extensions) series, the i.mx21 (mc9328mx21) provides a leap in performance with an arm926ej-s? microprocessor core that pr ovides native security and accelerated java support in addition to highly integrated system functions. the i.mx products specifically address the needs of the smartphone and portable product markets with their intelligent integrated peripherals, advanced pr ocessor core, and power management capabilities. the i.mx21 features the advanced and power-efficient arm926ej-s core operating at speeds up to 266 mhz and is part of a growing family of smart speed products that offer high performance processing optimized for lowest power consumption. on -chip modules such as a video accelerator module, lc d controller, usb on-the- go, cmos sensor interface, and two synchronous serial interfaces offer designers a ri ch suite of pe ripherals that can enhance any product seeking to provide a rich mc9328mx21 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2 signal descriptions. . . . . . . . . . . . . . . . . . . . . . . .5 3 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4 package information . . . . . . . . . . . . . . . . . . . . .102 5 document revision history . . . . . . . . . . . . . . .105
mc9328mx21 product preview, rev. 1.1 2 freescale semiconductor introduction multimedia experience. in addition, the i.mx21 provi des optional hardware enabled security features including high assurance boot mode, unique processor ids, secret key support, secure ram, and a security monitor. these optional features enable secu re e-commerce, digital ri ghts management (drm), information encryption, and se cure software downloads. for cost sensitive applications, the nand flash co ntroller allows the use of low-cost nand flash devices to be used as pr imary or secondary non-volat ile storage. the on-chip er ror correction code (ecc) and parity checking circuitry of the nand flash controller frees the cpu for other tasks. wlan, bluetooth and expansion options ar e provided through pcmcia/cf, usb, and mmc/sd host controllers. the i.mx21 is packaged in a 289-pin mapbga. figure 1. i.mx21 functional block diagram i.mx21 introduction mc9328mx21 product preview, rev. 1.1 freescale semiconductor 3 1.1 conventions this document uses the following conventions: ? overbar is used to indicate a signal that is active when pulled low: for example, reset . ? logic level one is a voltage that corresponds to boolean true (1) state. ? logic level zero is a voltage that corresponds to boolean false (0) state. ?to set a bit or bits means to establish logic level one. ?to clear a bit or bits means to establish logic level zero. ?a signal is an electronic construct whose state conv eys or changes in stat e convey information. ?a pin is an external physical connec tion. the same pin can be used to connect a number of signals. ? asserted means that a discrete signal is in active logic state. ? active low signals change from logic le vel one to logic level zero. ? active high signals change from logic le vel zero to logic level one. ? negated means that an asserted discrete signal changes logic state. ? active low signals change from logic le vel zero to logic level one. ? active high signals change from logic le vel one to logic level zero. ? lsb means least significant bit or bits , and msb means most significant bit or bits . references to low and high bytes or words are spelled out. ? numbers preceded by a percent sign (%) are bi nary. numbers preceded by a dollar sign ($) or 0x are hexadecimal. 1.2 target applications the i.mx21 is targeted for advanced information appliances, smart phon es, web browsers, digital mp3 audio players, handheld computers based on the popula r palm os platform, and messaging applications. 1.3 reference documentation the following documents are required for a complete description of the i.mx21 and are necessary to design properly with the device. especially for those no t familiar with the arm926ej-s processor or previous dragonball products, the fo llowing documents are helpful when used in conjunction with this manual. arm architecture reference manual (arm ltd., order number arm ddi 0100) arm7tdmi data sheet (arm ltd., order number arm ddi 0029) arm920t technical reference manual (arm ltd., order number arm ddi 0151c) mc9328mx21 product brief (order number mc9328mx21p/d) mc9328mx21 reference manual (order number mc9328mx21rm/d) mc9328mx1 product brief (order number mc9328mx1p/d) mc9328mx1 data sheet (order number mc9328mx1/d) mc9328mx1 reference manual (order number mc9328mx1rm/d) the freescale manuals are available on the freescale semiconductor web site at http://www.freescale.com. these documents may be downloaded directly from the freescale web site, or printed versions may be ordered. the arm ltd. documentation is ava ilable from http://www.arm.com. mc9328mx21 product preview, rev. 1.1 4 freescale semiconductor introduction 1.4 ordering information table 1 provides ordering in formation for the i.mx21. 1.5 features the i.mx21 boasts a robust array of features that can support a wide variety of applications. below is a brief description of i.mx21 features. ? arm926ej-s core complex ? enhanced multimedia accelerator (emma) ? optional security system ? display and video modules ? lcd controller (lcdc) ? smart lcd controller (slcdc) ? cmos sensor interface (csi) ? bus master interface (bmi) table 1. i.mx21 ordering information marking package size package type operating range mc9328mx21vg 289-lead mapbga 0.65mm, 14mm x 14mm lead 0 c?70 c mc9328mx21vk 289-lead mapbga 0.65mm, 14mm x 14mm lead-free 0 c?70 c mc9328mx21vh 289-lead mapbga 0.8mm, 17mm x 17mm lead 0 c?70 c mc9328mx21vm 289-lead mapbga 0.8mm, 17mm x 17mm lead-free 0 c?70 c mc9328mx21dvg 289-lead mapbga 0.65mm, 14mm x 14mm lead -30 c?70 c mc9328mx21dvk 289-lead mapbga 0.65mm, 14mm x 14mm lead-free -30 c?70 c mc9328mx21dvh 289-lead mapbga 0.8mm, 17mm x 17mm lead -30 c?70 c mc9328mx21dvm 289-lead mapbga 0.8mm, 17mm x 17mm lead-free -30 c?70 c mc9328mx21cvg 289-lead mapbga 0.65mm, 14mm x 14mm lead -40 c?85 c MC9328MX21CVK 289-lead mapbga 0.65mm, 14mm x 14mm lead-free -40 c?85 c mc9328mx21cvh 289-lead mapbga 0.8mm, 17mm x 17mm lead -40 c?85 c mc9328mx21cvm 289-lead mapbga 0.8mm, 17mm x 17mm lead-free -40 c?85 c signal descriptions mc9328mx21 product preview, rev. 1.1 freescale semiconductor 5 ? wireless connectivity ? fast infra-red interface (fast ir) ? wired connectivity ? usb on-the-go (usbotg) controller ? four universal asynchronous receiver/tra nsmitters (uart1, uart2, uart3, and uart4) ? two configurable serial peripheral interfaces (c spi1 and cspi2) for high speed data transfer ? inter-ic (i 2 c) bus module ? two synchronous serial interfac es (ssi) with inter-ic sound (i 2 s) ? digital audio mux ? one-wire controller ? keypad interface ? memory expansion and i/o card support ? two multimedia card and secure dig ital (mmc/sd) host controller modules ? memory interface ? external interface module (eim) ? sdram controller (sdramc) ? nand flash controller (nfc) ? pcmcia/cf interface ? standard system resources ? clock generation module (c gm) and power control module ? three general-purpose 32-bit counters/timers ? watchdog timer ? real-time clock/sampling timer (rtc) ? pulse-width modulator (pwm) module ? direct memory access controller (dmac) ? general-purpose i/o (gpio) ports ? debug capability 2 signal descriptions this section identifies and describes the i.mx21 signals an d their pin assignments. the i.mx21 signals are listed in table 2. table 2. i.mx21 signal descriptions signal name function/notes external bus/chip select (eim) a [25:0] address bus signals d [31:0] data bus signals eb0 msb byte strobe?active low external enable by te signal that controls d [31:24], shared with sdram dqm0. eb1 byte strobe?active low external enable byte signal that controls d [23:16], shared with sdram dqm1. mc9328mx21 product preview, rev. 1.1 6 freescale semiconductor signal descriptions eb2 byte strobe?active low external enable byte sig nal that controls d [15:8], shared with sdram dqm2 and pcmcia pc_reg . eb3 lsb byte strobe?active low external enable byte si gnal that controls d [7:0], shared with sdram dqm3 and pcmcia pc_iord . oe memory output enable?active low output enables external data bus, shared with pcmcia pc_iowr . cs [5:0] chip select?the chip select signals cs [3:2] are multiplexed with csd [1:0] and are selected by the function multiplexing control register (fmcr) in the system control chapter. by default csd [1:0] is selected. dtack is multiplexed with cs4 . ecb active low input signal sent by flash device to the eim whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. lba active low signal sent by flash device causing the external burst device to latch the starting burst address. bclk clock signal sent to external synchronous memories (such as burst flash) during burst mode. rw rw signal?indicates whether external access is a read (high) or wr ite (low) cycle. this signal is also shared with the pcmcia pc_we . dtack dtack signal?external input data acknowledge signal, multiplexed with cs4 . bootstrap boot [3:0] system boot mode select?the operational syste m boot mode of the i.mx21 upon system reset is determined by the settings of these pins. sdram controller sdba [4:0] sdram non-interleave mode bank address signals. these signals are multiplexed with address signals a[20:16]. sdiba [3:0] sdram interleave addressing mode bank address signals. these signals are multiplexed with address signals a[24:21]. ma [11:0] sdram address signals. ma[9:0] are multiplexed with address signals a[10:1]. dqm [3:0] sdram data qualifier mask multiplexed with eb [3:0]. dqm3 corresponds to d[31:24], dqm2 corresponds to d[23:16], dqm1 corresponds to d[15:8], and dqm0 corresponds to d[7:0]. csd0 sdram chip select signal. this signal is multiplexed with the cs2 signal. this sign al is selectable by programming the function multiplexing contro l register in the system control chapter. csd1 sdram chip select signal. this signal is multiplexed with the cs3 signal. this sign al is selectable by programming the function multiplexing contro l register in the system control chapter. ras sdram row address select signal cas sdram column address select signal sdwe sdram write enable signal sdcke0 sdram clock enable 0 sdcke1 sdram clock enable 1 sdclk sdram clock table 2. i.mx21 signal descriptions (continued) signal name function/notes signal descriptions mc9328mx21 product preview, rev. 1.1 freescale semiconductor 7 clocks and resets extal26m crystal input (26mhz), or a 16 mhz to 32 mhz oscillator (or square-wave) input when internal oscillator circuit is shut down. xtal26m oscillator output to external crystal extal32k 32 khz crystal input xtal32k oscillator output to 32 khz crystal clko clock out signal selected from internal clock signals. please refer to clock controller for internal clock selection. ext_48m this is a special factory test signal. to ensur e proper operation, connect this signal to ground. ext_266m this is a special factory test signal. to ensur e proper operation, connect this signal to ground. reset_in master reset?external active low schmitt trigger input signal. when this signal goes active, all modules (except the reset module, sdramc module, and the clock control module) are reset. reset_out reset out?internal active low output signal from the watchdog timer module and is asserted from the following sources: powe r-on reset, external reset (reset_in ), and watchdog time-out. por power on reset?active low schmitt trigger input signal. the por signal is normally generated by an external rc circuit designed to detect a power-up event. clkmode[1:0] these are special factory test signals. to ensu re proper operation, leave these signals as no connects. osc26m_test this is a special factory test signal. to ensure proper operation, leave this signal as a no connect. test_wb[2:0] these are special factory test signals. however, these signals are also multiplexed with gpio port e as well as alternate keypad signals. if not utilizing these signals for gpio functionality or for it?s other multiplexed functi on, then configure as gpio input with pull up enabled, and leave as a no connect. test_wb[4:3] these are special factory test signals. to ensu re proper operation, leave these signals as no connects. wkgd battery indicator input used to qualify the wa lk-up process. also multiplexed with tin. jtag trst test reset pin?external active low signal used to asynchronously initialize the jtag controller. tdo serial output for test instructions and data. changes on the falling edge of tck. tdi serial input for test instructions and data. sampled on the rising edge of tck. tck test clock to synchronize test logic and cont rol register access through the jtag port. tms test mode select to sequence t he jtag test controller ?s state machine. sampled on the rising edge of tck. jtag_ctrl jtag controller select signal?jtag_ctrl is sampled during the rising edge of trst. must be pulled to logic high for proper jtag interface to debugger. pulling jtag_crtl low is for internal test purposes only. rtck jtag return clock used to enhance stability of jtag debug interface devices. this signal is multiplexed with owire, hence utilizing owire will render rtck unusable and vice versa. table 2. i.mx21 signal descriptions (continued) signal name function/notes mc9328mx21 product preview, rev. 1.1 8 freescale semiconductor signal descriptions cmos sensor interface csi_d [7:0] sensor port data csi_mclk sensor port master clock csi_vsync sensor port vertical sync csi_hsync sensor port horizontal sync csi_pixclk sensor port data latch clock lcd controller ld [17:0] lcd data bus?all lcd signals are driven low af ter reset and when lcd is off. ld[15:0] signals are multiplexed with slcdc1_dat[15:0] from slcdc1 and bmi_d[15:0]. ld[17] signal is multiplexed with bmi_write of bmi. ld[16] signal is multiplexed with bmi_read_req of bmi and ext_dmagrant signals. flm_vsync (or simply referred to as vsync) frame sync or vsync?this signal also serves as the clock signal output for gate driver (dedicated signal sps for sharp panel hr- tft). this signal is multiplexed with bmi_rxf_full and bmi_wait of the bmi. lp_hsync (or simply referred to as hsync) line pulse or hsync lsclk shift clock. this signal is multip lexed with the bmi_clk_cs from bmi. oe_acd alternate crystal direction/output enable. contrast this signal is used to control the lcd bias volta ge as contrast control. this signal is multiplexed with the bmi_read from bmi. spl_spr sampling start signal for left and right scanning. this signal is multiplexed with the slcdc1_clk. ps control signal output for source driver (sharp panel dedicated signal). this signal is multiplexed with the slcdc1_cs. cls start signal output for gate driver. this signal is invert version of ps (sharp panel dedicated signal). this signal is multiplexed with the slcdc1_rs. rev signal for common electrode driving signal preparati on (sharp panel dedicated signal). this signal is multiplexed with slcdc1_d0. smart lcd controller slcdc1_clk slcdc clock output signal. this signal is multiple xed and available at 2 alternate locations. these are spl_spr and sd2_clk signals of lcdc and sd2, respectively. slcdc1_cs slcdc chip select output signal. this signal is multiplexed and available at 2 alternate signal locations. these are ps and sd2_cmd signals of lcdc and sd2, respectively. slcdc1_rs slcdc register select output signal. this signal is multiplexed and available at 2 alternate signal locations. these are cls and sd2_d3 signals of lcdc and sd2, respectively. slcdc1_d0 slcdc serial data output signal. this signal is multiplexed and available at 2 alternate signal locations. these are and rev and sd2_d2 signals of lcdc and sd2, respectively. this signal is inactive when a parallel data interface is used. table 2. i.mx21 signal descriptions (continued) signal name function/notes signal descriptions mc9328mx21 product preview, rev. 1.1 freescale semiconductor 9 slcdc1_dat[15:0] slcdc data output signals for connection to a parallel slcd panel interface. these signals are multiplexed with ld[15:0] while an alternate 8-bi t slcd muxing is available on ld[15:8]. further alternate muxing of these signals are avail able on some of the usb otg and usbh1 signals. slcdc2_clk slcdc clock input signal for pass through to slcd device. this signal is multiplexed with ssi3_clk signal from ssi3. slcdc2_cs slcdc chip select input signal for pass through to slcd device. this signal is multiplexed with ssi3_txd signal from ssi3. slcdc2_rs slcdc register select input signal for pass through to slcd device. this signal is multiplexed with ssi3_rxd signal from ssi3. slcdc2_d0 slcd data input signal for pass through to slcd device. this signal is multiplexed with ssi3_fs signal from ssi3. bus master interface (bmi) bmi_d[15:0] bmi bidirectional data bus. bus width is progra mmable between 8-bit or 16-bit.these signals are multiplexed with ld[15:0] and slcdc_dat[15:0]. bmi_clk_cs bmi bidirectional clock or chip select signal.this signal is multiplexed with lsclk of lcdc. bmi_write bmi bidirectional signal to indicate read or write access. this is an input signal when the bmi is a slave and an output signal when bmi is th e master of the interface. bmi_write is asserted for write and negated for read.this signal is muxed with ld[17] of lcdc. bmi_read bmi output signal to enable data read from extern al slave device. this signal is not used and driven high when bmi is slave.this signal is multiplexed with contrast signal of lcdc. bmi_read_req bmi read request output signal to external bus master. this signal is active when the data in the txfifo is larger or equal to the data transfer size of a single external bmi access.this signal is muxed with ld[16] of lcdc. bmi_rxf_full bmi receive fifo full active high output signal to reflect if the rxfi fo reaches water mark value.this signal is muxed with vsync of the lcdc. bmi_wait bmi wait?active low signal to wait for data ready (read cycle) or accepted (write_cycle). also multiplexed with vsync. external dma ext_dmareq external dma request input signal. this signal is multiplexed with cspi1_rdy . ext_dmagrant external dma grant output signal. this signal is multiplexed with ld[16]. nand flash controller nf_cle nand flash command latch enable output signal. th is signal is multiplexed with pc_poe of pcmcia. nf_ce nand flash chip enable output signal. this signal is multiplexed with pc_ce1 of pcmcia. nf_wp nand flash write protect output signal. this si gnal is multiplexed with pc_ce2 of pcmcia. nf_ale nand flash address latch enable output signal. this signal is multiplexed with pc_oe of pcmcia. nf_re nand flash read enable output signal. this signal is multiplexed with pc_rw of pcmcia. table 2. i.mx21 signal descriptions (continued) signal name function/notes mc9328mx21 product preview, rev. 1.1 10 freescale semiconductor signal descriptions nf_we nand flash write enable output signal. this signal is multiplexed with and pc_bvd2 of pcmcia. nf_rb nand flash ready busy input signal. this signal is multiplexed with pc_rst of pcmcia. nf_io[15:0] nand flash data input and output signals. nf_io[15:7] signals are multiplexed with a[25:21] and a[15:13]. nf_io[7:0] signals are mult iplexed with several pcmcia signals. pcmcia controller pc_a[25:0] pcmcia address signals. these sign als are multiplexed with a[25:0]. pc_d[15:0] pcmcia data input and output signals. t hese signals are mult iplexed with d[15:0]. pc_cd1 pcmcia card detect1 input signal. this signal is multiplexed with nfio[7] signal of nf. pc_cd2 pcmcia card detect2 input signal. this signal is multiplexed with nfio[6] signal of nf. pc_wait pcmcia wait input signal to exte nd current access this signal is multiplexed with nfio[5] signal of nf. pc_ready pcmcia ready input signal to indicate card is ready for access. this signal is multiplexed with nfio[4] signal of nf. pc_rst pcmcia reset output signal. this signal is multiplexed with nfrb signal of nf. pc_oe pcmcia memory read enable output signal asse rted during common or attribute memory read cycles. this signal is multiplexed with nfale signal of nf. pc_we pcmcia memory write enable ou tput signal asserted during comm on or attribute memory cycles. this signal is shared with rw of the eim. pc_vs1 pcmcia voltage sense1 input signal. this signal is multiplexed with nfio[2] signal of nf pc_vs2 pcmcia voltage sense2 input signal. this signal is multiplexed with nfio[1] signal of nf pc_bvd1 pcmcia battery voltage detect1 input signal. this signal is multiplexed with nfio[0] signal of nf pc_bvd2 pcmcia battery voltage detect2 input signa l. this signal is multiplexed with nf_we signal of nf pc_spkout pcmcia speaker out output signal. this signal is multiplexed with pwmo signal. pc_reg pcmcia register select output signal. this signal is shared with eb2 of eim. pc_ce1 pcmcia card enable1 output signal. this signal is multiplexed with nfce signal of nf. pc_ce2 pcmcia card enable2 output signal. this signal is multiplexed with nfwp signal of nf. pc_iord pcmcia io read output signal. this signal is shared with eb3 of eim. pc_iowr pcmcia io write output signal. this signal is shared with oe signal of eim. pc_wp pcmcia write protect input signal. this signal is multiplexed with nfio[3] signal of nf. pc_poe pcmcia output enable signal to enable voltage tran slation buffers and transceivers. this signal is multiplexed with nfcle signal of nf. pc_rw pcmcia read write output signal to control extern al transceiver direction. asserted high for read access and negated low for write access. this signal is multiplexed with nfre signal of nf. pc_pwron pcmcia input signal to indicate that the card power has been applied and stabilized. table 2. i.mx21 signal descriptions (continued) signal name function/notes signal descriptions mc9328mx21 product preview, rev. 1.1 freescale semiconductor 11 cspi cspi1_mosi master out/slave in signal cspi1_miso master in/slave out signal cspi1_ss[2:0] slave select (selectable polarity) signal. cs pi1_ss2 is also multiplexed with usbg_rxdat. cspi1_sclk serial clock signal cspi1_rdy serial data ready signal. also multiplexed with ext_dmareq. cspi2_mosi master out/slave in signal. this signal is multiplexed with usbh2_txdp signal of usb otg. cspi2_miso master in/slave out signal. this signal is multiplexed with usbh2_txdm signal of usb otg. cspi2_ss[2:0] slave select (selectable polarity) signals. these signals are multiplexed with usbh2_fs, usbh2_rxdp and usbh2_rxdm signal of usb otg cspi2_sclk serial clock signal. this signal is multiplexed with usbh2_oe signal of usb otg cspi3_mosi master out/slave in signal. this signal is multiplexed with sd1_cmd. cspi3_miso master in/slave out signal. this signal is multiplexed with sd1_d0. cspi3_ss slave select (selectable polarity ) signal multiplexed with sd1_d3. cspi3_sclk serial clock signal. this signal is multiplexed with sd1_clk. general purpose timers tin timer input capture or timer i nput clock?the signal on this input is applied to all 3 timers simultaneously. this signal is muxed with the walk-up guard mode wkgd signal in the pll, clock, and reset controller module. tout1 (or simply tout) timer output signal from general purpose ti mer1 (gpt1). this signal is multiplexed with ssi1_mclk and ssi2_mclk signal of ssi1 and ssi2. the pin name of this signal is simply tout. tout2 timer output signal from general purpose timer1 (gpt2). this signal is multiplexed with pwmo. tout3 timer output signal from general purpose timer1 (gpt3). this signal is multiplexed with pwmo. usb on-the-go usb_byp usb bypass input active low signal. usb_pwr usb power output signal usb_oc usb over current input signal usbg_rxdp usb otg receive data plus input signal. this signal is muxed with slcdc1_dat15. usbg_rxdm usb otg receive data minus input signal. this signal is muxed with slcdc1_dat14. usbg_txdp usb otg transmit data plus output signal. this signal is muxed with slcdc1_dat13. usbg_txdm usb otg transmit data minus output signal. this signal is muxed with slcdc1_dat12. usbg_rxdat usb otg transceiver differential data re ceive signal. multiplexed with cspi1_ss2. usbg_oe usb otg output enable signal. this signal is muxed with slcdc1_dat11. table 2. i.mx21 signal descriptions (continued) signal name function/notes mc9328mx21 product preview, rev. 1.1 12 freescale semiconductor signal descriptions usbg_on usb otg transceiver on output signal. this signal is muxed with slcdc1_dat9. usbg_fs usb otg full speed output signal. this signal is multiplexed with external transceiver usbg_txr_int signal of usb otg. this signal is muxed with slcdc1_dat10. usbh1_rxdp usb host1 receive data plus input signal. this signal is multiplexed with uart4_rxd and slcdc1_dat6. it also provides an al ternative multiplex for uart4_rts , where this signal is selectable by programming the function multiplexi ng control register in the system control chapter. usbh1_rxdm usb host1 receive data minus input signal. this signal is muxed with slcdc1_dat5. it also provides an alternative multiplex for uart4_cts . usbh1_txdp usb host1 transmit data plus output signal. this signal is multiplexed with uart4_cts and slcdc1_dat4. it also provides an alternative mu ltiplex for uart4_rxd, where this signal is selectable by programming the function multiplexi ng control register in the system control chapter. usbh1_txdm usb host1 transmit data minus output signal. this signal is multiplexed with uart4_txd and slcdc1_dat3. usbh1_rxdat usb host1 transceiver differential data receive signal. multiplexed with usbh1_fs. usbh1_oe usb host1 output enable signal. this signal is muxed with slcdc1_dat2. usbh1_fs usb host1 full speed output signal. this signal is multiplexed with uart4_rts and slcdc1_dat1 and usbh1_rxdat. usbh_on usb host transceiver on output signal. this signal is muxed with slcdc1_dat0. usbh2_rxdp usb host2 receive data plus input signal. this signal is multiplexed with cspi2_ss[1] of cspi2. usbh2_rxdm usb host2 receive data minus input signal. this signal is multiplexed with cspi2_ss[2] of cspi2. usbh2_txdp usb host2 transmit data plus output signal. th is signal is multiplexed with cspi2_mosi of cspi2. usbh2_txdm usb host2 transmit data minus output signal. th is signal is multiplexed with cspi2_miso of cspi2. usbh2_oe usb host2 output enable signal. this signal is multiplexed with cspi2_sclk of cspi2. usbh2_fs usb host2 full speed output signal. this signal is multiplexed with cspi2_ss[0] of cspi2. usbg_scl usb otg i 2 c clock output signal. this sign al is multiplexed with slcdc1_dat8. usbg_sda usb otg i 2 c data input/output signal. this signal is multiplexed with slcdc1_dat7. usbg_txr_int usb otg transceiver interrupt input. multiplexed with usbg_fs. secure digital interface sd1_cmd sd command bidirectional signal?if the system designer does not want to make use of the internal pull-up, via the pull-up enable register , a 4.7k?69k external pull up resistor must be added. this signal is multiplexed with cspi3_mosi. sd1_clk sd output clock. this signal is multiplexed with cspi3_sclk. table 2. i.mx21 signal descriptions (continued) signal name function/notes signal descriptions mc9328mx21 product preview, rev. 1.1 freescale semiconductor 13 sd1_d[3:0] sd data bidirectional signals?if the system desig ner does not want to make use of the internal pull-up, via the pull-up enable register, a 50 k? 69k external pull up resistor must be added. sd1_d[3] is muxed with cspi3_ss wh ile sd1_d[0] is muxed with cspi3_miso. sd2_cmd sd command bidirectional signal. this signal is multiplexed with slcdc1_cs signal from slcdc1. sd2_clk sd output clock signal. this signal is multiplexed with slcdc1_clk signal from slcdc1. sd2_d[3:0] sd data bidirectional signals. sd2_d[3:2] are which are multiplexed with slcdc1_rs and slcdc_d0 signals from slcdc1. uarts ? irda/auto-bauding uart1_rxd receive data input signal uart1_txd transmit data output signal uart1_rts request to send input signal uart1_cts clear to send output signal uart2_rxd receive data input signal. this signal is multiplexed with kp_row6 signal from kpp. uart2_txd transmit data output signal. this signal is multiplexed with kp _col6 signal from kpp. uart2_rts request to send input signal. this signal is multiplexed with kp_row7 signal from kpp. uart2_cts clear to send outpu t signal. this signal is multip lexed with kp_col7 signal from kpp. uart3_rxd receive data input signal. this signal is multiplexed with ir_rxd from firi. uart3_txd transmit data output signal. this signal is multiplexed with ir_txd from firi. uart3_rts request to send input signal uart3_cts clear to send output signal uart4_rxd receive data input signal which is mult iplexed with usbh1_rxdp and usbh1_txdp. uart4_txd transmit data output signal which is multiplexed with usbh1_txdm. uart4_rts request to send input signal which is multiplexed with usbh1_fs and usbh1_rxdp. uart4_cts clear to send output signal which is multiplexed with usbh1_txdp and usbh1_rxdm. serial audio port ? ssi (configurable to i 2 s protocol and ac97) ssi1_clk serial clock signal which is output in master or input in slave ssi1_txd transmit serial data ssi1_rxd receive serial data ssi1_fs frame sync signal which is output in master and input in slave ssi1_mclk ssi1 master clock. mu ltiplexed with tout. ssi2_clk serial clock signal which is output in master or input in slave. ssi2_txd transmit serial data signal ssi2_rxd receive serial data table 2. i.mx21 signal descriptions (continued) signal name function/notes mc9328mx21 product preview, rev. 1.1 14 freescale semiconductor signal descriptions ssi2_fs frame sync signal which is output in master and input in slave. ssi2_mclk ssi2 master clock. mu ltiplexed with tout. ssi3_clk serial clock signal which is output in master or input in slave. this signal is multiplexed with slcdc2_clk ssi3_txd transmit serial data signal which is multiplexed with slcdc2_cs ssi3_rxd receive serial data which is multiplexed with slcdc2_rs ssi3_fs frame sync signal which is output in master and in put in slave. this signal is multiplexed with slcdc2_d0. sap_clk serial clock signal which is output in master or input in slave. sap_txd transmit serial data sap_rxd receive serial data sap_fs frame sync signal which is output in master and input in slave. i 2 c i2c_clk i 2 c clock i2c_data i 2 c data 1-wire owire one wire input and output signal. this signal is multiplexed with jtag rtck. pwm pwmo pwm output. this signal is mu ltiplexed with pc_spkout of pc mcia, as well as tout2 and tout3 of the general purpose timer module. keypad kp_col[7:0] keypad column selection signals. kp_col[7:6] are multiplexed with uart2_cts and uart2_txd respectively. alternatively, kp_col6 is also available on the internal factory test signal test_wb2. the function multiplexing contro l register in the system control chapter must be used in conjunction with programming the gp io multiplexing (to select the alternate signal multiplexing) to choose which signal kp_col6 is available. kp_row[7:0] keypad row selection signals. kp_row[7 :6] are multiplexed with uart2_rts and uart2_rxd signals respectively. alternatively, kp_row7 and kp_row6 are available on the internal factory test signals test_wb0 and test_wb1 respectively . the function multiplexing control register in the system control chapter must be used in conjunction with programming the gpio multiplexing (to select the alternate signal multiplexing) to choose which signals kp_row6 and kp_row7 are available. noisy supply pins nvdd noisy supply for the i/o pins. there are six (6) i/o voltage rings, nvdd1 through nvdd6. nvss noisy ground for the i/o pins table 2. i.mx21 signal descriptions (continued) signal name function/notes specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 15 3 specifications this section contains the electrical specificatio ns and timing diagrams fo r the i.mx21 processor. 3.1 maximum ratings table 3 provides information on maximum ratings. 3.2 recommended operating range table 4 provides the recommen ded operating ranges for the supply voltages. the i.mx 21 processor has multiple pairs of vdd and vss power supply and return pins. qvdd , qvddx, and qvss pins are used for internal logic. all other vdd and vss pins are for the i/o pads voltage supply, and each pair of vdd and vss provides power to the enclosed i/o pads. this design allows differe nt peripheral supply voltage levels in a system. because avdd pins are supply voltages to the analog pads, it is recommended to isolate and noise-filter the avdd pins from other vdd pins. for more information about i/ o pads grouping per vdd, please refer to table 4 on page 15. supply pins ? analog modules vdda (formally avdd) supply for analog blocks qvss (internally connected to avss) quiet gnd for analog blocks (qvss and avss are synonymous) internal power supply qvdd power supply pins for silicon internal circuitry qvss quiet gnd pins for silicon internal circuitry qvddx power supply pin for the arm core, connect directly to qvdd table 3. maximum ratings rating symbol minimum maximum unit supply voltage v dd -0.3 3.3 v maximum operating temperature range of i.mx21 t a - 40 / -30 / 0 70 / 85 c storage temperature test -55 150 c table 4. recommended operating range rating symbol minimum maximum unit i/o supply voltage nvdd 2, 3, 4, 5, 6 2.70 3.30 v i/o supply voltage nvdd 1 1.70 3.30 v table 2. i.mx21 signal descriptions (continued) signal name function/notes mc9328mx21 product preview, rev. 1.1 16 freescale semiconductor specifications 3.3 dc electrical characteristics table 5 contains both maximum and mini mum dc characteristics of the i.mx21. internal supply voltage (core = 266 mhz) qvdd, qvddx 1.45 1.65 v analog supply voltage avdd 1.70 3.30 v table 5. maximum and minimum dc characteristics number or symbol parameter minimum typical maximum unit iop full running operating current qvdd & qvddx=1.65v, nvdd1=1.8v, nvdd2- 6 & avdd=3.1v, full run: core=266mhz, system=133mhz, doze: core=266mhz, system=53mhz, mpeg4 playback (qvga) from mmc/sd card, 30fps, 44.1khz audio) ? 120ma (qvdd+qvddx), 8ma (nvdd1) 6.6ma (nvdd2-6+avdd) ?ma sidd standby current (qvdd, qvddx= 1.55v) ? 360 ? a v ih input high voltage 0.7nvdd ? nvdd v v il input low voltage 0 ? 0.3nvdd v v oh output high voltage 0.8nvdd ? ? v v ol output low voltage ? ? 0.2nvdd v v it+ positive input threshold voltage, v i =v ih ? ? 2.15 v v it- negative input threshold voltage, v i =v il 0.75 ? ? v v hys hysteresis (v it+ ? v it-) =v ih ?0.3 ?? i il input low leakage current (v in = gnd, no pull-up or pull-down) ?? 1 a i ih input high leakage current (v in =v dd , no pull-up or pull-down) ?? 1 a i oh output high current vo = voh ??slow pad: -6 fast pad: -5 ma i ol output low current vo = vol slow pad: 6 fast pad: 5 ??ma i oz output leakage current (v out =v dd , output is tri-stated) ?? 5 a c i input capacitance ? ? 5 pf c o output capacitance ? ? 5 pf table 4. recommended operating range (continued) rating symbol minimum maximum unit specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 17 3.4 ac electrical characteristics the ac characteristics consist of output delays, input setup and hold times, and signal skew times. all signals are specified relative to an appropriate edge of other signals. all timing specifications are specified at a system operating frequency from 0 mhz to 133 mhz (core operating fre quency 266 mhz) with an operating supply voltage from v dd min to v dd max under an operating temperature from t l to t h . all timing is measured at 30 pf loading. table 6. tri-state signal timing pin parameter minimum maximum unit tristate time from tristate activate until i/o becomes hi-z ? 20.8 ns table 7. 32k/26m oscillator signal timing parameter minimum rms maximum unit extal32k input jitter (peak to peak) for both system pll and mcupll ? 5 20 ns extal32k input jitter (peak to peak) for mcupll only ? 5 100 ns extal32k startup time 800 ? ? ms table 8. clko rise/fall time (at 30pf loaded) best case typical worst case units rise time 0.80 1.00 1.40 ns fall time 0.74 1.08 1.67 ns mc9328mx21 product preview, rev. 1.1 18 freescale semiconductor specifications 3.5 dpll timing specifications parameters of the dpll are given in table 9. in this table, t ref is a reference clock period after the predivider and t dck is the output double clock period. table 9. dpll specifications parameter test conditions minimum typical maximum unit reference clock frequency range vcc = 1.5v 16 ? 320 mhz pre-divider output clock frequency range vcc = 1.5v 16 ? 32 mhz double clock frequency range vcc = 1.5v 160 ? 560 mhz pre-divider factor (pd) ? 1 ? 16 ? total multiplication factor (mf) includes both integer and fractional parts 5?15? mf integer part ? 5 ? 15 ? mf numerator should be less than the denominator 0 ? 1022 ? mf denominator ? 1 ? 1023 ? frequency lock-in time after full reset fol mode for non-integer mf (does not include pre-multi lock-in time) 350 400 450 t ref frequency lock-in time after partial reset fol mode for non-integer mf (does not include pre-multi lock-in time) 220 280 330 t ref phase lock-in time after full reset fpl mode and integer mf (does not include pre-multi lock-in time) 480 530 580 t ref phase lock-in time after partial reset fpl mode and integer mf (does not include pre-multi lock-in time) 360 410 460 t ref frequency jitter (p-p) ? ? 0.02 0.03 2t dck phase jitter (p-p) integer mf, fpl mode, vcc=1.5v ? 1.0 1.5 ns power dissipation fol mode, integer mf, f dck = 560 mhz, vcc = 1.5v ?1.5 ?mw (avg) specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 19 3.6 reset module the timing relationships of the reset module with the por and reset_in are shown in figure 2 and figure 3 on page 20. be aware that nvdd must ramp up to at least 1.7v for nvdd1 and 2.7v for nvdd2-6 before qvdd is powered up to prevent forward biasing. figure 2. timing relati onship with por por reset_por reset_dram hreset reset_out clk32 hclk 1 2 3 4 exact 300ms 7 cycles @ clk32 14 cycles @ clk32 can be adjusted depending on the crystal start-up time 32khz or 32.768khz mc9328mx21 product preview, rev. 1.1 20 freescale semiconductor specifications figure 3. timing rela tionship with reset_in table 10. reset module timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit min max min max 1 width of input power_on_reset 800 ? 800 ? ms 2 width of internal power_on_reset (clk32 at 32 khz) 300 300 300 300 ms 3 7k to 32k-cycle stretcher for sdram reset 7 7 7 7 cycles of clk32 4 14k to 32k-cycle stretcher for internal system reset hresert and output reset at pin reset_out 14 14 14 14 cycles of clk32 5 width of external hard-reset reset_in 4 ? 4 ? cycles of clk32 6 4k to 32k-cycle qualifier 4 4 4 4 cycles of clk32 14 cycles @ clk32 reset_in clk32 hclk 5 4 hreset reset_out 6 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 21 3.7 external dma request and grant the external dma request is an active low signal to be u sed by devices external to i.mx21 processor to request the dmac for data transfer. after assertion of external dma reques t the dma burst will start when the ch annel on which the external request is the source (as per the rssr settings) becomes the current highest priority ch annel. the external device using the external dma request should keep its request asserted until it is servic ed by the dmac. one external dma request will initiate one dma burst. the output external grant signal from the dmac is an active-low signal.when the fo llowing conditions are true, the external dma grant signal is asser ted with the initiation of the dma burst. ? the dma channel for which the dma burst is ongoin g has request source as external dma request (as per source select register setting). ? ren and cen bit of this channel are set. ? external dma request is asserted. after the grant is asserted, the external dma request w ill not be sampled until completion of the dma burst. as the external request is synchronized, th e request synchronization will not be done during this period. the priority of the external request becomes low for the next consecu tive burst, if another dma request signal is asserted. worst case?that is, the smallest burst (1 byte read/write ) timing diagrams are shown in figure 4 and figure 5 on page 21. minimum and maximum timings for the external request and external grant signals are present in table 11 on page 22. figure 4 shows the minimum time for wh ich the external grant signal rema ins asserted when an external dma request is de-asserted immediately after sensing grant signal active. figure 4. assertion of dma external grant signal figure 5 shows the safe maximum time fo r which external dma request can be kept asserted, after sensing grant signal active such that a new burst is not initiated. figure 5. safe maximum timings for external request de-assertion ext_dmareq ext_dmagrant t min_assert ext_dmareq data read from external device data written to external device ext_dmagrant t max_write t max_read t max_req_assert note: assumin g in worst case the data is read/written from /to external device as per the above waveform. mc9328mx21 product preview, rev. 1.1 22 freescale semiconductor specifications 3.8 bmi interface timing diagram 3.8.1 connecting bmi to ati mmd devices 3.8.1.1 ati mmd devices drive the bmi_clk/cs in this mode mmd_mode_sel bit is set a nd mmd_clkout bit is cleared. bmi_write and bmi_clk/cs are input signals to bmi driving by ati mmd chip set. output signal bmi_read_req can be used as interrupt signal to inform mmd that data is ready in bmi txfifo for read access. mmd can write data to bmi rxfifo anyt ime as cpu or dma can move data out from rxfifo much faster than the bmi interface. overflow interrupt is ge nerated if rxfifo overflow is detected. once this happens, the new coming data is ignored. 3.8.1.1.1 mmd read bmi timing figure 6 shows the mmd read bmi t iming when the mmd drives clock. on each rising edge of bmi_clk/cs bmi checks the bmi_write logic level to determine if the current cycle is a read cycle. it puts data into the data bus and enables the data out on the rising edge of bmi_clk/ cs if bmi_write is logic high. the bmi_read_req is negated one hclk cycle after the bmi_clk/ cs rising edge of last data read. the mmd cannot issues read command when bmi_read_req is low (no data in txfifo). table 11. dma external request and grant timing parameter table parameter description 3.0 v 1.8 v unit wcs bcs wcs bcs t min_assert minimum assertion time of external grant signal 8 hclk + 8.6 8 hclk + 2.74 8 hclk + 7.17 8 hclk + 3.25 ns t max_req_assert maximum external request assertion time a fter assertion of grant signal 9 hclk - 20.66 9 hclk - 6.7 9 hclk - 17.96 9 hclk - 8.16 ns t max_read maximum external request assertion time after first read completion 8 hclk - 6.21 8 hclk - 0.77 8 hclk - 5.84 8 hclk - 0.66 ns t max_write maximum external request assertion time afte r completion of first write 3 hclk - 15.87 3 hclk - 8.83 3 hclk - 15.9 3 hclk - 9.12 ns specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 23 figure 6. mmd (ati) drives clock, mmd read bmi timing (mmd_mode_sel=1, master_mode_sel=0,mmd_clkout=0) note: all the timings assume that the hclk is running at 133 mhz. note: the min period of the 1t is assumed that mmd latch data at falling edge. note: if the mmd latch data at next rising edge, the ideally max cl ock can be as much as double, but because the bmi data pads are slow pads and it max frequency can only up to 18mhz, the max clock frequency can only up to 36 mhz. 3.8.1.1.2 mmd write bmi timing figure 7 on page 24 shows the mmd writ e bmi timing when mmd drives cl ock. on each falling edge of bmi_clk/cs bmi checks the bmi_write logic level to determine if the current cycle is a write cycle. if the bmi_ write is logic low, it latches data into the rxfifo on each falling edge of bmi_clk/cs signal. table 12. mmd read bmi timing table when mmd drives clock item symbol minimum typical maximum unit clock period 1t 33.3 ? ? ns write setup time ts 11 ? ? ns read_req hold time trh 6 ? 24 ns transfer data setup time tds 6 ? 14 ns transfer data hold time tdh 6 - 14 ns bmi_clk/cs bmi_read_req bmi_write bmi_d[15:0] txd1 txd2 last txd trh 1t tds ts tdh mc9328mx21 product preview, rev. 1.1 24 freescale semiconductor specifications figure 7. mmd (ati) drives clock, mmd write bmi timing (mmd_mode_sel=1, master_mode_sel=0, mmd_clkout=0) note: all timings assume that the hclk is running at 133 mhz. note: at this mode, the maximum frequency of the bmi_clk/cs can be up to 36 mhz (doubles as maximum data pad speed). 3.8.1.2 bmi drives the bmi_clk/cs in this mode mmd_mode_sel and mmd_clkout ar e both set. the software must know which mode it is now (read or write). when the bmi_write is high, bmi drives bm i_clk/cs out if the txfifo is not emptied. when bmi_write is low, user can wr ite a 1 to read bit of control register1 to issue a write cycle (mmd write bmi). 3.8.1.3 mmd read bmi timing figure 13 on page 29 shows the mmd read bmi timi ng when bmi drives the bmi_clk/cs. when the bmi_write is high, the bmi drives bmi_clk/cs out if data is written to txfifo (bmi_read_req become high), bmi puts data into data bus and enab le data out on the rising edge of bmi_clk/cs. the mmd devices can latch the data on each falling edge of bmi_clk/cs. it is recommended that the mmd do not change the bmi_write signal from high to low when the bmi_read_req is asserted. if user writes data to the txfifo when the bmi_write is low, the bmi will drive bmi_clk/cs out once the bmi_write is changed from low to high. table 13. mmd write bmi timing item symbol minimum typical maximum unit write setup time ts 11 ? ? ns write hold time th 0 ? ? ns receive data setup time tds 5 ? ? ns can be asserted any time can be asserted any time bmi_clk/cs bmi_read_req bmi_write bmi_d[15:0] rxd1 rxd2 last rxd ts tds th specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 25 figure 8. bmi drives clock, mmd read bmi timing (master_mode_sel=0, mmd_mode_sel=1, mmd_clkout=1) note: in this mode, the max frequency of the bmi_clk/cs can be up to 36mhz(double as max data pad speed). note: the bmi_clk/cs can only be divided by 2,4,8,16 from hclk. 3.8.1.4 mmd write bmi timing figure on page 26 shows the mmd write bm i timing when bmi drives bmi_clk/cs. when the bmi_write signal is asserted, the bmi can write a 1 to read bit of control register to issue a write cycle. this bit is clear ed automatically when the write operation is completed. in a write burst the mmd will write count+1 da ta to the bmi. the user can i ssue another write operation if the mmd still has data to write after the first operation completed. the bmi can latch the data either at falling edge or the ne xt rising edge of the bmi_clk/cs according to the data_latch bit. when the data_latch bit is se t, the bmi latch data at the next rising edge and latch the last data us ing the internal clock. bmi_write signal can not be negated when the write operation is proceeding. table 14. mmd read bmi timing table when bmi drives clock item symbol min typ max unit transfer data setup time tds 2 ? 8 ns transfer data hold time tdh 2 ? 8 ns read_req hold time trh 2 ? 18 ns bmi_clk/cs bmi_read_req bmi_write bmi_d[15:0] txd1 txd2 last txd 1t tds trh dma or cpu write data to txfifo tdh mc9328mx21 product preview, rev. 1.1 26 freescale semiconductor specifications figure 9. bmi drives cloc k, mmd write bmi timing (master_mode_sel=0, mmd_mode_sel=1, mmd_clkout=1) note: the bmi_clk/cs can only be up to 30mhz if bmi latch data at the falling edge and can be up to 36mhz (double as max data pad speed) if bmi latch dat a at the next rising edge. note: tds1 is the receive data setup time when bmi latch data at the falling edge. note: tds2 is the receive data setup time when bmi latch data at the next rising edge. 3.8.2 connecting bmi to exte rnal bus master devices in this mode both master_sel bit and mmd_m ode_sel bit are cleared and the mmd_clkout bit is no useful. bmi_write and bmi_clk/cs are input signals driving by the external bus master. the output signal bmi_read_req can be used as an interrupt signal to inform external bus ma ster that data is ready in the bmi txfifo for a re ad access. the external bus master can write data to the bmi rxfifo anytime since the cpu or dma can m ove data out from rxfifo much fa ster than the bmi interface. an overflow interrupt is gene rated if rxfifo overflow is detected. once this happens, the new coming data is ignored. each falling edge of bmi_cl k/cs will determine if the current cycle is read or wr ite cycle. it drives data and enables data out if bmi_write is logic high. the d_en signal re mains active only while bmi_clk/ cs is logic low and bmi_write is logic high. each rising edge of bmi_cl k/cs will determine if da ta should be latched to rx fifo from the data bus. table 15. mmd write bmi timi ng table when bmi drives clock item symbol minimum typical maximum unit receive data setup time1 tds1 14 ? ? ns receive data setup time2 tds2 14 ? ? ns can be asserted any time can be asserted any time bmi_clk/cs bmi_read_req bmi_write bmi_d[15:0] rxd1 rxd2 last rxd tds1 tds2 a 1 is written to read bit of control register total has count+1 clocks in one burst specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 27 figure 10. memory interface slave mode, external bus master read/write to bmi timing (mmd_mode_sel=0, master_mode_sel=0) note: all the timings are assumed that the hclk is running at 133 mhz. 3.8.3 connecting bmi to external bus slave devices in this mode the bmi_write , bmi_read and bmi_clk/cs are output signals driving by the bmi module. the output signal bmi_read_req is still driv ing active-in on a write cycle, but it can be ignored in this case. instead, it is used to trigger internal logic to generate the read or write signals. data write cycles are continuously genera ted when txfifo is not emptied. to issue a read cycle, the user can write a value of 1 to the read bit of control register. this bit is cleared automatically when the read operat ion is completed. a read cycle read s count+1 data from the external bus slave. the user can write a 1 to the read bit while there is still data in the txfifo, but the read cycle will not start until all data in the txfifo is emp tied. if the read cycle begi ns, the write operation also cannot begin until this read cycle complete. in this master mode operation, int_clk is derived from hclk through an inte ger divider div of bmi control register and it is us ed to control the read/write cycle timing by generate write and clk/cs signals. table 16. external bus master read/write to bmi timing table item symbol minimum typical maximum unit write setup time ts 11 ? ? ns write hold time th 0 ? ? ns receive data hold time trdh 3 ? ? ns transfer data setup time ttds 6 ? 14 ns transfer data hold time ttdh 6 ? 14 ns read_req hold time trh 6 ? 24 ns bmi_clk/cs bmi_read_req bmi_write bmi_d[15:0] rxd txd last txd read bmi write bmi read bmi trdh trh th ts ts ttds ttdh mc9328mx21 product preview, rev. 1.1 28 freescale semiconductor specifications 3.8.3.1 memory interface master mode without wait signal the wait control bit (bmictlr1[29]) is used in th is mode. when this bit is cleared (default), the bmi_wait signal is ignored and the cs cycle is termin ated by wait state (ws) control bits. figure 11 shows the bmi timing when the wait bit is cleared. figure 11. memory interface master mode, bmi read/write to external slave device timing without wait signal (mmd_mode_sel=0, master_mode_sel=1) 3.8.3.2 memory interface master mode with wait signal when the wait control bit is set, the bmi_wait signal is used and the cs cycle is terminated upon sampling a logic high bmi_wait signal. figure 12 shows the bmi write timing when the wait bit is set. when the bmi_write is asserted, the bmi will detect the bmi_wait signal on every falling edge of the int_clk. when it detected the high level of the bmi_wait , the bmi_write will be negated after 1+ws int_clk period. if the bmi_wait is always high or already high before bmi_write is asserted, this timing will sa me as without wait signal. so the bmi_write will be asserted at least for 1+ws int_clk period. 1+ws 1+ws bmi_read bmi_write int_clk bmi_clk/cs bmi_read_req int_write bmi_d[15:0] txd1 txd2 last txd rxd1 rxd2 1+ws 1+ws dma or cpu write data to txfifo on the next int_clk bmi issues a write cycle bmi_read_req is still logic hi gh, bmi issues next write cycle a 1 is written to read bit of control reg1 bmi write bmi write bmi write tdh (reference only) (reference only) specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 29 figure 12. memory interface master mode, bmi write to external slave device timing with wait signal (mmd_mode_sel=0, master_mode_sel=1,wait=1) figure 13 shows the bmi read timing when the wait bit is set. as write timing, when the bmi_read is asserted, the bmi will detect the bmi_wait signal on every falling edge of the int_clk. when it detected the high level of the bmi_wait , the bmi_read will be negated after 1+ ws int_clk period. if the bmi_wait is always high or alr eady high before bmi_read is asserted, this timing will same as without wait signal. so the bmi_read will be asserted at l east for 1+ws int_clk period. figure 13. memory interface master mode, bmi read to external slave device timing with wait signal (mmd_mode_sel=0, master_mode_sel=1,wait=1) 3.9 spi timing diagrams to use the internal transmit (tx) a nd receive (rx) data fifos when the spi 1 module is configured as a master, two control signals are used for data transf er rate control: the ss signal (output) and the spi_rdy signal (input). the spi 1 sample period control regi ster (periodreg1) and the spi 2 sample period control register (periodreg2) can al so be programmed to a fixed data tr ansfer rate for either spi 1 or spi 2. when the spi 1 module is configured as a slav e, the user can configure the spi 1 control register (controlreg1) to match the external spi master?s timing. in this configuration, ss becomes an input 1+ws 1+ws int_clk bmi_clk/cs bmi_d[15:0] bmi_write bmi_read bmi_wait (reference only) txd_a txd_b 1+ws 1+ws int_clk bmi_clk/cs bmi_d[15:0] bmi_read bmi_write bmi_wait (reference only) rxd_a rxd_b mc9328mx21 product preview, rev. 1.1 30 freescale semiconductor specifications signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data fifo. . figure 14. master spi timing diagram using spi_rdy edge trigger figure 15. master spi timing diagram using spi_rdy level trigger figure 16. master spi timing diagram ignore spi_rdy level trigger figure 17. slave spi timing diagra m fifo advanced by bit count figure 18. slave spi timing di agram fifo advanced by ss rising edge 1 2 3 5 4 ss spirdy sclk, mosi, miso ss spirdy sclk, mosi, miso sclk, mosi, miso ss (output) ss (input) sclk, mosi, miso 6 7 ss (input) sclk, mosi, miso specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 31 3.10 lcd controller this section includes timing diagrams for the lcd c ontroller. for detailed timing diagrams of the lcd controller with various display configurations , refer to the lcd controller chapter of the i.mx21 reference manual . figure 19. sclk to ld timing diagram table 17. timing parameter table for figure 14 through figure 18 ref no. parameter minimum maximum unit 1 spi_rdy to ss output low 2t 1 1. t = cspi system clock period (perclk2). ?ns 2ss output low to first sclk edge 3tsclk 2 2. tsclk = period of sclk. ?ns 3 last sclk edge to ss output high 2tsclk ? ns 4ss output high to spi_rdy low 0 ? ns 5ss output pulse width tsclk + wait 3 3. wait = number of bit clocks (sclk) or 32.768 khz clocks per sample period control register. ?ns 6ss input low to first sclk edge t ? ns 7ss input pulse width t ? ns table 18. lcdc sclk timing parameter table symbol parameter 3.0 +/- 0.3v unit minimum maximum t1 sclk period 23 2000 ns t2 pixel data setup time 11 ? ns t3 pixel data up time 11 ? ns the pixel clock is equal to lcdc_clk / (pcd + 1). when it is in cstn, tft or monochrome mode with bus width = 1, sclk is equal to the pixel clock. when it is in monochrome with other bus width settings, sclk is equal to the pixel clock divided by bus width. the polarity of sclk and ld can also be programmed. maximum frequency of sclk is hclk / 3 for tft and cstn, otherwise ld output will be incorrect. lsclk ld[17:0] t1 t2 t3 mc9328mx21 product preview, rev. 1.1 32 freescale semiconductor specifications figure 20. 4/8/12/16/18 bit/pixe l tft color mode panel timing table 19. 4/8/12/1 6/18 bit/pixel tft color mode panel timing symbol description minimum value unit t1 end of oe to beginning of vsyn t5+t6+t7-1 (vwait1 t2)+t5+t6+t7-1 ts t2 hsyn period ? xmax+t5+t6+t7 ts t3 vsyn pulse wid th t2 vwidtht2 ts t4 end of vsyn to beginning of oe 1 (vwait2t2)+1 ts t5 hsyn pulse width 1 hwidth+1 ts t6 end of hsyn to beginning to oe 3 hwait2+3 ts t7 end of oe to beginning of hsyn 1 hwait1+1 ts note: ts is the sclk period. vsyn, hsyn and oe can be programmed as active high or active low. in figure 20, all 3 signals are active low. sclk can be programmed to be deactiv ated during the vsyn pulse or the oe de asserted period. in figure 20, sclk is always active. xmax is defined in number of pixels in one line. line 1 line y t1 t4 t3 (0,1) (0,2) (0,x-1) t5 t7 t6 xmax vsyn hsyn oe ld[17:0] sclk hsyn oe ld[15:0] t2 display region non-display region line y specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 33 figure 21. sharp tft panel timing table 20. sharp tft panel timing symbol description minimum value unit t1 spl/spr pulse width ? 1 ts t2 end of ld of line to beginning of hsyn 1 hwait1+1 ts t3 end of hsyn to beginning of ld of line 4 hwait2 + 4 ts t4 cls rise delay from end of ld of line 3 cls_rise_delay+1 ts t5 cls pulse width 1 cls_hi_width+1 ts t6 ps rise delay from cls negation 0 ps_rise_delay ts t7 rev toggle delay from last ld of line 1 rev_toggle_delay+1 ts note: falling of spl/spr aligns with first ld of line. falling of ps aligns with rising edge of cls. rev toggles in every hsyn period. d1 d2 d320 sclk ld spl_spr hsyn cls ps rev xmax t2 d320 t1 t3 t5 t4 t7 t6 t2 t4 t7 mc9328mx21 product preview, rev. 1.1 34 freescale semiconductor specifications figure 22. non-tft mode panel timing table 21. non-tft mode panel timing symbol description minimum value unit t1 hsyn to vsyn delay 2 hwait2+2 tpix t2 hsyn pulse width 1 hwidth+1 tpix t3 vsyn to sclk ? 0 t3 ts ? t4 sclk to hsyn 1 hwait1+1 tpix note: ts is the sclk period while tpix is the pixel clock period. vsyn, hsyn and sclk can be programmed as active high or active low. in figur e 67 on page 83 , all these 3 signals are active high. when it is in cstn mode or monochrome mode with bus width = 1, t3 = tpix = ts. when it is in monochrome mode with bus width = 2, 4, and 8, t3 = 1, 2 and 4 tpix respectively. t1 t2 t4 t3 xmax vsyn sclk hsyn ld[15:0] t2 t1 ts specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 35 3.11 smart lcd controller figure 23. slcdc serial transfer timing t2 t1 t4 t3 t5 t7 t6 t2 t1 t4 t3 t5 t7 t6 t2 t1 t4 t3 t5 t7 t6 lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 command data, rs=1 display data lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 command data, rs=1 display data sckpol = 1, cspol = 0 sckpol = 0, cspol = 0 lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 command data, rs=1 display data sckpol = 1, cspol = 1 lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 command data, rs=1 display data sckpol = 0, cspol = 1 t2 t1 t4 t3 t5 t7 t6 mc9328mx21 product preview, rev. 1.1 36 freescale semiconductor specifications figure 24. slcdc parallel transfers timing table 22. slcdc serial transfer timing symbol description minimum maximum unit t1 pixel clock period 42 962 ns t2 chip select setup time 5 ? ns t3 chip select hold time 5 ? ns t4 data setup time 5 ? ns t4 data hold time 5 ? ns t6 register select setup time 5 ? ns t7 register select hold time 5 ? ns lcd_clk lcd_data[15:0] lcd_rs command data lcd_cs display data t5 t4 t2 t3 t1 lcd_clk lcd_data[15:0] lcd_rs command data lcd_cs display data t5 t4 t2 t3 t1 cspol=0 cspol=1 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 37 3.12 multimedia card/secure digital host controller the dma interface block controls al l data routing between the external data bus (dma access), internal mmc/sd module data bus, and inte rnal system fifo a ccess through a dedicated state machine that monitors the status of fifo conten t (empty or full), fifo address, and byte/block counters for the mmc/ sd module (inner system) and the application (user programming). figure 25. chip-select read cycle timing diagram table 23. slcdc para llel transfers timing symbol description minimum maximum unit t1 pixel clock period 23 962 ns t2 data setup time 5 ? ns t3 data hold time 5 ? ns t4 register select setup time 5 ? ns t5 register select hold time 5 ? ns table 24. sdhc bus timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit min max min max 1 clk frequency at data transfer mode (pp) 1 ? 10/30 cards 0 25/5 0 25/5 mhz 2 clk frequency at identification mode 2 0 400 0 400 khz 3a clock high time 1 ? 10/30 cards 6/33 ? 10/50 ? ns 3b clock low time 1 ? 10/30 cards 15/75 ? 10/50 ? ns 4a clock fall time 1 ? 10/30 cards ? 10/50 (5.00) 3 ? 10/50 ns 4b clock rise time 1 ? 10/30 cards ? 14/67 (6.67) 3 ? 10/50 ns bus clock 5b 6b 6a 7 5a 4a 3a cmd_dat input cmd_dat output 4b 3b valid data valid data valid data valid data 1 2 mc9328mx21 product preview, rev. 1.1 38 freescale semiconductor specifications 3.12.1 command response timing on mmc/sd bus the card identification and card ope ration conditions timing are processe d in open-drain mode. the card response to the host command starts after exactly n id clock cycles. for the card address assignment, set_rca is also processed in the open-drain mode . the minimum delay betw een the host command and card response is ncr clock cycl es as illustrated in figure 26. the symbols for figure 26 through figure 30 are defined in table 25. 5a input hold time 3 ? 10/30 cards 5.7/5.7 ? 5/5 ? ns 5b input setup time 3 ? 10/30 cards 5.7/5.7 ? 5/5 ? ns 6a output hold time 3 ? 10/30 cards 5.7/5.7 ? 5/5 ? ns 6b output setup time 3 ? 10/30 cards 5.7/5.7 ? 5/5 ? ns 7 output delay time 3 0 16 0 14 ns 1. c l 100 pf / 250 pf (10/30 cards) 2. c l 250 pf (21 cards) 3. c l 25 pf (1 card) table 25. state signal parameters for figure 26 through figure 30 card active host active symbol definition symbol definition z high impedance state s start bit (0) d data bits t transmitter bit (host = 1, card = 0) * repetition p one-cycle pull-up (1) crc cyclic redundancy check bits (7 bits) e end bit (1) table 24. sdhc bus timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit min max min max specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 39 figure 26. timing diagrams at identification mode after a card receives its rca, it switches to data transfer mode. as shown on the first diagram in figure 27 on page 39, sd_cmd lines in this m ode are driven with push-pull driv ers. the command is followed by a period of two z bits (all owing time for direction switching on th e bus) and then by p bits pushed up by the responding card. the other two diagra ms show the sepa rating periods n rc and n cc . figure 27. timing diagrams at data transfer mode figure 28 on page 40 shows basic read operation timing. in a read operation, the sequence starts with a single block read command (which sp ecifies the start address in the ar gument field). the response is sent on the sd_cmd lines as usual. da ta transmission from the card starts after the access time delay n ac , beginning from the last bit of the r ead command. if the system is in mu ltiple block read mode, the card sends a continuous flow of da ta blocks with distance n ac until the card sees a stop transmission command. the data stops two clock cycles af ter the end bit of the stop command. set_rca timing identification timing host command cid/ocr n id cycles cmd content s t e z z s t content z z ****** crc z host command cid/ocr n cr cycles cmd content s t e z z s t content z z ****** crc z timing of command sequences (all modes) timing response end to next cmd start (data transfer mode) command response timing (data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z z ****** crc z response host command n rc cycles cmd content s t e z z s t content crc e z z ****** crc z host command host command n cc cycles cmd content s t e z z s t content crc e z z ****** crc z mc9328mx21 product preview, rev. 1.1 40 freescale semiconductor specifications figure 28. timing diag rams at data read figure 29 on page 41 shows the basic write operation timing. as with th e read operation, after the card response, the data tran sfer starts after n wr cycles. the data is suffixed wi th crc check bits to allow the card to check for transmi ssion errors. the card sends back the crc check result as a cc status token on the data line. if there was a transmission error, the card sends a negative crc st atus (101); otherwise, a positive crc status (010) is returned. the card expects a continuous flow of data bloc ks if it is configured to multiple block mode, with the flow terminated by a stop transmission command. n ac cycles read data timing of single block read n ac cycles read data timing of multiple block read n ac cycles n st timing of stop command (cmd12, data transfer mode) host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc dat z****z z z p p s d ***** d d d dat z****z z z p p s d ***** ****** d d d p ***** p s d d d d ****** host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc ***** read data host command response n cr cycles cmd content s t e z z p p s t content crc e z ****** crc valid read data dat ***** z z e ***** d d d d d d d d z specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 41 figure 29. timing diagrams at data write the stop transmission command may occur when the card is in diff erent states. figure 30 shows the different scenarios on the bus. write data busy write data write data host command response n cr cycles cmd dat timing of the block write command n wr cycles busy crc status cmd dat timing of the multiple block write command content crc status n wr cycles crc status e z z p p p p ****** z z p p s crc e z z s e z p p s content crc e z z s e s e z x x x x x x l*l x x x x x x status status dat content z z p p s crc e z z x x z p p s content crc e z z x x x x x x x x x x z n wr cycles x x x x x x z****z z z z p p s content crc e z z s e s e z l*l status x x x x x x x z x x x e z z p p s content crc z z z dat z****z content s t crc e z z p p s t content crc e z z p ****** ****** p p p mc9328mx21 product preview, rev. 1.1 42 freescale semiconductor specifications figure 30. stop transmission during different scenarios table 26. timing values for figure 26 through figure 30 parameter symbol minimum maximum unit mmc/sd bus clock, clk (all values are re ferred to minimum (vih) and maximum (vil) command response cycle ncr 2 64 clock cycles identification response cycle nid 5 5 clock cycles write data stop transmission during data transfer from the host. busy (card is programming) stop transmission during crc status transfer from the card. stop transmission received a fter last data block. card becomes busy programming. stop transmission received a fter last data block. card becomes busy programming. host command card response n cr cycles cmd content s t e z z p p s t content crc e z z ****** host command content s t crc e dat ****** d d d d d d z z z z d d d d d d d e z z s l z z z z z z z z z z z z z z z z z z z z z z e dat ****** d d d d d d z z z z d z z s z z s l z z z z z z z z z z z z z z z z z z z z z z e crc e crc dat ****** s l z z z z z z z z z z z z z z z z z z z z z z z z z z e dat ****** z z z z z z z z z z z z z z z z z z z z s l z z z z z z z z z z z z z z z z z z z z z z e z specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 43 3.12.2 sdio-irq and readwait service handling in sdio, there is a 1-bit or 4-bi t interrupt response from the sdio peripheral card. in 1-bit mode, the interrupt response is simply that the sd_dat[1] line is held low. the sd_dat[1] line is not used as data in this mode. the memory controller generates an interrupt according to this low and the system interrupt continues until the source is removed (s d_dat[1] returns to its high level). in 4-bit mode, the interrupt is less simple. the interrupt trigge rs at a particular period called the interrupt period during the data access, and the controller must sample sd_dat[1] during this short period to determine the irq status of the attached card. the interrupt period only happens at the boundary of each block (512 bytes). figure 31. sdio irq timing diagram readwait is another feature in sdio that allows the user to submit commands during the data transfer. in this mode, the block temporarily pauses the data tr ansfer operation counter and related status, yet keeps the clock running, and allows the user to submit commands as nor mal. after all comm ands are submitted, the user can switch back to the da ta transfer operation and all counter and status values are resumed as access continues. access time delay cycle nac 2 taac + nsac clock cycles command read cycle nrc 8 ? clock cycles command-command cycle ncc 8 ? clock cycles command write cycle nwr 2 ? clock cycles stop transmission cycle nst 2 2 clock cycles taac: data read access time -1 defined in csd register bit[119:112] nsac: data read access time -2 in clk cycles (nsac100) defined in csd register bit[111:104] table 26. timing values for fi gure 26 through figure 30 (continued) parameter symbol minimum maximum unit interrupt period irq irq dat[1] for 4-bit l h interrupt period dat[1] for 1-bit cmd content s t e z z p e z z ****** z z response crc s z z e s block data e s block data mc9328mx21 product preview, rev. 1.1 44 freescale semiconductor specifications figure 32. sdio readwa it timing diagram 3.13 nand-flash controller interface the timing diagrams figure 33 through figure 36show s the timing of the nand flash controller. table 27 on page 46 provides the relative timing requ irement for the different signals of nfc at the i.mx21 module level. figure 33. command latch cycle timing dat[1] for 4-bit dat[2] for 4-bit cmd ****** p s t e z z ****** cmd52 z crc e z z s block data l l l l l l l l l l l l l l l l l l l l l h z s e s block data e block data z z l h e s block data nfcle nfce nfwe nfale nfio7:0 command tdh tds tcls tclh twp tcs tch tals talh specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 45 figure 34. address latch cycle timing figure 35. input data latch cycle timing nfcle nfce nfwe nfale nfio7:0 address tdh tds tcls twp tcs tch tals twh twc talh nfcle nfce nfwe nfale nfio15:0 data to nf tdh tds tcls twp tcs tals twh twc talh mc9328mx21 product preview, rev. 1.1 46 freescale semiconductor specifications figure 36. output data latch cycle timing note: the data shown in figure 36 is generated using th e nand flash device and sampled with ipp_flash_clk. table 27. timing characteristics number timing parameter minimum maximum 1tcls0 ? 2tclh10 ? 3tcs0 ? 4tch10 ? 5twp25 ? 6tals0 ? 7talh10 ? 8tds20 ? 9tdh10 ? 10 twc 45 ? 11 twh 15 ? 12 tar 10 ? 13 tclr 10 ? 14 trr 20 ? 15 trp 25 ? 16 twb ? 100 nfcle nfce nfre nfale nfio15:0 data from nf trp trea treh trc trhz nfce trr specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 47 3.14 pulse-width modulator the pwm can be programmed to select one of two clock signals as it s source frequency. the selected clock signal is passed through a divi der and a prescaler before being i nput to the counter. the output is available at the pulse-width modulat or output (pwmo) external pin. figure 37. pwm output timing diagram 17 trc 50 ? 18 tcea ? 45 19 trea ? 30 20 trhz ? 30 21 tchz ? 20 22 toh 15 ? 23 treh 15 ? 24 tir 0 ? 25 twhr 60 ? table 28. pwm output timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum 1 system clk frequency 1 045045mhz 2a clock high time 1 12.29 ? 12.29 ? ns 2b clock low time 1 9.91?9.91?ns 3a clock fall time 1 ?0.5?0.5ns 3b clock rise time 1 ?0.5?0.5ns table 27. timing characteristics (continued) number timing parameter minimum maximum system clock 2a 1 pwm output 3b 2b 3a 4b 4a mc9328mx21 product preview, rev. 1.1 48 freescale semiconductor specifications 3.15 sdram memory controller the following figures (figure 38 through figure 41 on pa ge 52) and their associat ed tables specify the timings related to the sdramc module in the i.mx21. figure 38. sdram read cycle timing diagram 4a output delay time 1 9.37?3.61?ns 4b output setup time 1 8.71?3.03?ns 1. c l of pwmo = 30 pf table 28. pwm output timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum sdclk we addr dq dqm row/ba col/ba 3s 3h 3s 3h 3s 3 s 3h 3h 3h 4s 4h 5 3s 3 2 1 8 data 7 6 cs cas ras note: cke is high during the read/write cycle. specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 49 table 29. sdram ti ming parameter table ref no. parameter 1.8v 3.0v +/-10% unit minimum maximum minimum maximum 1 sdram clock high-level width 3.00 ? 4 ? ns 2 sdram clock low-level width 3.00 ? 4 ? ns 3 sdram clock cycle time 11.1 ? 7.5 ? ns 3s cs, ras, cas, we, dqm setup time 4.78 ? 3 ? ns 3h cs, ras, cas, we, dqm hold time 3.03 ? 2 ? ns 4s address setup time 3.67 ? 3 ? ns 4h address hold time 2.95 ? 2 ? ns 5 sdram access time (cl = 3) ? 5.4 ? 5.4 ns 5 sdram access time (cl = 2) ? 6.0 ? 6.0 ns 5 sdram access time (cl = 1) ? ? ? ? ns 6 data out hold time 3.0 ? 3.0 ?ns 7 data out high-impedance time (cl = 3) ? t hz 1 1. t hz = sdram data out high-impedance time, exter nal sdram memory device dependent parameter. ? t hz 1 ns 7 data out high-impedance time (cl = 2) ? t hz 1 ? t hz 1 ns 7 data out high-impedance time (cl = 1) ? ? ? ? ns 8 active to read/write command period (rc = 1) t rcd 2 2. t rcd = sdram clock cycle time. the t rcd setting can be found in the i.mx21 reference manual. ? t rcd 2 ?ns mc9328mx21 product preview, rev. 1.1 50 freescale semiconductor specifications figure 39. sdram write cycle timing diagram table 30. sdram write timing parameter table ref no. parameter 1.8v 3.0v +/-10% unit minimum maximum minimum maximum 1 sdram clock high-level width 3.00 ? 4 ? ns 2 sdram clock low-level width 3.00 ? 4 ? ns 3 sdram clock cycle time 11.1 ? 7.5 ? ns 4 address setup time 3.67 ? 3 ? ns 5 address hold time 2.95 ? 2 ? ns 6 precharge cycle period 1 t rp 2 ?t rp 2 ?ns 7 active to read/write command delay t rcd 2 ?t rcd 2 ?ns 8 data setup time 3.41 ? 2 ? ns sdclk cs cas we ras addr dq dqm / ba row/ba 3 4 6 1 col/ba data 2 5 7 8 9 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 51 figure 40. sdram refresh timing diagram 9 data hold time 2.45 ? 2 ? ns 1. precharge cycle timing is incl uded in the write timing diagram. 2. t rp and t rcd = sdram clock cycle time. these settings ca n be found in the i.mx21 reference manual. table 31. sdram refresh timing parameter table ref no. parameter 1.8v 3.0v +/-10% unit minimum maximum minimum maximum 1 sdram clock high-level width 3.00 ? 4 ? ns 2 sdram clock low-level width 3.00 ? 4 ? ns 3 sdram clock cycle time 11.1 ? 7.5 ? ns table 30. sdram write timing parameter table (continued) ref no. parameter 1.8v 3.0v +/-10% unit minimum maximum minimum maximum sdclk cs cas we ras addr dq dqm ba 3 4 6 1 2 5 7 row/ba 7 mc9328mx21 product preview, rev. 1.1 52 freescale semiconductor specifications figure 41. sdram self-refresh cycle timing diagram 3.16 synchronous serial interface the transmit and receive sections of the ssi can be synchronous or asynchronous. in synchronous mode, the transmitter and the receiver use a common clock and frame sync hronization signal. in asynchronous 4 address setup time 3.67 ? 3 ? ns 5 address hold time 2.95 ? 2 ? ns 6 precharge cycle period t rp 1 ?t rp 1 ?ns 7 auto precharge command period t rc 1 ?t rc 1 ?ns 1. t rp and t rc = sdram clock cycle time. these settings can be found in the i.mx21 reference manual. table 31. sdram refresh timi ng parameter table (continued) ref no. parameter 1.8v 3.0v +/-10% unit minimum maximum minimum maximum sdclk cs cas ras addr dq dqm ba we cke specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 53 mode, the transmitter and receive r each have their own clock a nd frame synchronization signals. continuous or gated clock mode can be selected. in continuous mode, the clock r uns continuously. in gated clock mode, the clock functions only during transmission. the internal and external clock timing diagrams are shown in figure 42 through figure 45 on page 54. normal or network mode can also be selected. in no rmal mode, the ssi functions with one data word of i/o per frame. in network mode, a frame can contain between 2 and 32 data words. network mode is typically used in star or ring-tim e division multiplex networks with ot her processors or codecs, allowing interface to time division multiple xed networks without additional logi c. use of the gated clock is not allowed in network mode. these distinctions result in the basic operating modes that allow the ssi to communicate with a wide variety of devices. the ssi can be connected to 4 set of ports, sap, ssi1, ssi2 and ssi3. note: srxd input in synchronous mode only. figure 42. ssi transmitter internal clock timing diagram figure 43. ssi receiver internal clock timing diagram ck output fs (bl) output fs (wl) output 1 2 6 8 10 11 stxd output srxd input 32 31 4 12 ck output fs (bl) output fs (wl) output 3 7 srxd input 13 14 1 5 9 mc9328mx21 product preview, rev. 1.1 54 freescale semiconductor specifications figure 44. ssi transmitter exte rnal clock timing diagram figure 45. ssi receiver exte rnal clock timing diagram table 32. ssi to sap ports timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum internal clock operation 1 (sap ports) 1 (tx/rx) ck clock period 1 90.91 ? 90.91 ? ns 2 (tx) ck high to fs (bl) high -3.30 -1.16 -2.98 -1.10 ns 3 (rx) ck high to fs (bl) high -3.93 -1.34 -4.18 -1.43 ns ck input 16 fs (bl) input fs (wl) input 17 18 22 24 26 stxd output srxd input 27 28 34 note: srxd input in synchronous mode only 33 20 15 ck input 16 fs (bl) input fs (wl) input 17 19 23 srxd input 29 30 21 25 15 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 55 4 (tx) ck high to fs (bl) low -3.30 -1.16 -2.98 -1.10 ns 5 (rx) ck high to fs (bl) low -3.93 -1.34 -4.18 -1.43 ns 6 (tx) ck high to fs (wl) high -3.30 -1.16 -2.98 -1.10 ns 7 (rx) ck high to fs (wl) high -3.93 -1.34 -4.18 -1.43 ns 8 (tx) ck high to fs (wl) low -3.30 -1.16 -2.98 -1.10 ns 9 (rx) ck high to fs (wl) low -3.93 -1.34 -4.18 -1.43 ns 10 (tx) ck high to stxd valid from high impedance -2.44 -0.60 -2.65 -0.98 ns 11a (tx) ck high to stxd high -2.44 -0.60 -2.65 -0.98 ns 11b (tx) ck high to stxd low -2.44 -0.60 -2.65 -0.98 ns 12 (tx) ck high to stxd high impedance -2.67 -0.99 -2.65 -0.98 ns 13 srxd setup time before (rx) ck low 23.68 ? 22.09 ? ns 14 srxd hold time after (rx) ck low 0 ? 0 ? ns external clock operation (sap ports) 15 (tx/rx) ck clock period 1 90.91 ? 90.91 ? ns 16 (tx/rx) ck clock high period 36.36 ? 36.36 ? ns 17 (tx/rx) ck clock low period 36.36 ? 36.36 ? ns 18 (tx) ck high to fs (b l) high 10.24 19.50 7.16 8.65 ns 19 (rx) ck high to fs (bl) high 10.89 21.27 7.63 9.12 ns 20 (tx) ck high to fs (b l) low 10.24 19.50 7.16 8.65 ns 21 (rx) ck high to fs (bl) low 10.89 21.27 7.63 9.12 ns 22 (tx) ck high to fs (w l) high 10.24 19.50 7.16 8.65 ns 23 (rx) ck high to fs (wl) high 10.89 21.27 7.63 9.12 ns 24 (tx) ck high to fs (w l) low 10.24 19.50 7.16 8.65 ns 25 (rx) ck high to fs (wl) low 10.89 21.27 7.63 9.12 ns 26 (tx) ck high to stxd valid fr om high impedance 12.08 19.36 7.71 9.20 ns 27a (tx) ck high to stxd high 10.80 19.36 7.71 9.20 ns table 32. ssi to sap ports timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum mc9328mx21 product preview, rev. 1.1 56 freescale semiconductor specifications 27b (tx) ck high to stxd low 10.80 19.36 7.71 9.20 ns 28 (tx) ck high to stxd hi gh impedance 12.08 19.36 7.71 9.20 ns 29 srxd setup time before (rx) ck low 0.37 ? 0.42 ? ns 30 srxd hole time after (rx) ck low 0 ? 0 ? ns synchronous internal clock operation (sap ports) 31 srxd setup before (tx) ck falling 23.00 ? 21.41 ? ns 32 srxd hold after (tx) ck falling 0 ? 0 ? ns synchronous external clock operation (sap ports) 33 srxd setup before (tx) ck falling 1.20 ? 0.88 ? ns 34 srxd hold after (tx) ck falling 0 ? 0 ? ns 1. all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame syn c (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted , all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync st fs/srfs shown in the tables and in the figures. table 33. ssi to ssi1 ports timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum internal cloc k operation 1 (ssi1 ports) 1 (tx/rx) ck clock period 1 90.91 ? 90.91 ? ns 2 (tx) ck high to fs (bl) high -0.68 -0.15 -0.68 -0.15 ns 3 (rx) ck high to fs (bl) high -0.96 -0.27 -0.96 -0.27 ns 4 (tx) ck high to fs (bl) low -0.68 -0.15 -0.68 -0.15 ns 5 (rx) ck high to fs (bl) low -0.96 -0.27 -0.96 -0.27 ns 6 (tx) ck high to fs (wl) high -0.68 -0.15 -0.68 -0.15 ns 7 (rx) ck high to fs (wl) high -0.96 -0.27 -0.96 -0.27 ns 8 (tx) ck high to fs (wl) low -0.68 -0.15 -0.68 -0.15 ns 9 (rx) ck high to fs (wl) low -0.96 -0.27 -0.96 -0.27 ns table 32. ssi to sap ports timing parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 57 10 (tx) ck high to stxd valid from high impedance -1.68 -0.36 -1.68 -0.36 ns 11a (tx) ck high to stxd high -1.68 -0.36 -1.68 -0.36 ns 11b (tx) ck high to stxd low -1.68 -0.36 -1.68 -0.36 ns 12 (tx) ck high to stxd high impedance -1.58 -0.31 -1.58 -0.31 ns 13 srxd setup time before (rx) ck low 20.41 ? 20.41 ? ns 14 srxd hold time after (rx) ck low 0 ? 0 ? ns external clock operation (ssi1 ports) 15 (tx/rx) ck clock period 1 90.91 ? 90.91 ? ns 16 (tx/rx) ck clock high period 36.36 ? 36.36 ? ns 17 (tx/rx) ck clock low period 36.36 ? 36.36 ? ns 18 (tx) ck high to fs (bl) high 10.22 17.63 8.82 16.24 ns 19 (rx) ck high to fs (bl) high 10.79 19.67 9.39 18.28 ns 20 (tx) ck high to fs (bl) low 10.22 17.63 8.82 16.24 ns 21 (rx) ck high to fs (bl) low 10.79 19.67 9.39 18.28 ns 22 (tx) ck high to fs (wl) high 10.22 17.63 8.82 16.24 ns 23 (rx) ck high to fs (wl) high 10.79 19.67 9.39 18.28 ns 24 (tx) ck high to fs (wl) low 10.22 17.63 8.82 16.24 ns 25 (rx) ck high to fs (wl) low 10.79 19.67 9.39 18.28 ns 26 (tx) ck high to stxd valid from high impedance 10.05 15.75 8.66 14.36 ns 27a (tx) ck high to stxd high 10.00 15.63 8.61 14.24 ns 27b (tx) ck high to stxd low 10.00 15.63 8.61 14.24 ns 28 (tx) ck high to stxd high impedance 10.05 15.75 8.66 14.36 ns 29 srxd setup time before (rx) ck low 0.78 ? 0.47 ? ns 30 srxd hole time after (rx) ck low 0 ? 0 ? ns synchronous internal clock operation (ssi1 ports) 31 srxd setup before (tx) ck falling 19.90 ? 19.90 ? ns table 33. ssi to ssi1 ports ti ming parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum mc9328mx21 product preview, rev. 1.1 58 freescale semiconductor specifications 32 srxd hold after (tx) ck falling 0 ? 0 ? ns synchronous external clock operation (ssi1 ports) 33 srxd setup before (tx) ck falling 2.59 ? 2.28 ? ns 34 srxd hold after (tx) ck falling 0 ? 0 ? ns 1. all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame syn c (tfsi/rfsi = 0). if the polarity of the clock and/or the fram e sync have been inverted, all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync st fs/srfs shown in the tables and in the figures. table 34. ssi to ssi2 ports timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum internal cloc k operation 1 (ssi2 ports) 1 (tx/rx) ck clock period 1 90.91 ? 90.91 ? ns 2 (tx) ck high to fs (bl) high 0.01 0.15 0.01 0.15 ns 3 (rx) ck high to fs (bl) high -0.21 0.05 -0.21 0.05 ns 4 (tx) ck high to fs (bl) low 0.01 0.15 0.01 0.15 ns 5 (rx) ck high to fs (bl) low -0.21 0.05 -0.21 0.05 ns 6 (tx) ck high to fs (wl) high 0.01 0.15 0.01 0.15 ns 7 (rx) ck high to fs (wl) high -0.21 0.05 -0.21 0.05 ns 8 (tx) ck high to fs (wl) low 0.01 0.15 0.01 0.15 ns 9 (rx) ck high to fs (wl) low -0.21 0.05 -0.21 0.05 ns 10 (tx) ck high to stxd valid fr om high impedance 0.34 0.72 0.34 0.72 ns 11a (tx) ck high to stxd high 0.34 0.72 0.34 0.72 ns 11b (tx) ck high to stxd low 0.34 0.72 0.34 0.72 ns 12 (tx) ck high to stxd high impedance 0.34 0.48 0.34 0.48 ns 13 srxd setup time before (rx) ck low 21.50 ? 21.50 ? ns 14srxd hold time after (rx) ck low 0?0?ns table 33. ssi to ssi1 ports ti ming parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 59 external clock operation (ssi2 ports) 15 (tx/rx) ck clock period 1 90.91 ? 90.91 ? ns 16 (tx/rx) ck clock high period 36.36 ? 36.36 ? ns 17 (tx/rx) ck clock low period 36.36 ? 36.36 ? ns 18 (tx) ck high to fs (bl) high 10.40 17.37 8.67 15.88 ns 19 (rx) ck high to fs (bl) high 11.00 19.70 9.28 18.21 ns 20 (tx) ck high to fs (bl) low 10.40 17.37 8.67 15.88 ns 21 (rx) ck high to fs (bl) low 11.00 19.70 9.28 18.21 ns 22 (tx) ck high to fs (wl) high 10.40 17.37 8.67 15.88 ns 23 (rx) ck high to fs (wl) high 11.00 19.70 9.28 18.21 ns 24 (tx) ck high to fs (wl) low 10.40 17.37 8.67 15.88 ns 25 (rx) ck high to fs (wl) low 11.00 19.70 9.28 18.21 ns 26 (tx) ck high to stxd valid from high impedance 9.59 17.08 7.86 15.59 ns 27a (tx) ck high to stxd high 9.59 17.08 7.86 15.59 ns 27b (tx) ck high to stxd low 9.59 17.08 7.86 15.59 ns 28 (tx) ck high to stxd high impedance 9.59 16.84 7.86 15.35 ns 29 srxd setup time before (rx) ck low 2.52 ? 2.52 ? ns 30 srxd hole time after (rx) ck low 0 ? 0 ? ns synchronous internal clock operation (ssi2 ports) 31 srxd setup before (tx) ck falling 20.78 ? 20.78 ? ns 32srxd hold after (tx) ck falling 0?0?ns synchronous external clock operation (ssi2 ports) 33 srxd setup before (tx) ck falling 4.42 ? 4.42 ? ns 34srxd hold after (tx) ck falling 0?0?ns 1. all the timings for the ssi are given for a non-inverted seri al clock polarity (tsckp/rsckp = 0) and a non-inverted frame syn c (tfsi/rfsi = 0). if the polarity of the clo ck and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync st fs/srfs shown in the tables and in the figures. table 34. ssi to ssi2 ports ti ming parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum mc9328mx21 product preview, rev. 1.1 60 freescale semiconductor specifications table 35. ssi to ssi3 ports timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum internal cloc k operation 1 (ssi3 ports) 1 (tx/rx) ck clock period 1 90.91 ? 90.91 ? ns 2 (tx) ck high to fs (bl) high -2.09 -0.66 -2.09 -0.66 ns 3 (rx) ck high to fs (bl) high -2.74 -0.84 -2.74 -0.84 ns 4 (tx) ck high to fs (bl) low -2.09 -0.66 -2.09 -0.66 ns 5 (rx) ck high to fs (bl) low -2.74 -0.84 -2.74 -0.84 ns 6 (tx) ck high to fs (wl) high -2.09 -0.66 -2.09 -0.66 ns 7 (rx) ck high to fs (wl) high -2.74 -0.84 -2.74 -0.84 ns 8 (tx) ck high to fs (wl) low -2.09 -0.66 -2.09 -0.66 ns 9 (rx) ck high to fs (wl) low -2.74 -0.84 -2.74 -0.84 ns 10 (tx) ck high to stxd valid from high impedance -1.73 -0.26 -1.73 -0.26 ns 11a (tx) ck high to stxd high -2.87 -0.80 -2.87 -0.80 ns 11b (tx) ck high to stxd low -2.87 -0.80 -2.87 -0.80 ns 12 (tx) ck high to stxd high impedance -1.73 -0.26 -1.73 -0.26 ns 13 srxd setup time before (rx) ck low 22.77 ? 22.77 ? ns 14 srxd hold time after (rx) ck low 0 ? 0 ? ns external clock operation (ssi3 ports) 15 (tx/rx) ck clock period 1 90.91 ? 90.91 ? ns 16 (tx/rx) ck clock high period 36.36 ? 36.36 ? ns 17 (tx/rx) ck clock low period 36.36 ? 36.36 ? ns 18 (tx) ck high to fs (bl) high 9.62 17.10 7.90 15.61 ns 19 (rx) ck high to fs (bl) high 10.30 19.54 8.58 18.05 ns 20 (tx) ck high to fs (bl) low 9.62 17.10 7.90 15.61 ns 21 (rx) ck high to fs (bl) low 10.30 19.54 8.58 18.05 ns 22 (tx) ck high to fs (wl) high 9.62 17.10 7.90 15.61 ns 23 (rx) ck high to fs (wl) high 10.30 19.54 8.58 18.05 ns specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 61 3.17 1-wire interface timing 3.17.1 reset sequence with reset pulse presence pulse to begin any communications with th e ds2502, it is required that an init ialization procedur e be issued. a reset pulse must be generated and th en a presence pulse must be detect ed. the minimum reset pulse length is 480 us. the bus master (one-wire) will generate th is pulse, then after the ds 2502 detects a rising edge on the one-wire bus, it will wait 15-60 us before it will transmit back a presen ce pulse. the presence pulse will exist for 60-240 us. the timing diagram for this sequence is shown in figure 46. 24 (tx) ck high to fs (wl) low 9.62 17.10 7.90 15.61 ns 25 (rx) ck high to fs (wl) low 10.30 19.54 8.58 18.05 ns 26 (tx) ck high to stxd valid from high impedance 9.02 16.46 7.29 14.97 ns 27a (tx) ck high to stxd high 8.48 15.32 6.75 13.83 ns 27b (tx) ck high to stxd low 8.48 15.32 6.75 13.83 ns 28 (tx) ck high to stxd high impedance 9.02 16.46 7.29 14.97 ns 29 srxd setup time before (rx) ck low 1.49 ? 1.49 ? ns 30 srxd hole time after (rx) ck low 0 ? 0 ? ns synchronous internal clock operation (ssi3 ports) 31 srxd setup before (tx) ck falling 21.99 ? 21.99 ? ns 32 srxd hold after (tx) ck falling 0 ? 0 ? ns synchronous external clock operation (ssi3 ports) 33 srxd setup before (tx) ck falling 3.80 ? 3.80 ? ns 34 srxd hold after (tx) ck falling 0 ? 0 ? ns 1. all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame syn c (tfsi/rfsi = 0). if the polarity of the cl ock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync st fs/srfs shown in the tables and in the figures. table 35. ssi to ssi3 ports ti ming parameter table (continued) ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum mc9328mx21 product preview, rev. 1.1 62 freescale semiconductor specifications figure 46. 1-wire initialization the reset pulse begins the initializati on sequence and it is initiated when th e rpp control register bit is set. when the presence pulse is detecte d, this bit will be clear ed. the presence pulse is used by the bus master to determine if at least one ds2502 is connected. soft ware will determine if mo re than one ds2502 exists. the one-wire will sample for the ds2502 presence pulse . the presence pulse is latched in the one-wire control register pst. when the pst bit is set to a one, it means that a ds2502 is present; if the bit is set to a zero, then no de vice was found. 3.17.2 write 0 the write 0 function simply writes a zero bit to th e ds2502. the sequence takes 117 us. the one-wire bus is held low for 100us. figure 47. write 0 timing the write 0 pulse sequence is initiated when the wr0 control bit register is set. when the write is complete, the wr0 register will be auto cleared. 3.17.3 write 1/read data the write 1 and read timing is iden tical. the time slot is first dr iven low. according to the ds2502 documentation, the ds2502 ha s a delay circuit which is used to synchronize the ds2502 with the bus master (one-wire). this delay circuit is trig gered by the falling edge of the da ta line and is used to decide when the ds2502 should sample the line. in the case of a write 1 or read 1, after a delay, a 1 will be transmitted / received. when a read 0 sl ot is issued, the delay circuit will hold the data line low to override the 1 generated by the bus master (one-wire). for the write 1 or read, the control register wr1/rd is set and auto-c leared when the sequence has been completed. after a read, the cont rol register rdst bit is set to the value of the read. one-wire ds2502 waits 15-60us ds2502 tx ?presence pulse? 60-240us 68us bus reset and presence pulses one-wire samples (set pst) 512us autoclear rpp control bit set rpp 511 us 100us one-wire 17us bus write 0 slot 128us autoclear wr0 set wr0 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 63 figure 48. write 1 timing figure 49. read timing the precision of the generated clock is very importa nt to get a proper behavior of the one-wire module. this module is based on a state machine wh ich undertakes actions at defined times. the most stringent constraint is 0.0645 as a relative time imprecision. the time relative precision is directly derived from the freque ncy of the derivative clock (f): time relative precision = 1/f -1 = divider/clock (mhz) - 1 the table 37 gathers relative time precisi on for different main clock frequencies. table 36. system timing requirements times values (microsec) minimum (microsec) maximum (microsec) absolute precision relative precision rstl 511 480 ? 31 0.0645 pst 68 60 75 7 0.1 rsth 512 480 ? 32 0.0645 low0 100 60 120 20 0.2 lowr 5 1 15 4 0.8 read_sample 13 ? 15 2 0.15 5us write ?1? slot 117us set wr1/rd auto clear wr1/ r 60us one-wire 5us bus read timing read ?0? slot 117us read ?1? slot 117us 13us 5us 13us one-wire samples one-wire samples set wr1/rd auto clear wr1/rd set wr1/rd auto clear wr1/ r (set rdst) (set rdst) mc9328mx21 product preview, rev. 1.1 64 freescale semiconductor specifications this shows that the user should take care of the main clock freque ncy when using the one-wire module. if the main clock is an exact integer multiple of 1 mhz, then the generate d frequency will be exactly 1 mhz. note: a main clock frequency below 10 mhz might cause a misbehavior of the module. 3.18 usb on-the-go four types of data transfer modes exist for the usb module: control tr ansfers, bulk transfers, isochronous transfers and interrupt transfers. fr om the perspective of th e usb module, the interr upt transfer type is identical to the bulk data transfer mode, and no additional hardware is supplied to support it. this section covers the transfer modes and how they work from the ground up. data moves across the usb in packets. groups of packets are combined to form data transfers. the same packet transfer mechanism applies to bulk, interrupt, and cont rol transfers. isochronou s data is also moved in the form of packets, but because isochronous pipe s are given a fixed portion of the usb bandwidth at all times, there is no end-of-transfer. table 37. system clock requirements main clock frequency (mhz) 13 16.8 19.44 clock divide ratio 13 17 19 generated frequency (mhz) 1 0.9882 1.023 relative time imprecision 0 0.0117 0.023 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 65 figure 50. usb timing diagram for data transfer to usb transceiver (tx) table 38. usb timing parameter table for data transfer to usb transceiver (tx) ref no. parameter 3.0 +/- 0.3v unit minimum maximum 1t oeb _txdp ; usbd_oe active to usbd_txdp low 83.14 83.47 ns 2t oeb _txdm ; usbd_oe active to usbd_txdm high 81.55 81.98 ns 3t txdp_ oeb ; usbd_txdp high to usbd_oe deactivated 83.54 83.8 ns 4t txdm_ oeb ; usbd_txdm low to usbd_oe deactivated (includes se0) 248.9 249.13 ns 5t feopt ; se0 interval of eop 160 175 ns 6t period ; data transfer rate 11.97 12.03 mb/s usb_on (output) usb_oe (output) usb_txdp (output) usb_txdm (output) usb_vp (input) usb_vm (input) t oeb_txdp t txdm_oeb t txdp_oeb t feopt t oeb_txdm t period 1 2 3 4 5 6 mc9328mx21 product preview, rev. 1.1 66 freescale semiconductor specifications figure 51. usb timing diagram for data transfer from usb transceiver (rx) the usbotg i 2 c communication protocol consists of six co mponents: start, data source/recipient, data direction, slave acknowledge, data, data acknowledge, and stop. figure 52. usb timing diagram for data transfer from usb transceiver (i 2 c) table 39. usb timing parameter table for data transfer from usb transceiver (rx) ref no. parameter 3.0 +/- 0.3v unit minimum maximum 1t feopr ; receiver se0 interval of eop 82 ? ns usb_on (output) usb_oe (output) usb_txdp (output) usb_txdm (output) usb_rxdp (input) usb_rxdm (input) t feopr 1 usbg_sda usbg_scl 1 2 3 4 6 5 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 67 3.19 external interface module (eim) the external interface module (eim) handles the in terface to devices external to the i.mx21, including generation of chip-selects for exte rnal peripherals and memory. the timing diagram for the eim is shown in figure 53, and table 41 on page 68 de fines the parameters of signals. table 40. usb timing parameter table for data transfer from usb transceiver (i 2 c) ref no. parameter 1.8 +/- 0.10v unit minimum maximum 1 hold time (repeated) start condition 188 ? ns 2 data hold time 0 188 ns 3 data setup time 88 ? ns 4 high period of the scl clock 500 ? ns 5 low period of the scl clock 500 ? ns 6 setup time for stop condition 185 ? ns mc9328mx21 product preview, rev. 1.1 68 freescale semiconductor specifications figure 53. eim bus timing diagram table 41. eim bus timing parameters ref no. parameter 1.8v +/- 0.1v 3.0v +/- 0.3v unit min typical max min typical max 1a clock fall to address valid 3.97 6.02 9.89 3.83 5.89 9.79 ns 1b clock fall to address invalid 3.93 6.00 9.86 3.81 5.86 9.76 ns 2a clock fall to chip-select valid 3.47 5.59 8.62 3.30 5.09 8.45 ns 2b clock fall to chip-select in valid 3.39 5.09 8.27 3.15 4.85 8.03 ns 3a clock fall to read (write ) valid 3.51 5.56 8.79 3.39 5.39 8.51 ns 1a 1b 2a 2b 3b 3a 4a 4b 4c 4d 5a 5b 5c 5d 6a 6a 6b 6c 7a 7b 7c 8a 8b 9b 9c 9a 9a 7d (hclk) bus clock address chip-select read (write ) oe (rising edge) lba (negated rising edge) oe (falling edge) burst clock (rising edge) lba (negated falling edge) eb (falling edge) eb (rising edge) burst clock (falling edge) read data write data (negated falling) write data (negated rising) dtack 10a 10a specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 69 3.19.1 eim external bus timing diagrams the following timing diagrams show the timi ng of accesses to memory or a peripheral. 3b clock fall to read (write ) invalid 3.59 5.37 9.14 3.36 5.20 8.50 ns 4a clock 1 rise to output enable valid 3.62 5.49 8.98 3.46 5.33 9.02 ns 4b clock 1 rise to output enable invalid 3.70 5.61 9.26 3.46 5.37 8.81 ns 4c clock 1 fall to output enable valid 3.60 5.48 8.77 3.44 5.30 8.88 ns 4d clock 1 fall to output enable invalid 3.69 5.62 9.12 3.42 5.36 8.60 ns 5a clock 1 rise to enable bytes valid 3.69 5.46 8.71 3.46 5.25 8.54 ns 5b clock 1 rise to enable bytes invalid 4.64 5.47 8.70 3.46 5.25 8.54 ns 5c clock 1 fall to enable bytes valid 3.52 5.06 8.39 3.41 5.18 8.36 ns 5d clock 1 fall to enable bytes invalid 3.50 5.05 8.27 3.41 5.18 8.36 ns 6a clock 1 fall to load burst address valid 3.65 5.28 8.69 3.30 5.23 8.81 ns 6b clock 1 fall to load burst address invalid 3.65 5.67 9.36 3.41 5.43 9.13 ns 6c clock 1 rise to load burst address invalid 3.66 5.69 9.48 3.33 5.47 9.25 ns 7a clock 1 rise to burst clock rise 3.50 5.22 8.42 3.26 4.99 8.19 ns 7b clock 1 rise to burst clock fall 3.49 5.19 8.30 3.31 5.03 8.17 ns 7c clock 1 fall to burst clock rise 3.50 5.22 8.39 3.26 4.98 8.15 ns 7d clock 1 fall to burst clock fall 3.49 5.19 8.29 3.31 5.02 8.12 ns 8a read data setup time 4.54 ? ? 4.54 ? ? ns 8b read data hold time 0.5 ? ? 0.5 ? ? ns 9a clock 1 rise to write data valid 4.13 5.86 9.16 3.95 6.36 10.31 ns 9b clock 1 fall to write data invalid 4.10 5.79 9.15 4.04 6.27 9.16 ns 9c clock 1 rise to write data invalid 4.02 5.81 9.37 4.22 5.29 9.24 ns 10a dtack setup time 2.65 4.63 8.40 2.64 4.61 8.41 ns 1. clock refers to the system clock signa l, hclk, generated from the system dpll table 41. eim bus timi ng parameters (continued) ref no. parameter 1.8v +/- 0.1v 3.0v +/- 0.3v unit min typical max min typical max mc9328mx21 product preview, rev. 1.1 70 freescale semiconductor specifications figure 54. wsc = 1, a.half/e.half hclk hselm_weim_cs[0] htrans hwrite haddr hready weim_hrdata weim_hready bclk a[24:0] cs [0] r/w lba oe eb (ebc=0) eb (ebc=1) data_in read seq/nonseq v1 last valid data last valid address read v1 v1 v1 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 71 figure 55. wsc = 1, wea = 1, wen = 1, a.half/e.half hclk hselm_weim_cs[0] htrans hwrite haddr hready hwdata weim_hready bclk a[24:0] cs [0] r/w lba oe eb d[31:0] write nonseq v1 last valid data last valid address weim_hrdata write data (v1) unknown last valid data v1 write last valid data write data (v1) mc9328mx21 product preview, rev. 1.1 72 freescale semiconductor specifications figure 56. wsc = 1, oea = 1, a.word/e.half hclk hselm_weim_cs[0] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [0] r/w lba oe eb (ebc=1) data_in weim_hrdata eb (ebc=0) read nonseq v1 last valid data address v1 v1 word read address v1 + 2 last valid addr 1/2 half word 2/2 half word specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 73 figure 57. wsc = 1, wea = 1, wen = 1, a.word/e.half hclk hselm_weim_cs[0] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [0] r/w lba oe eb d[31:0] weim_hrdata hwdata write nonseq v1 last valid data address v1 write data (v1 word) write address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data mc9328mx21 product preview, rev. 1.1 74 freescale semiconductor specifications figure 58. wsc = 3, oea = 2, a.word/e.half hclk hselm_weim_cs[3] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [3] r/w lba oe eb (ebc=0) data_in weim_hrdata eb (ebc=1) read nonseq v1 last valid data address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word read specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 75 figure 59. wsc = 3, wea = 1, wen = 3, a.word/e.half hclk hselm_weim_cs[3] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [3] r/w lba oe d[31:0] weim_hrdata eb hwdata write nonseq v1 last valid data address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data mc9328mx21 product preview, rev. 1.1 76 freescale semiconductor specifications figure 60. wsc = 3, oea = 4, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 77 figure 61. wsc = 3, wea = 2, wen = 3, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe d[31:0] hwdata eb weim_hrdata write nonseq v1 last valid data address v1 write data (v1 word) address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data write last valid data mc9328mx21 product preview, rev. 1.1 78 freescale semiconductor specifications figure 62. wsc = 3, oen = 2, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 79 figure 63. wsc = 3, oea = 2, oen = 2, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 v1 word address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data read mc9328mx21 product preview, rev. 1.1 80 freescale semiconductor specifications figure 64. wsc = 2, wws = 1, wea = 1, wen = 2, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe weim_hrdata eb d[31:0] hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) last valid data write specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 81 figure 65. wsc = 1, wws = 2, wea = 1, wen = 2, a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe weim_hrdata eb d[31:0] hwdata write nonseq v1 address v1 unknown address v1 + 2 last valid addr 1/2 half word 2/2 half word last valid data last valid data write data (v1 word) write last valid data mc9328mx21 product preview, rev. 1.1 82 freescale semiconductor specifications figure 66. wsc = 2, wws = 2, we a = 1, wen = 2, a.half/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe d[31:0] weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 write data address v8 last valid addr last valid data read write nonseq v8 last valid data read data write read data last valid data write data hwdata data_in specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 83 figure 67. wsc = 2, wws = 1, wea = 1, wen = 2, edc = 1, a.half/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 address v8 last valid addr read data last valid data read write nonseq v8 d[31:0] hwdata last valid data write data read data write last valid data write data read write idle mc9328mx21 product preview, rev. 1.1 84 freescale semiconductor specifications figure 68. wsc = 2, csa = 1, wws = 1, a.word/e.half write nonseq v1 address v1 address v1 + 2 last valid addr last valid data write data (word) write last valid data last valid data write data (1/2 half word) write data (2/2 half word) hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [3:0] r/w lba oe weim_hrdata eb d[31:0] hwdata specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 85 figure 69. wsc = 3, cs a = 1, a.half/e.half hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [4] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 address v8 last valid addr last valid data read last valid data read data write data write nonseq v8 write read data write data last valid data d[31:0] hwdata mc9328mx21 product preview, rev. 1.1 86 freescale semiconductor specifications figure 70. wsc = 2, oea = 2, cnc = 3, bcm = 1, a.half/e.half hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [4] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 read data (v1) address v2 last valid addr last valid data read read seq v2 idle read data (v2) cnc read data (v1) read data (v2) specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 87 figure 71. wsc = 2, oea = 2, wea = 1, wen = 2, cnc = 3, a.half/e.half hclk hselm_weim_cs[4] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [4] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) read nonseq v1 address v1 address v8 last valid addr read data last valid data read d[31:0] hwdata write nonseq v8 idle last valid data write data read data write cnc last valid data write data mc9328mx21 product preview, rev. 1.1 88 freescale semiconductor specifications figure 72. wsc = 3, sync = 1, a.half/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) nonseq nonseq read read idle v1 v5 address v1 last valid addr address v5 read v1 word v2 word v5 word v6 word ecb specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 89 figure 73. wsc = 2, sync = 1, dol = [1/0], a.word/e.word hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb nonseq seq read idle v1 seq seq read read read v2 v3 v4 last valid data v1 word v2 word v3 word v4 word address v1 last valid addr read v1 word v2 word v3 word v4 word mc9328mx21 product preview, rev. 1.1 90 freescale semiconductor specifications figure 74. wsc = 2, sync = 1, dol = [1/0], a.word/e.half hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb address v1 last valid addr read v1 1/2 v1 2/2 v2 1/2 v2 2/2 address v2 nonseq seq read idle v1 read v2 last valid data v1 word v2 word specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 91 figure 75. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 2, a.word/e.half non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last valid addr read v1 1/2 v1 2/2 v2 1/2 v2 2/2 hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb mc9328mx21 product preview, rev. 1.1 92 freescale semiconductor specifications figure 76. wsc = 7, oea = 8, sync = 1, dol = 1, bcd = 1, bcs = 1, a.word/e.half 3.20 dtack mode memory access timing diagrams when enabled, the dtack input signal is used to externally terminate a data transfer. for dtack enabled operations, a bus time-out monitor generat es a bus error when an external bus cycle is not terminated by the dtack input signal after 1024 hclk clock cy cles have elapsed, where hclk is the internal system clock dr iven from the pll module. for a 133 mhz hclk setting, this time equates to 7.7 s. refer to the section 3.5, ?dpll timing specifica tions,? on page 18 for mo re information on how to generate differe nt hclk frequencies. hclk hselm_weim_cs[2] htrans hwrite haddr hready weim_hready bclk a[24:0] cs [2] r/w lba oe data_in weim_hrdata eb (ebc=0) eb (ebc=1) ecb non seq seq read idle v1 read v2 last valid data v1 word v2 word address v1 last valid addr read v1 1/2 v1 2/2 v2 1/2 v2 2/2 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 93 there are two modes of operation for the dtack input signal: rising edge detection or level sensitive detection with a programmab le insensitivity time. dtack is only used during external asynchronous data transfers, thus the sync bit in the chip select control registers must be cleared. during edge detection mode, the eim w ill terminate an external data tran sfer following the detection of the dtack signal?s rising edge, so long as it occurs within the 1024 hclk cycle time. edge detection mode is used for devices that follow the pcmcia standard. note that dtack rising edge detection mode can only be used for cs [5] operations. to configure cs [5] for dtack rising edge detection, the following bits must be programmed in th e chip select 5 control register and eim configuration register: ? wsc bit field set to 0x3f and csa (or csn) set to 1 or greater in the chip select 5 control register ? age bit set in the eim configuration register other bits such as dsz, oea, oen, and so on, may be set according to system and timing requirements of the external device. the requirement of setting csa or csn is required to allow the eim to wait for the rising edge of dtack during back-to-back external transfers, such as during dma transfers or an internal 32-bit access through an ex ternal 16-bit data port. during level sensitive detection, the eim will first hold off sampling the dtack signal for at least 2 hclk cycles, and up to 5 hclk cycles as programm ed by the dct bits in the chip select control register. after this insensitivity time, the eim will sample dtack and if it detects that dtack is logic high, it will continue the data tran sfer at the programmed number of wait states. however, if the eim detects that dtack is logic low, it will wait until dtack goes to logic high to continue the access, so long as this occurs within the 1 024 hclk cycle time. if at anytime du ring an external data transfer dtack goes to logic low, th e eim will wait until dtack returns to logic high to resume the data transfer. level detection is often used for asynchro nous devices such graphic controller chips. level detection may be used with any chip select exce pt cs[4] as it is multiplexed with the dtack signal. to configure a chip select for dtack level sensitive detection, the followin g bits must be programmed in the chip select control register and eim configuration register: ? ew bit set, wsc set to > 1, and csn set to < 3 in the chip se lect control register ? bcd/dct set to desired ?insensitivity time? in th e chip select control register. the ?insensitivity time? is dictated by the extern al device?s timing requirements. ? age bit cleared in the eim configuration register other bits such as dsz, oea, oen, and so on, may be set according to system and timing requirements of the external device. the waveforms in the fo llowing section provide examples of the dtack signal operation. mc9328mx21 product preview, rev. 1.1 94 freescale semiconductor specifications 3.20.1 dtack example waveforms: internal arm ahb word accesses to word-width (32-bit) memory figure 77. dtack edge triggered read access, wsc=3f, oea=8, oen=5, age=1. last valid read hclk bclk addr dtack data_in addr cs [5] rw lba oe eb (ebc=0) eb (ebc=1) v1 v1 data internal signal specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 95 figure 78. dtack level sensitive sequential read accesses, wsc=2, ew=1, dct=1, age=0 (example of dtack staying high) last valid addr read v1 word v1+4 word v1+8 word hclk bclk addr dtack data_in cs [0] rw lba oe eb (ebc=0) eb (ebc=1) address v1 v1+4 v1+8 dct internal signal mc9328mx21 product preview, rev. 1.1 96 freescale semiconductor specifications figure 79. dtack level sensitive sequential wr ite accesses, wsc=2, ew=1, rwa=1, rwn=1, dct=1, age=0 (example of dtack asserting) last valid addr write hclk bclk addr dtack data_out cs [0] rw lba oe eb v1+4 word v1+8 v1 word address v1 v1+4 v1+8 rwa rwn dct internal signal specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 97 3.21 i 2 c module the i 2 c communication protocol consists of seven el ements: start, data source/recipient, data direction, slave acknowledge, data, data acknowledge, and stop. figure 80. definition of bus timing for i 2 c 3.22 cmos sensor interface the csi module consists of a control register to configure the interface timing, a control register for statistic data generation, a stat us register, interface logic, a 32 32 image data receive fifo, and a 16 32 statistic data fifo. 3.22.1 gated clock mode figure 81 shows the timing diagram when the cmos se nsor output data is c onfigured for negative edge and the csi is pr ogrammed to received data on the pos itive edge. figure 82 on page 98 shows the timing diagram when the cmos sensor output data is configured for positive edge and the csi is programmed to received data in negative edge. the parameters for the timing diagrams are listed in table 43 on page 98. the formula for calculating the pixel clock rise and fall time is located in section 3.22.3, ?calculation of pixel cl ock rise/fall time,? on page 101. table 42. i 2 c bus timing parameter table ref no. parameter 1.8v +/- 0.10v 3.0v +/- 0.30v unit minimum maximum minimum maximum scl clock frequency 0 100 0 100 khz 1 hold time (repeated) start condition 114.8 ? 111.1 ? ns 2 data hold time 0 69.7 0 72.3 ns 3 data setup time 3.1 ? 1.76 ? ns 4 high period of the scl clock 69.7 ? 68.3 ? ns 5 low period of the scl clock 336.4 ? 335.1 ? ns 6 setup time for stop condition 110.5 ? 111.1 ? ns sda scl 1 2 3 4 6 5 mc9328mx21 product preview, rev. 1.1 98 freescale semiconductor specifications figure 81. sensor output data on pixel clock falling edge csi latches data on pixel clock rising edge figure 82. sensor output data on pixel clock rising edge csi latches data on pixel clock falling edge table 43. gated clock mode timing parameters number parameter minimum maximum unit 1 csi_vsync to csi_hsync 9 * t hclk ?ns 2 csi_hsync to csi_pixclk 3 ( t p /2) - 3 ns 3 csi_d setup time 1 ? ns 4 csi_d hold time 1 ? ns 1 3 6 5 vsync hsync pixclk data[7:0] valid data valid data valid data 4 7 2 1 3 6 5 vsync hsync pixclk data[7:0] valid data valid data valid data 4 7 2 specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 99 hclk = ahb system clock t hclk = period for hclk t p = period of csi_pixclk the limitation on pixel clock rise time/fall time is not specified. it should be calculated from the hold time and setup time base d on the following assumptions: rising-edge latch data max rise time allowed = (positive duty cycle - hold time) max fall time allowed = (negative duty cycle - setup time) in most of case, duty cycle is 50 / 50, therefore max rise time = (period / 2 - hold time) max fall time = (period / 2 - setup time) for example: given pixel clock period = 10ns, duty cycle = 50 / 50, hol d time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns max fall time allowed = 5 - 1 = 4ns falling-edge latch data max fall time allowed = (neg ative duty cycle - hold time) max rise time allowed = (pos itive duty cycle - setup time) 3.22.2 non-gated clock mode figure 83 shows the timing diagram when the cmos se nsor output data is c onfigured for negative edge and the csi is programmed to received data on the positive edge. figure 84 on page 100 shows the timing diagram when the cmos sensor output data is conf igured for positive edge and the csi is programmed to receive d data in negative edge. the pa rameters for the timing diagrams are listed in table 44 on page 100. the formula for calculating the pixel clock rise and fall time is located in section 3.22.3, ?calculation of pixel clock rise/fall time,? on page 101. 5 csi_pixclk high time t hclk ?ns 6 csi_pixclk low time t hclk ?ns 7 csi_pixclk frequency 0 hclk / 2 mhz table 43. gated clock mode timing parameters number parameter minimum maximum unit mc9328mx21 product preview, rev. 1.1 100 freescale semiconductor specifications figure 83. sensor output data on pixel clock falling edge csi latches data on pixel clock rising edge figure 84. sensor output data on pixel clock rising edge csi latches data on pixel clock falling edge table 44. non-gated clock mode parameters number parameter minimum maximum unit 1 csi_vsync to csi_pixclk 9 * t hclk ?ns 2 csi_d setup time 1 ? ns 3 csi_d hold time 1 ? ns 4 csi_pixclk high time t hclk ?ns 1 vsync pixclk data[7:0] 23 6 4 5 valid data valid data valid data 1 vsync pixclk data[7:0] 2 3 6 5 4 valid data valid data valid data specifications mc9328mx21 product preview, rev. 1.1 freescale semiconductor 101 hclk = ahb system clock t hclk = period of hclk 3.22.3 calculation of pixel clock rise/fall time the limitation on pixel clock rise time/fall time is not spec ified. it should be calculated from the hold time and setup time based on the following assumptions: rising-edge latch data ? max rise time allowed = (pos itive duty cycle - hold time) ? max fall time allowed = (nega tive duty cycle - setup time) in most of case, duty cycle is 50 / 50, therefore: ? max rise time = (period / 2 - hold time) ? max fall time = (period / 2 - setup time) for example: given pixel clock period = 10ns, duty cy cle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns max fall time allowed = 5 - 1 = 4ns falling-edge latch data ? max fall time allowed = (nega tive duty cycle - hold time) ? max rise time allowed = (pos itive duty cycle - setup time) 5 csi_pixclk low time t hclk ?ns 6 csi_pixclk frequency 0 hclk / 2 mhz table 44. non-gated clock mode parameters (continued) number parameter minimum maximum unit mc9328mx21 product preview, rev. 1.1 102 freescale semiconductor pin-out and package information 4 pin-out and package information table 45. i.mx21 pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 a ld9 ld12 ld14 rev hsync oe_ acd sd2_d2 csi_ d0 csi_ pixclk csi_ vsync usbh1_ fs usbh1_ oe usbg_ fs tout sap_ txdat ssi1_ clk ssi2_ rxdat ssi2_txdat ssi3_ fs b ld7 ld5 ld11 ld16 ps con trast sd2_d0 sd2_ cmd csi_ d4 csi_d6 usb_ pwr usbg_ scl usbg_ txdm sap_ fs ssi1_ fs ssi2_ fs ssi3_ txdat i2c_data cspi2_ ss2 c ld1 ld3 ld6 ld10 ld17 vsync sd2_d3 csi_ d1 csi_ mclk csi_ hsync usb_ oc usbh1_ rxdm usbg_ rxdm tin ssi1_ txdat ssi3_ rxdat ssi3_ clk i2c_clk cspi2_ ss1 d ld2 ld0 ld13 cls qvdd qvss sd2_d1 sd2_ clk csi_ d2 csi_d7 usbh1_ txdm usbh1_ rxdp usbg_ on usbg_ rxdp sap_ rxdat ssi1_ rxdat ssi2_ clk cspi2_ss0 cspi2_ sclk e ld8 ld4 ld15 spl_ spr sap_ clk cspi2_ miso cspi1_ss2 cspi2_ mosi f a24_ nfio14 d31 a25_ nfio15 lsclk cspi1_ ss1 cspi1_ miso kp_row0 cspi1_ ss0 g a22_ nfio12 d29 a23_ nfio13 d30 nvdd6 nvss6 csi_d3 usb_ byp usbh_ on usbg_ sda usbg_ txdp kp_ row1 kp_ row3 uart2_cts kp_ row4 h a20 d27 a21_ nfio11 d28 nvdd1 nvss5 csi_d5 cspi1_ sclk cspi1_ rdy usbh1_ txdp usbg_ oe test_ wb4 test_ wb2 test_wb3 pwmo j a19 a18 d25 d26 nvdd1 nvdd5 nvdd4 kp_ row5 kp_ row2 cspi1_ mosi test_ wb0 uart2_ rts kp_col1 kp_col0 test_ wb1 k a16 a17 d23 d24 nvss1 nvss4 qvddx uart1_ rxd tdo qvdd qvss kp_ col3 kp_col5 kp_col4 kp_ col2 l a14_ nfio9 a15_ nfio10 d21 d22 nvss1 nvdd3 qvdd qvss nfio2 nfwp uart1_ txd uart2_ txd uart3_ rts uart3_cts uart3_ txd m d19 a13_ nfio8 d20 d18 nvdd2 nvdd3 nvss3 qvss nfio7 nfrb ext_ 48m uart2_ rxd uart3_ rxd uart1_rts uart1_ cts n a11 a12 d17 d16 lba nvss3 sdcke0 nvss1 nvss1 nvdd1 nvdd1 sd1_ d0 tck sd1_d1 rtck p a9 a10 d15 d14 sd1_ d2 sd1_ cmd tdi tms r a7 a8 d13 d12 sd1_ clk ext_ 266m nvss2 trst t a5 a6 eb3 d10 cs3 cs1 bclk ma11 ras cas nfio5 nfio3 nfwe reset_ in nfce boot1 sd1_d3 clkmode1 clk mode0 u d11 eb1 eb2 oe cs4 d6 ecb d3 ma10 pc_ pwron nfio4 nfio1 nfale nfcle por boot2 boot3 xtal32k v a4 eb0 d9 d8 cs5 d5 cs0 rw d1 jtag_ ctrl sdwe clko nfio6 qvss reset_ out boot0 osc26m_ test vdda extal 32k w a3 a2 d7 a1 cs2 a0 d4 d2 d0 sdclk sdcke1 nfio0 nfre qvdd qvss extal 26m xtal26m qvdd qvss pin-out and package information mc9328mx21 product preview, rev. 1.1 freescale semiconductor 103 4.1 mapbga package dimensions figure 85 illustrates the mapbga 14 mm 14 mm 1.41 mm package, whic h has 0.65 mm spacing between the pads. figure 85. i.mx21 mapbga mechanical drawing mc9328mx21 product preview, rev. 1.1 104 freescale semiconductor pin-out and package information 4.2 mapbga package dimensions figure 86 illustrates the mapbga 17 mm 17 mm 1.45 mm package, whic h has 0.8 mm spacing between the pads. figure 86. i.mx21 mapbga mechanical drawing document revision history mc9328mx21 product preview, rev. 1.1 freescale semiconductor 105 5 document revision history this revision, rev. 1.1, updates the functi onal block diagram, figure 1 on page 2. mc9328mx21/d rev. 1.1 09/29/2004 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: freescale semiconductor hong kong ltd. 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. learn more : for more information about freescale products, please visit www.freescale.com. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo, and arm926ej-s are trademarks of arm limited. arm is a registered trademark of arm ltd. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2004. all rights reserved. |
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