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TLE7269G twin lin transceiver data sheet, rev. 1.2, nov. 2007 automotive power
data sheet 2 rev. 1.2, 2007-11-13 TLE7269G table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 normal operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.1 normal slope mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.2 low slope mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2.3 flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 wake-up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 wake-up bus2 off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 bus wake-up via lin bus 1 and bus 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 local wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.9 mode transition via en pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.10 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.11 txd time out function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.12 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.13 3.3 v and 5 v logic capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.14 bus short to gnd feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.15 lin specifications 1.2, 1.3, 2.0 and 2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 functional device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 esd robustness according to iec61000-4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2 pin compatibility to the sing le lin transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 master termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.4 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.5 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table of contents
pg-dso-14 type package marking TLE7269G pg-dso-14 7269g data sheet 3 rev. 1.2, 2007-11-13 twin lin transceiver TLE7269G 1overview features ? two stand-alone lin transceivers up to 20 kbaud transmission rate ? pin compatible to single lin tr ansceivers (e.g tle7259-2ge/gu) ? compliant to lin specificatio n 1.3, 2.0, 2.1 and sae j2602 ? very high esd robustness, 8 kv according to iec61000-4-2 ? optimized for low electromagnetic emission (eme) ? optimized for high immunity against electromagnetic interference (emi) ? very low current consumption in sleep mode with wake-up functions ? wake-up source detection on wake-up disable function ? very low leakage current on the bus output ? control output for voltage regulator ? digital i/o levels compatible for 3.3 v and 5 v microcontrollers ? bus short to v bat protection and bus short to gnd handling ? over-temperature and under-voltage protection ? flash mode and low-slope mode ? green product (rohs compliant) ? aec compliant description the TLE7269G is a transceiver for the local interconne ct network (lin) with integrated wake-up and protection features. it is designed for in-vehicle networks using data transmission rates from 2.4 kbaud to 20 kbaud. the TLE7269G functions as a bus driver be tween the protocol controller and the physical bus inside the lin network. compliant to all lin standards and with a wide operational supply range the TLE7269G can be used in all automotive applications. two stand-alone lin transceivers are integrated on one monolithic circuit inside TLE7269G. both transceivers offer different operation modes and separate inh outputs to control external circuitry, like voltage regulators. in sleep-mode the TLE7269G draws less than 10 a of quiescent current for both integrated lin transceivers, while both transceivers are still able to wake up off of lin bus traffic or the lo cal wake-up input. the very low leakage current on the bus pins makes the TLE7269G especially suitable for partially supplied networks and supports the low quiescent current requirements of the lin network. based on the infineon smart power technology spt ? , the TLE7269G provides excellent esd robustness together with a very high electromagnetic immunity (emi). the TLE7269G reaches a very low level of electromagnetic emission (eme) within a broad frequenc y range and independent from the battery voltage. the infineon smart power technology spt ? allows bipolar and cmos control circuitry in accordance with dmos power devices to exist on the same monolithi c circuit. the TLE7269G and the infineon spt ? technology are aec qualified and tailored to withstand the harsh conditions of the automotive environment.
TLE7269G block diagram data sheet 4 rev. 1.2, 2007-11-13 2 block diagram figure 1 functional block diagram rxd1 12 bus1 inh1 14 13 v s 3 wk gnd 11 rxd2 bus2 txd2 w2o inh2 v io 8 driver current limit 10 5 r td temp - sensor v s receiver filter wake and bus comparators filter receiver filter mode control output stage 1 driver current limit r bus v s r bus v s txd input timeout txd input timeout txd1 4 r td 1 6 7 v io r w2o en r en 2 9 output stage 2
data sheet 5 rev. 1.2, 2007-11-13 TLE7269G pin configuration 3 pin configuration 3.1 pin assignment figure 2 pin configuration (top view) note: the pin configuration of the TLE7269G is pin co mpatible to the devices tle7259g and tle7259-2ge/gu. in comparison to the tle7259g and the tle 7259-2ge /gu, no pull up resistors on the rxd pins are required for the TLE7269G. details can be found inside the ?pin compatibility to the single lin transceivers? on page 28 . 3.2 pin definitions and functions table 1 pin definitions and functions pin no. symbol function 1 rxd1 receive data output 1; low in dominant state, active low after a wake-up event at bus1 or wk pin 2en enable input; integrated pull-down, device set to normal operation mode when high 3wk wake input; active low, negative edge triggered, internal pull-up 4txd1 transmit data input 1; integrated pull-down, low in dominant state; active low after wake-up via wk pin 5txd2 transmit data input 2; integrated pull-down, low in dominant state 6v io logic voltage supply input; 3.3v or 5v supply for the rxd and txd pins 7 rxd2 receive data output 2; low in dominant state, active low after a wake-up event at bus2 rxd1 1 2 3 4 5 6 78 en wk txd1 inh1 v s bus1 gnd txd2 v io rxd2 bus2 w2o inh2 9 10 11 12 13 14
TLE7269G pin configuration data sheet 6 rev. 1.2, 2007-11-13 8 inh2 inhibit output 2; battery supply related output high ( v s ) in normal and stand-by operation mode can be used to control an external voltage regulator can be used to contro l external bus termination resist or when the device will be used as master node 9w2o wake bus 2 off; switch off wake-up feature on bus 2; active high, integrated pull-down 10 bus 2 bus 2 input / output; lin bus line input/output low in dominant state internal termination and pull-up current source 11 gnd ground 12 bus 1 bus 1 input / output; lin bus line input/output low in dominant state internal termination and pull-up current source 13 v s battery supply input 14 inh1 inhibit output 1; battery supply related output high ( v s ) in normal and stand-by operation mode can be used to control an external voltage regulator can be used to contro l external bus termination resist or when the device will be used as master node table 1 pin definitions and functions (cont?d) pin no. symbol function
data sheet 7 rev. 1.2, 2007-11-13 TLE7269G functional description 4 functional description the lin bus is a single wire, bi-directional bus, used fo r in-vehicle networks. the lin transceiver TLE7269G is the interface between the microcontro ller and the physical lin bus (see figure 17 and figure 18 ). the logical values of the microcontroller are driven to the lin bu s via the txd inputs of the TLE7269G. the transmit data stream on the txd input is converted to a lin bus signal wit h optimized slew rate to minimize the eme level of the lin network. the rxd outputs read back the information fr om the lin bus to the microcontroller. the receiver has an integrated filter network to suppress noise on the li n bus and to increase the emi (electro magnetic immunity) level of the transceiver. two logical states are possible on the lin bus according to the lin sp ecification 2.1 (see figure 3 ): in dominant state, the volta ge on the lin bus is set to the gnd level. in recessive state, the voltage on the lin bus is set to the supply voltage v s . by setting the txd1, txd2 inputs of the TLE7269G to ?low? the transceiver generates a dominant level on the bus1, bus2 lin inte rface pins. the rxd1, rxd2 outputs read back the signal on the lin bus and indicate a dominant signal on the lin bus with a logical ?low? to th e microcontroller. setting the txd1, txd2 pins to ?high? the transceiver TLE7269G sets the bus1, bus2 lin interface pins to recessive level, at the same time the recessive level on the lin bus is indicated by a logical ?high? on the rxd1, rxd2 outputs. every lin network consists of a master node and one or more slave nodes. to configure the TLE7269G for master node applications, a resist or in the range of 1 k ? and a reverse diode must be connected between the lin bus and the power supply v s or between the lin bus and inh pin of the TLE7269G (see figure 17 and figure 18 ). both integrated transceivers can operate independent fr om each other and several operation modes and wake- up functions are implemented. the bus wake-up function of the transceiver 2 can be turned off via the w2o pin. figure 3 lin bus signals t txd1 txd2 v io recessive recessive bus1 bus2 v s recessive dominant recessive t t v io recessive recessive rxd1 rxd2 dominant dominant
TLE7269G functional description data sheet 8 rev. 1.2, 2007-11-13 4.1 operating modes figure 4 operation mode state diagram status txd1? high low stand-by mode low slope mode (transceiver 1 & transceiver 2) sleep mode inh1/inh2 = float en = low rxd1/rxd2 = float status w2o ? inh1, inh2 = high txd1 (see note 1) rxd1, rxd2 (see note 2) note 1: txd1: strong pull down > 1.5 ma after wake-up via pin wk txd1: weak pull down 350 k ? after power-up and wake-up via bus1 or bus2 inh1 = high inh2 = high en = high flash mode (transceiver 1 & transceiver 2) inh1 = high inh2 = high en = high normal operation mode note 2: rxd1: logical ?high? after power-up rxd1: logical ?low? after wake-up via bus1 or bus2 or after wake-up via pin wk rxd2: logical ?low? after wake-up via bus2 start-up power-up en en txd1 en high normal slope mode (transceiver 1 & transceiver 2) inh1 = high inh2 = high en = high txd1 en txd1 en en en en high low bus wake-up feature on bus2 turned off! sleep mode inh1/inh2 = float en = low rxd1/rxd2 = float en low en en wake-up via on pin wk via on pin bus1 or bus2 wake-up via on pin wk via on pin bus1 only ! txd1 en high en low go to normal operation mode go to sleep mode
data sheet 9 rev. 1.2, 2007-11-13 TLE7269G functional description the TLE7269G has 3 major operation modes: ? stand-by mode ? normal operation mode ? sleep mode the normal operation mode contains 3 sub-operation modes, which differentiate by the slew rate control of the lin bus signal (see figure 4 ). sub-operation modes with different slew rates on the bus1,bus2 pins: ? low slope mode, for data transmission rates up to 10.4 kbaud ? normal slope mode, for data transmission rates up to 20 kbaud ? flash mode, for programming of the external microcontroller the TLE7269G contains 2 separate lin transceivers, wh ich are able to operate in two independent lin networks with two different data transmission rates. the operation mo de of the TLE7269G is selected by the en pin and the txd1 pin. selecting the operation mode applies to th e whole device. transceiver1 and transceiver2 are always set to the same operation mode and sub-operation mode (see figure 4 ). 4.2 normal operation mode the TLE7269G enters the normal operation mode after the microcontroller sets en to ?high? (see figure 4 ). in normal operation mode both lin bus receivers and both lin bus transmitters are active. data from the microcontroller is transmitted to the li n bus1 or lin bus2 via the txd1 or txd2 pin, the receiver detects the data stream on the lin bus1 or bus2 and forwards it to the rxd1 or rxd2 output pins. in normal operation mode, the inh1 pin and the inh2 are ?high? (set to v s ) and the bus termination is set to 30 k ? for both integrated transceivers. normal slope mode, low slope mode and the flash mode are normal operation modes and in these sub-modes the behavior of the inh pin and the bu s termination is the same. to set the device into one of these 3 sub-modes the txd1 pin and the en pin are used for the sub-operatio n mode selection. in order to avoid any bus disturbance during a mode change, the output stage s of the TLE7269G are disabled and set to recessive state during the mode change procedure. to release the TLE7269G for data communication on the li n bus1 and lin bus2, the txd1 and txd2 pins need to be set to ?high? for the time t to,rec . table 2 operating modes mode en inh1 inh2 txd1 txd2 rxd1 rxd2 lin bus termination comments sleep low floating low high resistive high impedance no wake-up request detected stand-by low high low high 2) low high 1) 1) to indicate the wake-up sources via the rxd pins the power supply v io has to be present 30 k ? (typical) rxd1 ?low? after local or bus wake-up (bus 1, bus 2) rxd2 ?low? after bus wake-up on bus2. rxd2 ?high? on all other wake-up and power-up events. rxd1 ?high? after power-up txd1 strong pull down after local wake-up (wk pin) 2) txd1 weak pull down after bus wake-up (bus1, bus2) or power-up 2) 2) the txd1 input needs an external termination to indicate a ?high? or a ?low? signal. the external termination could be a pull-up resistor or an acti ve microcontroller output. normal operation high high low high low high 30 k ? (typical) rxd1, rxd2 reflects the signal on the bus1, bus2 txd1,txd2 driven by the microcontroller
TLE7269G functional description data sheet 10 rev. 1.2, 2007-11-13 4.2.1 normal slope mode in normal slope mode data transmission rates up to 20 kb auds are possible. setting the en pin to ?high? starts the transition to normal operation mode. depending on t he signal on the txd1 pin, the TLE7269G changes either into normal slope mode or low slope mode (see figure 5 ). the mode change to normal slope mode is defined by the time t mode and the time t txd,set . the time t mode specifies the delay time between the threshold, where the en pin detects a ?high? input signal, and the actual mode change of TLE7269G into normal slope mode. the time t txd,set defines the setup time in which the txd1 pin has be set to ?high?. after the time t txd,set expires, the logical ?high? signal on the txd1 pin has to be stable to put the part into normal slope mode. in the time window t mode - t txd,set the TLE7269G makes the transition to normal slope mode but remains in stand- by mode until the time t mode expires. finally to release the data communication it is required to set the txd1 and the txd2 pin to ?high? for the time t to,rec. figure 5 timing to enter normal slope mode 4.2.2 low slope mode in low slope mode data transmission rates up to 10.4 kba uds are possible. setting the en pin to ?high? starts the transition to normal operation mode. depending on the signal of the txd1 pin the TLE7269G changes either into normal slope mode or low slope mode (see figure 6 ). the mode change to low slope mode is defined by the time t mode and the time t txd,set . the time t mode specifies the delay time between the threshold, where the en pin de tects a ?high? input signal, and the actual mode change of TLE7269G to low slope mode. the time t txd,set defines the setup time in which the txd1 pin can be set to ?low?. after the time t txd,set expires, the logical ?low? sign al on the txd1 pin has to be stable to put the part into low slope mode. in the time window t mode - t txd,set the TLE7269G makes the transition into low slope mode but remains in stand- by mode until the time t mode expires. finally to release the data communication it is required to set the txd1 and the txd2 pin to ?high? for the time t to,rec. t mode stand-by mode / sleep mode normal slope mode en txd1 t txd,set v en,on mode transition t to,rec data transmission
data sheet 11 rev. 1.2, 2007-11-13 TLE7269G functional description . figure 6 timing to enter low slope mode 4.2.3 flash mode in flash mode it is possible to transmit and receive lin messages on the lin bus. the slew rate control mechanism of the lin bus signal is disabled. this allows higher data transmission rates, disregarding the emc limitations of the lin network. the flash mode is inte nded to be used during the ecu production for programming the microcontroller via th e lin bus interface. the TLE7269G can be set to flash mode either from normal slope mode or from low slope mode (see figure 4 ). flash mode is entered by setting t he en pin to ?low? for the time t fl1 and generating a falling and a rising edge at the txd1 pin with the timing t fl2 , t fl3 and t fl4 (see figure 7 ). leaving the flash mode by the same sequence, sets the TLE7269G back to its previous state, be that either normal slope mode or low slope mode. finally to release the data transmission it is required to set the tx d1 pin and the txd2 pin to ?high? for the time t to,rec . the TLE7269G can be set from flash mode directly to sl eep mode by switching the en pin to ?low?. setting the pin en to ?high? again, the dev ice will return to flash mode. figure 7 timing to enter and exit flash mode t mode stand-by mode / sleep mode low slope mode en txd1 t txd,set v en,on mode transition t to,rec data transmission normal slope mode low slope mode txd1 en t fl3 data transmission t fl1 flash mode t fl2 t fl4 t fl1 data transm. normal slope mode low slope mode t fl3 t fl2 t fl4 t torec t torec
TLE7269G functional description data sheet 12 rev. 1.2, 2007-11-13 4.3 stand-by mode the stand-by mode is entered automatically after: ? a power-up event on the supply v s . ? a bus wake-up event on pin bus1 or pin bus2. ? a local wake-up event on the pin wk. ? a power on reset caused by power supply v s or by the power supply v io ? in stand-by mode the wake-up sources are monitored by the txd1, rxd1 and rxd2 pins. in stand-by mode no communication on the lin bus is poss ible. the output stages are disabled and the lin bus termination remains activated on both integrated transce ivers. only the rxd1, rxd2 and the txd1 pin are used to indicate the wa ke-up source. the txd2 pin remains inactive. the rxd1 pin remains ?low? after a local wake- up event on the pin wk and a bus wake-up event on eith er the bus 1 or the bus 2. the rxd2 pin remains ?low? only after a bus wake-up event on the bus 2. a power-up event is indicated by a logical ?high? on the rxd1 pin. the signal on the txd1 pin indicates the wake-up source , a weak pull-down signals a bus wake-up event on the bus 1 and bus 2 and a strong pull-down signals a local wake-up event caused by the wk pin (see table 2 and table 3 ). in order to detect a wake-up event via the txd1 pi n, the external microcontrolle r output needs to provide a logical ?high? signal. the wake-up flags indicating the wake-up source on the pins txd1, rxd1 and rxd2 are reset by changing the operation mode to normal operation mode. the signal on the en pin remains ?low? due to an internal pull-down resistor. setting th e en pin to ?high?, by the microcontroller returns the TLE7269G to normal operation mode. in stand-by mode the inh1 and inh2 outputs are switching to v s . the inh outputs can be used to control external device like a voltage regulator. table 3 logic table for wake up monitoring inputs outputs power up wk bus1 bus2 rxd1 1) 1) to indicate the wake-up or power-up event on the rxd pin, the supply v io has to be present rxd2 1) txd1 2) 2) the txd1 input needs an external termination to indicate a ?high? or a ?low? signal. the external termination could be a pull-up resistor or an acti ve microcontroller output. remarks yes 1 1 1 1 1 1 no wake-up, power-up event no wake- up 3) 3) a local wake-up event is considered after a low signal on the pin wk (see chapter 4.8 ). 1 1 0 1 0 wake via wake pin no 1 wake- up 4) 1 0 1 1 wake via bus1 no 1 1 wake- up 4) 4) a bus wake-up event is considered after t he low to high transition on the bus (see chapter 4.7 ). note: in the case of a sequence of wa ke-up events only the first wake-up event will be monitore d on txd1, rxd1 and rxd2. subsequent wake-up events are ignored. 0 0 1 wake via bus2
data sheet 13 rev. 1.2, 2007-11-13 TLE7269G functional description 4.4 sleep mode in order to reduce the current consumption the tle72 69g offers a sleep mode. in sleep mode the quiescent current on v s and the leakage current on the pins bus1 and bus2 are cut back to a minimum. to switch the TLE7269G from normal operation mode to sleep mode, the en pin has to be set to ?low?. conversely a logical ?high? on the en pin sets the de vice directly back to normal operation mode (see figure 4 ). while the TLE7269G is in sleep mode the following functions are available: ? the output stages are disabled and the internal bus terminations are switched off (high impedance on the pins bus1 and bus2). internal current sources on the bus pins ensure that the levels on the pins bus1 and bus2 remain recessive and protect the lin netwo rk against accidental bus wake-up events. ? the receiver stages are turned off. ? rxd1, rxd2 output pins are inactive and ?high resistiv e?. the txd1, txd2 pins are disabled. the logical state on the txd1 pin and the txd2 pin is ?low? due to the internal pull-down resistors. ? the inh1 and inh2 outputs are switched off and floating. ? the bus wake-up comparator is active and turns the tl e7269g to stand-by mode in case of a bus wake-up event. ? the wk pin is active and turns the TLE7269G to stand-by mode in case of a local wake-up. ? the en pin remains active, switching the en pin to ?high? changes the operation mode to normal operation mode. 4.5 wake-up events a wake-up event changes the operation mode of the TLE7269G from sleep mode to stand-by mode. both integrated transceivers are changing the mode. there are 4 different ways to wake-up the TLE7269G from sleep mode. ? bus or also called remote wake-up via a dominant signal on the pin bus1. ? bus or also called remote wake-up via a dominant signal on the pin bus2. ? local wake-up via a minimum dominant time ( t wk ) on the wk pin. ? mode change from sleep mode to normal operation mode, by setting en pin to logical ?high?. 4.6 wake-up bus2 off a wake-up event on the lin bus1 or on the bus2 wakes up the TLE7269G and sets it to stand-by mode. in applications where a wake-up via bus1 is required but a wake-up via bus2 is not wanted, the bus wake-up event on the bus2 can be disabled. this is done by setting th e w2o pin to ?high?. during the mode change from normal operation mode to sleep mode the TLE7269G checks for the status on the pin w2o. in case the w2o pin is ?high?, the wake-up fe ature for the transceiver 2 will be disabled. the TLE7269G can still be wake off by a bus wake-up event on lin bus1 or by a local wake-up event on the pin wk. a bus wake-up event on the bus 2 won?t be recognized and the device remains in sleep mode (see figure 4 ). in case the wake-up bus2 off feature is not used, the w2o pin can be left open, due to the internal pull-down resistor, a not connected w2o pin is set to logical ?low?. the function of the en pin remain unchanged.
TLE7269G functional description data sheet 14 rev. 1.2, 2007-11-13 4.7 bus wake-up via lin bus 1 and bus 2 figure 8 bus wake-up behavior the bus wake-up event, often called remote wake-up, ch anges the operation mode from sleep mode to stand- by mode. the TLE7269G wakes-up via a bus wake-up event on either the pin bus1 or bus2. the bus wake- up behavior is identical on both pins. a falling edge on the lin bus, followed by a dominant bus signal t > t wk,bus results in a bus wake-up event. the mode change to stand-by mode becomes active with the following rising edge on the lin bus. the TLE7269G remains in sleep mode until it detects a change from dominant to recessive on the lin bus (see figure 8 ). in stand-by mode the txd1 pin indicates the source of the wake-up event, the txd2 pin remains inactive. a weak pull-down on the pin txd1 indicates a bus wake-up event (see figure 4 or table 2 ). the rxd1 pin signals if a wake-up event occurred or the power-up event. a ?low? si gnal on the rxd1 pin reports a local or bus wake-up event, a logical ?high? signal on rx d1 indicates a power-up event. a ?low? signal on the rxd2 pin indicates a wake-up event on the pin bus2. v bus1 &2 v bus,dom v bus,wk lin bus1 or bus2 signal sleep mode stand-by mode inh1/ inh2 t wk,bus
data sheet 15 rev. 1.2, 2007-11-13 TLE7269G functional description 4.8 local wake-up figure 9 local wake-up behavior beside the remote wake-up, a wake-up of the TLE7269G via the wk pin is possible. this type of wake-up event is called ?local wake up?. a falling edge on the wk pin follo wed by a ?low? signal for t > t wk results in a local wake-up (see figure 9 ) and changes the operation mode to stand-by mode. in stand-by mode the txd1 pin indicates the source of the wake-up event, the txd2 pin remains inactive. a strong pull-down on the pin txd1 indicates a bus wake-up event (see figure 4 ). the rxd1 pin signals if a wake- up event or the power-up event occurred. a ?low? signal on the rxd1 pin reports a local or bus wake-up event, a logical ?high? signal on rxd1 indicates a power-up event. a ?low? signal on the rxd2 pin indicates a wake-up event on the pin bus2. 4.9 mode transition via en pin figure 10 mode transition via en pin it is also possible to change from sleep mode to normal operation mode by setting the en pin to logical ?high?.this feature is useful if the external microcontroller is continuously powered and not connected to the inh1 pin or the inh2 pin. the en pin has an integrated pull-do wn resistor to ensure the device remains in sleep or stand-by mode even if the voltage on the en pin is floa ting. the en pin has an integr ated hysteresis to avoid the toggling of the operation modes during th e transition of the en signal (see figure 10 ). v wk v wk,l wk signal sleep mode stand-by mode inh1/ inh2 t wk v en en signal v en,off sleep mode / stand-by mode t mode v en,on en hysteresis sleep mode normal operation mode t mode
TLE7269G functional description data sheet 16 rev. 1.2, 2007-11-13 a transition from logical ?high? to logical ?low? on the en pin changes th e operation mode from normal operation mode to sleep mode. if the TLE7269G is already in slee p mode, changing the en from ?low? to ?high? results into a mode change from sleep mode to normal operation mo de. if the device is in stand-by mode a change from ?low? to ?high? on the en pin changes the mode to normal operation mode (see figure 4 ). 4.10 power-on reset figure 11 power-on reset and under-voltage situation a dropping power supply v s or a dropping microcontroller supply v io on a local ecu can effect the communication of the whole lin network. to avoi d any blocking of the lin network by a local ecu the TLE7269G has an integrated power-on reset at the supply v s and an under-voltage detection at the supply v s and the supply v io . in case the supply voltage v s is dropping below the power-on re set level v s < v s,uv,pon , the TLE7269G changes the operation mode to stand-by mode. in stand-by mode th e output stage of the tle7 269g is disabled and no communication to the lin bus is possible. the internal bu s termination remains active as well as the inh pins (see figure 11 and figure 4 ). supply voltage vs power on reset level v s,uv,pon power on reset normal operation mode reset and communication blocked stand-by mode blanking time t blank,uv supply voltage vs power on reset level v s,uv,pon normal operation mode communication blocked blanking time t blank,uv undervoltage level v s,uv,blk normal operation mode under voltage detection v s supply voltage v io normal operation mode communication blocked blanking time t blank,uv undervoltage level v io,uv normal operation mode under voltage detection v io
data sheet 17 rev. 1.2, 2007-11-13 TLE7269G functional description in stand-by mode the rxd1 pin signals the low power s upply condition with a ?high? signal. a logical ?high? on the en pin changes the operation mo de back to normal operation mode. in case the supply voltage v s is dropping below the specified operation range (see table 5 ), the TLE7269G disables the output and receiver st ages. this feature secures the communication on the lin bus. if the power supply v s reaches a higher level as the under-voltage level v s > v s,uv,blk the TLE7269G continues with normal operation. a mode change only applies if the power supply v s drops below the power on reset level ( v s < v s,uv,pon ). if the power supply v io drops below the under-voltage level v io > v io,uv the output and receiver stages will be disabled as well. when v io reaches a higher level as the under-voltage v io > v io,uv level the TLE7269G continues with normal operation and data transmission. 4.11 txd time out function if the txd1 or txd2 signal is dominant for a time t > t timeout the txd time-out function deactivates the transmission of the lin signal to the bus and disabl es both, the output stage 1 and the output stage 2. this is realized to prevent the bus from being blocked by a permanent ?low? signal on the txd1 or txd2 pin, caused by an error on the external microcontroller (see figure 12 ). the transmission is released again, after a risi ng edge at txd1 or txd2 has been detected. figure 12 txd time-out function txd1 t torec bus1 txd2 bus2 t timeout normal communication normal communication txd time-out due to microcontroller error release after txd time-out recovery of the microcontroller error t torec t timeout normal communication normal communication txd time-out due to microcontroller error release after txd time-out recovery of the microcontroller error t t t t
TLE7269G functional description data sheet 18 rev. 1.2, 2007-11-13 4.12 over temperature protection the TLE7269G has one integrated over temperature sens or to protect the device aga inst thermal overstress on the output stage 1 and output stage 2. in case of an over temperature even t, the temperature sensor will disable both output stages (see figure 1 ). an over temperature event will not cause any mode change nor will it be signaled by either the rxd pins or t he txd pins. when the junction temperat ure falls below the thermal shut down level t j < t jsd , the output stages are re-enabled and data communication can start again on bus1 and bus2. a 10c hysteresis avoids toggling during the temperature shut down. 4.13 3.3 v and 5 v logic capability the TLE7269G can be used for 3.3 v and 5 v microcontrollers. the inputs and the outputs are capable to operate with both voltage levels. the logic level is defined by suppling 3.3v or 5v to the v io . the inputs (txd1, txd2) take the reference voltage from the v io pin. the rxd1 output and rxd2 output ar e push-pull outputs, they work on the voltage given by v io pin. no external pull-up resistors are required. the pin en works without the voltage on the microcontroller supply v io . the TLE7269G can be set from sleep mode to normal operation mode by se tting en to ?high?, without supplying v io . 4.14 bus short to gnd feature the TLE7269G has a feature implemented to protect the batt ery from running out of charge in the case of bus short to gnd failure. in this failure case a normal master termination, a 1 k ? resistor and diode between the lin bus and the power supply v s , would cause a constantly drawn current even in sl eep mode. the resulting resistance of this short to gnd is in the range 1 k ? . to avoid this current during a generator off state, like in a parked car, the TLE7269G has a bus short to gnd feature implemented, which is activated in sleep mode. this feature is only applicable, if the master termination of bus1 is connected to inh1 pin and the master termination of bus2 is connected to inh2 pin, instead of being connected to the power supply v s (see figure 17 and figure 18 ). internally, the 30 k ? path is also switched off from the power supply v s (see figure 1 ). a separate master termination switch is implemented at pins bus1 and bus2, to avoid a voltage drop on the recessive level of lin bus, in case of a domin ant level or a short to ground on at the lin bus. 4.15 lin specifications 1. 2, 1.3, 2.0 and 2.1 the device fulfills the physical layer spec ification of lin 1.2, 1.3, 2.0 and 2.1. the differences between lin specificati on 1.2 and 1.3 is mainly the physical layer specification. the reason was to improve the compatib ility between the nodes. the lin specification 2.0 is a super set of the 1.3 versio n. the 2.0 version offers new features. however, it is possible to use the lin 1.3 slave node in a 2.0 node cluster, as long as the new features are not used. vice versa it is possible to use a lin 2.0 node in the 1.3 cluster without using the new features. in terms of the physical layer the lin 2.1 specification doesn?t include any changes and is fully compliant to the lin specification 2.0. lin 2.1 is the latest version of the lin specification, released in december 2006.
data sheet 19 rev. 1.2, 2007-11-13 TLE7269G general product characteristics 5 general product characteristics 5.1 absolute maximum ratings note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. table 4 absolute maximum ratings 1) all voltages with respect to ground; positive current flowing into pin; (unless otherwise specified) 1) not subject to production test, specified by design pos. parameter symbol limit values unit remarks min. max. voltages 5.1.1 battery supply voltage v s -0.3 40 v lin spec 2.1 param. 10 5.1.2 logic supply voltage v io -0.3 5.5 v ? 5.1.3 bus and wk input voltage versus gnd versus v s v bus,g v bus,vs -40 -40 40 40 v v ? 5.1.4 logic voltages at en, w2o, txd1, txd2, rxd1, rxd2 v logic -0.3 5.5 v ? 5.1.5 inh1, inh2 voltage versus gnd versus v s v inh,g v inh,vs -0.3 -40 40 0.3 v v ? currents 5.1.6 output current at inh1, inh2 i inh -150 80 ma 2) 2) output current is internally limited to -150 ma temperatures 5.1.7 junction temperature t j -40 150 c? 5.1.8 storage temperature t s -55 150 c? esd resistivity 5.1.9 electrostatic discharge voltage at v s , bus1, bus2, wk versus gnd v esd -6 6 kv human body model (100pf via 1.5 k ? ) 3) 3) esd susceptibility hbm acco rding to eia / jesd 22-a 114 5.1.10 electrostatic discharge voltage w2o versus v s v esd -1 1 kv human body model (100pf via 1.5 k ?) 3) 5.1.11 electrostatic discharge voltage all pins except w2o versus v s v esd -2 2 kv human body model (100pf via 1.5 k ?) 3)
TLE7269G general product characteristics data sheet 20 rev. 1.2, 2007-11-13 5.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 5.3 thermal characteristics table 5 operating range pos. parameter symbol lim it values unit remarks min. typ. max. supply voltages 5.2.1 supply voltage range for normal operation v s(nor) 7 ? 27 v lin spec 2.1 param. 10 5.2.2 extended supply voltage range for operation v s(ext) 5 ? 40 v parameter deviations possible 5.2.3 supply voltage v io v io 3?5.5v? thermal parameters 5.2.4 junction temperature t j -40 ? 150 c 1) 1) not subject to production test, specified by design table 6 thermal characteristics 1) 1) not subject to production test, specified by design pos. parameter symbol limit values unit remarks min. typ. max. thermal resistance 5.3.5 junction to soldering point r thjsp ? ? 25 k/w measured to pin 11 5.3.6 junction to ambient r thja ?130?k/w 2) 2) jesd 51-2, 51-3, fra4 76,2 mm x 114,3 mm x 1,5 mm, 70 m cu, minimal footprint, ta = 27c thermal shutdown junction temperature 5.3.7 thermal shutdown temp. t jsd 150 170 190 c? 5.3.8 thermal shutdown hyst. ? t ?10?k?
data sheet 21 rev. 1.2, 2007-11-13 TLE7269G electrical characteristics 6 electrical characteristics 6.1 functional device characteristics table 7 electrical characteristics 7.0 v < v s < 27 v; r l = 500 ? ; v io = 5v; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max. current consumption 6.1.1 current consumption at v s (both channels recessive) i s,rec 0.5 1.6 3.0 ma recessive state, without r l ; v s = 13.5 v v txd = v io 6.1.2 current consumption normal mode at v io i vio,norm ? 10 50 a normal operation mode. v io =5 v 6.1.3 current consumption at v s (both channels dominant) i s,dom ? 3 5.0 ma dominant state, without r l ; v s = 13.5 v; v txd = 0 v 6.1.4 current consumption in sleep mode at v io i vio,sleep ? 1 10 a sleep mode, v io =5 v 6.1.5 current consumption in sleep mode i s,sleep ?712 a sleep mode, v s = 18 v; v bus = v wk = v s ; 6.1.6 current consumption in sleep mode i s,sleep,typ ? 5 10 a sleep mode, t j < 85 c; v s = 13.5 v; v wk = v s = v bus ; under voltage detection 6.1.7 blocking under voltage detection at v s ( v s on the falling edge) v s,uv,blk 3.5 ? 5 v communication blocked no reset (see figure 11 ) 6.1.8 power on under voltage detection at v s v s,uv,pon ? ? 3.5 v device reset to stand-by- mode 1) (see figure 11 ) 6.1.9 under voltage detection at v io v io,uv 1.5 2.5 3 v communication blocked no reset (see figure 11 ) 6.1.10 under voltage blanking time t blankuv ?5?s 1) receiver outputs: rxd1, rxd2 6.1.11 high level output current i rd,h ?10 -4 -2 ma v rd = 0.8 v io 6.1.12 low level output current i rd,l 2410ma v rd = 0.2 v io
TLE7269G electrical characteristics data sheet 22 rev. 1.2, 2007-11-13 transmission inputs: txd1, txd2 6.1.13 high level input voltage range v td,h 0.7 v io ? v io v recessive state 6.1.14 input hysteresis v td,hys ?0.12 v io ?v 1) 6.1.15 low level input voltage range v td,l 0 ? 0.3 v io v dominant state 6.1.16 pull-down resistance r td 100 350 800 k ? v txd = v io 6.1.17 low level leakage current i td ?010 a v en = 0 v; v txd = 0 v 6.1.18 dominant current standby mode after wake-up i td,l 1.5 3 10 ma v txd = 0.9 v; wk = 0 v; v s = 13.5 v. only valid for txd 1 6.1.19 input capacitance ci ? 5 ? pf 1) w2o input 6.1.20 high level input voltage range v w2o,h 0.7 v io ? v io v? 6.1.21 low level input voltage range v w2o,l 0 ? 0.3 v io v? 6.1.22 input hysteresis v w2o,hys ?0.12 v io ?v 1) 6.1.23 pull-down resistance r w2o 15 35 60 k ? ? 6.1.24 input capacitance ci w2o ?5?pf 1) enable input: en 6.1.25 high level input voltage range v en,on 2? v io v normal operation mode 6.1.26 low level input voltage range v en,off 0 ? 0.8 v sleep mode or stand-by mode 6.1.27 input hysteresis v en,hys 300 mv 1) 6.1.28 pull-down resistance r en 15 30 60 k ? ? 6.1.29 input capacitance ci en ?5?pf 1) inhibit, master terminati on outputs: inh1, inh2 6.1.30 inhibit r on resistance r inh,on 22 36 50 ? i inh = -15 ma 6.1.31 maximum inh output current i inh -150 ? -40 ma v inh = 0 v 6.1.32 leakage current i inh,lk -5.0 ? 5.0 a sleep mode; v inh = 0 v table 7 electrical characteristics (cont?d) 7.0 v < v s < 27 v; r l = 500 ? ; v io = 5v; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max.
data sheet 23 rev. 1.2, 2007-11-13 TLE7269G electrical characteristics wake input: wk 6.1.33 high level input voltage v wk,h v s - 1 v ? v s + 3v v v s = 13.5 v; 6.1.34 low level input voltage v wk,l -0.3 ? v s - 4 v v v s = 13.5 v; 6.1.35 pull-up current i wk,pu -60 -30 -3 a v wk = 0v 6.1.36 high level leakage current i wk,h,leak -5 ? 5 a v s = 0 v; v wk = 40 v 6.1.37 dominant time for wake-up t wk 30 ? 150 s? 6.1.38 input capacitance ci wk ?15?pf 1) bus receiver: bus1, bus2 6.1.39 receiver threshold voltage, recessive to dominant edge v th_dom 0.4 v s 0.48 v s ?v? 6.1.40 receiver dominant state v busdom v s - 40 v ?0.4 v s v lin spec 2.1 (par. 17) 2) 6.1.41 receiver threshold voltage, dominant to recessive edge v th_rec ?0.52 v s 0.6 v s v? 6.1.42 receiver recessive state v busrec 0.6 v s ?1.15 x v s v lin spec 2.1 (par. 18) 3) 6.1.43 receiver center voltage v bus_cnt 0.475 v s 0.5 v s 0.525 v s v lin spec 2.1 (par. 19) 4) 6.1.44 receiver hysteresis v hys 0.02 v s 0.04 v s 0.175 v s v lin spec 2.1 (par. 20) 5) 6.1.45 wake-up threshold voltage v bus,wk 0.40 v s 0.5 v s 0.6 v s v? 6.1.46 dominant time for bus wake- up t wk,bus 30 ? 150 s? bus transmitter: bus1, bus2 6.1.47 bus recessive output voltage v bus,ro 0.8 v s ? v s v v txd = high level 6.1.48 bus dominant output voltage maximum load v bus,do ? ? ? ? ? ? 1.2 0.2 x v s 2.0 v v v v txd = 0 v; r l = 500 ? 6,0 v s 7,3 v; 7,3 < v s 10 v; 10 < v s 18 v; (see figure 14 ) 6.1.49 bus short circuit current i bus_lim 40 100 150 ma v bus = 13.5 v; lin spec 2.1 (par. 12); 6.1.50 leakage current i bus_no_gnd -1000 -450 ? a v s = 0 v; v bus = -12 v; lin spec 2.1 (par. 15) 6.1.51 leakage current i bus_no_bat ?28 a v s = 0 v; v bus = 18 v; lin spec 2.1 (par. 16) table 7 electrical characteristics (cont?d) 7.0 v < v s < 27 v; r l = 500 ? ; v io = 5v; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max.
TLE7269G electrical characteristics data sheet 24 rev. 1.2, 2007-11-13 6.1.52 leakage current i bus_pas_dom -1 ? ? ma v s = 18 v; v bus = 0 v; lin spec 2.1 (par. 13) 6.1.53 leakage current i bus_pas_rec ??20 a v s = 8 v; v bus = 18 v; lin spec 2.1 (par. 14) 6.1.54 bus pull-up resistance r slave 20 30 47 k ? normal mode lin spec 2.1 (par. 26) 6.1.55 lin output current i bus -60 -30 -5 a sleep mode v s = 13.5 v; v en = 0 v 6.1.56 input capacitance ci bus ?15?pf 1) dynamic transceiver characteristics: bus1, bus2 6.1.57 propagation delay lin bus to rxd dominant to rxd low recessive to rxd high t rx_pdf t rx_pdr ? ? 1 1 6 6 s s lin spec 2.1 (par. 31) v io = 5 v; c rxd = 20 pf 6.1.58 receiver delay symmetry t rx_sym -2 ? 2 s lin spec 2.1 (par. 32) t rx_sym = t rx_pdf - t rx_pdr ; v io = 5 v; c rxd = 20 pf 6.1.59 delay time for mode change t mode ??120 s 1) see figure 5 , figure 6 6.1.60 txd1 setup time for mode selection t txd,set ??50 s 1) see figure 5 , figure 6 6.1.61 txd dominant time out t timeout 61220ms v txd = 0 v 6.1.62 txd dominant time out recovery time t torec ??15 s 1) 6.1.63 en toggling to enter the flash mode t fl1 25 35 50 s 1) see figure 7 6.1.64 txd1 time for flash activation t fl2 t fl3 t fl4 5 10 10 ? ? ? ? ? ? s 1) see figure 7 table 7 electrical characteristics (cont?d) 7.0 v < v s < 27 v; r l = 500 ? ; v io = 5v; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max.
data sheet 25 rev. 1.2, 2007-11-13 TLE7269G electrical characteristics 6.1.65 duty cycle d1 (for worst case at 20 kbit/s) d1 0.396 ? ? ? duty cycle 1 6) th rec (max) = 0.744 v s; th dom (max) =0.581 v s ; v s = 7.0 ? 18 v; t bit = 50 s; d1 = t bus_rec(min) /2 t bit ; lin spec 2.1 (par. 27) 6.1.66 duty cycle d2 (for worst case at 20 kbit/s) d2 ? ? 0.581 ? duty cycle 2 6) th rec (min)= 0.422 v s ; th dom (min)= 0.284 v s v s = 7.6 ? 18 v; t bit = 50 s; d2 = t bus_rec(max) /2 t bit ; lin spec 2.1 (par. 28) 6.1.67 duty cycle d3 (for worst case at 10.4 kbit/s) low slope mode d3 0.417 ? ? ? duty cycle 3 6) th rec (max) = 0.778 v s; th dom (max) =0.616 v s v s = 7.0 ? 18 v; t bit = 96 s; d3 = t bus_rec(min) /2 t bit ; lin spec 2.1 (par. 29) 6.1.68 duty cycle d4 (for worst case at 10.4 kbit/s) low slope mode d4 ? ? 0.590 ? duty cycle 4 6) th rec (min) = 0.389 v s; th dom (min) =0.251 v s v s = 7.6 ? 18 v; t bit = 96 s; d4 = t bus_rec(max) /2 t bit ; lin spec 2.1 (par. 30) 1) not subject to production test, specified by design 2) minimum limit specified by design 3) maximum limit specified by design 4) v bus_cnt =(v th_dom -v th rec )/2; 5) v hys =v busrec - v busdom 6) bus load concerning lin spec 2.1: load 1 = 1 nf / 1 k ? = c bus / r bus load 2 = 6,8 nf / 660 ? = c bus / r bus load 3 = 10 nf / 500 ? = c bus / r bus table 7 electrical characteristics (cont?d) 7.0 v < v s < 27 v; r l = 500 ? ; v io = 5v; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max.
TLE7269G electrical characteristics data sheet 26 rev. 1.2, 2007-11-13 6.2 diagrams figure 13 simplified test circuit for dynamic characteristics figure 14 simplified test circuit for static characteristics bus1 en rxd1 100 nf v s c bus inh1 txd1 wk gnd bus2 w2o rxd2 c bus txd2 inh2 vio r bus r bus c rxd c rxd bus1 en rxd1 100 nf v s c bus inh1 txd1 wk gnd bus2 w2o rxd2 c bus txd2 inh2 vio r bus r bus c rxd c rxd
data sheet 27 rev. 1.2, 2007-11-13 TLE7269G electrical characteristics figure 15 timing diagram for dynamic characteristics t bit t bit t bit t bus_dom(max) t bus_rec(min) thresholds of receiving node 1 thresholds of receiving node 2 th rec(max) th dom(max) th rec(min) th dom(min) t bus_dom(min) t bus_rec(max) t rx_pdf(1) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) v sup (transceiver supply of transmitting node) txd (input to transmitting node) rxd (output of receiving node 1) rxd (output of receiving node 2) duty cycle 1 = t bus_rec(min) / (2 x t bit ) duty cycle 2 = t bus_rec(max) / (2 x t bit )
TLE7269G application information data sheet 28 rev. 1.2, 2007-11-13 7 application information 7.1 esd robustness acco rding to iec61000-4-2 test for esd robustness according to iec61000-4-2 ?gun test? (150 pf, 330 ? ) have been performed. the results and test conditions are available in a separate test report. 7.2 pin compatibility to the single lin transceivers the twin lin transceiver TLE7269G is pin and function compatible to the single lin transceivers like the tle7259g, the tle7259-2ge and its derivative the tle7259-2gu. the TLE7269G has a pin for the v io supply. this supply pin is usually connected to the power supply of the external microcontroller. the tle7259g and the tle7259-2ge/u don?t have a v io pin. in order to provide the same functions on the tle7259g and tle7259- 2ge/gu, these two lin transceiver need an external pull-up resistor between the rxd pin and the microcontroller supply. figure 16 pin configuration TLE7269G and tle7259g, tle7259-2ge/gu table 8 esd robustness according to iec61000-4-2 performed test result unit remarks electrostatic discharge voltage at pin v s , bus1 and bus2 versus gnd +9 kv 1) positive pulse 1) esd susceptibility ?esd gun? according lin emc 1.3 test spec ification, section 4.3. (iec 61000-4-2) -tested by external test house (ibee zwickau, emc testreport nr. 05-06-06). electrostatic discharge voltage at pin v s , bus1 and bus2 versus gnd -9 kv 1) negative pulse electrostatic discharge voltage at pin wk versus gnd +8 kv 1) positive pulse electrostatic discharge voltage at pin wk versus gnd -8 kv 1) negative pulse rxd1 1 2 3 4 5 6 78 en wk txd1 inh1 v s bus1 gnd txd2 v io rxd2 bus2 w2o inh2 9 10 11 12 13 14 rxd 1 2 3 45 6 7 8 en wk txd inh v s bus gnd tle7259g tle7259-2ge tle7259-2gu and other single lin transceivers TLE7269G
data sheet 29 rev. 1.2, 2007-11-13 TLE7269G application information 7.3 master termination to achieve the required timings for the dominant to recess ive transition of the bus signal an additional external termination resistor of 1 k ? is mandatory. it is recommended to place this resistor at the master node. to avoid reverse currents from the bus line into the battery supply lin e it is recommended to place a diode in series with the external pull-up. for small systems (low bus capacitance ) the emc performance of the system is supported by an additional capacitor of at least 1 nf at the master node (see figure 17 and figure 18 ).the values for the master termination resistor and the bus capa citance influence the perf ormance of the lin network. they depend on the number of nodes inside the lin network and on the par asitic cable capacitances of the lin bus wiring. 7.4 external capacitors a capacitor of 10 f at the supply voltage input v s buffers the input voltage. in combination with the required reverse polarity diode this prevents the device from detecting a power down conditions in case of negative transients on the supply line (see figure 17 and figure 18 ). the 100 nf capacitor close to the v s pin and a 33 nf capacitor close to the v io pin of the TLE7269G are required to get the best emc performance.
TLE7269G application information data sheet 30 rev. 1.2, 2007-11-13 7.5 application example figure 17 simplified application circuit with bus short to gnd feature applied txd2 gnd TLE7269G bus2 micro controller e.g xc22xx gnd wk inh1 v s v q gnd inh v i rxd2 w2o v bat lin bus1 master node for lin bus1 & lin bus2 txd1 rxd1 en bus1 v io inh2 33 nf 100 nf 10 f e.g. tle4678 100 nf 22 f 100 nf 1 nf 1 nf 1 k ? 5 v or 3.3v ecu1 1 k ? txd2 gnd TLE7269G bus2 micro controller e.g xc22xx gnd wk inh1 v s v q gnd inh v i rxd2 w2o slave node for lin bus1 & lin bus2 txd1 rxd1 en bus1 v io inh2 33 nf 100 nf 10 f e.g. tle4678 100 nf 22 f 100 nf 220 pf 5 v or 3.3v ecu x 220 pf n.c. lin bus2
data sheet 31 rev. 1.2, 2007-11-13 TLE7269G application information figure 18 simplified application circui t without bus short to gnd feature n.c. txd2 gnd TLE7269G bus2 micro controller e.g xc22xx gnd wk inh1 v s v q gnd inh v i rxd2 w2o v bat lin bus1 master node for lin bus1 & lin bus2 txd1 rxd1 en bus1 v io inh2 33 nf 100 nf 10 f e.g. tle4678 100 nf 22 f 100 nf 1 nf 1 nf 1 k ? 5 v or 3.3v ecu1 1 k ? txd2 gnd TLE7269G bus2 micro controller e.g xc22xx gnd wk inh1 v s v q gnd inh v i rxd2 w2o slave node for lin bus1 & lin bus2 txd1 rxd1 en bus1 v io inh2 33 nf 100 nf 10 f e.g. tle4678 100 nf 22 f 100 nf 220 pf 5 v or 3.3v ecu x 220 pf lin bus2 n.c.
TLE7269G package outlines data sheet 32 rev. 1.2, 2007-11-13 8 package outlines figure 19 pg-dso-14 (plastic dual small outline pg-dso-14-24) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gps09032 for further information on alternativ e packages, please vi sit our website: http://www.infineon.com/packages . dimensions in mm
edition 2007-11-13 published by infineon technologies ag 81726 munich, germany ? 2007 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
TLE7269G revision history data sheet 34 rev. 1.2, 2007-11-13 9 revision history revision date changes 1.2 2007-10-02 data sheet created

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