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? semiconductor components industries, llc, 2010 april, 2010 ? rev. 0 1 publication order number: NCV8855/d NCV8855 quad-output automotive system power supply ic with integrated high-side 2a switch the NCV8855 is a multiple output controller / regulator ic with an integrated high ? side load switch. the NCV8855 addresses automotive radio system and instrument cluster power supply requirements. in addition to the high ? side load switch, the NCV8855 includes a switch ? mode power supply (smps) buck controller, a 2.5 a smps buck regulator and two low dropout (ldo) linear regulator controllers. the NCV8855 in combination with the ultra ? low quiescent current ncv861x ic forms an eight ? output automotive radio or instrument cluster power solution. the NCV8855 has an internally set switching frequency of 170, with a sync pin for external frequency synchronization. the NCV8855 is intended to supply power to various loads, such as a tuner, cd logic, audio processor and cd / tape control within a car radio. the high ? side switch can be used for a cd / tape mechanism or switching an electrically ? powered antenna or display unit. in an instrument cluster application, the NCV8855 can be used to power graphics display, flash memory and can transceivers. in addition, the high ? side switch can be used to limit power to a tft display during a battery over ? voltage condition. features ? < 1 a shutdown current ? meets es ? xw7t ? 1a278 ? ab test pulse g ? loaded conditions ? v in operating range 9.0 to 18.0 v ? 1 smps controller with adjustable current limit ? 1 smps regulator with internal 300 m nmos switch ? 2 ldo controllers with current limit and short circuit protection ? 1 high ? side load switch with internal 300 m nmos fet ? adjustable output voltage for all controllers / regulators ? 800 mv, 1% reference voltage ? system enable pin ? single enable pin for both ldo controllers ? independent enable for high ? side load switch ? thermal shutdown with thermal warning indicator ? this is a pb ? free device applications ? automotive radio ? instrument cluster, driver information system (dis) 40 pin qfn, 6x6 mn suffix case 488ar device package shipping ? ordering information NCV8855bmnr2g qfn ? 40 (pb ? free) 2500 / tape & reel marking diagram aa = assembly location wl = wafer lot yy = year ww = work week = pb ? free package NCV8855 aawlyyww 1 http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 40 1
NCV8855 http://onsemi.com 2 typical application schematic showing detailed block diagram 22 agnd 37 vin 5 35 sys _en i limit v r drv_vpp 26 28 vin hs_s hs_en vbatt hs_out 7 29 sw_fb1 ss1 i limit v ref 23 21 24 s r q q gh1 sn1 gl1 vbatt vout1 25 27 ocset bst1 30 comp1 9 i limit bst2 10 s r q 11 vin_sw sn2 3 sw_fb2 ss2 vout2 v ref 2 comp2 4 sync osc 180 out ? of ? phase ga te control vout4 vout3 1 38 70% v ref lr_g1 lr_fb1 vout1 39 isns1 ? 40 i limit isns1+ 33 34 v ref lr _g2 lr_fb2 32 isns2 ? 31 i limit isns2+ pgnd 20 vin i limit v1 v1 bandgap v r 5v_ic int. rails and references main logic / fault control uvlo tsd1 tsd2 clk1 ramp1 clk2 ramp2 ramp2 clk2 clk1 ramp1 v ref 8 hot_flg 5v _ic drv_vpp 5v_ ic drv_vpp 6 ldo_en vbatt vbatt control clk1 vneg clamp vhigh clamp current limit charge pump vin ea ea ea ea scp 5v _ic twarn1 twarn2 70% v ref scp scp 70% v ref scp d1 q1 q2 q3 q4 36 drail ldo vin figure 1. components part number value manufacturer d1 mbrs4201t3 200 v, 4 a, schottky, 0.61 v vf, smc on semiconductor q1, q2 ntd24n06 60 v, n type mosfet, 32 m , dpak on semiconductor q3, q4 ntd20p06lt4g ? 60v, p type mosfet, 130 m , dpak on semiconductor
NCV8855 http://onsemi.com 3 pin function descriptions pin no. symbol description 5 sys_en main enable pin for the ic. a logic high on this pin will enable the part. leaving this pin floating or driving it to ground will place the ic in shutdown mode. 6 ldo_en enable pin for both ldo controllers. a logic high on this pin will enable both ldo controllers. if this pin is left floating, an internal pull down keeps the ldos disabled. 7 hs_en enable pin for the high ? side load switch. a logic high on this pin will enable the hss. if this pin is left floating, an internal pull down keeps the hss disabled. 8 hot_flg thermal warning indicator. this pin provides an early warning signal of an impending thermal shutdown. 22 drv_vpp output of the internal 7.2 v linear regulator. bypass this pin with 1 f to ground. 35 5v_ic output of the internal 5 v linear regulator. bypass this pin with 0.1 f to ground. 36 drail output of the internal 4.2 v linear regulator. bypass this pin with 0.1 f to ground. 4 sync synchronization pin. use this pin to synchronize the internal oscillator to an external clock. if synchronization is not used, connect this pin to agnd. 37 agnd analog ground. reference point for internal signals. switch ? mode power supply 1 (smps1) pin connections 27 ocset overcurrent set pin, used to set the current limit threshold. a resistor connected from this pin and the upper mosfet drain sets the current limit protection level. 29 sw_fb1 output voltage feedback pin. connect a resistor divider network to vout1 to set the desired output voltage. 30 comp1 this pin is the output of the error amplifier and the non-inverting input of the pwm comparator. use this pin in conjunction with the sw_fb1 pin to compensate the voltage-mode control feedback loop. 25 bst1 this pin is the supply rail for the upper n ? channel mosfet. an internal bootstrap diode brings drv_vpp to this pin. connect a ceramic capacitor (c bst1 ) between this pin and the sn1 pin. a typical value for c bst1 is 0.1 f. 24 gh1 gh1 is the output pin of the internal upper n ? channel mosfet gate driver. keep the trace from this pin to the gate of the upper mosfet as short as possible to achieve the best turn ? on and turn ? off performance and to reduce electro ? magnetic emissions. 23 sn1 this pin is the return path of the upper floating gate driver. connect this pin to the source of the upper mosfet. this pin is also used to sense the current flowing through the upper mosfets. 21 gl1 gl1 is the output pin of the synchronous rectifier gate driver. connect this pin to the lower n ? channel mosfet. 20 pgnd this pin is the return path for smps1 lower mosfet driver current. connect this pin to the source of the lower mosfet. pins not internally connected to silicon ep ? exposed pad of qfn package. connect to printed circuit board ground to improve thermal performance. 12 thru 19 these pins can be left floating or tied to ground to improve thermal performance. switch ? mode power supply 2 (smps2) pin connections 10 vin_sw this pin is the supply rail for the internal upper n ? channel mosfet. bypass this pin with a local ceramic capacitor. additional bulk capacitance may be required based off output requirements. refer to application section for more information. 3 sw_fb2 output voltage feedback pin. connect a resistor divider network to vout2 to set the desired output voltage. 2 comp2 this pin is the output of the error amplifier and the non ? inverting input of the pwm comparator. use this pin in conjunction with the sw_fb2 pin to compensate the voltage ? controlled feedback loop. 11 bst2 this pin is the supply rail for the internal upper n ? channel mosfet. an internal bootstrap diode brings drv_vpp to this pin. connect a ceramic capacitor (c bst2 ) between this pin and the sn2 pin. a typical value for c bst2 is 0.1 f. 9 sn2 source output of the internal upper n ? channel mosfet.
NCV8855 http://onsemi.com 4 pin function descriptions pin no. description symbol low dropout linear regulator controller 1 (ldo1) pin connections 38 lr_fb1 ldo controller output voltage feedback pin. connect a resistor divider network to vout3 to set the desired output voltage. 1 lr_g1 error amplifier output of the ldo controller. connect to gate of p ? channel mosfet pass element. 40 isns1+ current sense positive input. connect this pin to the supply side of the current sense resistor. this pin also serves as the supply rail for the linear regulator controller. a local bypass capacitor with a value of 0.1 f to 1 f is recommended. 39 isns1 ? current sense negative input. when using a current sense resistor, connect this pin to the pass element side of the current sense resistor. if current limit is not used, connect this pin to the supply rail of the pass element. low dropout linear regulator controller 2 (ldo2) pin connections 34 lr_fb2 ldo controller output voltage feedback pin. connect a resistor divider network to vout3 to set the desired output voltage. 33 lr_g2 error amplifier output of the ldo controller. connect to gate of p ? channel mosfet pass element. 31 isns2+ current sense positive input. connect this pin to the supply side of the current sense resistor. this pin also serves as the supply rail for the linear regulator controller. a local bypass capacitor with a value of 0.1 f to 1 f is recommended. 32 isns2 ? current sense negative input. when using a current sense resistor, connect this pin to the pass element side of the current sense resistor. if current limit is not used, connect this pin to the supply rail of the pass element. high ? side load switch (hss) pin connections 26 vin this pin is the supply rail for the internal high ? side load switch, drv_vpp and 5v_ic. bypass this pin with a 1 f ceramic capacitor. 28 hs_s source node output of the internal high ? side n ? channel mosfet load switch. maximum ratings (voltages are with respect to agnd unless noted otherwise) pin name value unit max dc voltage (gh1, bst1, sn1, sn2, bst2, hs_s) ? 0.3 to 30 v negative transient (t < 50 ns) (sn1, sn2) ? 2 v max dc voltage: 5v_ic 6 v max dc voltage: drv_vpp 9 v max dc voltage (bst1 & gh1w/respect to sn1, gl1, bst2 w/respect to sn2) ? 0.3 to 15 v max dc voltage (ocset, isns1+, isns1 ? , lr_g1, vin, vin_sw, isns2+, isns2 ? , lr_g2) ? 0.3 to 40 v peak transient (es ? xw7t ? 1a278 ? ab test pulse g ? loaded conditions) (ocset, isns1+, isns1 ? , lr_g1, vin, vin_sw, isns2+, isns2 ? , lr_g2) ? 0.3 to 45 v max dc voltage (sw_fb1, comp1, lr_fb1, ldo_en, hot_flg, sw_fb2, comp2, lr_fb2, hs_en, sys_en, sync) ? 0.3 to 7 v max dc voltage: pgnd ? 0.3 to 0.3 v maximum operating junction temperature range, t j ? 40 to 150 c maximum storage temperature range, t stg ? 55 to +150 c peak reflow soldering temperature: pb ? free 60 to 150 seconds at 217 c 260 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
NCV8855 http://onsemi.com 5 attributes description symbol value unit thermal characteristic r ja generated from 1 sq in / 1 oz copper 1 sided pcb r ja 36 c/w r jc 3 c/w esd capability human body model machine model 2 150 kv v moisture sensitivity level msl 1 recommended operating conditions description value vbatt range (refer to figure 1) 9 v to 18 v ambient temperature range ? 40 c to 105 c figure 2. agnd comp1 bst2 pgnd lr_fb2 lr_g2 lr_g1 comp2 hot_flg sn2 vin_sw ldo_en isns2+ isns2 ? sync/rosc hs_en 5v_ic drail sys_en lr_fb1 isns1 ? top view sw_fb2 isns1+ sw_fb1 hs_s vin gh1 sn1 drv_vpp gl1 bst1 ocset 1 electrical characteristics (v in_sw = v in = v isns1+ = v isns1 ? = v isns2+ = v isns2 ? = 13.2 v, sys_en = ldo_en = hs_en = 5 v, vout3 = 3.3 v, vout4 = 8.5 v, iout[1:4] = 0 a) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter symbol conditions min typ max unit supply voltages and system specification supply current and operating voltage range vin_sw quiescent current no switching, v sw_fb2 = 1v, sn2 = pgnd1, t j = 25 c 175 a vin_sw shutdown current sys_en = 0 v, t j = 25 c 100 500 na high vin detect voltage v ovp vin rising 18 18.5 19 v high vin detect hysteresis vin falling 0.2 0.6 1 vin quiescent current t j = 25 c 4 ma 1. guaranteed by design, not fully tested in production. 2. indirectly guaranteed by test coverage of other parameters.
NCV8855 http://onsemi.com 6 electrical characteristics (v in_sw = v in = v isns1+ = v isns1 ? = v isns2+ = v isns2 ? = 13.2 v, sys_en = ldo_en = hs_en = 5 v, vout3 = 3.3 v, vout4 = 8.5 v, iout[1:4] = 0 a) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol supply voltages and system specification supply current and operating voltage range vin shutdown current sys_en = 0 v, t j = 25 c 100 500 na internal voltage reference internal voltage reference range v ref t j = 25 c ? 40 c t j 150 c 0.792 0.784 0.8 0.808 0.816 v internal linear regulator 5 v supply rail 5v_ic uvlo threshold voltage v 5v_ic rising 4.00 4.35 4.70 v 5v_ic uvlo hysteresis v 5v_ic falling 100 150 300 mv voltage range no load 4.8 5 5.2 v current limit 10 21 50 ma load regulation 1ma i 5v_ic 10 ma 50 mv line regulation i 5v_ic = 5 ma, 9 v vin 18 v 100 mv internal drv_vpp supply rail drv_vpp uvlo threshold voltage v drv_vpp rising 4.00 4.35 4.70 v drv_vpp uvlo hysteresis v drv_vpp falling 100 150 300 mv voltage range v drv_vpp no load 6.9 7.1 7.3 v current limit 30 67 110 ma load regulation 1 ma i drv_vpp 25 ma 50 mv line regulation i drv_vpp = 1 ma, 9 v vin 18 v 200 mv dropout voltage i drv_vpp = 25 ma, v drv_vpp = 2 % 400 mv oscillator oscillator frequency f sw 154.7 170 185.3 khz sync logic high 2.0 v logic low 0.8 v pull down current v sync = 5 v v sync = 0.8 v 2 5 5 10 a leakage current sys_en = 0 v, v sync = 5 v 100 500 na clock synchronization range 190 255 khz synchronization delay to smps1 from falling sync edge 200 400 ns synchronization delay to smps2 from rising sync edge 200 400 ns minimum sync pulse width (high) smps1 synchronizing 50 ns minimum sync pulse width (low) smps2 synchronizing 50 ns thermal monitoring (t mon_hss, high ? side junction temperature monitor) thermal warning temperature t warn1 140 150 160 c t warn1 hysteresis 10 20 c thermal shutdown temperature tsd1 160 170 180 c delta junction temperature (tsd1 ? t warn1 ) 10 20 30 c 1. guaranteed by design, not fully tested in production. 2. indirectly guaranteed by test coverage of other parameters.
NCV8855 http://onsemi.com 7 electrical characteristics (v in_sw = v in = v isns1+ = v isns1 ? = v isns2+ = v isns2 ? = 13.2 v, sys_en = ldo_en = hs_en = 5 v, vout3 = 3.3 v, vout4 = 8.5 v, iout[1:4] = 0 a) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol supply voltages and system specification thermal monitoring (t mon_sw, smps2 internal mosfet temperature monitor) thermal warning temperature t warn2 140 150 160 c t warn2 hysteresis 10 20 c thermal shutdown temperature tsd2 160 170 180 c delta junction temperature (tsd2 ? t warn2 ) 10 20 30 c hot_flg voltage low threshold t j > twarn[x], 1 k pullup to 5 v 0.4 v leakage current 1 k pull ? up to 5 v, t j = 25 c 100 500 na sink capability v hot_flg = 0.8 v 4.6 ma system enable logic high 2.0 v logic low 0.8 v pull down resistance t j = 25 c 500 k high ? side enable hs_en logic high 2.0 v hs_en logic low 0.8 v pull down current v hs_en = 5 v v hs_en = 0.8 v 2 5 5 10 a leakage current i hs_en sys_en = 0 v, v hs_en = 5 v 100 500 na ldo enable logic high 2.0 v logic low 0.8 v pull down current v ldo_en = 5 v v ldo_en = 0.8 v 2 5 5 10 a leakage current i ldo_en sys_en = 0 v, v ldo_en = 5 v 100 500 na switch ? mode power supply controller (smps1, vout1) specifications over current protection ocset current sink r ocset = 10 k connected to 13.2 v 45 55 65 a ocset leakage current sys_en = 0 v, v ocset = 13.2 v, t j = 25 c 100 500 na ocset comparator differential range (note 1) 50 750 mv ocset comparator common ? mode range (note 1) 4.0 19 v current limit response time from rising edge of sn1 100 200 275 ns short circuit threshold voltage scth1 v sw_fb1 % of v ref 75 80 85 % short circuit protection startup delay from sys_en rising edge, % of t ss1, sw_fb1 = 0.5 v, (note 2) 100 125 150 % internal soft ? start soft ? start time t ss1 3 5 7 ms 1. guaranteed by design, not fully tested in production. 2. indirectly guaranteed by test coverage of other parameters.
NCV8855 http://onsemi.com 8 electrical characteristics (v in_sw = v in = v isns1+ = v isns1 ? = v isns2+ = v isns2 ? = 13.2 v, sys_en = ldo_en = hs_en = 5 v, vout3 = 3.3 v, vout4 = 8.5 v, iout[1:4] = 0 a) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol switch ? mode power supply controller (smps1, vout1) specifications error amplifier dc gain (note 1) 70 85 db gain ? bandwidth product (note 1) 8 10 mhz sw_fb1 input bias current sw_fb1 = 0.8 v 100 na input offset voltage (note 1) 800 v slew rate c comp1 = 50 pf, 1 ma dc load slew rate within ramp voltage levels (note 1) 6 8 v/ s comp1 source current v comp1 = 2.2 v 1.5 8 ma v comp1 = 3.2 v 1.6 8 ma comp1 sink current v comp1 = 2.2 v 1.1 8 ma v comp1 = 1.1 v 0.7 8 ma minimum comp1 voltage i comp1 = 500 a 1.05 v maximum comp1 voltage i comp1 = 2 ma 3.3 v ramp maximum voltage 2.8 3.0 3.2 v ramp minimum voltage 1.1 1.2 1.3 v ramp voltage amplitude v ramp1 1.6 1.8 2.0 v duty cycle limitations minimum off time t minoff1 gh1 falling to gl1 rising 80 140 200 ns minimum pulse width t minon1 gh1 rising to gh1 falling 120 250 300 ns gate driver gh1 source current v gh1 ? v sn1 = 4 v, t j = 25 c 1.5 a gh1 sink current v gh1 ? v sn1 = 2 v, t j = 25 c 1.5 a gl1 source current v gl1 ? pgnd = 4 v, t j = 25 c 1.5 a gl1 sink current v gl1 ? pgnd = 1 v, t j = 25 c 1.5 a sn1 falling to gl1 rising, non ? overlap time t nolt 30 70 ns gl1 falling to gh1 rising, non ? overlap time 30 70 ns sn1 falling non ? overlap threshold voltage 1.0 1.8 3.0 v gl1 falling non ? overlap threshold voltage 2 v sn1 falling override timer 50 100 150 ns switch ? mode power supply regulator (smps2, vout2) specifications over current protection internal current limit 2.5 3.05 4.2 a current limit blanking time 100 200 ns short circuit threshold voltage scth2 v sw_fb2 % of v ref 75 85 95 % short circuit protection startup delay from sys_en rising edge, % of t ss2, sw_fb2 = 0.5 v 100 125 150 % 1. guaranteed by design, not fully tested in production. 2. indirectly guaranteed by test coverage of other parameters.
NCV8855 http://onsemi.com 9 electrical characteristics (v in_sw = v in = v isns1+ = v isns1 ? = v isns2+ = v isns2 ? = 13.2 v, sys_en = ldo_en = hs_en = 5 v, vout3 = 3.3 v, vout4 = 8.5 v, iout[1:4] = 0 a) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol switch ? mode power supply regulator (smps2, vout2) specifications internal soft ? start soft ? start time t ss2 sync floating 3 5 7 ms error amplifier dc gain (note 1) 70 85 db gain ? bandwidth product (note 1) 8 10 mhz sw_fb2 input bias current sw_fb2 = 0.8 v 100 500 na input offset voltage 800 v slew rate c comp2 = 50 pf, 1 ma dc load slew rate within ramp voltage levels (note 1) 6 8 v/ s comp2 source current v comp2 = 2.2 v 1.5 8 ma v comp2 = 3.2 v 1.6 8 ma comp2 sink current v comp2 = 2.2 v 1.1 8 ma v comp2 = 1.1 v 0.7 8 ma minimum comp2 voltage i comp2 = 500 a 1.05 v maximum comp2 voltage i comp2 = 2 ma 3.3 v ramp maximum voltage 2.8 3.0 3.2 v ramp minimum voltage 1.1 1.2 1.3 v ramp voltage amplitude v ramp2 1.6 1.8 2.0 v duty cycle limitations minimum off time t minoff2 sn2 falling to sn2 rising 80 140 200 ns minimum pulse width t minon2 sn2 rising to sn2 falling, 120 250 300 ns switching mosfet n ? channel mosfet r ds(on) t j = 25 c, guaranteed at probe 300 360 m turn ? on time sn2 0 v to 13.2 v, iout = 1 a (inductive load), t j = 25 c 30 ns turn ? off time sn2 13.2 v to 0 v, iout = 1 a (inductive load), t j = 25 c 30 ns low dropout linear regulator controller (ldo1, vout3) specifications output voltage regulation output voltage accuracy v lr_fb1 tied to vout3 directly, ntd20p06l pass device ? 2 2 % output voltage line regulation iout3 = 10 ma, 4.5 v v isns1+ 5.5 v, ntd20p06l pass device ? 0.25 0.01 0.25 % output voltage load regulation 1 ma iout3 500 ma, v isns1+ = 5 v, ntd20p06l pass device ? 0.5 0.2 0.5 % output load capacitance range c out3 (note 1) 10 100 f output load capacitance esr range (note 1) 0.01 5 power supply ripple rejection psrr1 ntd20p06l pass device (note 1) 60 db current limit current limit threshold voltage v sns1 v isns1+ ? v isns1 ? 90 110 130 mv 1. guaranteed by design, not fully tested in production. 2. indirectly guaranteed by test coverage of other parameters.
NCV8855 http://onsemi.com 10 electrical characteristics (v in_sw = v in = v isns1+ = v isns1 ? = v isns2+ = v isns2 ? = 13.2 v, sys_en = ldo_en = hs_en = 5 v, vout3 = 3.3 v, vout4 = 8.5 v, iout[1:4] = 0 a) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol low dropout linear regulator controller (ldo1, vout3) specifications current limit isns1+ leakage current i isns1+ sys_en = 0, t j = 25 c, v isns1+ = 13.2 v 100 500 na isns1 ? leakage current i isns1 ? sys_en = 0, t j = 25 c, v isns1 ? = 13.2 v 100 500 na short circuit threshold voltage v lr_fb1 % of v ref 60 70 80 % short circuit blanking time from rising edge of ldo_en 10 12 14 ms error amplifier feedback bias current lr_fb1 = 0.5 v 100 500 na maximum |v gs | 2 ma, internally clamped 10 11.7 13.5 v low dropout linear regulator controller (ldo2, vout4) specifications output voltage regulation output voltage accuracy v lr_fb2 tied to vout4 directly, ntd20p06l pass device ? 2 2 % output voltage line regulation iout4 = 10 ma, 9 v v isns2+ 18 v, ntd20p06l pass device ? 0.25 0.01 0.25 % output voltage load regulation 1 ma iout4 500 ma, ntd20p06l pass device ? 0.5 0.2 0.5 % output load capacitance range c out4 (note 1) 10 100 f output load capacitance esr range (note 1) 0.01 5 power supply ripple rejection psrr2 ntd20p06l pass device (note 1) 60 db current limit current limit threshold voltage v sns2 v isns2+ ? v isns2 ? 90 110 130 mv isns2+ leakage current i isns2+ sys_en = 0, t j = 25 c, v isns2+ = 13.2 v 100 500 na isns2 ? leakage current i isns2 ? sys_en = 0, t j = 25 c, v isns2 ? = 13.2 v 100 500 na short circuit threshold voltage v lr_fb2 % of v ref 60 70 80 % short circuit blanking time from rising edge of ldo_en 10 12 14 ms error amplifier feedback bias current lr_fb2 = 0.5 v 100 500 na maximum |v gs | 2 ma, internally clamped 10 11.7 13.5 v high ? side load switch (hss) current limit peak current limit i hsslim 2.00 2.80 3.64 a short circuit timeout t scp 1.300 1.506 1.800 ms short circuit threshold voltage v scp(hs_s) 4.0 4.5 5.0 v current overload threshold voltage v ds v in ? v hs_s 3.3 3.95 4.6 v current overload timeout 2.600 3.012 3.600 ms voltage clamp source output positive clamping voltage v clamp+ 1 ma i hs_s 2 a v clamp+ v in v ovp 15.4 16.0 16.6 v source output negative clamping voltage v clamp ? i loadsw = 50 ma ? 1.6 v 1. guaranteed by design, not fully tested in production. 2. indirectly guaranteed by test coverage of other parameters.
NCV8855 http://onsemi.com 11 electrical characteristics (v in_sw = v in = v isns1+ = v isns1 ? = v isns2+ = v isns2 ? = 13.2 v, sys_en = ldo_en = hs_en = 5 v, vout3 = 3.3 v, vout4 = 8.5 v, iout[1:4] = 0 a) min/max values are valid for the temperature range ? 40 c t j 150 c unless noted otherwise. min/max values are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol high ? side load switch (hss) mosfet hss r ds(on) v gs(hss) = 8 v 233 442 m hss dropout voltage i hs_s = 1 a 233 442 mv turn on/off turn on time (resistive load) r hs_s = 6.6 , 90% vin 40 80 120 s turn off time r hs_s = 6.6 , 10% vin 50 125 200 s 1. guaranteed by design, not fully tested in production. 2. indirectly guaranteed by test coverage of other parameters. v hs_s i load 2.8a v ds = 3.75v hs current overload (latched shutdown of hs only) hs_en 4.5v 1.506 msec v ds 3.75 v 3.012 m sec figure 3.
NCV8855 http://onsemi.com 12 theory of operation device description the NCV8855 is a multiple output controller / regulator ic with an integrated high ? side load switch. the NCV8855 will address automotive radio system and instrument cluster power supply requirements. in addition to the high ? side load switch, the NCV8855 comprise a switch ? mode power supply (smps) buck controller, a 2 a smps buck regulator, and two low dropout linear regulator controllers (ldo). the NCV8855 in combination with the ultra ? low iq ncv861x ic forms an eight output automotive radio or instrument cluster power solution. 22 7 hot_flg agnd 36 5 5v_ic 4 35 sys_en ldo_en drv_vpp 26 28 vin hs_s hs_en 6 29 sw_fb1 23 21 24 gh1 sn1 gl1 25 27 ocset bst1 30 comp1 8 bst2 9 10 sn2 2 sw_fb2 1 comp2 3 sync/ rosc 40 37 lr_g1 lr_fb1 38 isns1 ? 39 isns1+ 33 34 lr_g2 lr_fb2 32 isns2 ? 31 isns2+ pgnd 20 vin_sw smps1 vout1 smps2 vout2 ldo2 vout4 high ? side switch main ldo1 vout3 figure 4. the NCV8855 has an internally set switching frequency of 170 khz and provides an sync pin for external frequency synchronization. the NCV8855 is designed to operate within the range of 9 v to 18 v. the switch ? mode power supplies are voltage ? mode controlled and the ldo controllers drive p ? channel mosfets as pass devices. system enable (sys_en) the system enable (sys_en) pin is used to start device operation or place it in low quiescent shutdown. driving this pin high will allow the two main internal voltage rails (drv_vpp and 5v_ic) to power up. these voltage rails require external bypassing and have independent uvlo trip points. both rails must be operational in order for the ic to function. after exceeding its uvlo threshold, the ic will power up the switch ? mode power supplies with a soft ? start. conversely, a logic ? low on the pin will power down the drv_vpp and 5v_ic rails and place the ic in an ultra ? low current shutdown state. linear regulator enable (ldo_en) the low ? dropout linear regulators (ldos) have a dedicated enable pin. this pin controls the startup and shutdown of the ldos. the sys_en pin must be logic high for this pin to function. it is possible to drive this pin high coincidentally with sys_en, but the ldo outputs will not startup until dr v_vpp and 5v_ic have increased above its uvlo thresholds. high ? side switch enable (hs_en) the high ? side switch enable controls only the high ? side switch. similar to ldo_en, the sys_en pin must be logic high for this pin to function. the voltage level on all enable pins have been designed to work with 3.3 v or 5 v logic. ic power (vin, vin_sw, drv_vpp, 5v_ic) there are many input voltage rails for the NCV8855. the main power supply input for the ic is vin. the dr v_vpp, 5v_ic and the high ? side switch drain are all driven from v in . the drv_vpp voltage rail is the power rail for smps1 & smps2?s gate driver circuits. the 5v_ic voltage rail is the main supply for the ic. the vin_sw rail is the supply rail for smps2?s internal upper mosfet. vin_sw is directly tied to the drain of the n ? channel mosfet. drv_vpp internal regulator 5v_ic internal regulator high ? side switch smps1 & 2 gate drivers main ic drv_vpp 5v_ic ldo1 ldo2 vin smps2 internal upper mosfet vin_sw isns1+ isns1 ? isns2+ isns2 ? figure 5. two additional inputs rails are isns1+ and isns2+. these inputs not only serve as the positive reference for the current sense circuit, but also serve as the supply rail for the ldo error amplifier. startup and shutdown behavior the startup sequence primary depends on the system configuration. however, in every case, enable sys_en first. the sync pin must not be held at logic high before sys_en is enabled. below shows typical startup and
NCV8855 http://onsemi.com 13 shutdown behavior when vout3 is derived from vout1 (as shown in figure 1). startup and shutdown behavior sys_en ldo_en vin vout1 vout2 8v_ic vout3 vout4 5v_ic 17.9 v natural startup controlled soft ? sta r natural decay figure 6. 18.5 v >2.2 v <0.8 v 4.35 v 4.2 v 4.35 v 4.2 v >2.2 v <0.8 v in addition to the enable pins, the ic features an automatic shutdown during a high battery condition. when vin exceeds 18.5 v (typ) the ic will shutdown all outputs. when v in falls below 17.9 v (typ), the ic will go through a typical start up and resume normal operation. out ? of ? phase synchronization by default, the turn ? on of smps2 is delayed by half the switching cycle, which corresponds to 180 phase delay. advantages of out ? of ? phase synchronization are many. interleaving the current pulses at the input reduces the input rms current. this reduction minimizes the input filter requirement, allowing the use of smaller components, hence a more cost ef fective solution. in addition, since peak current is reduced, emitted emi is also reduced. synchronizing (sync) synchronizing the NCV8855 to an external frequency is achieved by providing a 10 to 90% duty cycle clock to the snyc pin. the rising edge of the clock signal will immediately reset the internal ramp of smps2 and begin a new pulse for smps2. conversely , the falling edge of the clock signal will immediately reset the internal ramp of smps1 and begin a new pulse for smps1. the first rising edge of the external clock signal may cause a momentary phase diversion between smps1 and smps2, but will lock into desired phase on the subsequent falling edge. during start up, the sync pin must not be held at a logic high. thermal warning (hot_flg) and thermal shutdown there are two thermal sensors in the NCV8855 devices. if any of these two exceeds the warning threshold, the hot_flg will assert low. in addition, if thermal monitor 1 (t mon_hss ) exceeds the warning threshold, the high ? side switch current limit will fold back to 1.4 a (typ). if t mon_hss exceeds its tsd point, the high ? side switch will latch off while the other device functions will continue to operate. a hs_en or sys_en toggle will be required to re ? start the high ? side switch in the case of a t mon_hss tsd event. if thermal monitor 2 (t mon_sw ) exceeds it tsd point, the entire chip (regardless of the state of t mon_hss ) will latch off, and a sys_en toggle will be required to restart. overcurrent protection (smps1) overcurrent protection for smps1 is implemented via v ds(on) sensing of the upper mosfet. at the beginning of each switching cycle, after a short blanking time, the voltage is sampled across the upper mosfet and compared to the threshold set by r ocset . 50 a r ocset 27 ocset 23 sn1 ilimit external upper mosfet figure 7. if this comparator is tripped, then the pulse is immediately halted. this operation repeats every cycle until the overcurrent condition is removed. the over ? current limit can be calculated with the following equation: i limit r ocset i ocset r ds(on) (eq. 1) where, i ocset is 50 a (typ.). to calculate the r ocset value, the maximum r ds(on) (at temperature) and the minimum value of i ocset must be used. in addition to this, the following relationship should be met: i limit iout1 max i pk ? pk 2 (eq. 2) where iout1 (max) is the maximum dc current allowed, and i pk ? pk /2 is the peak ripple current above the dc value. this will insure that undesirable trigger of the over ? current protection is avoided. to protect in the case of a short circuit event, a comparator monitoring the feedback voltage is incorporated. if the output voltage goes below 70% of nominal after start ? up, the part is latched off, requiring sys_en to be toggled to restart the part. the over current protection circuitry is active upon startup (short circuit protection is not). during soft ? start, under normal conditions, the current limit circuit should not trip. however, with large output capacitance, the current limit circuit may determine the output voltage rise time instead of the soft ? start circuit. to ensure that the output voltage is
NCV8855 http://onsemi.com 14 controlled by the soft ? start circuit make dt limit t ss1 , where t ss1 is the soft ? start time and dt limit is equal to: cout1 * vout1 i limit (eq. 3) overcurrent protection (smps2) the current limit for smps2 is internally set at 3.05 a (typ). the operation is similar to smps1 in that it immediately ends the pulse upon overcurrent detection. this repeats every cycle until the overcurrent condition is removed. similar to smps1, the over current protection circuitry is active upon startup. as with smps1, short circuit protection is implemented with a comparator monitoring the feedback. if the output voltage goes below 70% of nominal after start ? up, the part is latched off, requiring sys_en to be toggled to restart the part. overcurrent protection (ldo1 and ldo2) there are two overcurrent protection circuits incorporated; one provides a current limit feature, the other provides a short circuit protection feature. under normal operation, the current is sensed through a sense resistor connected to isns[x]+ and isns[x] ? and limited by the equation: i limit(ldo) v sns[x] r sns[x] (eq. 4) where, r sns[x] is the sense resistor for ldo1 and ldo2, and v sns[x] is the current limit threshold. to calculate r sns[x] , the minimum v sns[x] value and the maximum operating current should be used. output 70% vref lr _ g[x] lr _ fb [x] supply isns [x] ? ilimit isns [x ]+ vref ea scp figure 8. to thermally protect the pass device during a short circuit event, a comparator monitoring the feedback voltage is incorporated. if the output voltage goes below 70% of nominal (typ), the ldo will latch of f. this is an independent operation, meaning, a short circuit on one ldo does not affect the operation of the other, nor does it affect the smps or high ? side switch. an ldo_en toggle is required to re ? start an ldo if it latched off due to a short circuit event. in addition, the current limit should be chosen such that the output voltage will rise to greater than 70% of the final vout within 2.74 ms in order to keep the short ? circuit circuit from falsely tripping. overcurrent protection (high ? side load switch) there are two primary protection features of the internal high ? side 2.8 a (typ.) current limit. the first protection involves a short circuit condition during startup, and the second involves an overload condition after startup. during startup, if the output does not exceed 4.5 v (typ.) in 1.5 ms (typ.), the device is considered to be in a ?hard? short circuit condition, and is latched off. in addition, if the device does not exceed vin ? 3.75 v (typ.) in 3 ms (typ), the device is considered to be in a ?soft? short circuit condition, and is latched of f. furthermore, if v hs_s goes below vin ? 3.75 v (typ), during normal operation, for more than 3 ms (typ), the device is considered to be in a ?soft? short circuit condition, and is latched off. once the high ? side switch has been latched off, a hs_en toggle will be required to reset it. overvoltage clamp (high ? side load switch) the source output of the high ? side switch is clamped during a high battery condition. this protects any load connected to the source from seeing a double battery or load dump condition. if the input rises above 16 v (typ), the internal gate of the high ? side switch will be pulled low to keep the source from rising. the high ? side switch will operate in this linear mode until the input voltage exceeds 18.5 v (typ) at which point the entire ic will shutdown. application information setting the output voltage to set the output voltage of any of the controllers or regulators, use the following equation: v out[x] v ref 1 r1 r2 (eq. 5) where, r1 is the resistor that is connected from vout[x] to the feedback pin of its respective channel and r2 is connected from that feedback pin to ground. to reduce the effect of input offset current error, it is customary to calculate r1 with r2 equal to 1 k . ldo1 and ldo2 pass device selection the ldo controllers have been optimized to give the best performance with the ntd20p06l p ? channel mosfet. while other p ? channel mosfet can be used, specifications in the electrical table are guaranteed only with the ntd20p06l, and using a different mosfet may require external compensation to stabilize the output. the ntd20p06l can be used as the pass device for both controllers, and is rated with a ? 60 v max v ds. this device comes in two different packages allowing great flexibility
NCV8855 http://onsemi.com 15 when designing the thermal solution. the ipak package can be attached to the radio?s metal enclosure or it can be attached to an independent heatsink. if output current demands are low, then a dpak package can be used for a surface mount solution. ldo output capacitor selection the ldo controllers have been optimize and compensated to work with a variety of output capacitors. aluminum electrolytic capacitors with an esr up to 5 to ceramic capacitors with an esr down to 10 m can be used. depending on load requirements, the output capacitor can range from 10 f to as much as 100 f. there are many capacitor vendors which supply automotive rated parts that fall within these ranges. for example, the nichicon ud or pm type capacitors are suited well for the ldo controllers and automotive radio application. values outside of these ranges can be used, but may require external compensation. smps1 mosfet selection smps1 has integrated mosfet drivers optimized for driving n ? channel mosfets in a synchronous buck configuration. the lower mosfet driver is designed to drive a ground ? referenced low r ds(on) n ? channel mosfet. the supply rail for the lower driver is internally connected to drv_vpp and the pgnd pin is it?s ground reference. the upper mosfet driver is a floating gate driver designed to drive low r ds(on) n ? channel mosfets. a bootstrap circuit referenced to sn1 as shown in figure 1 develops the supply rail for the upper mosfet driver. the driver circuitry includes non ? overlap protection. the non ? overlap protection prevents both q1 (upper mosfet) and q2 (lower mosfet) from being on at the same time, and minimizes the associated off times. this helps reduce power losses in the switching elements. the non ? overlap protection circuit accomplishes this by controlling the delay from q1?s turn ? off to q2?s turn ? on, and from q2?s turn ? off to q1?s turn on by monitoring the voltage at the sn1 and gl1 pins. when the internal pwm signal goes low, gh1 will go low , turning q1 off. however, before q2 can turn on, the non ? overlap protection circuit waits for the voltage at the sn1 pin to fall below 1.8 v. once sn1 falls below the 1.8 v threshold, gl1 will go high, turning q2 on. however , if sn1 does not fall below 1 v in 100 ns, the safety timer circuit will override the normal control scheme and drive gl1 high. this will help insure that if q1 fails to turn off it will not produce an over ? voltage at the output. similarly, to prevent cross conduction during q2?s turn ? off and q1?s turn ? on, the non ? overlap circuit monitors the voltage at the gate of q2 through the gl1 pin. when the internal pwm signal goes high, gl1 will go low turning q2 off. however, before q1 can turn on, the non ? overlap protection circuit waits for the voltage at gl1 to drop below 2 v. once this has occurred, gh1 will go high, turning q1 on. for the drv_vpp supply, a local bypass capacitor is not only required for stability, but also to reduce noise and supply peak currents during operation. use a 1 to 4.7 f, low esr capacitor. multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size. this capacitor must be referenced to pgnd. the bootstrap circuit comprises a charge storage capacitor (c bst1 ) and the internal bootstrap diode. typical c bst1 values range from 100 nf to 1 f. the average forward current can be estimated by the following equation: i bst1 q gate fsw (eq. 6) where, q gate is the total gate charge. the average forward current through the internal diode should not exceed its rated maximum of 12 ma. this puts a limitation on the mosfets used at a particular switching frequency. the power dissipation for the internal mosfet drivers can be calculated using the following equation: pd smps1_drv pd gh1_drv pd gl1_drv (eq. 7) pd gh1_drv q gh1 v gh1 fsw (eq. 8) pd gl1_drv c gl1 v gl1 2 fsw (eq. 9) where, q gh1 is the total gate charge of the upper mosfet, c gl1 is the total input capacitance of the lower mosfet, v gh1 = v gl1 = 7.2 v (typ.) which is the drv_vpp output voltage. one method to improve the ic power dissipation is to diode ? or the 8 v smps output to the drv_vpp pin. this will override the internal regulator and the ic will run from the smps output. doing this will incrementally increase the gate drivers power dissipation, but will reduce the loss associated with the drv_vpp running from battery. for example, if the drv_vpp is operating at 12 ma from a 14.4 v battery to power smps1?s gate driver circuit, the power dissipation from this will be 90 mw. in addition, with a 20 nc gh1 change and a 1.8 nf gl1 capacitance, the gate driver loss will be 80 mw. this is a total of 170 mw of power dissipation due to running the gate drivers at 340 khz. however, if there was a diode ? or to the dr v_vpp from the 8 v output of one of the smpss, then the drv_vpp ldo losses are eliminated, and the total power dissipation from running the smps1 gate drivers reduce to 95 mw. the improvement gets better when accounting for smps2?s gate driver loss. this savings can prove to be beneficial in fast fsw and high current applications. there are two recommended n ? channel mosfet for smps1, the ntd24n06, which has a 60 v max vds, and the ntd5407n, which has a 40 v max vds. determining which mosfet to use is predicated by the load dump requirements. the same device can be used for the upper and lower mosfet. the benefit of this is reduced cost due to economies of scale.
NCV8855 http://onsemi.com 16 smps2 diode selection the diode in smps2 provides the inductor current path when the power switch turns off. this is known as the non ? synchronous diode or commutation diode. the peak reverse voltage is equal to the maximum operating input voltage. the peak conducting current is determined by the internal current limit. the average current can be calculated from: i d(avg) iout2 1
vout2 vin_sw (eq. 10) however, the worse case diode average current occurs during a short circuit condition. for a diode to survive an indefinite short circuit condition, the current rating of the diode should be equal to the maximum current limit which is 3.6 a. thus the mbrs4201t3 is the diode of choice. inductor selection both mechanical and electrical considerations influence the selection of an output inductor. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the largest components in smps system, a minimum inductor value is particularly important in space ? constrained applications. from an electrical perspective, smaller inductor values correspond to faster transient response. the maximum current slew rate through the output inductor for a buck regulator is given by: inductor slew rate di l dt v l l (eq. 11) where i l is the inductor current, l is the output inductance, and v l is the voltage drop across the inductor. this equation indicates that larger inductor values limit the regulator?s ability to slew current through the output inductor in response to output load transients. consequently, output capacitors must supply (or store) sufficient charge to maintain regulation while the inductor current ?catches up? to the load. this results in larger values of output capacitance to maintain tight output voltage regulation. in contrast, smaller values of inductance increase the regulator?s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. in continuous conduction mode, the peak ? to ? peak ripple current is calculated using the following equation: i pp fsw vout l 1
vout vbatt (eq. 12) from this equation it is clear that the ripple current increases as l de creases, emphasizin g the trade ? off between dynamic response and ripple current. for most applications, the inductor value falls in the range between 2.2 h and 22 h. there are many magnetic component vendors providing standard product lines suitable for smps1 and smps2?s requirements. tdk offers the rlf12545 ? pf series inductors, which are recommended for the automotive radio application. smps output capacitor selection the output capacitor is a basic component for the fast response of the power supply. in fact, during load transient, for first few microseconds they supply the current to the load. the controller recognizes the load transient and proceeds to increase the duty cycle to its maximum. neglecting the effect of the esl, the output voltage has a first drop due to the esr of the bulk capacitor(s). vout esr iout esr (eq. 13) a lower esr produces a lower v during load transient. in addition, a lower esr produces a lower output voltage ripple. the voltage drop due to the output capacitor discharge can be approximated using the following equation: vout discharge ( iout ) 2 l 2 cout vin min d max
vout (eq. 14) where, d max is the maximum duty cycle value, which is 90%. although the esr effect is not in phase with the discharging of the output voltage, vout (esr) can be added to vout (discharge) to give a rough indication of the maximum vout during a transient condition. simulation can also help determine the maximum vout; howe ver, it will ultimately have to be verified with the actual load since the esl effect is dependent on layout and the actual load?s di/dt. smps input capacitor selection the primary consideration for selecting the input capacitor is input rms current. however, since there are two smps running out ? of ? phase with each other, calculating the input rms current can be complicated. the graphs below shows how the input rms current is affected by differing phase angles between smps1 and smps2. the plot below was generated with vout1 at 5 v with a load of 2 a and an output inductor value of 10 h, and vout2 at 8 v with a load of 4 a and an output inductor value of 10 h. 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 0.00 60.00 120.00 180.00 240.00 300.00 360.00 phase (vout1 vs vout2) irms 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00 figure 9. irms vs phase
NCV8855 http://onsemi.com 17 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 0.00% 20.00% 40.00% 60.00% 80.00% 100.00% clock duty cycle irms 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00 figure 10. irms vs phase here it is shown that the ?sweet spot? phase angle (where the input rms current is the lowest) happens at the same location (in terms of phase relationship) regardless of input voltage. thus, once the output voltages are known, a sweet spot can be determined. after determining the sweet spot, the input capacitors can be chosen accordingly to handle the rms current. the purpose of interleaving the two smps is to eliminate any overlapping of there input currents. this will reduce the overall input rms current. since the outputs are running at different voltages, they will have different duty cycles, and thus running with 180 phase dif ference does not necessarily guarantee an optimal input rms current reduction. the figures below describe, graphically, this point. 50% duty cycle clock 2t 8v delayed by 180deg or 1/2t input current overlap t 5v figure 11. since the 8 v rail has a wider pulse, with a 50% internal clock duty cycle, there will be some amount of input current overlapping which will produce a less than ideal rms current. the following figure shows an optimized duty cycle where there is no overlapping. 2t 8 v delayed by 144deg or 2/5t input current no input current overlap t 40% duty cycle clock 5v figure 12. to achieve this optimization, the sync function on the NCV8855 will have to be used with a 40% duty cycle clock. however, when looking at the worst ? case input rms (which occurs at high battery) a 40% duty cycle clock will yield the same input rms current as a 50% duty cycle clock. thus, the only true benefit of this optimization occurs when a narrow input voltage range is assured. therefore, a 50% duty cycle clock is always recommended. smps compensation the NCV8855 utilizes voltage mode control. the control loop regulates v out by sampling v out and controlling the duty cycle. inherent with all voltage ? mode control loops is a compensation network. v ref v ramp esr c out l out c1 c2 c3 r1 r3 r2 v out v in comp fb ea pwm comparator dcr figure 13. the compensation network consists in the internal error amplifier and the impedance networks z in (r1, r3 and c3) and z fb (r2, c1 and c2). the compensation network has to provide a closed loop transfer function with the highest 0 db crossing frequency to have fast response and the highest gain in dc conditions to minimize the load regulation. a
NCV8855 http://onsemi.com 18 stable control loop has a gain crossing with ? 20 db/decade slope and a phase margin greater than 45 . error amplifier closed loop gain compensation network modulator gain db figure 14. z1 1 r 2 c 2 z2 1 r 1 r 3 c 3 p1 1 c 1 c 2 c 1 c 2 p2 1 r 3 c 3 lc 1 l out c out esr 1 esr c out to reiterate, there are 3 primary goals to compensating. goal 1 is to have a high a unity gain bandwidth (ugb) that is greater than 1/10 the switching frequency, but less than 1/2 the switching frequency. ugb is also known as the crossover frequency. this is the point where the closed loop gain = 0 db or a gain of 1. in the plot above, the ugb is the point where the red line crosses the axis. goal 2 is to have the closed loop gain cross 0 db with a ? 20 db/decade slope also known as a ? 1 slope. goal 3 is to achieve over 45 of phase margin when the gain crosses 0 db. these are just goals. sometimes the crossover frequency is reduced below 1/10 fsw in order to meet goal 3. conversely, some designs will push the crossover frequency as high as it can (as long as it is below 1/2 fsw) with a reduce phase margin of 30 in order to get a faster transient response. the only two absolutes are that the crossover frequency cannot exceed 1/2 fsw and the phase margin has to be greater than 0 at crossover. however, a smps operating towards these absolutes will experience sever ringing before it dampens out. to achieve the above goals, the following guidelines should be adopted. ? place wz1 at half the resonance of wlc ? place wz2 at or around wlc ? place wp1 at wesr ? place wp2 at half the switching frequency performing these calculations will take some amount of iterations and bench testing to verify results. however, on semiconductor has developed a tool to speed up the design process tremendously with great ease and accuracy. this tool can be downloaded by following the below link. http://www.onsemi.com/pub/collateral/compcalc.zip
NCV8855 http://onsemi.com 19 automotive radio system block diagram example NCV8855 with ncv8612 10 hot_flg 5 4 sys_en ldo_en 26 28 vin hs_s hs_en 6 29 sw_fb1 23 21 24 gh1 sn1 gl1 25 27 ocset bst1 30 comp1 8 bst 9 7 sn2 3 sw_fb2 2 comp2 37 sync 1 38 lr_g1 lr_fb1 39 isns1 ? 40 isns1+ 33 34 lr_g2 lr_fb2 32 isns2 ? 31 isns2+ vin_sw smps1 vout1 smps2 vout2 ldo2 vout4 high ? side switch main ldo1 vout3 smps1 power stage 8v output, 4a ilimit smps2 power stage 5v output, 2a ilimit ldo1 power stage 8.5v output, 0.4a ilimit ldo2 power stage 3.3v output, 1a ilimit am/fm tuner dvd rom drive active antenna fan headunit can usb connector main dsp NCV8855 8v 8.5v 3.3v 5v ldo_en hot_flg hs_en sys_en misc. 5 v logic misc. 3.3 v logic 5v 3.3v vbatt vbatt vbatt vbatt sync vin ? h vin ? a vin ? b 1 2 3 4 5 6 7 10 11 12 16 20 18 14 15 19 17 vbatt _mon hv_det bo_det hot_flg ignout ignin vout3 vout2 vout1 ldo1 vout1 reset / delay ldo2 vout2 ldo3 v out3 auto switchover monitoring logic ingito in buffer 8 en dly rst vin_s3 ignition filter body can main c vpp ncv8612 sdars output filter & fb netwo rk 5vs 3.3vs 8v output filter output filter ldo_en hot_flg hs_en sys_en 6v rst dly hot_flg_s from external can transceiver bo_det hv_det hot_flg_s bo_det hv_det power amplifier oring diodes & filter vbatt 8v ignition vpp 3.3vs vout3 fb aso_rail figure 15. note: pins 11,20,21,35,36 are not shown on the NCV8855 above and pins 9 and 13 are not shown on the ncv8612 above
NCV8855 http://onsemi.com 20 package dimensions qfn40, 6x6, 0.5p case 488ar ? 01 issue a seating 40x k 0.15 c (a3) a a1 d2 b 1 11 20 21 40 2x 2x e2 40x 10 30 40x l 40x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 31 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30mm from terminal 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 6.00 bsc d2 4.00 4.20 e 6.00 bsc 4.20 e2 4.00 e 0.50 bsc l 0.30 0.50 k 0.20 ??? 36x plane dimensions: millimeters 0.50 pitch 4.20 0.30 4.20 40x 36x 0.65 40x 6.30 6.30 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCV8855/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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