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cl7128e cl7160e cl7192e cl7256e cl7128s cl7160s cl7192s cl7256s useable gates 2,500 3,200 3,750 5,000 macrocells 128 160 192 256 logic blocks 8 10 12 16 max us er i/o pins 100 104 124 164 -5, -6, -7, -10, -5, -6, -7, -10, -6, -7, -10, -6, -7, -10, -12, -15, -20 -12, -15, -20 -12, -15, -20 -12, -15, -20 84-pin plcc 84-pin plcc 160-pin pqfp 160-pin pqfp 100-pin tqfp 100-pin tqfp 208-pin pqfp 100-pin pqfp 100-pin pqfp 208-pin rqfp 160-pin pqfp 160-pin pqfp 7k tbl 01b parameter packages speed grades december 2000 page 1 u laser processed logic device (lpld?) technology offers the ultimate combination of performance, flexibility, and low cost u functionally, architecturally, and electrically compatible with industry-standard altera ? max ? 7000 u high density - 2,500 usable gates - 128 macrocells - 120 maximum user i/o pins u laser fuse technology provides very fast, dense interconnect routing u low current consumption u supports 3.3 volt or 5.0 volt i/o operation u alpha particle immune cl7000 product family overview cl7128e cl7128s laser processed logic device family key features
the clear logic cl7000 laser processed logic device (lpld ? ) family offers the ultimate combination of performance, flexibility, and cost. this family is a system level second source to altera max ? 7000, 7000e, and 7000s products. for designs not requiring in-system reprogrammability, design verification can be performed using the programmable altera devices, and clear logic lplds can be used for low cost, high volume production. clear logic?s innovative laser-based technology eliminates nre costs, test vector development, ordering minimums and long lead times. no re-simulation or re-layout is required, as the device uses a cell-based, pld-like architecture. clear logic?s nofault ? technology ensures complete test coverage through the use of specialized testing modes which are transparent to the user. the clear logic cl7000 laser processed logic device family is based upon a large array of macrocells. each macrocell contains a logic array with five product terms, a product-term select matrix, and a configurable register. a group of sixteen macrocells forms a block. laser-configured metal fuses implement logical functions and control signal routing. laser configuration provides reduced cost and enhanced performance. these inherent performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events. for further information on designing with the cl7000 lpld family, please consult the following documents: u an-01: requesting a first article. this document provides instructions on how to submit a bitstream file for generation of first articles. u an-02: clear logic packaging guide. this document provides specifications and drawings for packages used by the cl7000 family. u an-09: cl7000 technology white paper. this document outlines the technologies employed by the cl7000 lpld family. u an-10: calculating cl7000 power consumption. this document provides guidelines for calculating power consumption based on design characteristics. u an-11: cl7000 test methodology. this document discribes how clear logic provides 100% stuck-at fault coverage. description cl7128e and cl7128s laser processed logic devices page 2 additional information
cl7128e and cl7128s laser processed logic devices page 3 block diagram i n p u t / g c l k 1 i n p u t / o e 2 / g c l k 2 i n p u t / o e 1 i n p u t / g c l r n 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k b l o c k a m a c r o c e l l s 1 - 1 6 b l o c k c m a c r o c e l l s 3 3 - 4 8 b l o c k e m a c r o c e l l s 6 5 - 8 0 b l o c k g m a c r o c e l l s 9 7 - 1 1 2 b l o c k b m a c r o c e l l s 1 7 - 3 2 b l o c k d m a c r o c e l l s 4 9 - 6 4 b l o c k f m a c r o c e l l s 8 1 - 9 6 b l o c k h m a c r o c e l l s 1 1 3 - 1 2 8 6 o u t p u t e n a b l e s 6 o u t p u t e n a b l e s 6 t o 1 6 6 t o 1 6 6 t o 1 6 1 6 3 6 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 1 6 3 6 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 1 6 3 6 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 1 6 3 6 6 t o 1 6 1 6 3 6 6 t o 1 6 6 t o 1 6 6 6 t o 1 6 1 6 3 6 6 t o 1 6 6 t o 1 6 6 6 t o 1 6 1 6 3 6 6 t o 1 6 6 t o 1 6 6 6 t o 1 6 1 6 3 6 6 t o 1 6 6 t o 1 6 l a s e r - c o n f i g u r e d i n t e r c o n n e c t a r r a y ( l i a ) 7 1 2 8 d r w 0 1 u an-12: cl7000 lpld timing and function compatability. this document shows how a seamless conversion from cpld to asic can be achieve with no additional engineering with clear logic.
p i n n a m e 8 4 p i n p l c c 1 0 0 p i n p q f p 1 0 0 p i n t q f p 1 6 0 p i n p q f p i n p u t / g c l k 1 8 3 8 9 8 7 1 3 9 i n p u t / g c l r n 1 9 1 8 9 1 4 1 i n p u t / o e 1 8 4 9 0 8 8 1 4 0 i n p u t / o e 2 / g c l k 2 2 9 2 9 0 1 4 2 t d i 1 4 6 4 9 t m s 2 3 1 7 1 5 2 2 t c k 6 2 6 4 6 2 9 9 t d o 7 1 7 5 7 3 1 1 2 g n d i n t 4 2 , 8 2 4 0 , 8 8 3 8 , 8 6 6 0 , 1 3 8 g n d 7 , 1 9 , 3 2 , 4 7 , 5 9 , 7 2 1 3 , 2 8 , 4 5 , 6 1 , 7 6 , 9 7 1 1 , 2 6 , 4 3 , 5 9 , 7 4 , 9 5 1 7 , 4 2 , 6 6 , 9 5 , 1 1 3 , 1 4 8 v c c i n t 3 , 4 3 4 1 , 9 3 3 9 , 9 1 6 1 , 1 4 3 v c c i o 1 3 , 2 6 , 3 8 , 5 3 , 6 6 , 7 8 5 , 2 0 , 3 6 , 5 3 , 6 8 , 8 4 3 , 1 8 , 3 4 , 5 1 , 6 6 , 8 2 8 , 2 6 , 5 5 , 7 9 , 1 0 4 , 1 3 3 n c ( n o c o n n e c t ) - - - 1 , 2 , 3 , 4 , 5 , 6 , 7 , 3 4 , 3 5 , 3 6 , 3 7 , 3 8 , 3 9 , 4 0 , 4 4 , 4 5 , 4 6 , 4 7 , 7 4 , 7 5 , 7 6 , 7 7 , 8 1 , 8 2 , 8 3 , 8 4 , 8 5 , 8 6 , 8 7 , 1 1 4 , 1 1 5 , 1 1 6 , 1 1 7 , 1 1 8 , 1 1 9 , 1 2 0 , 1 2 4 , 1 2 5 , 1 2 6 , 1 2 7 , 1 5 4 , 1 5 5 , 1 5 6 , 1 5 7 t o t a l u s e r i / o p i n s 6 4 8 0 8 0 9 6 7 1 2 8 t b l 0 1 cl7128e and cl7128s laser processed logic devices page 4 macrocell diagram pin configuration g l o b a l c l o c k s g l o b a l c l e a r l o c a l a r r a y 3 6 s i g n a l s f r o m l i a 1 6 e x p a n d e r p r o d u c t t e r m s s h a r e d l o g i c e x p a n d e r s p r o d u c t t e r m s e l e c t m a t r i x p a r a l l e l l o g i c e x p a n d e r s c l e a r s e l e c t v c c c l o c k / e n a b l e s e l e c t r e g i s t e r b y p a s s f a s t i n p u t s e l e c t c o n f i g u r a b l e r e g i s t e r t o l i a t o i / o c o n t r o l b l o c k f r o m i / o p i n p r n e n a c l r n q d 2 7 k d r w 0 1
cl7128e and cl7128s laser processed logic devices page 5 absolute maximum ratings dc electrical s pecifications s y m b o l p a r a m e t e r c o n d i t i o n s m i n m a x u n i t v c c s u p p l y v o l t a g e w i t h r e s p e c t t o g r o u n d - 2 . 0 7 . 0 v v i d c i n p u t v o l t a g e [ 1 ] w i t h r e s p e c t t o g r o u n d - 2 . 0 7 . 0 v i o u t d c o u t p u t c u r r e n t , p e r p i n - 2 5 2 5 m a t s t g s t o r a g e t e m p e r a t u r e n o b i a s - 6 5 1 5 0 c t a m b a m b i e n t t e m p e r a t u r e u n d e r b i a s - 6 5 1 3 5 c t j j u n c t i o n t e m p e r a t u r e u n d e r b i a s 1 3 5 c 7 k t b l 0 3 s y m b o l p a r a m e t e r c o n d i t i o n s m i n m a x u n i t s u p p l y v o l t a g e , i n t e r n a l l o g i c a n d i n p u t b u f f e r s c o m m e r c i a l g r a d e d e v i c e s 4 . 7 5 5 . 2 5 v i n d u s t r i a l g r a d e d e v i c e s 4 . 5 0 5 . 5 0 v d c i n p u t v o l t a g e 5 . 0 v o l t c o m m e r c i a l 4 . 7 5 5 . 2 5 v 5 . 0 v o l t i n d u s t r i a l 4 . 5 0 5 . 5 0 v 3 . 3 v o l t o p e r a t i o n 3 . 0 0 3 . 6 0 v v i i n p u t v o l t a g e - 0 . 5 v c c i n t + 0 . 5 v v o o u t p u t v o l t a g e 0 v c c i o v o p e r a t i n g t e m p e r a t u r e c o m m e r c i a l t e m p e r a t u r e r a n g e 0 7 0 c i n d u s t r i a l t e m p e r a t u r e r a n g e - 4 0 8 5 c j u n c t i o n o p e r a t i n g t e m p e r a t u r e c o m m e r c i a l t e m p e r a t u r e r a n g e 0 9 0 c i n d u s t r i a l t e m p e r a t u r e r a n g e - 4 0 1 0 5 c t r i n p u t s i g n a l r i s e t i m e 4 0 n s t f i n p u t s i g n a l f a l l t i m e 4 0 n s t r v c c v c c r i s e t i m e 1 0 0 m s v c c i n t v c c i o t a 7 k t b l 0 2 t j recommended operating conditions
capacitance dc electrical s pecifications cont. s y m b o l p a r a m e t e r c o n d i t i o n s m i n m a x u n i t c i n i n p u t c a p a c i t a n c e v i n = 0 v , f = 1 . 0 m h z 1 0 p f c o u t o u t p u t c a p a c i t a n c e v o u t = 0 v , f = 1 . 0 m h z 1 0 p f 7 k t b l 0 5 cl7128e and cl7128s laser processed logic devices page 6 dc electrical characteristics (over the operating range) s y m b o l p a r a m e t e r c o n d i t i o n s m i n m a x u n i t v i h h i g h - l e v e l i n p u t v o l t a g e 2 . 0 v c c i n t + 0 . 5 v v i l i n p u t l o w v o l t a g e [ 1 ] - 0 . 5 0 . 8 v 5 . 0 - v h i g h - l e v e l t t l o u t p u t v o l t a g e i o h = - 4 m a d c , v c c i o = 4 . 7 5 v 2 . 4 v 3 . 3 - v h i g h - l e v e l t t l o u t p u t v o l t a g e i o h = - 4 m a d c , v c c i o = 3 . 0 0 v 2 . 4 v 3 . 3 - v h i g h - l e v e l c m o s o u t p u t v o l t a g e i o h = - 0 . 1 m a d c , v c c i o = 3 . 0 v v c c i o - 0 . 2 v 5 . 0 - v h i g h - l e v e l t t l o u t p u t v o l t a g e i o l = 1 2 m a d c , v c c i o = 4 . 7 5 v 0 . 4 5 v 3 . 3 - v h i g h - l e v e l t t l o u t p u t v o l t a g e i o l = 1 2 m a d c , v c c i o = 3 . 0 0 v 0 . 4 5 v 3 . 3 - v h i g h - l e v e l c m o s o u t p u t v o l t a g e i o l = 0 . 1 m a d c , v c c i o = 3 . 0 v 0 . 2 v i i n i n p u t l e a k a g e c u r r e n t v i = v c c o r g n d - 1 0 1 0 a i o z o u t p u t l e a k a g e c u r r e n t v o = v c c o r g n d - 4 0 4 0 a v o h v o l 7 k t b l 0 4
cl7128e and cl7128s laser processed logic devices page 7 p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x m i n m a x u n i t t p d 1 i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 5 . 0 6 . 0 7 . 5 n s t p d 2 i / o i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 5 . 0 6 . 0 7 . 5 n s t s u g l o b a l c l o c k s e t u p t i m e 2 . 9 3 . 4 6 . 0 n s t h g l o b a l c l o c k h o l d t i m e 0 . 0 0 . 0 0 . 0 n s t f s u g l o b a l c l o c k s e t u p t i m e o f f a s t i n p u t 2 . 5 2 . 5 3 . 0 n s t f h g l o b a l c l o c k h o l d t i m e o f f a s t i n p u t 0 . 0 0 . 0 0 . 5 n s t c o 1 g l o b a l c l o c k t o o u t p u t d e l a y c l = 3 5 p f 3 . 2 4 . 0 4 . 5 n s t c h g l o b a l c l o c k h i g h t i m e 2 . 0 3 . 0 3 . 0 n s t c l g l o b a l c l o c k l o w t i m e 2 . 0 3 . 0 3 . 0 n s t a s u a r r a y c l o c k s e t u p t i m e 0 . 7 0 . 9 3 . 0 n s t a h a r r a y c l o c k h o l d t i m e 1 . 8 1 . 8 2 . 0 n s t a c o 1 a r r a y c l o c k t o o u t p u t d e l a y c l = 3 5 p f 5 . 4 6 . 5 7 . 5 n s t a c h a r r a y c l o c k h i g h t i m e 2 . 5 3 . 0 3 . 0 n s t a c l a r r a y c l o c k l o w t i m e 2 . 5 3 . 0 3 . 0 n s t o d h o u t p u t d a t a h o l d t i m e a f t e r c l o c k c l = 3 5 p f 1 . 0 1 . 0 1 . 0 n s t c n t m i n i m u m g l o b a l c l o c k p e r i o d 5 . 7 6 . 8 8 . 0 n s f c n t m a x . i n t e r n a l g l o b a l c l o c k f r e q u e n c y 1 7 5 . 4 1 4 7 . 1 1 2 5 . 0 m h z t a c n t m i n i m u m a r r a y c l o c k p e r i o d 5 . 5 6 . 8 8 . 0 n s f a c n t m a x . i n t e r n a l a r r a y c l o c k f r e q u e n c y 1 7 5 . 4 1 4 7 . 1 1 2 5 . 0 m h z 7 k t b l 0 6 b 1 s y m b o l s p e e d : - 7 s p e e d : - 5 s p e e d : - 6 ac electrical s pecifications i/o element timing parameters
page 8 p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x m i n m a x u n i t t p d 1 i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 1 0 . 0 1 0 . 0 1 2 . 0 n s t p d 2 i / o i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 1 0 . 0 1 0 . 0 1 2 . 0 n s t s u g l o b a l c l o c k s e t u p t i m e 7 . 0 7 . 0 1 0 . 0 n s t h g l o b a l c l o c k h o l d t i m e 0 . 0 0 . 0 0 . 0 n s t f s u g l o b a l c l o c k s e t u p t i m e o f f a s t i n p u t 3 . 0 3 . 0 3 . 0 n s t f h g l o b a l c l o c k h o l d t i m e o f f a s t i n p u t 0 . 5 0 . 5 0 . 0 n s t c o 1 g l o b a l c l o c k t o o u t p u t d e l a y c l = 3 5 p f 5 . 0 5 . 0 6 . 0 n s t c h g l o b a l c l o c k h i g h t i m e 4 . 0 4 . 0 4 . 0 n s t c l g l o b a l c l o c k l o w t i m e 4 . 0 4 . 0 4 . 0 n s t a s u a r r a y c l o c k s e t u p t i m e 2 . 0 2 . 0 4 . 0 n s t a h a r r a y c l o c k h o l d t i m e 3 . 0 5 . 0 4 . 0 n s t a c o 1 a r r a y c l o c k t o o u t p u t d e l a y c l = 3 5 p f 1 0 . 0 1 0 . 0 1 2 . 0 n s t a c h a r r a y c l o c k h i g h t i m e 4 . 0 4 . 0 5 . 0 n s t a c l a r r a y c l o c k l o w t i m e 4 . 0 4 . 0 5 . 0 n s t o d h o u t p u t d a t a h o l d t i m e a f t e r c l o c k c l = 3 5 p f 1 . 0 1 . 0 1 . 0 n s t c n t m i n i m u m g l o b a l c l o c k p e r i o d 1 0 . 0 1 0 . 0 1 1 . 0 n s f c n t m a x . i n t e r n a l g l o b a l c l o c k f r e q u e n c y 1 0 0 . 0 1 0 0 . 0 9 0 . 9 m h z t a c n t m i n i m u m a r r a y c l o c k p e r i o d 1 0 . 0 1 0 . 0 1 1 . 0 n s f a c n t m a x . i n t e r n a l a r r a y c l o c k f r e q u e n c y 1 0 0 . 0 1 0 0 . 0 9 0 . 9 m h z 7 k t b l 0 6 b 2 s y m b o l s p e e d : - 1 2 s p e e d : - 1 0 p s p e e d : - 1 0 external timing parameters ac electrical s pecifications cont. cl7128e and cl7128s laser processed logic devices
cl7128e and cl7128s laser processed logic devices page 9 p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x u n i t t p d 1 i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 1 5 . 0 2 0 . 0 n s t p d 2 i / o i n p u t t o n o n - r e g i s t e r e d o u t p u t c l = 3 5 p f 1 5 . 0 2 0 . 0 n s t s u g l o b a l c l o c k s e t u p t i m e 1 1 . 0 1 2 . 0 n s t h g l o b a l c l o c k h o l d t i m e 0 . 0 0 . 0 n s t f s u g l o b a l c l o c k s e t u p t i m e o f f a s t i n p u t 3 . 0 5 . 0 n s t f h g l o b a l c l o c k h o l d t i m e o f f a s t i n p u t 0 . 0 0 . 0 n s t c o 1 g l o b a l c l o c k t o o u t p u t d e l a y c l = 3 5 p f 8 . 0 1 2 . 0 n s t c h g l o b a l c l o c k h i g h t i m e 5 . 0 6 . 0 n s t c l g l o b a l c l o c k l o w t i m e 5 . 0 6 . 0 n s t a s u a r r a y c l o c k s e t u p t i m e 4 . 0 5 . 0 n s t a h a r r a y c l o c k h o l d t i m e 4 . 0 5 . 0 n s t a c o 1 a r r a y c l o c k t o o u t p u t d e l a y c l = 3 5 p f 1 5 . 0 2 0 . 0 n s t a c h a r r a y c l o c k h i g h t i m e 6 . 0 8 . 0 n s t a c l a r r a y c l o c k l o w t i m e 6 . 0 8 . 0 n s t o d h o u t p u t d a t a h o l d t i m e a f t e r c l o c k c l = 3 5 p f 1 . 0 1 . 0 n s t c n t m i n i m u m g l o b a l c l o c k p e r i o d 1 3 . 0 1 6 . 0 n s f c n t m a x i m u m i n t e r n a l g l o b a l c l o c k f r e q u e n c y 7 6 . 9 6 2 . 5 m h z t a c n t m i n i m u m a r r a y c l o c k p e r i o d 1 3 . 0 1 6 . 0 n s f a c n t m a x i m u m i n t e r n a l a r r a y c l o c k f r e q u e n c y 7 6 . 9 6 2 . 5 m h z s y m b o l s p e e d : - 2 0 s p e e d : - 1 5 7 k t b l 0 6 b 3 external timing parameters ac electrical s pecifications cont.
p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x m i n m a x u n i t t i n i n p u t p a d a n d b u f f e r d e l a y 0 . 2 0 . 2 0 . 5 n s t i o i / o i n p u t p a d a n d b u f f e r d e l a y 0 . 2 0 . 2 0 . 5 n s t f i n f a s t i n p u t d e l a y 2 . 2 2 . 6 1 . 0 n s t s e x p s h a r e d e x p a n d e r d e l a y 3 . 1 3 . 7 4 . 0 n s t p e x p p a r a l l e l e x p a n d e r d e l a y 0 . 9 1 . 1 0 . 8 n s t l a d l o g i c a r r a y d e l a y 2 . 6 3 . 0 3 . 0 n s t l a c l o g i c c o n t r o l a r r a y d e l a y 2 . 5 3 . 0 3 . 0 n s t i o e i n t e r n a l o u t p u t e n a b l e d e l a y 0 . 7 0 . 7 2 . 0 n s o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v t x z o u t p u t b u f f e r d i s a b l e d e l a y c l = 5 p f [ 3 ] 4 . 0 4 . 0 4 . 0 n s t s u r e g i s t e r s e t u p t i m e 0 . 8 1 . 0 3 . 0 n s t h r e g i s t e r h o l d t i m e 1 . 7 1 . 7 2 . 0 n s t f s u r e g i s t e r s e t u p t i m e o f f a s t i n p u t 1 . 9 1 . 9 3 . 0 n s t f h r e g i s t e r h o l d t i m e o f f a s t i n p u t 0 . 6 0 . 6 0 . 5 n s t r d r e g i s t e r d e l a y 1 . 2 1 . 4 1 . 0 n s t c o m b c o m b i n a t o r i a l d e l a y 0 . 9 1 . 0 1 . 0 n s t i c a r r a y c l o c k d e l a y 2 . 7 3 . 1 3 . 0 n s t e n r e g i s t e r e n a b l e t i m e 2 . 6 3 . 0 3 . 0 n s t g l o b g l o b a l c o n t r o l d e l a y 1 . 6 2 . 0 1 . 0 n s t p r e r e g i s t e r p r e s e t t i m e 2 . 0 2 . 4 2 . 0 n s t c l r r e g i s t e r c l e a r t i m e 2 . 0 2 . 4 2 . 0 n s t l i a l i a d e l a y 1 . 1 1 . 4 1 . 0 n s 4 . 5 9 . 0 9 . 0 7 k t b l 0 7 b 1 n s n s 2 . 0 4 . 5 n s 4 . 0 n s 7 . 0 0 . 7 0 . 2 n s 0 . 9 2 . 5 n s 0 . 4 9 . 0 4 . 5 4 . 0 5 . 2 4 . 0 5 . 4 c l = 3 5 p f c l = 3 5 p f c l = 3 5 p f c l = 3 5 p f t z x 3 c l = 3 5 p f c l = 3 5 p f t z x 1 t z x 2 t o d 3 s p e e d : - 5 s p e e d : - 6 s y m b o l s p e e d : - 7 t o d 1 t o d 2 cl7128e and cl7128s laser processed logic devices page 10 ac electrical s pecifications cont. internal timing parameters [4]
p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x m i n m a x u n i t t i n i n p u t p a d a n d b u f f e r d e l a y 0 . 5 0 . 5 2 . 0 n s t i o i / o i n p u t p a d a n d b u f f e r d e l a y 0 . 5 0 . 5 2 . 0 n s t f i n f a s t i n p u t d e l a y 1 . 0 1 . 0 1 . 0 n s t s e x p s h a r e d e x p a n d e r d e l a y 5 . 0 5 . 0 7 . 0 n s t p e x p p a r a l l e l e x p a n d e r d e l a y 0 . 8 0 . 8 1 . 0 n s t l a d l o g i c a r r a y d e l a y 5 . 0 5 . 0 5 . 0 n s t l a c l o g i c c o n t r o l a r r a y d e l a y 5 . 0 5 . 0 5 . 0 n s t i o e i n t e r n a l o u t p u t e n a b l e d e l a y 2 . 0 2 . 0 2 . 0 n s o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v t x z o u t p u t b u f f e r d i s a b l e d e l a y c l = 5 p f [ 3 ] 5 . 0 5 . 0 6 . 0 n s t s u r e g i s t e r s e t u p t i m e 2 . 0 2 . 0 4 . 0 n s t h r e g i s t e r h o l d t i m e 3 . 0 5 . 0 4 . 0 n s t f s u r e g i s t e r s e t u p t i m e o f f a s t i n p u t 3 . 0 3 . 0 2 . 0 n s t f h r e g i s t e r h o l d t i m e o f f a s t i n p u t 0 . 5 0 . 5 2 . 0 n s t r d r e g i s t e r d e l a y 2 . 0 2 . 0 1 . 0 n s t c o m b c o m b i n a t o r i a l d e l a y 2 . 0 2 . 0 1 . 0 n s t i c a r r a y c l o c k d e l a y 5 . 0 5 . 0 5 . 0 n s t e n r e g i s t e r e n a b l e t i m e 5 . 0 5 . 0 5 . 0 n s t g l o b g l o b a l c o n t r o l d e l a y 1 . 0 1 . 0 0 . 0 n s t p r e r e g i s t e r p r e s e t t i m e 3 . 0 3 . 0 3 . 0 n s t c l r r e g i s t e r c l e a r t i m e 3 . 0 3 . 0 3 . 0 n s t l i a l i a d e l a y 1 . 0 1 . 0 1 . 0 n s t o d 1 t o d 2 s p e e d : - 1 0 p s p e e d : - 1 0 s y m b o l s p e e d : - 1 2 t z x 1 t z x 2 t o d 3 t z x 3 c l = 3 5 p f c l = 3 5 p f c l = 3 5 p f c l = 3 5 p f c l = 3 5 p f c l = 3 5 p f 5 . 0 5 . 5 5 . 0 9 . 0 5 . 5 2 . 0 1 . 5 n s 2 . 0 4 . 0 n s 1 . 5 3 . 0 7 . 0 n s 6 . 0 n s 7 . 0 1 0 . 0 5 . 5 7 k t b l 0 7 b 2 n s n s 5 . 5 9 . 0 cl7128e and cl7128s laser processed logic devices page 11 ac electrical s pecifications cont. internal timing parameters [4]
p a r a m e t e r c o n d i t i o n s m i n m a x m i n m a x u n i t t i n i n p u t p a d a n d b u f f e r d e l a y 2 . 0 3 . 0 n s t i o i / o i n p u t p a d a n d b u f f e r d e l a y 2 . 0 3 . 0 n s t f i n f a s t i n p u t d e l a y 2 . 0 4 . 0 n s t s e x p s h a r e d e x p a n d e r d e l a y 8 . 0 9 . 0 n s t p e x p p a r a l l e l e x p a n d e r d e l a y 1 . 0 2 . 0 n s t l a d l o g i c a r r a y d e l a y 6 . 0 8 . 0 n s t l a c l o g i c c o n t r o l a r r a y d e l a y 6 . 0 8 . 0 n s t i o e i n t e r n a l o u t p u t e n a b l e d e l a y 3 . 0 4 . 0 n s o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r a n d p a d d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 5 . 0 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o f f , v c c i o = 3 . 3 v o u t p u t b u f f e r e n a b l e d e l a y s l o w s l e w r a t e = o n , v c c i o = 5 . 0 v o r 3 . 3 v t x z o u t p u t b u f f e r d i s a b l e d e l a y c l = 5 p f [ 3 ] 6 . 0 1 0 . 0 n s t s u r e g i s t e r s e t u p t i m e 4 . 0 4 . 0 n s t h r e g i s t e r h o l d t i m e 4 . 0 5 . 0 n s t f s u r e g i s t e r s e t u p t i m e o f f a s t i n p u t 2 . 0 4 . 0 n s t f h r e g i s t e r h o l d t i m e o f f a s t i n p u t 1 . 0 3 . 0 n s t r d r e g i s t e r d e l a y 1 . 0 1 . 0 n s t c o m b c o m b i n a t o r i a l d e l a y 1 . 0 1 . 0 n s t i c a r r a y c l o c k d e l a y 6 . 0 8 . 0 n s t e n r e g i s t e r e n a b l e t i m e 6 . 0 8 . 0 n s t g l o b g l o b a l c o n t r o l d e l a y 1 . 0 3 . 0 n s t p r e r e g i s t e r p r e s e t t i m e 4 . 0 4 . 0 n s t c l r r e g i s t e r c l e a r t i m e 4 . 0 4 . 0 n s t l i a l i a d e l a y 2 . 0 3 . 0 n s s p e e d : - 1 5 s p e e d : - 2 0 s y m b o l 7 k t b l 0 7 b 3 t o d 1 c l = 3 5 p f 4 . 0 5 . 0 n s t o d 2 c l = 3 5 p f 5 . 0 6 . 0 n s 9 . 0 n s t o d 3 c l = 3 5 p f t z x 1 c l = 3 5 p f 8 . 0 6 . 0 1 0 . 0 n s 1 1 . 0 n s t z x 2 c l = 3 5 p f t z x 3 c l = 3 5 p f n s 7 . 0 1 0 . 0 1 4 . 0 cl7128e and cl7128s laser processed logic devices page 12 ac electrical s pecifications cont. internal timing parameters [4]
cl7128e and cl7128s laser processed logic devices page 13 1. during transitions, inputs may undershoot to -2.0v for periods shorter than 20ns. otherwise, minimum dc input voltage is 0.3v. 2. typical values are at v cc of 5.0 volts and ambient temperature of 25 oc. 3. guaranteed but not tested. characterized initially, and after any design changes which may affect these parameters. 4. internal timing delays are based on characterization, and cannot be explicitly tested. internal timing parameters should be used for performance estimation only. 11 jan. 1999: created new document 30 apr. 1999: recompiled databook, no changes. 31 july 1999: added -5ns speed grade, revised product family overview 13 oct. 1999: corrected typographical error in ac test condition diagram (w changed to w ) 1 dec. 2000: updated application note reference. ac t est conditions 464 w 250 w 35 pf v ccio output includes jig capacitance 464 w 250 w 5 pf v ccio output includes jig capacitance (a) (b) 3ns 3ns 3.0v 90% 10% gnd 90% 10% all input pulses 7 k d r w 0 2 a notes to t ables revision history
cl7128e and cl7128s laser processed logic devices page 14 ordering information p a r t n u m b e r t e m p e r a t u r e r a n g e p a c k a g e t y p e s p e e d a l t e r a e q u i v a l e n t c l 7 1 2 8 e l c 8 4 - 2 0 c o m m e r c i a l 8 4 - p i n p l a s t i c l c c - 2 0 e p m 7 1 2 8 e l c 8 4 - 2 0 c l 7 1 2 8 e l c 8 4 - 1 5 - 1 5 e p m 7 1 2 8 e l c 8 4 - 1 5 c l 7 1 2 8 e l c 8 4 - 1 2 - 1 2 e p m 7 1 2 8 e l c 8 4 - 1 2 c l 7 1 2 8 e l c 8 4 - 1 0 - 1 0 e p m 7 1 2 8 e l c 8 4 - 1 0 c l 7 1 2 8 e l c 8 4 - 7 - 7 e p m 7 1 2 8 e l c 8 4 - 7 c l 7 1 2 8 e l c 8 4 - 6 - 6 n / a c l 7 1 2 8 e l i 8 4 - 2 0 i n d u s t r i a l - 2 0 e p m 7 1 2 8 e l i 8 4 - 2 0 c l 7 1 2 8 e q c 1 0 0 - 2 0 c o m m e r c i a l 1 0 0 - p i n p l a s t i c q f p - 2 0 e p m 7 1 2 8 e q c 1 0 0 - 2 0 c l 7 1 2 8 e q c 1 0 0 - 1 5 - 1 5 e p m 7 1 2 8 e q c 1 0 0 - 1 5 c l 7 1 2 8 e q c 1 0 0 - 1 2 - 1 2 e p m 7 1 2 8 e q c 1 0 0 - 1 2 c l 7 1 2 8 e q c 1 0 0 - 1 0 - 1 0 e p m 7 1 2 8 e q c 1 0 0 - 1 0 c l 7 1 2 8 e q c 1 0 0 - 1 0 p - 1 0 p c i e p m 7 1 2 8 e q c 1 0 0 - 1 0 p c l 7 1 2 8 e q c 1 0 0 - 7 - 7 e p m 7 1 2 8 e q c 1 0 0 - 7 c l 7 1 2 8 e q c 1 0 0 - 6 - 6 e p m 7 1 2 8 e q c 1 0 0 - 6 c l 7 1 2 8 e q i 1 0 0 - 2 0 i n d u s t r i a l - 2 0 e p m 7 1 2 8 e q i 1 0 0 - 2 0 c l 7 1 2 8 e q i 1 0 0 - 1 5 - 1 5 e p m 7 1 2 8 e q i 1 0 0 - 1 5 c l 7 1 2 8 e q c 1 6 0 - 2 0 c o m m e r c i a l 1 6 0 - p i n p l a s t i c q f p - 2 0 e p m 7 1 2 8 e q c 1 6 0 - 2 0 c l 7 1 2 8 e q c 1 6 0 - 1 5 - 1 5 e p m 7 1 2 8 e q c 1 6 0 - 1 5 c l 7 1 2 8 e q c 1 6 0 - 1 2 - 1 2 e p m 7 1 2 8 e q c 1 6 0 - 1 2 c l 7 1 2 8 e q c 1 6 0 - 1 0 - 1 0 e p m 7 1 2 8 e q c 1 6 0 - 1 0 c l 7 1 2 8 e q c 1 6 0 - 1 0 p - 1 0 p c i e p m 7 1 2 8 e q c 1 6 0 - 1 0 p c l 7 1 2 8 e q c 1 6 0 - 7 - 7 e p m 7 1 2 8 e q c 1 6 0 - 7 c l 7 1 2 8 e q c 1 6 0 - 6 - 6 n / a
cl7128e and cl7128s laser processed logic devices page 15 p a r t n u m b e r t e m p e r a t u r e r a n g e p a c k a g e t y p e s p e e d a l t e r a e q u i v a l e n t c l 7 1 2 8 s l c 8 4 - 1 5 c o m m e r c i a l 8 4 - p i n p l a s t i c l c c - 1 5 e p m 7 1 2 8 s l c 8 4 - 1 5 c l 7 1 2 8 s l c 8 4 - 1 0 - 1 0 e p m 7 1 2 8 s l c 8 4 - 1 0 c l 7 1 2 8 s l c 8 4 - 7 - 7 e p m 7 1 2 8 s l c 8 4 - 7 c l 7 1 2 8 s l c 8 4 - 6 - 6 e p m 7 1 2 8 s l c 8 4 - 6 c l 7 1 2 8 s l c 8 4 - 5 - 5 n / a c l 7 1 2 8 s l i 8 4 - 1 0 i n d u s t r i a l - 1 0 e p m 7 1 2 8 s l c 8 4 - 1 0 c l 7 1 2 8 s q c 1 0 0 - 1 5 c o m m e r c i a l 1 0 0 - p i n p l a s t i c q f p - 1 5 e p m 7 1 2 8 s q c 1 0 0 - 1 5 c l 7 1 2 8 s q c 1 0 0 - 1 0 - 1 0 e p m 7 1 2 8 s q c 1 0 0 - 1 0 c l 7 1 2 8 s q c 1 0 0 - 7 - 7 e p m 7 1 2 8 s q c 1 0 0 - 7 c l 7 1 2 8 s q c 1 0 0 - 6 - 6 e p m 7 1 2 8 s q c 1 0 0 - 6 c l 7 1 2 8 s q c 1 0 0 - 5 - 5 n / a c l 7 1 2 8 s q i 1 0 0 - 1 0 i n d u s t r i a l - 1 0 e p m 7 1 2 8 s q i 1 0 0 - 1 0 c l 7 1 2 8 s t c 1 0 0 - 1 5 c o m m e r c i a l 1 0 0 - p i n t h i n q f p - 1 5 e p m 7 1 2 8 s t c 1 0 0 - 1 5 c l 7 1 2 8 s t c 1 0 0 - 1 0 - 1 0 e p m 7 1 2 8 s t c 1 0 0 - 1 0 c l 7 1 2 8 s t c 1 0 0 - 7 - 7 e p m 7 1 2 8 s t c 1 0 0 - 7 c l 7 1 2 8 s t c 1 0 0 - 6 - 6 e p m 7 1 2 8 s t c 1 0 0 - 6 c l 7 1 2 8 s t c 1 0 0 - 5 - 5 n / a c l 7 1 2 8 s t i 1 0 0 - 1 0 i n d u s t r i a l - 1 0 e p m 7 1 2 8 s t i 1 0 0 - 1 0 c l 7 1 2 8 s q c 1 6 0 - 1 5 c o m m e r c i a l 1 6 0 - p i n p l a s t i c q f p - 1 5 e p m 7 1 2 8 s q c 1 6 0 - 1 5 c l 7 1 2 8 s q c 1 6 0 - 1 0 - 1 0 e p m 7 1 2 8 s q c 1 6 0 - 1 0 c l 7 1 2 8 s q c 1 6 0 - 7 - 7 e p m 7 1 2 8 s q c 1 6 0 - 7 c l 7 1 2 8 s q c 1 6 0 - 6 - 6 e p m 7 1 2 8 s q c 1 6 0 - 6 c l 7 1 2 8 s q c 1 6 0 - 5 - 5 n / a c l 7 1 2 8 s q i 1 6 0 - 1 0 i n d u s t r i a l - 1 0 e p m 7 1 2 8 s q i 1 6 0 - 1 0 7 1 2 8 t b l 0 2 ordering information
cl7128e and cl7128s laser processed logic devices page 16

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