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tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 copyright ? 1994, texas instruments incorporated 1 post office box 1443 ? houston, texas 772511443 this data sheet is applicable to all tms416100/ps symbolized with revision abo and subsequent revisions as described on page 24. ? organizatio n...16777216 1 ? single 5-v power supply ( 10% tolerance) ? performance ranges: access access access read time time time or write t rac t cac t aa cycle (max ) (max ) (max ) (min) '416100- 60 60 ns 15 ns 30 ns 110 ns '416100- 70 70 ns 18 ns 35 ns 130 ns '416100- 80 80 ns 20 ns 40 ns 150 ns ? enhanced page mode operation for faster memory access ? cas -before-ras refresh ? long refresh period 4096 cycle refresh in 64 ms (tms416100) 256 ms for extended refresh version (tms416100p) ? 3-state unlatched output ? low power dissipation (tms416100p only) 500- m a cmos standby current 500- m a self-refresh current 500- m a extended refresh battery backup current ? all inputs, outputs and clocks are ttl compatible ? operating free-air temperature range: 0 c to 70 c description the tms416100/p series are high-speed, 16 777 216-bit dynamic random-access memories, organized as 16 777 216 words of one bit each. the tms416100p series feature self refresh and extended refresh. they employ state-of-the-art epic ? (enhanced performance implanted cmos) technology for high performance, reliability, and low power at a low cost. these devices feature maximum ras access times of 60 ns, 70 ns, and 80 ns. all inputs, outputs, and clocks are compatible with series 74 ttl. all addresses and data-in lines are latched on chip to simplify system design. data out is unlatched to allow greater system flexibility. the tms416100/p are offered in 300-mil 24/26-lead plastic surface-mount soj packages (dj suffix) and 24/26-lead plastic small-outline packages (dga suffix). all packages are characterized for operation from 0 c to 70 c. pin nomenclature a0 a11 address inputs cas column-address strobe d data in q data out nc no internal connection ras row-address strobe v cc 5-v supply v ss ground w write enable 1 2 3 4 5 6 v cc d nc w ras a11 8 9 10 11 12 13 a10 a0 a1 a2 a3 v cc 19 18 17 16 15 14 a8 a7 a6 a5 a4 v ss v ss q nc cas nc a9 26 25 24 23 22 21 dj package ( top view ) v cc d nc w ras a11 26 25 24 23 22 21 19 18 17 16 15 14 1 2 3 4 5 6 v ss q nc cas nc a9 8 9 10 11 12 13 a10 a0 a1 a2 a3 v cc a8 a7 a6 a5 a4 v ss dga package ( top view ) production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. epic is a trademark of texas instruments incorporated.
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 2 post office box 1443 ? houston, texas 772511443 logic symbol 2 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 ras cas w d 9 10 11 12 15 16 17 18 19 21 5 23 4 2 30d12/21d0 31d23/21d11 c30 [row] g33 [refresh row] 34 [pwr dwn] c31 [col] g34 33c32 33, 31d 34 en a, 32d a 0 16 383k ram 16 384k 1 & a10 8 27 q a ? a11 6 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. pin numbers shown are for the dj and dga packages.
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 3 post office box 1443 ? houston, texas 772511443 functional block diagram a0 a1 a11 2 10 12 12 4 4 2 timing and control column- address buffers row- address buffers i/o buffers 1 of 4 selection data in reg. data out reg. column decode sense amplifiers 64 256k array 256k array 256k array ras cas w row decode d q operation enhanced page mode enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. the time for row-address setup and hold and address multiplex is thus eliminated. the maximum number of columns that can be accessed is determined by t rasp , the maximum ras -low time. unlike conventional page-mode drams, the column-address buffers in this device are activated on the falling edge of ras . the buffers act as transparent or flow-through latches while cas is high. the falling edge of cas latches the addresses and enables the output. this feature allows the tms416100/p to operate at a higher data bandwidth than conventional page-mode parts because retrieval begins as soon as the column address is valid rather than when cas transitions low. this performance improvement is referred to as enhanced page mode . valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of cas . in this case, data is obtained after t cac max (access time from cas low), if t aa max (access time from column address) and t rac have been satisfied. in the event that the column address for the next cycle is valid at the time cas goes high, access time for the next cycle is determined by the later occurrence of t cpa or t cac . address (a0 a11) twenty-four address bits are required to decode 1 of 16 777 216 storage cell locations. twelve row-address bits are set up on inputs a0 through a11 and latched during a normal access and during ras -only refresh as the device requires 4096 refresh cycles. twelve column-address bits are set up on inputs a0 a11 and latched onto the chip by cas . all addresses must be stable on or before the falling edges of ras and cas . ras is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. cas is used as a chip select, activating the output buffer as well as latching the address bits into the column-address buffer.
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 4 post office box 1443 ? houston, texas 772511443 write enable ( w ) the read or write mode is selected through the write-enable ( w ) input. a logic high on the w input selects the read mode and a logic low selects the write mode. the write-enable terminal can be driven from standard ttl circuits without a pullup resistor. the data input is disabled when the read mode is selected. when w goes low prior to cas (early write), data out remains in the high-impedance state for the entire cycle, permitting common i/o operation. data in (d) data is written during a write or read-modify-write cycle. depending on the mode of operation, the falling edge of cas or w strobes data into the on-chip data latch. in an early-write cycle, w is brought low prior to cas and the data is strobed in by cas with setup and hold times referenced to this signal. in a delayed-write or read-modify-write cycle, cas is already low and the data is strobed in by w with setup and hold times referenced to this signal. data out (q) the 3-state output buffer provides direct ttl compatibility (no pullup resistor required) with a fanout of two series 74 ttl loads. the output is in the high-impedance (floating) state until cas is brought low. in a read cycle, the output becomes valid at the latest occurrence of t rac , t aa , t cac , or t cpa and remains valid while cas is low. cas going high returns it to the high-impedance state. refresh a refresh operation must be performed at least once every 64 ms to retain data. this can be achieved by strobing each of the 4096 rows (a0 a11). a normal read or write cycle refreshes all bits in each row that is selected. a ras -only operation can be used by holding cas at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. externally generated addresses must be used for a ras -only refresh. hidden refresh can be performed by holding cas at v il after a read operation and cycling ras after a specified precharge period, similar to a ras -only refresh cycle except with cas held low. valid data is maintained at the output throughout the hidden refresh cycle. an internal address provides the refresh address during hidden refresh. cas -before-ras refresh cas -before-ras (cbr) refresh is utilized by bringing cas low earlier than ras (see parameter t csr ) and holding it low after ras falls (see parameter t chr ). for successive cas -before-ras refresh cycles, cas remains low while cycling ras . for this mode of refresh, the external addresses are ignored and the refresh address is generated internally. a low-power battery-backup refresh mode that requires less than 500 m a refresh current is available on the tms416100p. data integrity is maintained using cas -before-ras refresh with a period of 62.5 m s while holding ras low for less than 1 m s. to minimize current consumption, all input levels need to be at cmos levels (v il 0.2 v, v ih v cc 0.2 v). power up to achieve proper device operation, an initial pause of 200 m s followed by a minimum of eight initialization cycles is required after full v cc level is achieved. these eight initialization cycles need to include at least one refresh (ras -only or cas -before-ras ) cycle.
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 5 post office box 1443 ? houston, texas 772511443 self refresh ( tms416100p) the self-refresh mode is entered by dropping cas low prior to ras going low. cas and ras are both held low for a minimum of 100 m s. the chip is then refreshed by an on-board oscillator. no external address is required because the cbr counter is used to keep track of the address. to exit the self-refresh mode, both ras and cas are brought high to satisfy t chs . upon exiting the self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before continuing with normal operation. this ensures the dram is fully refreshed. test mode the test mode is initiated with a cas -before-ras refresh cycle while simultaneously holding the w input low (wcbr). the entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or write on subsequent cycles. while in the test mode, any data sequence can be performed. the device exits the test mode if a cas -before-ras (cbr) refresh cycle with w held high or a ras -only refresh (ror) cycle is performed. the device is configured as 1024k 16 bits with a 16-bit parallel read-and-write data path in the test mode. column addresses a0, a1, a10, and a11 are not used. during a read cycle, all 16 bits of the internal data bus are compared. if all bits are in the same data state, the output pin goes high. if one or more bits disagree, the output pin goes low. test time is reduced by a factor of 16, compared to normal memory mode. ras cas w test-mode cycle entry cycle exit cycle normal mode note: the states of w , data input, and address are defined by the type of cycle used during test mode. figure 1. test-mode cycle
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 6 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, v cc 1 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range (see note 1) 1 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . short-circuit output current 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range 55 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values in this data sheet are with respect to v ss . recommended operating conditions min nom max unit v cc supply voltage 4.5 5 5.5 v v ih high-level input voltage 2.4 6.5 v v il low-level input voltage (see note 2) 1 0.8 v t a operating free-air temperature 0 70 c note 2: the algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data s heet for logic voltage levels only.
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 7 post office box 1443 ? houston, texas 772511443 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions '416100 - 60 '416100p - 60 '416100 - 70 '416100p - 70 '416100 - 80 '416100p - 80 unit min max min max min max v oh high-level output voltage i oh = 5 ma 2.4 2.4 2.4 v v ol low-level output voltage i ol = 4.2 ma 0.4 0.4 0.4 v i i input current (leakage) 2 v i = 0 v to 6.5 v all other pins = 0 v to v cc 10 10 10 m a i o output current (leakage) 2 v o = 0 v to v cc , cas high 10 10 10 m a i cc1 read- or write-cycle current (see notes 3 and 5) v cc = 5.5 v, minimum cycle 80 70 60 ma i standby current after 1 memory cycle, ras and cas high, v ih = 2.4 v ( ttl) 2 2 2 ma i cc2 st an db y curren t after 1 memory cycle, ras and cas high '416100 1 1 1 ma ras an d cas hi g h , v ih = v cc 0.2 v (cmos) '416100p 500 500 500 m a i cc3 average refresh current (ras -only or cbr) (see notes 3 and 5) 2 ras cycling, cas high (ras -only); ras low after cas low (cbr) 80 70 60 ma i cc4 average page current (see notes 4 and 5) 2 ras low, cas cycling 70 60 50 ma i cc6 self-refresh current ('416100p only) cas and ras < 0.2 v, measured after t rass min 500 500 500 m a i cc7 standby current, output enable (see note 5) 2 ras = v ih , cas = v il , data out = enabled 5 5 5 ma i cc10 extended-refresh battery backup ('416100p only) t rc = 62.5 m s, t ras 1 m s, v cc 0.2 v v ih 6.5 v, 0 v v il 0.2 v, w and oe = v ih , address and data stable 500 500 500 m a 2 minimum cycle, v cc = 5.5 v notes: 3. measured with a maximum of one address change while ras = v il 4. measured with a maximum of one address change while cas = v ih 5. measured with no load connected
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 8 post office box 1443 ? houston, texas 772511443 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 mhz (see note 6) parameter min max unit c i(a) input capacitance, address inputs 5 pf c i(d) input capacitance, data inputs 5 pf c i(rc) input capacitance, strobe inputs 7 pf c i(w) input capacitance, write-enable input 7 pf c o output capacitance 7 pf note 6: v cc = 5 v 0.5 v, and the bias on pins under test is 0 v. switching characteristics over recommended ranges of supply voltage and operating free-air temperature parameter '416100 - 60 '416100p - 60 '416100 - 70 '416100p - 70 '416100 - 80 '416100p - 80 unit min max min max min max t aa access time from column address 30 35 40 ns t cac access time from cas low 15 18 20 ns t cpa access time from column precharge 35 40 45 ns t rac access time from ras low 60 70 80 ns t clz cas to output in low-impedance state 0 0 0 ns t oh output disable time, start of cas high 3 3 3 ns t off output disable time after cas high (see note 7) 0 15 0 18 0 20 ns note 7: t off is specified when the output is no longer driven.
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 9 post office box 1443 ? houston, texas 772511443 timing requirements over recommended ranges of supply voltage and operating free-air temperature '416100 - 60 '416100p - 60 '416100 - 70 '416100p - 70 '416100 - 80 '416100p - 80 unit min max min max min max t rc cycle time, random read or write (see note 8) 110 130 150 ns t rwc cycle time, read-write (see note 8) 130 153 175 ns t pc cycle time, page-mode read or write (see notes 8 and 9) 40 45 50 ns t prwc cycle time, page-mode read-write (see note 8) 60 68 75 ns t rasp pulse duration, page-mode, ras low (see note 10) 60 100 000 70 100 000 80 100 000 ns t ras pulse duration, nonpage-mode, ras low (see note 10) 60 10 000 70 10 000 80 10 000 ns t cas pulse duration, cas low (see note 11) 15 10 000 18 10 000 20 10 000 ns t cp pulse duration, cas high 10 10 10 ns t rp pulse duration, ras high (precharge) 40 50 60 ns t wp pulse duration, w low 10 10 10 ns t asc setup time, column address before cas low 0 0 0 ns t asr setup time, row address before ras low 0 0 0 ns t ds setup time, data (see note 12) 0 0 0 ns t rcs setup time, w high before cas low 0 0 0 ns t cwl setup time, w low before cas high 15 18 20 ns t rwl setup time, w low before ras high 15 18 20 ns t wcs setup time, w low before cas low (early-write operation only) 0 0 0 ns t wrp setup time, w high before ras low (cas -before-ras refresh only) 10 10 10 ns t wts setup time, w low before ras low (test mode only) 10 10 10 ns t cah hold time, column address after cas low 10 15 15 ns t dh hold time, data (see note 12) 10 15 15 ns t rah hold time, row address after ras low 10 10 10 ns t rch hold time, w high after cas high (see note 13) 0 0 0 ns t rrh hold time, w high after ras high (see note 13) 0 0 0 ns t wch hold time, w low after cas low (early-write operation only) 10 15 15 ns t wrh hold time, w high after ras low (cas -before-ras refresh only) 10 10 10 ns t wth hold time, w low after ras low (test mode only) 10 10 10 ns t rhcp hold time, ras high from cas precharge 35 40 45 ns t chs hold time, cas low after ras high (self refresh) 50 50 50 ns notes: 8. all cycle times assume t t = 5 ns. 9. to assure t pc min, t asc should be greater than or equal to t cp . 10. in a read-write cycle, t rwd and t rwl must be observed. 11. in a read-write cycle, t cwd and t cwl must be observed. 12. referenced to the later of cas or w in write operations 13. either t rrh or t rch must be satisfied for a read cycle.
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 10 post office box 1443 ? houston, texas 772511443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) '416100 - 60 '416100p - 60 '416100 - 70 '416100p - 70 '416100 - 80 '416100p - 80 unit min max min max min max t awd delay time, column address to w low (read-write operation only) 30 35 40 ns t chr delay time, ras low to cas high (cas -before-ras refresh only) 10 10 10 ns t crp delay time, cas high to ras low 5 5 5 ns t csh delay time, ras low to cas high 60 70 80 ns t csr delay time, cas low to ras low (cas -before-ras refresh only) 5 5 5 ns t cwd delay time, cas low to w low (read-write operation only) 15 18 20 ns t rad delay time, ras low to column address (see note 14) 15 30 15 35 15 40 ns t ral delay time, column address to ras high 30 35 40 ns t cal delay time, column address to cas high 30 35 40 ns t rcd delay time, ras low to cas low (see note 14) 20 45 20 52 20 60 ns t rpc delay time, ras high to cas low 0 0 0 ns t rsh delay time, cas low to ras high 15 18 20 ns t rwd delay time, ras low to w low (read-write operation only) 60 70 80 ns t cpw delay time, w low after cas precharge (read-write operation only) 35 40 45 ns t rass pulse duration, self-refresh entry from ras low 100 100 100 m s t rps pulse duration, ras precharge after self refresh 110 130 150 ns t taa access time from address (test mode) 35 40 45 ns t tcpa access time from column precharge (test mode) 40 45 50 ns t trac access time from ras (test mode) 65 75 85 ns t ref refresh time interval '416100 64 64 64 ms t ref refresh time inter v al '416100p 256 256 256 ms t t transition time 3 30 3 30 3 30 ns note 14: the maximum value is specified only to assure access time. parameter measurement information 1.31 v v cc = 5 v c l = 100 pf output under test output under test c l = 100 pf (b) alternate load circuit (a) load circuit r l = 218 w r 1 = 828 w r 2 = 295 w figure 2. load circuits
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 11 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a11 w q t rc row column don't care don't care don't care valid data out t ras t rp t csh t t t rcd t rsh t crp t cas t rad t asc t ral t asr t rcs t cah t rrh t rch t cac t off t aa t clz t rac t cp (see note a) hi-z t rah t cal note a: output can go from 3-state to an invalid data state prior to the specified access time. figure 3. read-cycle timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 12 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a11 w d t rc row column don't care don't care don't care valid data don't care t rp t ras t rsh t crp t cas t rcd t t t csh t asc t asr t ral t cah t cp t rad t cwl t rwl t wch t wcs t wp t dh t ds t cal t rah q hi-z figure 4. early-write-cycle timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 13 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a11 w d t rc row column don't care don't care don't care valid data don't care don't care t ras t rp t rsh t crp t cas t rcd t csh t t t asr t asc t ral t cah t rad t cwl t rwl t wp t ds t dh t cp t cal not valid t clz t off q t rah t oh figure 5. write-cycle timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 14 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a11 w d t rwc row column don't care don't care don't care t ras t rcd t t t cas t rp t crp t cp t t t cah t asc t rah t asr t rcs t awd t rwl t wp t cwl q valid out valid in don't care t ds t cwd t rwd t dh t clz (see note a) t cac t aa t rac hi-z t off t rad note a: output can go from 3-state to an invalid data state prior to the specified access time. figure 6. read-write-cycle timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 15 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a11 w q t rp row column don't care valid out (see note a) valid out t rasp t rcd t cas t cp t pc t rsh t rah t asc t ral t asr t aa 2 t rrh t rch t cpa 2 t rad t cac t aa t rac t clz t off column t cah t rcs t cal t crp t csh t rhcp t cac 2 2 access time is t cpa , t cac , or t aa dependent. note a: output can go from 3-state to an invalid data state prior to the specified access time. figure 7. enhanced-page-mode read-cycle timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 16 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a11 w d row column don't care (see note a) (see note a) valid in t rp valid data in don't care don't care don't care don't care column t rasp t csh t pc t rsh t cas t rcd t asc t rah t cah t cp t asr t rad t cwl t wp t cwl t rwl t dh t dh t ds t ds t ral t cal t crp q hi-z (see note a) (see note a) t rhcp notes: a. referenced to cas or w , whichever occurs last b. a read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications a re not violated. figure 8. enhanced-page-mode write-cycle timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 17 post office box 1443 ? houston, texas 772511443 parameter measurement information valid out valid out ras t rasp t rp cas a0 a11 w d q t cp t crp t cah t asc t asr t rah t awd t rcs t wp t cwd t rwl t cwl t dh t ds valid don't care valid don't care don't care column don't care column row t cac t aa t rac t clz (see note a) t off t cpa t csh t rcd t prwc t cas t rsh (see note a) t rad t rwd t cpw t rhcp notes: a. output can go from 3-state to an invalid data state prior to the specified access time. b. a read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not vi olated. figure 9. enhanced-page-mode read-write-cycle timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 18 post office box 1443 ? houston, texas 772511443 parameter measurement information t rc t ras t rp t t t asr t rah t crp t rpc ras cas a0 a11 w d don't care don't care row row don't care don't care don't care q t crp hi-z figure 10. ras -only-refresh-cycle timing ras cas w a0 a11 d q t rc don't care don't care hi-z t ras t rp t csr t rpc t t t chr t wrp t wrh figure 11. automatic (cas -before-ras ) refresh-cycle timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 19 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a11 row col don't care w q valid data t ras t rp t rp t ras t cas t cah t asc t wrp t wrh t wrh t wrp t cac t aa t off t chr refresh cycle refresh cycle memory cycle t wrp t wrh t rah t asr d don't care t clz t rac t rcs t rrh figure 12. hidden-refresh-cycle (read) timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 20 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas a0 a11 w d q row col don't care don't care refresh cycle memory cycle refresh cycle t ras t rp t ras t rp t chr t cas t cah t asc t rah t asr t wcs t wp t rrh t wrp t wrh t dh t ds t wch hi-z figure 13. hidden-refresh-cycle (write) timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 21 post office box 1443 ? houston, texas 772511443 parameter measurement information t rass t csr t rpc ras cas a0 a11 t rps t cp w oe dq1 dq4 t chs t off hi-z don't care don't care don't care figure 14. self-refresh-cycle timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 22 post office box 1443 ? houston, texas 772511443 parameter measurement information ras cas w a0 a11 d q t rc don't care hi-z t ras t rp t csr t rpc t t t chr t wts t wth don't care don't care figure 15. test-mode-entry-cycle timing ras cas a0 a11 w q t rp t rc t ras t rpc t csr t t t chr t wrp t wrh don't care don't care don't care t off don't care hi-z figure 16. test-mode-exit-cycle (cas -before-ras refresh cycle) timing
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 23 post office box 1443 ? houston, texas 772511443 mechanical data 113 14 26 0.050 (1,27) typ r pdso j24 / 26 dj 24 / 26 lead plastic small-outline j-lead package 0.305 (7,75) 0.295 (7,49) 0.148 (3,76) 0.128 (3,25) 0.260 (6,60) 0.275 (6,99) 0.680 (17,27) 0.670 (17,02) 0.020 (0,51) 0.340 (8,64) 0.330 (8,38) 0.026 (0,66) 0.032 (0,81) 0.016 (0,41) 0.106 (2,69) nom seating plane 0.004 (0,10) notes: a. all linear dimensions are in inches (millimeters). b. plastic body dimensions do not include mold protrusion. maximum mold protrusion is 0.005 (0,125).
tms416100, tms416100p 16777216-bit dynamic random-access memories smks611 february 1994 24 post office box 1443 ? houston, texas 772511443 mechanical data dga 24 / 26 lead plastic thin small-outline package r pdso g24 / 26 1,27 (0.050) typ index 9 1 2 3 4 5 10 11 12 13 14 15 16 17 18 22 23 24 25 26 1,20 (0.047) max 8,20 (0.323) typ 21 19 6 8 17, 25 (0.679) 17, 04 (0.671) 3 7, 72 (0.304) 7, 52 (0.296) 2 9, 42 (0.371) 9, 02 (0.355) 0, 60 (0.024) 0, 40 (0.016) 0, 15 (0.006) 0, 05 (0.002) 0, 51 (0.020) 0, 31 (0.012) 0 to 5 0, 21 (0.008) 0, 12 (0.005) 2 plastic body width does not include mold protrusion. maximum mold protrusion is 0,25 ( 0.010) per side from the edge of the pac kage bottom. 3 plastic body length does not include mold protrusion. maximum mold protrusion is 0,15 (0.006) per side from the edge of the pac kage bottom. note a: all linear dimensions are in millimeters and parenthetically in inches. device symbolization tms416100 ti w lot traceability code date code assembly site code die revision code wafer fab code package code speed (- 60, -70, -80) low-power/self-refresh code b p xxx lll dj p -ss printed in u. s. a. smks611
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