? semiconductor components industries, llc, 2006 march, 2006 ? rev. 2 1 publication order number: NTQD6968N/d NTQD6968N power mosfet 7.0 a, 20 v, common drain, dual n ? channel, tssop ? 8 features ? low r ds(on) ? higher efficiency extending battery life ? logic level gate drive ? 3 mm wide tssop ? 8 surface mount package ? high speed, soft recovery diode ? tssop ? 8 mounting information provided ? pb ? free package is available applications ? battery protection circuits maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage v dss 20 vdc gate ? to ? source voltage ? continuous v gs 12 vdc drain current ? continuous @ t a 25 c (note 1) ? continuous @ t a 70 c (note 1) ? pulsed (note 3) i d i d i dm 7.0 5.6 20 adc total power dissipation @ t a 25 c (note 1) p d 1.81 w drain current ? continuous @ t a 25 c (note 2) ? continuous @ t a 70 c (note 2) ? pulsed (note 3) i d i d i dm 6.2 4.9 18 adc total power dissipation @ t a 25 c (note 2) p d 1.39 w operating and storage temperature range t j , t stg ? 55 to +150 c thermal resistance ? junction ? to ? ambient (note 1) junction ? to ? ambient (note 2) r ja 69 90 c/w maximum lead temperature for soldering pur- poses for 10 seconds tl 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. mounted onto a 2 square fr ? 4 board (1 in sq, 2 oz. cu 0.06 thick single sided), t 10 sec. 2. mounted onto a 2 square fr ? 4 board (1 in sq, 2 oz. cu 0.06 thick single sided), steady state. 3. pulse test: pulse width = 300 s, duty cycle = 2%. device package shipping ? ordering information n ? channel d s1 g1 NTQD6968Nr2 tssop ? 8 4000/tape & reel n ? channel d s2 g2 ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 20 v 17 m @ 4.5 v r ds(on) typ 7.0 a i d max v (br)dss tssop ? 8 case 948s plastic 1 marking diagram & pin assignment 8 e68 = specific device code a = assembly location y = year ww = work week = pb ? free package s1 e68 yww a g1 s2 g2 dddd 1 http://onsemi.com NTQD6968Nr2g tssop ? 8 (pb ? free) 4000/tape & reel NTQD6968N tssop ? 8 100 units / rail
NTQD6968N http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source breakdown voltage (v gs = 0 vdc, i d = 250 adc) temperature coefficient (positive) v (br)dss 20 ? ? 16 ? ? vdc mv/ c zero gate voltage collector current (v ds = 16 vdc, v gs = 0 vdc, t j = 25 c) (v ds = 16 vdc, v gs = 0 vdc, t j = 125 c) i dss ? ? ? ? 1.0 10 adc gate ? body leakage current (v gs = 12 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics gate threshold voltage (v ds = v gs , i d = 250 adc) temperature coefficient (negative) v gs(th) 0.6 ? 0.75 3.0 1.2 ? vdc mv/ c static drain ? to ? source on ? state resistance (v gs = 4.5 vdc, i d = 7.0 adc) (v gs = 2.5 vdc, i d = 7.0 adc) (v gs = 2.5 vdc, i d = 3.5 adc) r ds(on) ? ? ? 0.017 0.022 0.022 0.022 0.030 0.030 forward transconductance (v ds = 10 vdc, i d = 7.0 adc) g fs ? 19.2 ? mhos dynamic characteristics input capacitance (v ds = 16 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss ? 630 ? pf output capacitance c oss ? 260 ? transfer capacitance c rss ? 95 ? switching characteristics (notes 4 and 5) turn ? on delay time (v dd = 16 vdc, i d = 7.0 adc, v gs = 4.5 vdc, r g = 6.0 ) t d(on) ? 8.0 ? ns rise time t r ? 25 ? turn ? off delay time t d(off) ? 60 ? fall time t f ? 65 ? gate charge (v ds = 16 vdc, v gs = 4.5 vdc, i d = 7.0 adc) q tot ? 12.5 17 nc q gs ? 1.0 ? q gd ? 5.0 ? body ? drain diode ratings (note 4) forward on ? voltage (i s = 7.0 adc, v gs = 0 vdc) v sd ? 0.82 1.2 vdc reverse recovery time (i s = 7.0 adc, v gs = 0 vdc, di s /dt = 100 a/ s) t rr ? 35 ? ns t a ? 15 ? t b ? 20 ? reverse recovery stored charge q rr ? 0.02 ? c 4. pulse test: pulse width = 300 s, duty cycle = 2%. 5. switching characteristics are independent of operating junction temperature.
NTQD6968N http://onsemi.com 3 12 10 14 8 6 4 2 0 0.04 0.03 0.02 0.01 v ds , drain ? to ? source voltage (volts) i d , drain current (amps) v gs , gate ? to ? source voltage (volts) i d , drain current (amps) v gs , gate ? to ? source voltage (volts) i d , drain current (amps) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) t j , junction temperature ( c) v ds , drain ? to ? source voltage (volts) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) 2 1.5 1 0 1000 100 10000 100000 0 12 0.6 10 0.4 0.2 8 figure 1. on ? region characteristics figure 2. transfer characteristics 0 0.03 2 0.02 0 410 figure 3. on ? resistance versus gate ? to ? source voltage figure 4. on ? resistance versus drain current and gate voltage figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current versus voltage 14 ? 50 50 25 0 ? 25 75 125 100 0 2.5 1 012 81620 6 4 2 0 2 628 6 41014 12 150 0.8 1 1.5 2 v ds 10 v t j = 25 c t j = 125 c i d = 7.0 a t j = 25 c v gs = 2.5 v v gs = 0 v t j = 150 c t j = 125 c i d = 3.5 a v gs = 4.5 v v gs = 10, 5, 3 and 2.2 v resp. 1.6 v 1.4 v 1.2 v 1.8 v v gs = 4.5 v 1.2 1.4 1.6 1.8 t j = 25 c t j = 25 c 0.5 0.015 0.025 0.035 0.5 t j = ? 55 c 0.01 8 4
NTQD6968N http://onsemi.com 4 gate ? to ? source or drain ? to ? source voltage (volts) c, capacitance (pf) q g , total gate charge (nc) v gs , gate ? to ? source voltage (volts) r g , gate resistance ( ) v sd , source ? to ? drain voltage (volts) i s , source current (amps) t, time (ns) v ds , drain ? to ? source voltage (volts) i d , drain current (amps) 100 10 1 0.1 0.01 1000 100 1 5 4 3 2 1 0 1.2 0.8 0.6 0.4 0.2 0 10 3000 2000 10 1500 15 5 0 1000 500 0 5 figure 7. capacitance variation figure 8. gate ? to ? source voltage versus total charge figure 9. resistive switching time variation versus gate resistance figure 10. diode forward voltage versus current figure 11. maximum rated forward biased safe operating area figure 12. diode reverse recovery waveform 20 0 5 2.5 7.5 1 10 100 0.5 0.525 0.6 0.1 10 100 1 10 10 12.5 i d = 7.0 a t j = 25 c v gs v gs = 0 v t j = 25 c c rss c iss c oss c rss c iss v gs = 20 v single pulse v dd = 16 v i d = 7.0 a v gs = 4.5 v v gs = 0 v t j = 25 c t r t d(off) t d(on) t f r ds(on) limit q t q 2 q 1 10 ms 1 ms 100 s dc v gs v ds thermal limit package limit di/dt t rr t a t p i s 0.25 i s time i s t b 2500 v ds = 0 v 1 0.575 t c = 25 c 1.4 0.55
NTQD6968N http://onsemi.com 5 10 0.001 0.0001 figure 13. thermal response t, time (s) r(t), transient thermal resistance (normalized) 0.000001 0.0001 0.001 1 0.01 100 10 1 0.1 0.01 0.00001 d = 0.5 0.1 0.2 0.1 0.05 0.02 0.01 single pulse
NTQD6968N http://onsemi.com 6 package dimensions tssop ? 8 case 948s ? 01 issue a dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 4.30 4.50 0.169 0.177 c ??? 1.10 ??? 0.043 d 0.05 0.15 0.002 0.006 f 0.50 0.70 0.020 0.028 g 0.65 bsc 0.026 bsc l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane ?w?. seating plane pin 1 1 4 85 detail e b c d a g l 2x l/2 ? u ? s u 0.20 (0.008) t s u m 0.10 (0.004) v s t 0.076 (0.003) ? t ? ? v ? ? w ? 8x ref k ident k 0.19 0.30 0.007 0.012 s u 0.20 (0.008) t p1 p detail e f m 0.25 (0.010) ???? ???? k1 k jj1 section n ? n j 0.09 0.20 0.004 0.008 k1 0.19 0.25 0.007 0.010 j1 0.09 0.16 0.004 0.006 p ??? 2.20 ??? 0.087 p1 ??? 3.20 ??? 0.126 n n mm inches 0.038 0.95 0.252 6.4 0.018 0.45 0.026 0.65 0.177 4.5 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
NTQD6968N http://onsemi.com 7 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?t ypicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license un der its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended f or surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in a ny manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NTQD6968N/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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