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1/18 june 2003 m68aw511a 4 mbit (512k x8) 3.0v asynchronous sram features summary n supply voltage: 2.7 to 3.6v n 512k x 8 bits sram with output enable n equal cycle and access times: 55ns n low standby current n low v cc data retention: 1.5v n tri-state common i/o n low active and standby power figure 1. packages tsop32 type ii (nc) 32 1 so32 (mc)
m68aw511a 2/18 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3. tsop and so connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 6. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. chip enable or output enable controlled, read mode ac waveforms. . . . . . . . . . . . . . . 9 table 7. read and standby mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. write enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11. chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12. low v cc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. low v cc data retention characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 13. tsop 32 type ii - 32 lead plastic thin small outline type ii, package outline . . . . . . 14 table 10. tsop32 type ii - 32 lead plastic thin small outline typeii, package mechanical data 14 figure 14. so32 - 32 lead plastic small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. so32 - 32 lead plastic small outline, package mechanical data. . . . . . . . . . . . . . . . . . 15 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3/18 m68aw511a summary description the m68aw511a is a 4 mbit (4,194,304 bit) cmos sram, organized as 524,288 words by 8 bits. the device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. it requires a single 2.7 to 3.6v supply. this device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. the m68aw511a is available in two different packages: 32-lead tsop type ii and 32-lead so. figure 2. logic diagram table 1. signal names ai05445c 19 a0-a18 w dq0-dq7 v cc m68aw511a g v ss 8 e a0-a18 address inputs dq0-dq7 data input/output e chip enable g output enable w write enable v cc supply voltage v ss ground
m68aw511a 4/18 figure 3. tsop and so connections dq5 dq6 dq7 dq0 v ss dq3 dq4 dq1 dq2 a12 a15 a14 a16 a6 a17 g w a8 a10 a11 a9 a13 a5 a7 a2 a0 a3 a4 a1 ai05446c m68aw511a 8 1 9 16 17 24 25 32 v cc a18 e
5/18 m68aw511a figure 4. block diagram maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 2. absolute maximum ratings note: 1. one output at a time, not to exceed 1 second of duration. 2. up to a maximum operating v cc of 3.6v only. ai05916 row decoder a8 a18 dq0 dq7 column decoder i/o circuits a0 a7 w g memory array e v cc v ss symbol parameter value unit i o (1) output current 20 ma t a ambient operating temperature C55 to 125 c t stg storage temperature C65 to 150 c v cc supply voltage C0.5 to 4.6 v v io (2) input or output voltage C0.5 to v cc +0.5 v p d power dissipation 1 w
m68aw511a 6/18 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions figure 5. ac measurement i/o waveform figure 6. ac measurement load circuit parameter m68aw511a v cc supply voltage 2.7 to 3.6v ambient operating temperature range 1 0 to 70c range 6 C40 to 85c load capacitance (c l ) 30pf output circuit protection resistance (r 1 ) 3.0k w load resistance (r 2 ) 3.1k w input rise and fall times 1ns/v input pulse voltages 0 to v cc input and output timing ref. voltages v cc /2 input and output transition timing ref. voltages v ol = 0.3v cc ; v oh = 0.7v cc ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc i/o transition timing reference voltage 0v 0.7v cc 0.3v cc ai03853 v cc out c l includes jig capacitance device under test c l r 1 r 2
7/18 m68aw511a table 4. capacitance note: 1. sampled only, not 100% tested. 2. at t a = 25c, f = 1mhz, v cc = 3.0v. table 5. dc characteristics note: 1. average ac current, cycling at t avav minimum. 2. e = v il , v in = v ih or v il . 3. e 0.2v, v in 0.2v or v in 3 v cc C 0.2v. 4. output disable. symbol parameter (1,2) test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 6pf c out output capacitance v out = 0v 8pf symbol parameter test condition min typ max unit i cc1 (1,2) operating supply current v cc = 3.6v, f = 1/t avav , i out = 0ma 30 ma i cc2 (3) operating supply current v cc = 3.6v, f = 1mhz , i out = 0ma 5ma i li input leakage current 0v v in v cc C1 1 a i lo (4) output leakage current 0v v out v cc C1 1 a i sb standby supply current cmos v cc = 3.6v, e 3 v cc C 0.2v, f=0 510a v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage C0.3 0.6 v v oh output high voltage i oh = C1ma 2.4 v v ol output low voltage i ol = 2.1ma 0.4 v
m68aw511a 8/18 operation the m68aw511a has a chip enable power down feature which invokes an automatic standby mode whenever chip enable is de-asserted (e = high). an output enable (g ) signal provides a high speed tri-state control, allowing fast read/write cy- cles to be achieved with the common i/o data bus. operational modes are determined by device con- trol inputs w and e as summarized in the operat- ing modes table (table 6). table 6. operating modes note: x = v ih or v il . read mode the m68aw511a is in the read mode whenever write enable (w ) is high with output enable (g ) low, and chip enable (e ) is asserted. this pro- vides access to data from eight of the 4,194,304 locations in the static memory array, specified by the 19 address inputs. valid data will be available at the eight output pins within t avqv after the last stable address, providing g is low and e is low. if chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t elqv or t glqv ) rather than the address. data out may be indeterminate at t elqx and t glqx , but data lines will always be valid at t avqv . figure 7. address controlled, read mode ac waveforms note: e = low, g = low, w = high. operation e w g dq0-dq7 power output disabled v il xv ih hi-z active (i cc ) read v il v ih v il data output active (i cc ) write v il v il x data input active (i cc ) deselect v ih x x hi-z standby (i sb ) ai03034 tavav tavqv taxqx a0-a18 dq0-dq7 valid data valid
9/18 m68aw511a figure 8. chip enable or output enable controlled, read mode ac waveforms. note: write enable (w ) = high. figure 9. chip enable controlled, standby mode ac waveforms ai03035 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a18 e g dq0-dq7 valid ai03036 tpd i cc1 tpu i cc2 50% e
m68aw511a 10/18 table 7. read and standby mode ac characteristics note: 1. test conditions assume transition timig reference level = 0.3v cc or 0.7v cc . 2. at any given temperature and voltage condition, t ehqz is less than t elqx and t ghqz is less than t glqx for any given device. 3. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. 4. tested initially and after any design or process changes that may affect these parameters symbol parameter m68aw511a unit 55 70 t avav read cycle time min 55 70 ns t avqv address valid to output valid max 55 70 ns t axqx (1) data hold from address change min 5 5 ns t ehqz (2,3) chip enable high to output hi-z max 20 25 ns t elqv chip enable low to output valid max 55 70 ns t elqx (1) chip enable low to output transition min 5 5 ns t ghqz (2,3) output enable high to output hi-z max 20 25 ns t glqv output enable low to output valid max 25 35 ns t glqx (1) output enable low to output transition min 5 5 ns t pd (4) chip enable high to power down max 0 0 ns t pu (4) chip enable low to power up min 55 70 ns
11/18 m68aw511a write mode the m68aw511a is in the write mode whenever the w and e pins are low. either the chip enable input (e ) or the write enable input (w ) must be de- asserted during address transitions for subse- quent write cycles. write begins with the concur- rence of chip enable being active with w low. therefore, address setup time is referenced to write enable and chip enable as t avwl and t aveh respectively, and is determined by the latter occur- ring edge. the write cycle can be terminated by the earlier rising edge of e , or w . if the output is enabled (e = low and g = low), then w will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the ris- ing edge of write enable, or for t dveh before the rising edge of e , whichever occurs first, and re- main valid for t whdx or t ehdx . figure 10. write enable controlled, write ac waveforms ai03037 tavav twhax tdvwh data input a0-a18 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx
m68aw511a 12/18 figure 11. chip enable controlled, write ac waveforms table 8. write mode ac characteristics note: 1. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t wlqz is less than t whqx for any given device. symbol parameter m68aw511a unit 55 70 t avav write cycle time min 55 70 ns t aveh address valid to chip enable high min 45 60 ns t ave l address valid to chip enable low min 0 0 ns t avwh address valid to write enable high min 45 60 ns t avw l address valid to write enable low min 0 0 ns t dveh input valid to chip enable high min 25 30 ns t dvwh input valid to write enable high min 25 30 ns t ehax chip enable high to address transition min 0 0 ns t ehdx chip enable high to input transition min 0 0 ns t eleh chip enable low to chip enable high min 45 60 ns t elwh chip enable low to write enable high min 45 60 ns t whax write enable high to address transition min 0 0 ns t whdx write enable high to input transition min 0 0 ns t whqx (1) write enable high to output transition min 5 5 ns t wleh write enable low to chip enable high min 45 60 ns t wlqz (1,2) write enable low to output hi-z max 20 25 ns t wlwh write enable low to write enable high min 45 60 ns ai05914 tavav tehax tdveh a0-a18 e w dq0-dq7 valid taveh tavel twleh teleh tehdx data input
13/18 m68aw511a figure 12. low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. all other inputs at v ih 3 v cc C0.2v or v il 0.2v. 2. tested initially and after any design or process may affect these parameters. t avav is read cycle time. 3. no input may exceed v cc +0.2v. symbol parameter test condition min typ max unit i ccdr (1) supply current (data retention) v cc = 1.5v, e 3 v cc C 0.2v, f = 0 (3) 4.5 9 a t cdr (1,2) chip disable to power down 0 ns t r (2) operation recovery time t avav ns v dr (1) supply voltage (data retention) e 3 v cc C 0.2v, f = 0 1.5 v ai05447 data retention mode tr 3.6v tcdr v cc 2.7v v dr > 1.5v e e 3 v dr C 0.2v
m68aw511a 14/18 package mechanical figure 13. tsop 32 type ii - 32 lead plastic thin small outline type ii, package outline note: drawing is not to scale. table 10. tsop32 type ii - 32 lead plastic thin small outline typeii, package mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.30 0.52 0.012 0.020 c 0.12 0.21 0.005 0.008 cp 0.10 0.004 d 20.82 21.08 0.820 0.830 e 1.27 C C 0.050 C C e 11.56 11.96 0.455 0.471 e1 10.03 10.29 0.395 0.405 l 0.40 0.60 0.016 0.024 a 0 5 0 5 n32 32 tsop-e n 1 cp a l a1 a n/2 d e b e1 e c a2
15/18 m68aw511a figure 14. so32 - 32 lead plastic small outline, package outline note: drawing is not to scale. table 11. so32 - 32 lead plastic small outline, package mechanical data symbol millimeters inches typ min max typ min max a 3.00 0.118 a1 0.10 0.004 a2 2.57 2.82 0.101 0.111 b 0.36 0.51 0.014 0.020 c 0.15 0.30 0.006 0.012 d 20.14 20.75 0.793 0.817 e 11.18 11.43 0.440 0.450 e1 13.87 14.38 0.546 0.566 e 1.27 C C 0.050 C C l 0.58 0.99 0.023 0.039 l1 1.19 1.60 0.047 0.063 cp 0.10 0.004 e 16 e a2 d c e1 a 17 32 1 b so-c cp a1 l l1
m68aw511a 16/18 part numbering table 12. ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. example: m68aw511 a l 55 nc 6 t device type m68 mode a = asynchronous operating voltage w = 2.7 to 3.6v array organization 511 = 4 mbit (512k x8) option 1 a = 1 chip enable option 2 l = l-die m = m-die speed class 55 = 55 ns 70 = 70 ns package nc = tsop32 type ii mc = so32 operative temperature 1 = 0 to 70c 6 = C40 to 85 c shipping t = tape & reel packing
17/18 m68aw511a revision history table 13. document revision history date version revision details august 2001 1.0 first issue 27-sep-2001 2.0 55ns speed class replaces 70ns 27-feb-2002 3.0 from preliminary data to data sheet 70ns speed class added temperature range 1 (0 to 70c) added block diagram clarified (figure 4) operating and ac measurement conditions table clarified (table 3) ac measurement load circuit clarified (figure 6) dc characteristics table clarified (table 5) write, read and standby mode ac characteristics tables clarified (table 8 and 7) chip enable controlled, write ac waveforms clarified (figure 11) low v cc data retention ac waveforms and characteristics clarified (figure 12 and table 9) 01-mar-2002 4.0 so32 package added 25-mar-2002 5.0 read and standby mode ac characteristics table clarified (table 7) low v cc data retention ac waveforms and characteristics clarified (figure 12 and table 9) 26-apr-2002 6.0 dc characteristics table clarified (table 5) write mode ac characteristics table clarified (table 8) 17-jun-2002 6.1 minor changes 09-sep-2002 6.2 load capacitance (c l ) changed from 100pf to 30pf (table 3) 02-oct-2002 6.3 new part number added. 09-oct-2002 6.4 commercial code modified. 12-jun-2003 6.5 correction to wording in operating modes table
m68aw511a 18/18 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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