the communications company tm overview the cw001100 processor core is a 200 mhz implementation of the popu- lar arm946e-s?, synthesized onto lsi logic?s g12p 0.18 micron high perfor- mance process technology. the arm946e-s, which is based on the five stage pipeline arm9e-s ? harvard architecture processor, also contains a complete memory subsystem of instruction and data caches (16 kbytes each), and configurable tightly coupled instruction and data memories (tcms). the core also includes an embedded trace macrocell (etm) interface, and an amba ? (advanced microprocessor bus architecture) ahb (advanced high performance bus) interface unit. this high level of integration helps ease the task of integrating the core into your system-on-chip (soc) design. cw001100 - 200 mhz synthesized arm946e-s ? core with cache memories arm946e-s block diagram features and benefits 200 mhz operating frequency (worst case commercial conditions) implemented on lsi logic?s g12p 0.18 micron, 1.8 v process 1.9 mw/mhz power dissipation, (with 0 kbytes tcms) arm946e-s industry standard architecture 16 kbyte instruction and data caches (4-way set associative) configurable tcms synthesized core for optimal timing accuracy and asic compatible design flow regional arm coreware design support
the communications company tm the inclusion of both cache memories and tcms gives this core the flexibility to address a very broad range of system applications. the cache memories offer a convenient cost-effective solution for handling applications with large memory requirements, and the tcms are ideal for highly deterministic code where precise memory cycle counts are required. the ahb interface provides a write buffer capable of burst transfers and split transactions. the etm interface, when used with the optional etm core, provides extensive real-time trace capabilities. the arm946e-s has full support for the armv5te instruction set including all of the arm9e-s family dsp instruction extensions. the core has full support for both the arm ? 32-bit and thumb ? 16-bit instruction sets, making it upwardly code-compatible with both the arm7tdmi ? and arm9tdmi ? families. the ability to switch on the fly between arm ? and thumb ? instruction sets allows the user to trade between high performance and code density. the built in amba bus interface of the arm946e-s core is an ideal stan- dard bus for building a complete cpu subsystem design. lsi logic offers both an amba subsystem reference design, and a library of popular amba cpu peripherals for use by customers on soc designs. customers can also incorporate their own amba-based blocks into this widely used industry standard bus. the arm946e-s is supported by a wide array of software development tools available from arm limited as well as third party vendors. the core is implemented in lsi logic?s g12p high performance 0.18 micron (drawn) process, giving a maximum speed of 200 mhz (worst case commercial conditions) and making it ideal for high performance applica- tions. power consumption for the core is 1.9 mw/mhz (including cache memories but excluding tcms). the cw001100 core is synthesized onto the g12p soc cell library and is provided complete with highly accurate timing models that fully support static timing analysis (sta) through the core. this can be a significant benefit for achieving timing closure on high performance designs. the core is fully compatible with lsi logic?s entire flexstream ? soc asic design flow making it straightforward to integrate into complex customer designs. the core comes complete with built-in full scan chains for good testability, and is provided with a comprehensive set of deliverables including design files, sta and atpg scripts, and detailed integration guidelines. to further assist customers with their designs, lsi logic provides specialized arm coreware ? integration support through our team of regionally based field coreware engineers. for more information please call: lsi logic corporation north american headquarters milpitas, ca tel: 800 574 4286 lsi logic europe ltd. european headquarters united kingdom tel: 44 1344 426544 fax: 44 1344 481039 lsi logic kk headquarters tokyo, japan tel: 81 3 5463 7165 fax: 81 3 5463 7820 lsi logic web site: www.lsilogic.com lsi logic logo design, coreware and flexstream are registered trademarks and g12 is a trade- mark of lsi logic corporation. arm and thumb are registered trademarks of arm limited. arm966e-s, arm9e-s, amba, arm7tdmi, and arm9tdmi are trademarks of arm limited. all other brand and product names may be trade- marks of their respective companies. lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic con- vey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or of third parties. copyright ?2001 by lsi logic corporation. all rights reserved. order no. r20050.a 1201.1k.sr.xx - printed in usa 200 mhz arm946e-s ? core
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